Overview of Renesas Microcontrollers

10/07/2008

Confidential
©2007. Renesas Technology Singapore Pte Ltd., All rights reserved.
 10/07/2008

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 Renesas MCU Position
- As NO.1 Supplier-
By Region (2007 Sales Record）） 　1st
W/W　
Renesas
　2nd
Europe　 21%
　1st
Asia　
A
13% Others
North
12%
A
America 2nd
B Japan 1st
F B
E D C Ａ
41%

D社
14%

By Application (2007 Sales Record））

　2nd
Automotive　 　1st
Consumer　 Industrial 1st Communications 　2nd
PC　
1st
18%
31% 41% C
A

17%
10/07/2008
16%

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 W/W No.1 Flash MCU Supplier
Flash MCU Total Shipment: 1.3B peaces! As of March 2008
Total shipment Annual shipment CY2007
(M pcs) (M pcs/Y) ) Others
3,000 J 2.7%
5.9%
1400 I 3.1%

2,500 H 3.4%
1200 Renesas
G 4.1%
2,000
March 2008
1000 25.5%
F 4.5%
Total : 1.3B pcs 800
1,500
E \736B
600 6.3%
1,000 A
D
400 9.0%
15.9%

500 200 C
B
9.3%
ACT FCT 10.3%
0 0
'94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04 '05 '06 '07 '08 '09 '10
Data: Marketing Eye 2008 edition

Flash MCU Shipment W/W Flash MCU Sales

90nm process realizes MONOS Flash memory achieves Today: 2.5MB FLASH MCU
200MHz high-speed access 1 cycle access at 100MHz Future: 4MB FLASH MCU
10/07/2008

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 Overview of MCU Family
32-bit RISC SuperH Family Core development
SH-2A
Processor type SH-4A
Controller type SH2-DSP
32-bit CISC SH3-DSP SH-4
SH-2
H8SX Family SH-1 SH-3 Superscalar
1 instruction in H8SX/1600
1 clock cycle SH/Tiny MMU
H8SX/1500
16 bits Tiny
H8S Family H8S/2600
1 instruction H8S/2500
Under development M32R Family
in 1 clock cycle M16C Family R32C/100 M32R/ECU
H8S/2400
1 instruction M32C/90
H8S/2300
in 1 clock cycle M32C/80
H8S/2200
H8S/2100 M16C/80
8 bits H8/300H M16C/60
H8 Family Tiny M16C/30
H8/300L M16C/Tiny
H8/Tiny
48 to 80 pins
32 to 100 pins
H8/300L
Super Low Power R8C/Lx R8C/Tiny
20 pins and more

4 bits 740 Family 7600

38000
4500
740
720
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 Overview of MCU Family

10/07/2008

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 Trend of High-speed Systems (e.g. automotive powertrain)
- X 20 performance in every 10 years -

Performance (MIPS)
1000 Dual core
32-bit
200MHz
Performance has improved 20-fold
100 every 10 years 80MHz
40MHz
32-bit
20MHz X 20
10 10 years

16MHz X 20
16-bit
1 10MHz
10 years

X 20
0.1 8-bit
2MHz
10 years

0.01
1980 1990 2000 2010 FY
10/07/2008

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 Trend of Memory Capacity (e.g. automotive powertrain)
- X8 capacity in every 10 years -
10 1MB
FLASH
512KB SH7xxxE
FLASH 4MB
Memory capacity has
SH725x
increased 8-hold every 2MB
10 years SH7058
1 1MB
SH7055
512kB
SH7051 X8
(MB) 256kB

10 years
H8/539
128kB
0.1
H8/536
64kB X8
H8/532 10 years
32kB

6300
8 to 16kB X8
0.01
10 years

1980 1990 2000 2010

10/07/2008

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 90nm-MCU with MONOS (SH-2A)
- The world’s first 2.5MB Flash MCU & Currently planning 4MB Flash -

- CPU : SH2A 200MHz Flash Flash

- FPU : Single/Double 1.25MB 1.25MB
- Flash : 2.5MB
- Data Flash: 128KB
- RAM : 128KB
- A/D : 12-bit x 37ch
- PKG : BGA2121-272

(1st sample was shipped in May 2007)

10/07/2008

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 High-Performance and Low Current Consumption
- Dual Core Technology -
MIPS Advantage to single core:
Performance Improve performance with lower
(relative value) current consumption

1.6 SH7265(SH2A-DUAL)
200MHz x 2 CPU
1.4

1.2 Competitor A: 400MHz

1.0

0.8
SH7263
0.6 SH-2A 200MHz Dual Core CPU
0.4 Single Core CPU
SH7261
0.2 SH-2A 100MHz

Icc core current

100 200 300 400 500 (mA)
10/07/2008 Current value in standard environment without using peripheral functions

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 Multi-Core LSI with 8 CPUs for Next Generation Embedded
Multi-core Technology
Announced on ISSCC 2008 (Paper No. 4.5)

ILRAM I-cache
Process: 90nm CMOS
LBSC

Core#0 8-layer metal,

Core#1
URAM
DLRAMD-cache
3 types of Vth
SNC0

DBG0 Chip size: 104.8mm2

Core#2 Core#3 10.61 x 9.88 mm
SHWY
GDBG

Power voltage: 1.0 to 1.4V (core)

Core#6 Core#7 1.8/3.3V (I/O)
SNC1

DBG1
VSWC
Operating Frequency: 600MHz
Core#4 Core#5
CPU Performance: 8,640MIPS
CSM

DBSC CPGM (Dhrystone2.0)

DDRPAD
10/07/2008
FPU Performance: 33.7GFLOPS
11
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 High precision fast OCO
- The highest level in the world +/-1% -
Oscillation accuracy
[%] -20 to 85 degrees C
4
R8C/2x R8C/3xA
3

0 +/-1% Vcc
3 3.5 4 4.5 5 5.5
-1 [V]

-2

-3

-4

<Customers’ advantages>
• External oscillator is no longer necessary

Reduce the number of parts and board size
•10/07/2008
Reduce EMI noise
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 PMC (Peripheral I/O Mapping Controller)
- Easy-to-design board layout-
Programmable pin assignment and
digital peripheral functions per each ports
Initial layout After setting PMC register
I/O port timer port

PMC
timer SCI
port port
SCI I/O Timer
port port
SCI
Pin function
Analog can be Analog
Pin changed by Pin
register setting

System Pin System Pin

In the future, all pins will be changed flexibly by improving function.

10/07/2008

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 Renesas Solutions to Meet Customer Demand
- Next Generation On-chip Memory -

Customer Voice Renesas Solution

New Generation Memory
MRAM
On-chip memory with zero Apply MRAM to
standby current next generation memory
- Lower current than SRAM - Zero standby current

On-chip memory MRAM: Memory without E/W

without E/W limitation limitation
- 1E5 E/W cycles are not enough -1E16 E/W cycles

Nonvolatile high-speed
Memory usable for read/writing operation
both ROM and RAM - Unified memory @ > 100MHz
10/07/2008

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 　 Next Generation Memory Solution
- MRAM can retain data at “zero” standby current -
◆ MRAM realized “zero” standby current at SRAM speed
- High-speed mixed memory： up to 200MHz
　
- Realized magnetic write by using magnetic field integrating bit-line current and
digit line current and read by using TMR effect
BL order BL reverse
magnetic field magnetic field
Hbitline
Bit-line
Write
MTJ cell
Hdigitline
(magnetic tunneling junction)
Digit-line
Bit-line

Bit-line

Read

Free layer
Digit-line low R Tunnel film
high R
Pin layer
D G
S TG
：Tunnel magneto　
TMR： 　
drain resistance
source
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 Memory Solution: E/W Cycle without limitation
- MRAM E/W cycle (1E16) and high-speed 100MHz operation -
F: Min. half-pitch feature size

Phase change MONOS

MRAM
MRAM SRAM memory FeRAM (90nm)

Readout method Non-destructive Non-destructive Non-destructive Destructive Non-destructive

Calkogenite Type
Material CoFe etc. Normal Tr (GeSb Te) PZT Type Si Type

Cell surface (F2 ) 30 120 20 40 27

Write Speed <10 nsec 5 nsec 100 nsec 50 nsec 30µ sec

Read Speed <10 nsec

<10 nsec 5 nsec 20 nsec 50 nsec 10 nm

E/W Cycle 1E16 ∞)

(no limitation)
1 E16( No limitation 1E12 1E8 to 1E12 1E3 to 1E5
No special Large capacity
高速
High-speed
Advantage structure required Simple Mid-speed
Unified memory configuration High-speed
ﾕﾆﾌｧｲﾄﾞﾒﾓﾘ High-speed
operation readout

Software errors Inflexible

Heat disturb scalability Long write time
Disadvantage Magnetic disturb Power dissipation Weak read Weak read/write Weak write
Large cell size endurance endurance endurance
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 High-speed read and writing Nonvolatile
- Unified Memory -
Memory Configuration Memory Configuration
(Existing product) (MRAM)
ROM Area Non-volatile Non-volatile
-Program memory memory
-Fixed data

RAM Area Volatile

-Stack memory
-Work data
1. RAM data disappears when the power 1. Data does not disappear when the
supply is turned off power supply is turned off
2. FLASH write speed is slower than RAM
RAM area is usable as ROM
2. High-speed read/write targeting
>100MHz operations
Advantage of MRAM: Flexible ratio of ROM/RAM areas
Memory A Memory B Memory C

ROM area

RAM area

10/07/2008 MRAM can satisfy various memory combination products!

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 Renesas Future Lineup
 Further exploit MCU market with RX Family by combining the merits of
H8S/H8SX(16-bit MCU) and M16C/R32C (32-bit MCU)
 R8C, RX and SH will cover the whole embedded MCU market
from 8-bit to 16-bit and to 32-bit

RX: Renesas eXtreme

New product realizing excellent
performance and usability

32bit RISC

4bit 8bit 16/32bit CISC

10/07/2008

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 Naming the New CPU

Next-generation CPU

RX Family

RX stands for “Renesas eXtreme” and

designates a product combining outstanding
performance and superb ease of use.

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 High-speed/High-performance CPU
- Realized high Code efficiency and High speed (MIPS/MHz) -

Conventional
CPU Target Design
Ratio

Improved basic performance

Max.
Max. Operating
Operating Frequency
Frequency (MHz)
(MHz) X
X 55 200MHz
200MHz

and code efficiency

Performance
Performance (MIPS/MHz)
(MIPS/MHz) X
X 22 1.25MIPS/MHz
1.25MIPS/MHz

Code
Code Efficiency
Efficiency Improved
Improved by
by 30%
30%

Low
Low Power
Power Consumption
Consumption 0.03mA/MHz
1/3
1/3 0.03mA/MHz
(CPU
(CPU current
current mA/MHz)
mA/MHz)
High
High Integration
Integration X
X 44 4MB
4MB
(Max.
(Max. Capacity
Capacity of
of Flash
Flash Memory)
Memory)

10/07/2008

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 The RX Concept

■ Overcome problems and meet market demand by developing a new CPU.

Even better
performance

Even better Even lower

code power
efficiency consumption

Even
higher Continuity
integration with earlier
(90 nm process) products

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 Back to Basic – System Requirement

System Requirement

Performance:
FAST & SMALL Code

System Core Design Compiler Peripheral Integration

Instruction set, Intelligence of converting

Addressing mode, high level C language into Core Assembly code
…

10/07/2008

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Features of RX CPU – Efforts to Improve Performance

1.
1.5-stage
5-stage pipeline
pipeline
2.
2.Harvard
Harvard architecture
architecture
3.
3.DSP
DSP arithmetic
arithmetic functions
functions
4.
4.Single-precision
Single-precision floating-point
floating-point unit
unit
5.
5.Instruction
Instruction Sets
Sets
6.
6.Addressing
Addressing Mode
Mode
-- 3x
3x Operands
Operands
7.
7.Register
Register Numbers
Numbers
8.
8.Interrupt
Interrupt
1. Performance

10/07/2008
2. Code efficiency
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 Product Evolution Based on MCU Development Platform

■ The RX family will include competitive products for many different fields.

Operating frequency
• 20 MHz to 200 MHz

Low power consumption

RX for office equipment • Low-leakage process for reduced current consumption
• Precise power control for reduced power consumption
during standby
On-chip peripheral functions
• Continuation of peripheral functions from earlier
MCU products
RX for consumer products
development • Addition of new peripheral functions offering more
platform flexibility
• ASSP functions (Ethernet, USB, CAN, LIN, FlexRay, etc.)

RX for industrial Many on-chip flash memory configurations

applications • High reliability and fast access
• Capacities from 128 KB to 4 MB

Many package configurations

RX for automotive field • LQFP packages with low to high pin counts
• Lineup of smaller and higher density LGA and FBGA
packages
10/07/2008

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 Features of MCU Development Platform
Ability to develop products with optimal combinations of memory configuration, peripheral
functions, low power consumption technology, and improved flexibility
Improved design efficiency for faster development and easier rollout of new product versions

MCU development platform (90 nm process)

Many memory configurations
Flash (up to 4 MB), RAM (up to 256 KB) ＣＰＵ
RX for office
equipment
Technologies for reduced power consumption Existing
• Multi-threshold H8SX/H8S functions
• Clock gating R32C/M16C functions Simul- RX for consumer
taneous
• Power gating products
• Power-down (low-power) modes Timer functions develop-
• Low-voltage operation ment of
Analog functions
• Subclock oscillator multiple RX for industrial
Communication, etc. products applications
Technology to boost flexibility
New functions
• Power-on reset RX for automotive
• Low-voltage detection Timer functions field
• High-speed/low-speed on-chip oscillator Analog functions
• Peripheral I/O mapping controller
• Event link controller Communication, etc.
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 Overview of MCU/MPU

10/07/2008

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 Basic Classification of MCU

MCU (Tiny)

MCU (Big)
with external memory access

MPU

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 SH1-4

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 H8/ H8300H/ H8S/ H8SX

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 H8300 / H8300L / H8300H / H8S2000

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 SLP (300L /300H/ H8S)

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 R8C /M16C /M32C /R32C

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 M16C
/ M32C
/ R32C

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 R8C

10/07/2008

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