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This Study Resource Was: Chapter No 2 The Microprocessor

This document contains questions and answers about microprocessor registers, memory addressing modes, and descriptor tables. Some key points: - Program-visible registers are used directly in instructions and include registers like EAX, EBX, ECX, etc. Segment registers address memory locations in real mode. - Protected mode uses descriptor tables and segment selector registers to access memory locations beyond the first 16MB. Descriptors define base addresses, limits, and access privileges. - Memory addressing combines a segment register and offset to calculate a physical memory address. Real and protected modes use different addressing schemes. - Questions cover details of common microprocessors like functions of registers, flag bits, memory mapping, and descriptor fields.

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0% found this document useful (0 votes)
762 views4 pages

This Study Resource Was: Chapter No 2 The Microprocessor

This document contains questions and answers about microprocessor registers, memory addressing modes, and descriptor tables. Some key points: - Program-visible registers are used directly in instructions and include registers like EAX, EBX, ECX, etc. Segment registers address memory locations in real mode. - Protected mode uses descriptor tables and segment selector registers to access memory locations beyond the first 16MB. Descriptors define base addresses, limits, and access privileges. - Memory addressing combines a segment register and offset to calculate a physical memory address. Real and protected modes use different addressing schemes. - Questions cover details of common microprocessors like functions of registers, flag bits, memory mapping, and descriptor fields.

Uploaded by

vanshik
Copyright
© © All Rights Reserved
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CHAPTER NO 2

THE MICROPROCESSOR

Question & Answers


1. What are program-visible registers?
A. Program visible register are the registers that are directly used in an instruction
2. The 80286 addresses registers that are 8 and _________ bits wide.
A. 16
3. The extended registers are addressable by which microprocessors?
A. The 80386 through the Core2
4. The extended BX register is addressed as _________.
A. EBX
5. Which register holds a count for some instructions?
A. CL, CX, ECX, or RCX
6. What is the purpose of the IP/EIP register?
A. Holds the offset address of the next step in the
program.
7. The carry flag bit is not modified by which arithmetic operations?
A. INC and DEC

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8. Will an overflow occur if a signed FFH is added to a signed 01H?

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A. No, if you add +1 and –1 you have zero, which is a

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valid number.

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9. A number that contains 3 one bits is said to have _________ parity.
A. Odd

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10. Which flag bit controls the INTR pin on the microprocessor?
A. The I-flag. rs e
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11. Which microprocessors contain an FS segment register?
A. The 80386 through the Core2
12. What is the purpose of a segment register in the real mode operation of the
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microprocessor? A. The segment register addresses the lowest


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address in
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a 64K memory segment.


13. In the real mode, show the starting and ending addresses of each segment located by
the following segment register values:
(a) 1000H
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(b) 1234H
(c) 2300H
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(d) E000H
(e) AB00H
A. (a) 10000H—1FFFFH (b) 12340H—2233FH (c) 23000H—32FFFH (d) E0000H—
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EFFFFH (e) AB000H—BAFFFH


14. Find the memory address of the next instruction executed by the microprocessor, when
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operated in the real mode, for the following CS:IP combinations:


(a) CS = 1A00H and IP = B000H
(b) CS = 2300H and IP = 1A00H
(c) CS = 2000H and IP = 1000H
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(d) CS = 1000H and IP = 2000H


(e) CS = 3456H and IP = ABCDH
A. (a) 12000H (b) 21000H (c) 24A00H (d) 25000H
(e) 3F12DH
15. Real mode memory addresses allow access to memory below which memory address?

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CHAPTER NO 2
THE MICROPROCESSOR

A. 100000H

16. Which register or registers are used as an offset address for the string instruction
destination
in the microprocessor?
A. DI
17. Which 32-bit register or registers are used to hold an offset address for data segment
data in
the Pentium 4 microprocessor?
A. EAX, EBX, ECX, EDX, EBP, ESI, and EDI
18. The stack memory is addressed by a combination of the _________ segment plus
_________ offset.
A. SS plus either SP or ESP
19. If the base pointer (BP) addresses memory, the _________ segment contains the data.
A. Stack
20. Determine the memory location addressed by the following real mode 80286 register

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combinations:

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(a) DS = 1000H and DI = 2000H

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(b) DS = 2000H and SI = 1002H

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(c) DS = A000H and BX = 1000H
(d) SS = 2300H and BP = 3200H

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(e) SS = 2900H and SP = 3A00H
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A. (a) 12000H (b) 21002H (c) A1000H (d) 26200H
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(e) 2CA00H
21. Determine the memory location addressed by the following real mode Core2 register
combinations:
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(a) SS = 8000H and ESP = 00009000H


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(b) DS = C000H and ESI = 0000A000H


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(c) DS = 1A00H and ECX = 00002000H


(d) DS = 2000H and EAX = 00003000H
(e) DS = 1239H and EDX = 0000A900H
A. (a) 23000H (b) 1C000H (c) CA000H (d) 89000H (e) 1CC90H
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22. Protected mode memory addressing allows access to which area of the memory in the
80286
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microprocessor?
A. All 16M bytes
23. Protected mode memory addressing allows access to which area of the memory in the
Pentium 4 microprocessor?
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A. Any location in the memory system


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24. What is the purpose of the segment register in protected mode memory addressing?
A. The segment register is a selector that selects the
descriptor from a descriptor table. It also sets privilege level of the request and chooses
either the global
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or local table.
25. How many descriptors are accessible in the global descriptor table in the protected
mode? A. 8,192
26. For an 80286 descriptor that contains a base address of A00000H and a limit of 1000H,
what
starting and ending locations are addressed by this descriptor?
A. A00000H–A01000H

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CHAPTER NO 2
THE MICROPROCESSOR
27. For a Core2 descriptor that contains a base address of 01000000H, a limit of 0FFFFH,
and
, what starting and ending locations are addressed by this descriptor?
A. 01000000H—0100FFFFH
28. For a Core2 descriptor that contains a base address of 00280000H, a limit of 00010H,
and
G = 1, what starting and ending locations are addressed by this descriptor?

G=0
DS = 1239H and EDX = 0000A900H
SS = 8000H and ESP = 00009000H
DS = C000H and ESI = 0000A000H
DS = 1A00H and ECX = 00002000H
DS = 2000H and EAX = 00003000H
SS = 2900H and SP = 3A00H
DS = A000H and BX = 1000H
SS = 2300H and BP = 3200H

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DS = 2000H and SI = 1002H

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DS = 1000H and DI = 2000H

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CS = 3456H and IP = ABCDH

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CS = 1A00H and IP = B000H
CS = 2300H and IP = 1A00H

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CS = 2000H and IP = 1000H
CS = 1000H and IP = 2000H rs e
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A. 00280000H–00290FFFH
29. If the DS register contains 0020H in a protected mode system, which global descriptor
table
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entry is accessed?
A. 4
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30. If in a protected mode system, the requested privilege level is _________.


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A. 3
31. If in a protected mode system, which entry, table, and requested privilege
level are selected?
A. Descriptor 20H, local table, a privilege ring 1
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32. What is the maximum length of the global descriptor table in the Pentium 4
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microprocessor? A. 64K
33. Code a descriptor that describes a memory segment that begins at location 210000H
and
ends at location 21001FH. This memory segment is a code segment that can be read. The
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descriptor is for an 80286 microprocessor.


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A. ------------
34. Code a descriptor that describes a memory segment that begins at location 03000000H
and
ends at location 05FFFFFFH. This memory segment is a data segment that grows upward in
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the memory system and can be written. The descriptor is for a Pentium 4 microprocessor
A. 0000 0011 1101 0000
1001 0010 0000 0000
0000 0000 0000 0000
0010 1111 1111 1111
35. Which register locates the global descriptor table?
A. GDTR

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CHAPTER NO 2
THE MICROPROCESSOR
36. How is the local descriptor table addressed in the memory system?
A. Through a descriptor stored in the global table
37. Describe what happens when a new number is loaded into a segment register when the
microprocessor is operated in the protected mode.
A. The internal cache is loaded with the base address, offset address, and access
rights byte
38. What are the program-invisible registers?
A. The program invisible registers are the cache portions
of the segment registers and also the GDTR, LDTR,
and IDTR registers.
39. What is the purpose of the GDTR?
A. The GDTR address the Global Descriptor Table
40. How many bytes are found in a memory page?
A. 4K

41. What register is used to enable the paging mechanism in the 80386, 80486, Pentium,

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Pentium Pro, Pentium 4, and Core2 microprocessors?

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A. 4,096

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42. How many 32-bit addresses are stored in the page directory?

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A. 1024
43. Each entry in the page directory translates how much linear memory into physical

o.
memory? A. 4M
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44. If the microprocessor sends linear address 00200000H to the paging mechanism, which
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paging directory entry is accessed, and which page table entry is accessed?
A. Entry zero or the first entry
45. What value is placed in the page table to redirect linear address 20000000H to physical
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address 30000000H?
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A. 30000000H
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46. What is the purpose of the TLB located within the Pentium class microprocessor?
A. The TLB caches the most recent memory accesses
through the paging mechanism.
47. Using the Internet, write a short report that details the TLB. Hint: You might want to go to
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the Intel Web site and search for information.


A.
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48. Locate articles about paging on the Internet and write a report detailing how paging is
used
in a variety of systems
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49. What is the flat mode memory system?


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A. The flat mode memory system is used with 64-bit operation of the Core2
50. A flat mode memory system in the current version of the 64-bit Pentium 4 and Core2
allow
these microprocessors to access _________ bytes of memory.
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A. 1T

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