Online Instructor’s Manual to accompany Intel Microprocessors Eighth Edition Barry B. Brey ate Upper Saddle River, New Jersey Columbus, Ohioprotected by United States copyright laws and is provided solely for the use of instructors in teaching their courses and assessing student learning. Dissemination or sale of any part of this work (includ- ing on the World Wide Web) will destroy the integrity of the work and isnot permitted. The work and materials from it should never be made available to students except by instructors using the accom- panying text in their classes. All recipients of this work are expected to abide by these restrictions and to honor the intended pedagogical pur- poses and the needs of other instructors who rely on these materials. Copyright © 2009 by Pearson Education, Inc., Upper Saddle River, New Jersey 07458. Pearson Prentice Hall. All rights reserved. Printed in the United States of America. This publication is protected by Copyright and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. For information regarding permission(s), write to: Rights and Permissions Department. Pearson Prentice Hall™ is a trademark of Pearson Education, Inc. Pearson® is a registered trademark of Pearson ple Prentice Hall* is a registered trademark of Pearson Edueation, Ine. Instructors of classes using Barry B. Brey’s, The Jntel Microprocessors, may reproduce ‘material from the instructor's manual for classroom usePreface This is the eighth edition of this text and since its inception there have been many changes in the coverage, The Intel architecture and the personal computer have proved to be resilient and ever improving technology with no end in sight. Over the years there have been many attempts at displacing this technology, but none have succeeded. What may uot have been understood is that the hardware is relatively inexpensive, especially today, and software continues to become more expensive, Whether this is the best teclmology is a moot point. The software has caused it to survive and thrive and as time passes the assaults become fewer and weaker. The Intel architecture has truly become the standard to master. tn the beginning of this architecture we had a relatively primitive machine (8086/8088) that has evolved into a very powerfull machine (Pentium Core2 with two cores). What the future holds is parallel processing (an 80 core version has been demoustrated by Intel) ‘and somewhat higher clock frequencies and applications that communicate through light waves in place of wires. Even though I write of this wonderful technology 1 sometimes doubt my sanity since I first learned digital technology using vacuum tubes. T recall building my first decade counter using four dual tiode vacuum tubes for the flip-flops, neon lamps as indicators, and @ power supply voltage of 200 volts, I recall when the 7400 NAND gate first appeared for $19.95. I was amazed when the Intel 4004 appeared in 1971, a year after I started teaching digital electronics and computers. If you are relatively young, can you imagine what you will see in your lifetime in this incredible field? T thank each and every one of you for your continued support. If you have any comments or suggestions, please do not hesitate to write because I do answer all my e-mail. ‘You might also enjoy visiting my website at if Vv The publisher also has a set PowerPoint slides for this text for instructors only. If you need them contact your representative.Chapter One . Charles Babbage Herman Hollerith, 5. To decode the Enigma code during World Was II . Intel Corporation . Grace Hopper 8080 8086/8088 5. 4G bytes 1995 80486 through the Core? ‘Complex Instruction Set Computer 3. 1024 1024 1,000,000 2G or 3G for 32-bit mode and currently 8G for 64-bit mode 1G Currently 1T byte using a 40-bit address Protected memory or extended memory An early operating system called the Disk Operating System Video Electronies Standards Association Universal Serial Bus 3. Extended Memory System System Area 47. The BIOS controls the computer at its most basic level and provides for compatibility between computers. 49. The microprocessor is the controlling element in a computer system, 51. Address bus 53. The 1/0 read signal causes an 1/O device to be read. 55. (a) defines a byte or bytes of memory (b) defines a quadword or quadwords of memory (c) defines a word or words of memory (a) defines a doubleword or doublewords of memory 57. (a) 13.25 (b) 57.1875 (6) 43.3125 (A) 7.0625 59. (a) 163.1875 (b) 297.75 (c) 172.859375 (d) 401.1875 (e) 3000.05078125 61. (a) 0.101 0.5 0.A (b)0.0000101 0.024 0.0 (c) 0.10100001 0.502 0.A1 (0.11 06 OC (01111 0.74 OF 63. (a) C2 (b) FD (©) BC (a) 10 (e) SBA 68. (a) 0111 1111 (b) 0101 0100 (¢) 0101 0001 (a) 1000 0000 67. (a) 4G 52 4F 47, (b) 41 72 63, (¢) 57 61 74 65 72, and (d) 57 65 6C 6C 69. The Unicode is the 16-bit alphanumeric code used with Windows 71. (a) 0010 0000 (b) 1111 0100 (c) 0110 0100 (4) 1010 0100 73, DB -3475. (a) (b) © 12 Al Bl 34 00 77. DW 1234H 79. (a) -128 (b) 51 (&)-110 (@)-118 81. (a) 0 O1111111 10000000000000000000000 (b) 1 10000010 01010100000000000000000 (c) 0 10000101 10010001000000000000000 (d) L_ 10001001 00101100000000000000000 Chapter Two Program visible register are the registers that are directly used in an instruction, The 80386 through the Core2 CL, CX, ECX, or RCX INC and DEC Odd 11. The 80386 through the Core2 13. (a) 10000H—1FFFFH (b) 12340H—2233FH (c) 23000H—32FFFH (d) E0000H—EFFFFH (e) ABOO0H—BAFFFH 15. 1000008 17. EAX. EBX, ECX. EDX, EBP, ESI, aud EDI 19. Stack 21. (a) 23000H (b) 1COOOH (c) CADOOH (d) 89000 (e) 1CC9OH 23. Any location in the memory system 25, 8,192 27. 01000000H—0100FFFFH 29.4 31, Deseriptor 20H, local table, a privilege ring 1 33. GDIR 37. The intemal cache is loaded with the base address, offset address, and access rights byte 39. The GDTR address the Global Descriptor Table 414.096 43.4M 45, 300000001 49. The flat mode memory system is used with 64-bit operation of the Core2Chapter Three 1. (@) the contents of BX is copied into AX (b) The coutents of AX are copied into BX (c) the contents of CH are copied into BL (4) the contents of EBP are copied into ESP (e) the contents of RCX are copied into RAX 3. AX, BX, CX, DX, SP, BP, SI, DI, CS, DS, ES, $5, FS, and GS 5. RAX. RBX, RCX, RDX. RSP, RBP, RSI, RDI and R8—R1S 7. The register sizes must be equal, 16-bit cannot be fit into 8-bits 9. (a) MOV EDX.EBX (b) MOV CL.BL (c) MOV BX.SI (d) MOV AX.DS. (©) MOV AH,AL (f) MOV RIO.RS Lt 13, CODE 15. Opcode 17. Itends the program by exiting to the operating system 19. The STARTUP directive loads the DS register 21. Inditect addressing 23. Memory to memory transfers are not allowed with the MOV instruction 25. INC WORD PTR [EDI] 27. DEC QWORD PTR [RAX] 29. (a) 21110H (b) 10100H (c) 21000 31. (a) 12100H (b) 12350H (c) 12220H 33. (a) 11750H (b) 11950H (e) 11700H 35. (a) 15700H (b) 05100H (c) 07100H 39. 5, the first byte is the opcode, followed by a two byte segment address, followed by a two byte offset address 41, 232K 43, A far jump always a jump to any location in the memory map 45. (a) short (b) near (c) short (d) far 47. IMP NEAR 49, PUSH [DI] places the 16-bit contents of the location addressed by DS and DI onto the stack. 51. Places the 32-bit contents of he register array onto the stack 53. no Chapter Four 1. Opcode 3. The MOD field specifies the type of access for the R/M field and the size of the displacement. 5. If operated in the 16-bit mode, a register-size and/or address-size prefix is used to specify a 32-bit register. 7. (a) SS (b) DS (¢) DS (4) SS (e) DS 9. MOV BX[BP+4COOH] 11, 67 66 8B 30 13. The contents of CS will change causing an unpredictable jump 15.3217.¢8 19. EAX, EBX, ECX, EDX, ESP, EBP, EDI and EST 21. The BH register is moved to memory location 020FFH and the BL register is moved to location 020FEH then SP is changed to 0OFEH. 23.2 25, The MOV DLNUMB instruction copies the 16-bit number in the data segment location NUMB into DI while the LEA DLNUMB loads DI with the offset address of location NUMB. 27. The MOV with the OFFSET directive 29. LDS loads DS and LSS loads SS along with another 16-bti register for the offset address 1. If the direction flag is cleared it selects auto-increment for the string instructions and if the direction flag is set is selects anto-decrement. 3. MOVS 35. A 4-bit number is loaded into RAZ from the data segment memory location addressed by ESI and then EST is either incremented or decrement by 8 depending on the setting of the direction flag. 37. The STOSW instruction copies AX into the extra segment memory location addressed by DI then DI is either incremented or decremented by two as dictated by the direction flag 39. The REP prefix repeats a string instruction CX number of times 41. DX register 43. TABLE DB 30H, 318, 32H, 398 DE 34H, 35H, 36H, 37H, 36x, 39H CD2A PROC NEAR Mov BX, OFFSET TABLE ERT Er BCD2A ENDP 45. IN AL, 12H copies the byte fiom 1/0 device 12H into AL 47. The segment override prefix allows the default segment to be changed to any segment 49. XCHG AX, BX XeHG Eek, EDX xcHe Sr, Dr SL. DX is copied into CX if a not zero or not equal condition exists. 53 1asti DB 30 dup(?) 55, The .686 directive informs the assembler that a Pentium Pro or newer microprocessor is the target of the assembled program. 57. models 59. The program terminates and control is passed back to the operating system. 61. The uses directive specifies which registers are saved on the stack at the beginning of a procedure and popped at the end of the procedure. 63. If the model statement precedes the processor directive the code generated is 16- Dit.Chapter Five 1. @ ADDAXBX (b) ADD AL.12H (¢) ADDEBPEDI (@) ADD CX.22H (@) ADD AL{SI] (f) ADD FROGCX (g) ADD RCX.234H 3. No instruction is available to add to a segment register. mop aH aD app AH BE app AR co ADD AK DE Mov DH a 1, Mov EDT, ECK ADD EDI, EDX aD EDI, EST 9. ADC DX.BX 11, The instruction does not specify the size of the data addressed by BX and ean be comrected with a BYTE PTR, WORD PTR, DWORD PTR, or QWORD PTR 13. DL= 81H, $=1,Z=0,C=0,A-0,P=0,0=1 15. DEC EBX 17, Both instructions subtract, but compare doe not return the difference, it only changes the flag bits to reflect the difference 19. AH contains the most significant part of the result and AL contains the least significant part of the result. 21. EDX and EAX as a 64-bit product 23. IMUL is signed multiplication while MUL is unsigned. 25. AX 27.RAX 29. IDIV is seined division, while DIV is unsigned division, 3L.RAX 33. DAA and DAS 35. AAA, AAS, AAD, and AAM. 37 PUSH Ax Mov) AL RL aD> DAR nov ape DAR nov PoP abe DAR XCHS AK, apc AL.cH DAR XCHOAH,AL 39.(a) ANDBX.DX (b) AND DH.EAH (c) AND DLBP (@) ANDEAX,1122H (¢) AND [BP].CX (f) AND DX{SI-8] (g) AND WHAT,AL 41.@) ORAHBL (b) ORECX,88H (c) OR SI] ge 8 g BORER RR OB Be (@) OR BP,1122H(@) OR[RBX].RCX (f) OR AL,[BP+40] (g) OR WHEN.AH 43.(a) XOR AH.BH_ (b) XOR CL,99H _(c) XORDX.DI_(d) XOR RSP,1A23H (@) XOR[EBX].DX () XOR DL[BP+60] (g) XOR DIWELL 45. The only difference is that the logical product is lost after TEST. 47. NOT is one’s complement and NEG is two’s complement. 49. AL is compared with the byte contents of the extra segment memory location addressed by DL 51. The D flag selects whether SI/DI are incremented (D = 0) or decremented (D = 1). 53. An equal condition or if CX decrements to 0 55. Mov. DI, OFFSET LIST Mov cx, 3008 cD Mov AL, 668 ERNE ScasB Chapter Six 1. A short jump allows a program to branch forward 127 bytes or backwards 128 bytes from the next instruction’s address in the program. Far jump 22G . A label followed by a single colon is a short of near address and a double colon denotes a far address 9. The code segment register and the instruction address register LL. A IMP DI copies the contents of DI into the instruction address register and a IMP [DI] copies the 16-bit number fiom the data segment memory location addressed by DI into the instruction address register 13. Sign (S), Zero (Z), Carry (C), Overflow (0), and Parity (P) 15. A JO instruction jumps on an overflow condition 17. NZ, INE, JZ. JE, JB, BE, JA, JAE 19. Tests the contents of CX and jumps if it is zero 21.3 23.RCX 23. The LOPE instruction jumps is an equal condition exists and CX is uot a zero and it also decrements CX on each iteration of the loop. 27. SI,OFFSET BLOCK veo Doin, 0 cx, 1008 AL, 42H ua: 3 23 12 xe Dom oe 13 2: INC UP 13: Loop ia euBgSSSSS29. An infinite loop is created 31. A BREAK can be used to break out of a, WHILE construct. 33. The main difference between a near and a far call is the distance from the call and the type of call and return that assembles. 35, The near return retrieves the return address from the stack and places it into the instruction address register 37, PROC 30, The RET 6 deletes 6 bytes from the stack before returning from a procedure. 4 SUMS PROC NEAR Mov EDI,0 ADD EAK,EBX ic SUMAL Moy EDI)1 sumsi: aD EAK,ECK Nc suMs2 Mov EDI,1 sums2: ADD BAX, EDX ac SU Mov EDI,1 sums3: SUMS END 43. INT 45. An interrupt vector contains the offset address followed by the segment address in 4 bytes of memory 47. The IRETD instruction pops the flags, a 32-bit offset address, and the protected mode selector for the CS register. 49. The IRETQ instruction is used in the 64-bit mode to return from an interrupt service procedure $1. 100H—103H 53. WAIT 55. 16 57, ESC Chapter Seven 1. No, macro sequences and dot commands are not supported by the inline assembler. 3. Labels are defined in the inline assembler exactly as they are in the assembler 5. EAX 7. Dot commands are not usable in the inline assembler. 9. The program uses SI and SI is not saved by the inline assembler so it must be saved and restored using a PUSH and POP. 11 The main difference is that when using the 16-bit version a program should attempt to use only 8- and 16- bit registers, while when using the 32-bit version a program should attempt to use 8- and 32-bit registers 13. The conio header allows the putch() getche() functions to be used in a program.15, Embedded applications use different 1/O than the PC so the conio library would not be used in an embedded application. 17. The disp procedure divides by the number base and saves the remainders to generate a number in any number base. 19. The PUBLIC statement identifies a label as being available outside of the module 21. It defines that the Getlt function has a single integer passed to it and retums nothing. 23. A control is usually some visible object that is obtained from the tool box in most cases. 25. It is a 32-bit pointer. 27. Extemal procedures are defined using the extem prototype. 29. It uses a 32-bit (DWORD) number. 31 int RotateLert3 (int numer) ‘ Af ( ( number & 0120000000 ) ) 33, The green arrow is clicked in the development environment. 35. An ActiveX control is a control such as an edit box or textbox used to build a visual application. Chapter Eight Object Library EXTRN indicates that a label is outside of the current program module. Only the fimetion used fiom the library file are placed in a program. A macro sequence is a short list of instruction placed in a program when the macro is invoked, AL aD032_ wacro DD AK, Cx apc BX,DX ENDM B ADDLIST MACRO PARAL, PARAZ FUSE AX BUSH DI BUSH ST PUSH BX Mov BX,CFFSET PARAL Mov DI, PARAZ “REPEAT Mov AL, [DI] ADD AL, [BX]Mov [p11 ,AE INC Dr INC BX LUNTILcKZ BOP cx BOP BK BOP DI BOP AK ENDM 15, The include directive allows a file containing macros to be included in a program. 17. private: system: :Void textsox1_Keybown (system: :object” sender, system: :Windows: ‘Forme: ‘ J/ this is called first keyHandled = true: Reyeventargs* 0) AE (@->Keycode >= Keys: :umpadd && e->xeycode <= Keys: Reya!:D9 66 ‘e->KeyCode >= Keys! !DO && e->Keycode e->shift == false || e->KeyCode >= Keys::A G6 e->KeyCode <= Keys e->KeyCode == Keys! :Back) keyHandled = false; randont+; — // increment randomw number private: system: :Void textBoxt_KeyPress (system: ;object” system: :Windows: ‘Forms: :xeyPressEventargs” AE (@->MeyChar >= 'a! Ge e->KeyChar <= 'f') t e->ReyChar -= 32; ) AE (@->MeyChar >= ‘A! Ge e->KeyChar <= 'F') t e->Keychar += 327 ) else if (e->KeyChar == 13) t ant mumber = 0; for (int a= 0; { a < textBoxl->rext->iength: nrumpad® || Fil sender, e at) number = Converts (number, textBox1->text fal) : > textBox2->Text = Convert: :Tostring (number) : keyHandled = true; ) e->Handled = keyHandled; > 21, Refer to Table 8-2 23. The MouseEventsArg Clicks is a 2 for double click, 25. The Color class contains most common colors. 27. AAM 29. If Homer’s algorithm uses an 8 instead of a 10 the umber will octal, 31. 30H be converted to33. Subtract 30 from each digit, multiply the result (initial value of 0) by 10, add a digit, and continue this for all three digits. 35 char Gettt (char temp) t char tookupt] = (107,12 127,13,87,18", 16,177, ee a ee return lookup[ temp] ; > 37. The master file table contains descriptors that describe the location of the file or folder. 39. The boot record (track zero, sector zero) contains the bootstrap loader program. The bootstrap loader program loads the operating system from the disk into the system, 414K 43. Unicode 45.3 47. String" fileWame = "c:\\resti.txt"; array* Array = gonew array(512) ; try t Filestrean* fs = File: :opennead (filename) ; ts->Read (Array, 0, 512); Es-sClose(); ) catch (...) { MessageBox: :Show ("Disk ezzor") ; Application: :Exit(); > 49. The remove fiction removes a file or folder from the disk. Chapter Nine ‘The main differences are the data bus width and the 10/M signal. 1 @)5 ©@s These bits indicate the segment being addressed by the current instruction. The WAIT instruction waits for the TEST pin to become a logic zero. 9. Maximum mode LL Never 13. During a HOLD, the microprocessor stops processing instructions and places the address, data, and coutrols buses at the high-impedance state. 15. The LOCK pin becomes a logic zero during instructions that pre prefixed with the LOCK: prefix. 17. The clock signal is provided, the RESET input is synchronized, and the READY input is synchronized 1019. EFT input 21. zero 23, Address/Data bus 25. The BHE signal is shared with a status bit ($7). 27. DT/R 29.1.0 us 31.2.5 MIPS 33, 600 ns ~ 110 ns ~ 30 ns = 460 us 35.0 37.0 39, It generates system control signals Chapter Ten 1. All memory devices have address, data, and control connections. 3. (a) 2048 four bit mumbers (b) 1024 one bit numbers (c) 4096 eight bit numbers (a) 16,384 one bit numbers. (e) 65,536 four bit numbers, 5. It causes the memory device to read data from a location. 7.(a) IK (b)2K (c)4K (d) 8K (e) 128K 9. Flash memory requires an extended amount of time to accomplish an erase and write. 11. The G input cause a read, the W input causes a write, and the § input selects the chip. 13. Dynami random access memory. 15. These inputs strobe the column and row addresses into a DRAM. 17. Memory rarely fills the entire memory, which requires some form of decoder to select the memory device for a specific range of memory addresses. al19, So Fs SPEEEFERI 23. The 748139 is a dual 2-to-4 line decoder 25. and or nand nor not 27. begin ROM <= AL9 or (not AlS) or ALT or MIO; RAM <= ALG and AL? and (not MIO); BH19 <= not ALS; end vi:33. Single bit error flag 35. The main differences are the data bus size and the /O, memory control signal, 37. Bank low enable has replaced the AO pin. 39. Upper memory bank 41. It does not matter if 16-bit or §-bit are read because the microprocessor just ignores any data bus bits that are not needed. 43 B47. A.cycle that does not read data, it only refreshes a row of memory. 49. 15.625 jis Chapter Eleven 1. The IN instruction inputs data fiom an extemal device into the accumulator and the OUT instruction sends data out to an external device from the accumulator 3. DX 5. AX 7. The INSW inputs data fiom the LO port addressed by DX, as a word, into the extra segment memory location addressed by DI; it then increments DI by 2 9. The basic input interface is a three-state buffer that is enabled for the IN instruction. When the buffer is enabled data is gated onto the data bus and into the accumulator. 11. Handshaking is the act of synchronizing two systems that operate asynchronously. 13. D8-DI5 15 cr7. 19, FEEFED EEF 2 Library ieee; use ieee. std logic 116¢,all; entity DECODER_21 is port ( AIS, Ald, AL3, Al2, All, A10, A9, AB, AT, AG, AS, Ad, A3, 22, Al: in ‘TD _zosrc; 1000, $1002, 51004, $1006, si008, S100A, 5100, S100: out sTD>_LoGTC de end; architecture Vi of DECODER 21 is begin $1000 <= AIS or Aié or A13 or (not Ai2) or Ail or ALO oF A1L 15or ALO or AS or AS or AT or AS or AS or Ad or A oF AZ oF Al; $1002 <= Ai5 or Ald or A13 or (not Ai2) or All or ALO or All ‘or ALO or A9 or AG or AT or AS or AS or A or A3 or AZ or (not Al); AIS or Ald or A13 or (not Ai2) or ALL or ALO or AIL or AiO or AO or AG or AT oF AS or AS or Ad or AS or (not A2) or Al; 51006 <= AIS or Alé or A13 or (not Ai2) or All or ALO or AIL or ALO or A9 or AB or AT or AS or AS or Ad or A3 or (not AZ) or (not At); AIS or ALé or A13 of (not Al2) or All or AlO or AlL ‘ox ALO or A9 or AG or AT or AS or AS oF A oF (not A3) oF AZ or AL; Si00A <= AIS or Ald or A13 or (not Ai2) or All or ALO or AIL er Al0 or A9 or AS or AT or AS or AS or Ad oF (not AS) or AZ or (not Al); 100¢ <= AIS or Alé or A13 or (not Ai2) or All or ALO or AIL er AiO or AO or AG or AT oF AS or AS or Ad oF (not A3) or (not A2) or Al; S1O0E <= AIS or Alé or A13 or (not Ai2) or All or ALO or AIL or ALO or A9 or AG or AT or AS or AS or Ad or (not A3) or (not AZ) or (not At); sio04 s1008 end vi: 23 Library ieee; use iece.std logic 1166.a11; entity DECODER 23 is port ( BHE, ALS, Ald, A13, AL2, All, ALO, A9, AG, AT, AG, AS, Ad, A3, A2, Al: in ‘stp _Locrc? 30D, 83008, 51005, $1007: out s7>_LoGrc de end; architecture V1 of DECODER 23 is begin 83000 <= AIS or Alé or (not AL3) or (not A12) oF Ali or ALO or ALL or ALO or A or AG or AT or A or AS or Ad or (not A3) ex (not A2) or Al or BRE: = AIS of Alé or (not Al3) oF (not Al2) or All or AlO or All ‘ox ALO or A9 or AG or AT oF AS or AS or AG oF (not A3) or AZ or (not Al) or BEE; 1005 <= Ai5 or Ald or A13 or (not Ai2) or All or ALO or AIL er Al0 or A9 or AS or AT or AS or AS or Ad or AS or (not AZ) or Ai or BRE; AIS or Ald or A13 or (not Ai2) or All or ALO or AIL or AiO or AO or AG or AT or AS or AS or Ad oF AS or (not A2) er (not Al) or BEE; 3008 1007 end vi; 25. D0-D7 27.24 1629. AO and Al 3h. Library tee; use iece.std_logic 1166.al. entity DECODER 31 is BLE, AIS, Ald, A13, AZ, All, AlO, AS, Af in stp ‘Losrc; cs: out sm _xeare AT, RG, AS, Ad, AB: de end; architecture VI of DECODER 31 is begin cS <= AIS or Ald oF AI3 oF Al2 oF All or AIO or (not A9) oF (not AS) for (not A?) of A6 or AS or Ad or A3 or BLE end vi: 33. Modes 0, 1, and 2 35. DELAY PROC NEAR 7Mov_Ecx, 479904 “REPEAT UNTIL BCX rer DELAY ENDP 37. The 4-coil stepper is moved by activating (passing current through) a single coil at a time in round-robin fashion to move the armature a step at a time. 39. im aL, porte oR an, 80H our PoRTA, AL 41. The ACK signal is used by the 1/0 device to inform the 8255 that the output data has been processed by the output device. 43. IN AL, PORTC Br ALA 32 TF zero 43. PCO, PCL, aud PC2 47. A display position is select by sending a command that contains the 7-bit address with the 8% and most significant bit set 49. A read command is issued and the leftmost bit of the data read from the LCD display is the BUSY bit. S51. 10-20 ms. 53. 10 MHz Library ieee; use iece.std logic 1166.a11; 18,entity DECODER_55 is port ( BLE, AT, AS, AS, A¢, AB: in STD_LoGTC; cs: out sto’ zoste dM fend; architecture V1 of DECODER 55 12 begin 5 < AT or AS oF AS or (not AS) oF A3 or BLE end vi; 57.300 59, The counter is latched then the counter read-back control reads the counter at the time of the latching 61. The motor attempts to move forward and reverse for equal amounts of time. This causes it to remain stationary. 63. The mumber of transmitted bits per second including data, start, stop and any other bits that are transferred. 65. 614,400 Hz 67. The MR input pin resets the device. 69.1.0 ws 73. 100 us 75, Start conversion Chapter Twelve An interrupt interrupts the currently executing program. The interrupt service procedure is called by an interrupt. 5. NMI, INTR, and INTA 7. The interrupt vector is the address of the interrupt service procedure. 9. 256 11, INT 0 occurs for a divide error. 13. A real mode interrupt vector is 4 bytes in length and contains the segment and offset address of the interrupt service procedure, while a protected mode interrupt vector is 8 bytes in length and contains the selector and 32-bit offset address of the interrupt service procedure 15. The BOUND instruction tests the contents of a 16-bit register with two numbers stored in the memory. If the register contains a number that is outside of the boundaries set by the memory data, INT 5 occurs. 17. INT 44H is stored at vector locations 110H-113H. 1919. INT 7 is used to emulate a coprocessor. 21. The T flag controls whether the INTR pin si enabled or disabled. 23. CLI aud STI clear and set the intenupt flag. 25. INT2 27. Level 29. Vector 31 33. The pull-ups force the inputs of the data bus to FFH when the interrupt acknowledge cycle executes. 35. Since the signals are ORed together to generate the intermupt, the only way to determine which device caused the interrupt is to ask (poll) the devices, 37.9 39. The CAS pins are used to cascade the 8259. 41. The ICW is the initialization control word. 433 45. LTIM in ICWL 47. The nonspecific end of interrupt is used to clear the most recent interrupt request. 49. The interrupt request register can be used to determine the levels found on the interrupt inputs. 51. INT 70H through INT 77H Chapter Thirteen 1. HOLD and HLDA 3. Memory to VO 5. A0-A7 and DO-D7 (where address bits AS—15 appear), 7. A memory-to-memory DMA transfer occurs when one channel addresses the source address and another channel address a destination address. Data are then ‘transferred from source to destination. 9. The DMA controller is in its hold state and the microprocessor operates normally 11, 2002H and 20034 2013. 64K 17. Miero 19. Sectors 21. NRZ recording is used because it erases old data when it records new data. 25. The disk heads must be parked over a landing zone when power is removed so the heads do not damage the surface of the disk. 27. A wtite once optical disk such as a CD-R or DVD-R. 29. 4.7G bytes 31. Red, green, and blue 33. The smallest video picture element 35. By using 2 levels of brightness for each of the three primary colors 37. Because the analog signal are continuously variable an infinite number of colors are possible. 39.540 Chapter Fourteen 1. Integer, BCD, and floating-point 3. ABCD number is stored in 10 bytes of memory with 9 bytes containing the BCD integer magnitude as packed BCD and the 10* byte containing only the sign of the number. 5. (a) 0 10000011 1100110000000000000000 (b)0 10001000 0011100000000000000000 (©) 1 11111110 0100000000000000000000 (d) 0 00000000 0000000000000000000000 (e) 1 10001000 1111010001000000000000 7. The coprocessor may be idle or it may execute a coprocessor instruction at the same time. 9. These bits indicate the relative size of a number after a test or compare instruction as well as if the number is valid or invalid. 11 An error bit 13, By programming the rounding control bits in the coprocessor control register 15, FFF8H-FFFFH 17. ANAN (not a number) is a number with an exponent of all ones and a significand not equal to zero, 19. Truncate 21. ESC 23.(a) FROG DQ 23.44 (b) DATA3 DD -123 (c) DATAL DD -23.8 (@) DATA2 DQ ? 25. An integer is loaded from memory location DATA to the top of the stack. 27. FADD (no operands) pops the top two stack elements and adds them then retmums the sum (pushes) to the top of the stack, 29. It stores the BCD version of the top of the stack into memory location DATA hen it pops the stack. 2131. The FCOMI instruction replaces the FCOM, FSTSW AX, and SAHF instructions. 3. Usually an FCOMI instruction nmust appear before an FCMOV. 35, PIST compares ST against zero, while FXAM changes the status flags to indicate the type of number at ST (positive, negative, a NAN, etc.). 37.1E 39. FLDI 41. FSTENV 43. AREA PROC NEAR mD OL AOL OW FOr A RED AREA ENDP 45. RooT PROC NEAR Mov EC, 9) MOV _EBX,OFFSET ROOTS REPEAT Mov EAK,11 SUB EAK,ECK Mov TEMP, EAX ;TEMP is defined as DD FILD TEMP SRT STP DWORD PIR [EBX] ADD EBK, 4 Juwtrzcxz er ROOT ENDP 47. One does a wait the other does not. 49. cos cos Swe wor 53, nosi0 PROC NEAR Mov TEMP, EA FLD TEMP FLDPT FADD ST,S7(0) Drv cos SPD TEMP MOV. EAX, TEMP RED ENDE PROC NEAR Mov TEM, Ex FLDPT ELD TEMP MUL OTP TEMP Mov EBX, TEMP rer ENDP. PROC NEAR FIDL FXCH ST(2) PYL2x ILD TEN FIDLFXCH sT(1) FYLOx FIDL EDIVR mW BET uN Dw 10 55. The multimedia extension allows integer arithmetic and logic on umultiple data with a single instruction, 57. The MM registers use the coprocessor stack registers 59. Unsigned saturation is where the carry is dropped after the addition or borrow after a subtraction 61 Mov Eox, 64 [REPEAT EMOV MMO, QWORD PER ARRAY [ECK*8-8] PMULLW MMO,QRORD PTR ARRAY? [ECK*8-8] MOV QWORD PTR ARRAY3 [ECK*8-8+256] Junarzcx2 63. Streaming SIMD extensions 65.4 67. An octal word is a 128-bit wide number. Chapter Fifteen 1. Industry Standard Architecture 3._Itwas long ago, but today because of its relativel VO expansion. 5 low speed, it is only suited to 2313. On the first positive edge of the clock after FRAME goes low. 15. Plug and Play is where the computer polls the PCI cards in a system to determine what interrupts are required and also the type of the card. 17. Ifoperating in DOS, the BIOS is tested for PCT if an 0B101H is placed in AX followed by an INT LAH. If carry is set upon return PCT is not present. 19. Speed and data width 21. 378H-37FH 23.25 pins 29. NRZ 31. For many applications it has replaced the ISA and PCI bus. 33, Non-return to zero inverted Soe DLL 2437. ACK acknowledges the receipt of data and NAK does not acknowledge the receipt of data. 39.2 GBps Chapter Sixteen 1. The main differences are the internal timers, the chip selection unit, the additional interrupt inputs, aud in some models the serial communications ports aud the enhanced 4-chamnel DMA controller. 3. Leadless chip carrier (LCC) and pin grid array (PGA) 5. The main difference is that the EB version contains 10 chip selection pins anda pair of serial communications ports 4 9. Memory access time is the amount of time that the microprocessor allows the memory to look up data. If not enough time exists, wait states are inserted to allow additional time for access. 11, VO ports FFOOH-FFFFH 13. INT 12/INT 0CH 15. Master and slave modes ate available. 71 19. The EOI register is used to clear the interrupt from the microprocessor. If not, the interrupt will never occur again. 21. Times 0 and 1 23. If both compare registers are used one determines the length for the logie 0 output, and the other determines the length of the logic 1 output 25. The P bit selects the system clock as the input to the timer 27. The timer output pins are used to provide wither a single pulse or an output with a selectable logic 1 and logic 0 time. 29. Mov Ax,0 MoV Dx/OFESOH QUE Dx ax Mov Ax, 105 Mov Dx, OFFS2H Our Dx.AX Mov Ax, 0co0eH MoV Dx, OFES6H our Dx/ax Mov AX, 1F44H Mov Dx, OFFASE Dx,AX, 2 4L ‘AX, 20028 Dx, OFFEcH Dx, aX ‘AX, 300AH S988 25Mov Dx, OFFSEH OUR Dx,ax 43. 16M 45, 8086 47. Loads the segment limit 49. Multiple threads are handled by a scheduler that starts a new thread on each tick: of the scheduler. Chapter Seventeen 1. 4G 3._ The DX has a full 32 bit address bus, while the SX is a scaled down version with 24-bit address bus 5. 4 or 5 mA depending on the pin compared to the 8086 which has 2 mA on each output pin. 7. A hardware reset causes the address bus to start at memory location FFFFFFFOH. 9. A cache memory is a high-speed store of data and/or instructions. Because the ‘main memory is relatively slow, when data or instructions are accessed a second time, they are accessed from the cache at a high speed increasing system performance 11, 800000F 8H-800000FFH 13, 40MHz 15, CRO mainly selects protected mode and paging, CRI is reserved by Intel, CR2 contains the linear fault address for debugging, and CR3 contains the base address of the page directory 17. ave 2 or type 1 ‘19. Mov AX, CRO 21. ov Fs: (DT) RAK 23. Yes 25. Coprocessor not available intermupt 27. The double fault interrupt occurs when two interrupts occur simultaneously. 29. A descriptor describes a memory segment, or a gate 31. The TI bitin the selector is set to select the local descriptor table. 33. 8K 35. A segment descriptor defines a memory segment and a system descriptor defines a memory location for a call or interrupt or a task state segment 37. The TSS is address by the task register 39. The switeh occurs when a 0 is placed into the PE bit of CRO. 41. Where ever he programmer decides to place it as dictated by CR3. 43. The entry in the page table and entry that corresponds to address D0000000H contains a CO000000H. 45. The FLUSH input causes the internal cache to be erased. 47. The flags are almost identical except for the AC flag. 49. Even 51.16 2653. A cache write-through is when data are written into the cache and the DRAM at ‘the same time. Chapter Eighteen AG bytes 64 bits 66 MHz Addess parity 9. BRDY 11, If the instructions are not dependent then two can be executed simultaneously, one by each integer mit. 13, 5.8ns 15. The SMI input causes an interrupt to the system memory management interrupt at address 38000H unless changed to some other location in the first IM byte of memory. 17. The SMM is exited by using the RSM instruetion. 19. Modify the dump base address register at locations 3FEFSH-3FEFBH. 2L1 23. CRA 28. The TSC counts system clock pulses in a 64-bit counter located within the microprocessor. It can be used to time events by storing its value when the event begins and at the end of the event read TCS and subtract the stored number to obtain the count in clock pulses. 27. The bank enable signals are multiplexed with address (A1S—A8) information and anust be extracted fiom the addiess bus during the second clock eycle of a bus cyele. 29. PAE and PSE have been added to control the additional address bits (A32-A35) 31. Emror correction code Chapter Nineteen 1. 30K 3. The Level 2 cache operated at the bus speed (66 MHz) in the Pentium and at the microprocessor speed in the Pentium II 5.2 7. No, the Pentium Il is on a cartridge. 9. Used for serial messages between the Pentium IT and APIC LL. 66 MHz or 100 MHz 13. 72 bits 15. Version number and features have been added to CPUID. 277. Mov ECK, 175H Mov EDX, 0 Mov EAK,128 WRUSR, 19. SYSEXIT 21. Ring 0 23. FSAVE saves the state of the coprocessor and FXSAVE saves the state of the MMX unit. 25. SIMD extension SSE2 28