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Bài 1: thiết kế mạch giải mã 3 -8

This document contains descriptions of 8 digital circuit design problems/exercises involving common components like decoders, ALUs, comparators, counters, and LED displays. The circuits described include a 3-8 decoder, 4-bit ALU, 4-bit comparator, parity checker, Gray code counter, and LED patterns for running lights and Johnson counter.

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129 views7 pages

Bài 1: thiết kế mạch giải mã 3 -8

This document contains descriptions of 8 digital circuit design problems/exercises involving common components like decoders, ALUs, comparators, counters, and LED displays. The circuits described include a 3-8 decoder, 4-bit ALU, 4-bit comparator, parity checker, Gray code counter, and LED patterns for running lights and Johnson counter.

Uploaded by

Thắng Trần
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Bài 1 : thiết kế mạch giải mã 3 -8

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity GIAIMA3_8 is
port(
rst: in std_logic;
D : in STD_LOGIC_VECTOR(2 downto 0);
Q : out STD_LOGIC_VECTOR(7 downto 0)
);
end GIAIMA3_8;
architecture GIAIMA3_8 of GIAIMA3_8 is
begin
process (D)
begin
case D is
when "000"=>Q <="10000000";
when "001"=>Q <="01000000";
when "010"=>Q <="00100000";
when "011"=>Q <="00010000";
when "100"=>Q <="00001000";
when "101"=>Q <="00000100";
when "110"=>Q <="00000010";
when others=>Q <="00000001";

end case;
end process;
end GIAIMA3_8;

Bài 2: thiết kế bộ ALU 4 bít

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;

entity ALU_4BIT is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
sel1 : in STD_LOGIC_VECTOR;
sel2 : in STD_LOGIC_VECTOR;
Q : out STD_LOGIC_VECTOR(7 downto 0)
);
end ALU_4BIT;
architecture ALU_4BIT of ALU_4BIT is
function chuyen(x:in std_logic_vector(3 downto 0)) return integer is
variable n: integer;
begin

n:=conv_integer(x(3))*8+conv_integer(x(2))*4+conv_integer(x(1))*2+conv_in
teger(x(0));
return n;
END chuyen ;
begin
process(A,B,sel1,sel2)
variable sel:std_logic_vector (1 downto 0);
begin
sel:= sel1&sel2 ;
if sel="00" then
Q<= conv_std_logic_vector(chuyen(A)+chuyen(B),8);
elsif sel="01" then
Q<=conv_std_logic_vector(chuyen(A)-chuyen(B),8);
elsif sel="10" then
Q<=conv_std_logic_vector(chuyen(A)*chuyen(B),8);

else
Q<=A or B;

end if;
end process;
end ALU_4BIT;

bài 3: thiết kế bộ so sánh 2 số nhị phân 4 bít

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity bososanh2sonhiphan4bit is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
Q : out STD_LOGIC_VECTOR(2 downto 0)
);
end bososanh2sonhiphan4bit;
architecture bososanh2sonhiphan4bit of bososanh2sonhiphan4bit is
begin
process(A,B)
begin
if A(3)='1'and B(3)='0' then
Q<="100";
elsif A(3)='0'and B(3)='1' then
Q<="001";
else
Q<="010";

if A(2)='1'and B(2)='0' then


Q<="100";
elsif A(2)='0'and B(2)='1' then
Q<="001";
else
Q<="010";

if A(1)='1'and B(1)='0' then


Q<="100";
elsif A(1)='0'and B(1)='1' then
Q<="001";
else
Q<="010";

if A(0)='1'and B(0)='0' then


Q<="100";
elsif A(0)='0'and B(0)='1' then
Q<="001";
else
Q<="010";

end if;
end if;
end if;
end if;
end process;
end bososanh2sonhiphan4bit;

bài 4: thiết kế mạch tạo mã chẵn lẻ chuỗi nhị phận 7 bít


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity KIEMTRACHANLE is
port(
A : in STD_LOGIC_VECTOR(6 downto 0);
B : out STD_LOGIC_VECTOR(7 downto 0)
);
end KIEMTRACHANLE;
architecture KIEMTRACHANLE of KIEMTRACHANLE is
begin
process (A)
variable i: integer range 0 to 7;
variable dem: integer range 0 to 7;
begin
for i in 0 to 6 loop
if A(i)='1' then
dem:=dem+1;
end if;
B(i)<=A(i);
end loop;
if (dem mod 2)=0 then
B(7)<='0';
else
B(7)<='1';
end if;
end process;
end KIEMTRACHANLE;

Bài 5 : Bộ đếm theo mã Gray 4 bit hiển thị kết quả trên LED0>>>>LED3
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity demgray is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0)
);
end demgray;
architecture demgray of demgray is
begin
process(clk,rst)
variable x: integer range 0 to 15;
begin
if rst='1' then
Q<="0000";
elsif clk'event and clk='1' then
if x=15 then
x:=0 ;
else
x:=x+1;
end if;
end if;
case x is
when 0=> Q<="0000";
when 1=> Q<="0001";
when 2=> Q<="0011";
when 3=> Q<="0010";
when 4=> Q<="0110";
when 5=> Q<="0101";
when 6=> Q<="0111";
when 7=> Q<="0100";
when 8=> Q<="1100";
when 9=> Q<="1111";
when 10=> Q<="1101";
when 11=> Q<="1110";
when 12=> Q<="1010";
when 13=> Q<="1001";
when 14=> Q<="1011";
when 15=> Q<="1000";
when others =>Q<="ZZZZ";

end case;
end process;
end demgray;

Bài 6 : thiết kế mạch LED sáng lan sang 2 bên


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity sanglan2ben is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(7 downto 0)
);
end sanglan2ben;

architecture sanglan2ben of sanglan2ben is


begin
process(clk,rst)
variable x: integer range 0 to 4;
begin
if rst='0' then
x:=0;
else
if clk'event and clk='1' then
if x=4 then
x:=0;
else
x:=x+1;
end if;
end if;
end if;
case x is
when 0=>Q<= "00000000";
when 1=>Q<= "00011000";
when 2=>Q<= "00111100";
when 3=>Q<= "01111110";
when others=>Q<= "11111111";
end case;
end process;
end sanglan2ben;

Bài 7 thiết kế LED sáng lần lượt giống bài 6


Bài 8 thiết kế bộ đếm Jonhson giống bài đếm gray.

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