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DICD Multiple Choice Questions UNIT-1

This document contains multiple choice questions from various units related to digital integrated circuit design and semiconductor memories. There are questions related to CMOS inverter regions, NAND/NOR gate characteristics, dynamic and domino logic, memory types like RAM and ROM, and components of memory like sense amplifiers and decoders. The document tests knowledge of key concepts across digital circuits, logic design and memory systems.

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TARUN PRASAD
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130 views5 pages

DICD Multiple Choice Questions UNIT-1

This document contains multiple choice questions from various units related to digital integrated circuit design and semiconductor memories. There are questions related to CMOS inverter regions, NAND/NOR gate characteristics, dynamic and domino logic, memory types like RAM and ROM, and components of memory like sense amplifiers and decoders. The document tests knowledge of key concepts across digital circuits, logic design and memory systems.

Uploaded by

TARUN PRASAD
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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DICD Multiple Choice Questions

UNIT-1:

1. How many operating regions are present in cmos inverter?


a. 3
b. 4
c. 5
d. 1
2. when Vin=Vth nmos transistor is oprating in the__________region
a. SATURATION
3. when Vin= V IL NMOS is operating in the __region and PMOS is operating in the__region
a. saturation & linear
b. linear & saturation
c. both saturation
d. none
4. when Vin= V IH NMOS is operating in the __region and PMOS is operating in the__region
a. linear & saturation
b. saturation & linear
c. both saturation
d. none
5. What is the advantage of pseudo nmos logic
a. simple circuit
b. little area
c. introduce only small load
d. all the above
6. 12.if nmos is in cut off an pmos is in linear then inverter operates in region______
a. B
b. A
c. C
d. E
a)

7. How many conditions to consider to find Vol of NAND gate?


a) 1
b) 2
c) 3
d) 4

8. How many capacitive components are present in transient analysis of NAND gate
a) 9
b) 7
c) 6
d) 5

9.How many regions are present in the DC analysis of transmission gate?


a) 1
b) 3
c) 2
d) 4

10.How many transistors are required to implement y=(A(D+E)+BC)^ in NMOS only logic?
a) 4
b) 5
c) 6
d) 7

11.How many transistors are required to implement y=(A(D+E)+BC)^ in CMOS logic?


a) 7
b) 8
c) 9
d) 10

12. WHEN S=Vol R=Vol NAND BASED SR LATCH IS OPERATING IN______


a. HOLD
b. SET
c. RESET
d. NOT ALLOWED
13. WHEN S=Vol R=VoH NAND BASED SR LATCH IS OPERATING IN______
a. HOLD
b. SET
c. RESET
d. NOT ALLOWED
14. WHEN S=VoH R=VoL NAND BASED SR LATCH IS OPERATING IN______
a. HOLD
b. SET
c. RESET
d. NOT ALLOWED
15. WHEN S=VoH R=VoH NAND BASED SR LATCH IS OPERATING IN______
a. SET
b. RESET
c. HOLD
d. NOT ALLOWED
16. WHEN J=Vol K=VoH JK LATCH IS OPERATING IN______
a. RESET
b. SET
c. HOLD
d. TOGGLE
17. WHEN J=VoH K=VoL JK LATCH IS OPERATING IN______
a. SET
b. RESET
c. HOLD
d. TOGGLE
18. WHEN J=Vol K=Vol JK LATCH IS OPERATING IN______
a. HOLD
b. SET
c. RESET
d. NONE

UNIT-4:
1. In dynamic logic when clock signal is high, PMOS turned OFF and single NMOS at PDN will
a) Turned OFF
b) Turned ON
c) Doesn’t change
d) Goes to breakdown region

2. Low noise margin for dynamic logic circuit is equal to


a) 5 V
b) 3 V
c) Threshold voltage
d) Input voltage

3. Output of DOMINO CMOS gate is low at beginning of


a) Pre-charge phase
b) Evaluation phase
c) Dynamic phase
d) Static phase

4. High noise margin for dynamic logic circuits is equal to


a) V DD−V TH
b) 3 V
c) Threshold voltage
d) Input voltage

5. design of address decoders in memory chips can be done in


a) TTL logic
b) PTL logic
c) DOMINO CMOS logic
d) CMOS logic

6. In pre-charge phase, when capacitor is fully charge it becomes equal to


a) Input signal
b) Output signal
c) Supply voltage
d) 2 V

7. Leakage current will cause load capacitor to


a) Charge
b) Discharge
c) Become infinite
d) Remain intact

UNIT-5: INTERCONNECTS

1. ________ should me monitored carefully which affects the performance of the gate;
Answer: Crosstalk

2. Crosstalk is propotional to _________


a) Resistance
b) Capacitance
c) Noise source
d) None of the above

UNIT-6: SEMICONDUCTOR MEMORIES

1. Memory permits data to be stored and retrieved at comparable speed is called


a) R/W memory
b) RAM memory
c) ROM memory
d) EPRAM memory

2. Amplifier which provides full swing digital signal is termed as


a) Swing amplifier
b) Sense amplifier
c) Rest amplifier
d) Full amplifier

3. Each cell in the memory array is connected to one of the column lines, these column lines are
termed as:
a) Word lines
b) Digit lines
c) Dye lines
d) Selected lines

4. With the increase of number of cells in array, transistor size will


a) Increase
b) Decrease
c) Remain default
d) Doesn’t change

5. Disk and tapes are type of


a) Serial memory
b) Combinational memory
c) State memory
d) Flipflop

6. Minimum time allowed between two consecutive memory operations are called
a) Memory access time
b) Memory cycle time
c) Memory dynamic time
d) Memory static time

7. Who writes the applied signal into the selected cell?


a) Selector
b) Decoder
c) Encoder
d) Driver

8. 64M bit chip needs


a) 16-bit address
b) 24-bit address
c) 256-bit address
d) 1024-bit address

9. Sense amplifier of the selected column acts as a


a) Selector
b) Decoder
c) Encoder
d) Driver

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