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Introduction to FPGA
A jumpstart to Field-Programmable Gate Arrays
Engr. Brian Jay R. Lumauag

2021

• Prerequisites to jumpstart on FPGA

• Training Objectives
• What is Hardware Descriptive Language?
• What is an FPGA?
• Difference Between Microcontroller and
FPGA
Morning Session • Review on Basic Logic Gates
• Hardware Descriptive Language – Verilog
• The Gate-level Modelling
• The Test Bench
• Simulation

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Things you need to know first

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Prerequisites to Jumpstart on FPGA 2021

Things you need to know first

o Basic Electronics
o Basic Logic Circuits
o Familiar with C Programming (Verilog)
o Familiar with Pascal Programming (VHDL)

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Our goals for this training

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Training Objectives 2021

Our goals for this training

o Jumpstart your learnings to basic designs on FPGA

o Learn Basic Verilog HDL (Hardware Description
Language)
o Simulate Combinational Logic Circuits on Modelsim
o Synthesize Combinational Logic Circuits and other basic
designs on FPGA

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Field-Programmable Gate Arrays

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What is an FPGA? 2021

Getting to know the system as simple as possible.

o FPGA stands for Field-Programmable Gate Array.
o It is a programmable logic device that a user can program to
carry out one or more logical operations.
o An integrated circuit that has arrays that contains
programmable logic gates, memory and other elements.
o Think of it as a blank slate of IC, which you can make
whatever functional/logic circuit you want or transform the
FPGA to be a CPU, memory, GPU

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Components
1. I/O Blocks
2. Logic Blocks
3. Programmable Interconnect
Other components can be:
1. Multiplexers
2. Flip-flops
3. Memories
4. LUTs, Etc.

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FPGA Manufacturers 2021

o Intel - Altera

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FPGA Manufacturers 2021

o Xilinx

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FPGA Manufacturers 2021

o Lattice Semiconductor

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FPGA Manufacturers 2021

o Microchip Technology

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FPGA Manufacturers 2021

o Gowin Semiconductor

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Applications of FPGA 2021

Systems that use FPGAs

1. Video and Image

2. Medical & Scientific
3. Telecoms and Datacom
4. Server and Cloud
5. Aerospace and Defense
6. Artificial Intelligence
7. Others
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Hardware Description Language

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What is an HDL? 2021

Getting to know how the HDL works as simple as possible.

o Hardware Description Language
o Describes how the hardware will be connected inside the chip or
describes the hardware of digital systems and logic circuit’s behavior in
textual form.
o This is a literal “Hardware Programming” written in a high-level
abstraction.
o The code executes in Parallel in contrast to Serial execution of the
CPU/Microcontroller.
o HDL codes are Synthesized while Assembly Language and High-level
Programming Languages are assembled or compiled respectively.

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What is Synthesis? 2021

o Synthesis converts Verilog HDL to gate-level

implementations automatically.

HDL Code (Verilog)

module test(a,b,out); Hardware Equivalent
input a,b;
output out; Synthesis
wire andAB;
and(andAB,a,b);
not(out,andAB);
endmodule

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How HDL do Parallel Execution? 2021

o Serial Execution of code (C++ Arduino)

void setup() {
// initialize digital pin LED_BUILTIN as an output.
pinMode(LED_BUILTIN, OUTPUT);
}

// the loop function runs over and over again forever

void loop() {
digitalWrite(LED_BUILTIN, HIGH); // turn the LED on (HIGH is the voltage level)
delay(1000); // wait for a second
digitalWrite(LED_BUILTIN, LOW); // turn the LED off by making the voltage LOW
delay(1000); // wait for a second
}

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How HDL do Parallel Execution? 2021

o Parallel Execution (HDL Verilog)

module blink(clk,led); always (@posedge clk)
input clk; begin
output led; clk_counter<=clk_counter+1’b1;
reg led_status; if(clk_counter>50000000)
reg [31:0] clk_counter; begin
led_status<=!led_status;
initial begin clk_counter<=32’b0;
clk_counter<=32’b0; end
led_status<=1’b0; end
end assign led=led_status;
endmodule

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Why do we need HDLs ? 2021

o HDL can describe both circuit structure and behavior

• Schematics describe only circuit structure
• C language describes only behaviors
o Provide high level abstraction to speed up design
o High portability and readability
o Enable rapid prototyping
o Support different hardware styles
o HDLs are used in several major steps in the design flow of an
integrated circuit (IC) (shown on the next page)

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Two Major Types HDLs 2021

o Verilog
o Slightly better at gate / transistor level
o Language style close to C / C++
o Pre-defined data type, easy to use
o VHDL - VHSIC (very high speed integrated circuit) HDL
o Slightly better at system level
o Language style close to Pascal
o User-defined data type, more flexible

o Note: both HDLs are equally effective, personal preference

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Choosing the right development board systems for your designs.

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MCU/CPU vs FPGA 2021

Choosing the Right System for Your Design

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MCU/CPU vs FPGA 2021

Microcontroller/CPU FPGA
Programming Design Software-Based Hardware-Based
Programming Language C,C++, etc HDL, Verilog, VHDL
Code Execution Serial Execution Parallel Execution
Limitation Limited by Time (Depends on Limited by Space (More
the MCU Clock) Complicated Design, More
Blocks , More Space)
External Components No need for external Needs memory , ROM, RAM,
components Serial Ports, ADC, DAC, etc
Programmer Needs Programmer Chip (FTDI, JTAG)
Price Cheap Expensive
Design Difficulty Easy to Use More Complicated

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MCU/CPU vs FPGA 2021

MICROCONTROLLER/CPU FPGA

Code > Compile > Binary > ROM > Code > Register-Transfer Level (RTL)
Use Existing Hardware > Synthesis > Create NEW Hardware
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2021

Going back to Logic Circuits

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AND 2021

a b a.b
0 0 0

0 1 0

1 0 0

1 1 1

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OR 2021

a b a+b
0 0 0

0 1 1

1 0 1

1 1 1

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NOT (Inverter) 2021

a 𝒂
0 1

1 0

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XOR (Exclusive OR) 2021

a b 𝑎⨁𝑏
0 0 0
a⨁b 0 1 1

1 0 1

1 1 0

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NAND 2021

a b 𝑎. 𝑏
0 0 1

0 1 1

1 0 1

1 1 0

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NOR 2021

a b 𝑎+𝑏
0 0 1

0 1 0

1 0 0

1 1 0

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BUFF or BUFFER 2021

a 𝒂
0 0

1 1

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XNOR (Exclusive NOR) 2021

a b 𝑎⨁𝑏
0 0 1

𝑎⨁𝑏 0 1 0

1 0 0

1 1 1

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A Jumpstart to Verilog
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Verilog Rules 2021

Let’s learn the Verilog as simple as possible

o Verilog is very similar to C/C++ Language rules like

identifier rules, case-sensitive, etc.
o “ // “ is interpreted as comment, which has no effect on
the Verilog Code. Multiline comments uses “ /*
comment */ “.
o Blank spaces are ignored bit not on between keywords,
identifiers, operators,etc.

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Verilog Modelling Concepts 2021

The manner or ways of creating a Verilog code

o Gate-Level Modelling – more on lower-level abstraction
with the use of logic gates.
o Dataflow Modelling – makes use of the functions that
define the working circuit instead of gate structure.
o Behavioral Modelling – more Algorithmic just like in C or
other high-level programming languages.
o User-Defined Primitives (UDP) – creating new primitives
just like creating a truth table.

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Creating a Module 2021

The first step to create a Verilog code.

A module is the fundamental descriptive unit in the Verilog language. It is
declared by the keyword module and must always be terminated by the
keyword endmodule.
module module_name (port list);
//Verilog statements
endmodule
Port List order : (list of input variables, output variable)
The port list of a module is the interface between the module and its
environment. This list is enclosed in parentheses, and commas are used to
separate elements of the list. The statement is terminated with a semicolon
(;).

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Creating a Module 2021

The first step to create a Verilog code.

The keywords input and output specify which of the ports are inputs
and which are outputs. Internal connections are declared as wires. This
connection is declared with the keyword wire.

input in1, in2, inN;

output out;
wire x, y, z;

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Describing the circuit on Gate-Level Abstraction

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Gate-Level Modeling 2021

• Gate-level or structural modelling describes a circuit by specifying

its gates and how they are connected with each other.
• It provides a textual description of a schematic diagram.
• Verilog HDL includes 12 basic gates as predefined primitives. Four
of these primitive gates are of the three-state types. The other
eight are all declared with the lowercase keywords and, nand, or,
nor, xor, xnor, not, and buf.
• N-input primitives such as nand and or can have any number of
scalar inputs (e.g., a three-input and gate) while n-output
primitives such as not and buf can drive multiple output lines from
a single input distinguished by their identifiers.

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Gate-Level Modeling 2021

Remember that the output is always listed first in

the port list of a primitive, followed by the inputs.

and U1 (output variable, input var 1, input var 2);

Adding a timing element:

and #(t) U1 (output variable, input var 1, input var 2);

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module adder(A,B,S,C);
input A,B;
output S,C;
xor(S,A,B);
and(C,A,B);
endmodule

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2021

module example2(A,B,C,X);
input A,B,C;
output X;
A B C wire wire1, wire 2, wire 3;
wire1
xor EOR2(wire1,B,C);
EOR2 wire3 and AND2(wire3,wire1,A);
AND2
not NOT(wire2,A);
X nor NOR2(x,wire3,wire2);
NOR2
wire2
endmodule
NOT

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Ways to Test the Circuit 2021

• Verilog Testbench (Software Simulation)

• FPGA – Field-Programmable Gate Arrays

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Other things to know 2021

A little bit from Behavioral Modelling with

sequential block:
initial
begin
//sequential codes
end
The initial statement executes only once and begins
at the start of the time 0.
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Other things to know 2021

A little bit from Behavioral Modelling with

sequential block:
always
begin
//sequential codes
end
The always statement executes repeatedly and
begins also at the start of the time 0.
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Other things to know 2021

A little bit from Behavioral Modelling:

reg_name<=RHS_expression
A procedural assignment is an assignment within an
initial statement or an always statement. It is used
only to assign to a register data type.

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Other things to know 2021

A little bit from Data flow modeling:

assign [ delay ] LHS_net = RHS_expression

A continuous assignment assigns a value to a net; it

cannot be used to assign a value to a register.

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Other things to know 2021

Handling binary values:

1’b0 - 1 bit with value of 0
2’b10 - 2 bits with value of 2
3’b001 - 3 bits with value of 1
4’b0101 - 4 bits with value of 5

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Example 2021

module blink(clk,led); always (@posedge clk)

input clk; begin
output led; clk_counter<=clk_counter+1’b1;
reg led_status; if(clk_counter>50000000)
reg [31:0] clk_counter; begin
led_status<=!led_status;
initial begin clk_counter<=32’b0;
clk_counter<=32’b0; end
led_status<=1’b0; end
end assign led=led_status;
endmodule

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Simulation Test Platform of the Circuit

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The Testbench 2021

Testing the module we’ve made.

• Testbench is used to simulate the output or behavior of the circuit.
• In its simplest form, a test bench is a module containing a single
generator and an instantiation of the model that is to be verified.
• It has no input or output ports, because it does not interact with
its environment.

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The Testbench 2021

Testing the module we’ve made.

TESTBENCH
IN1
Module IN1
Reg A Module
OUT1
IN2 OUT1 Wire
IN2
Reg B A

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The Testbench 2021

Testing the module we’ve made.

• The inputs to the circuit are declared with keyword reg and the
outputs are declared with the keyword wire.
reg a, b, c;
wire w1, w2;

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The Testbench 2021

Testing the module we’ve made.

• The response to the stimulus generated by the initial and always
blocks will appear in text format as standard output and as
waveforms (timing diagrams) in simulators having graphical output
capability.
• Numerical outputs are displayed by using Verilog system tasks.
These are built-in system functions that are recognized by
keywords that begin with the symbol $.

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The Testbench 2021

Testing the module we’ve made.

• Some of the system tasks that are useful for display are:
$display – display a one-time value of variables or strings with an end-of-line return,
$write – same as $display, but without going to next line,
$monitor – display variables whenever a value changes during a simulation run,
$time – display the simulation time,
$finish – terminate the simulation.

The syntax is of the form:

Task_name(format specification, argument list);

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The Testbench 2021

Testing the module we’ve made.

Task_name(format specification, argument list);

The format specification uses the symbol % to specify radix of

numbers that are to be displayed and may have a string enclosed in
quotes. The base may be binary (%b), decimal (%d), and
hexadecimal (%h).

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Testbench Example 2021

module testbench;
module adder(A,B,S,C); reg x,y;
input A,B; wire sum,carry; (Testbench)
output S,C; adder tb(x,y,sum,carry);
xor(S,A,B); initial begin
and(C,A,B); x=1’b0; y=1’b0;
endmodule $display(“Simulating Half-Adder”);
$display(“A B SUM CARRY”);
$monitor(“%b %b %b %b”, x,y,sum,carry);
#5 x=1’b0; y=1’b0;
#5 x=1’b0; y=1’b1;
#5 x=1’b1; y=1’b0;
#5 x=1’b1; y=1’b1;
#5 $finish;
end
endmodule

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Let’s make our first HDL with Modelsim

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 FPGA Synthesis Overview

 The Cyclone IV FPGA Development Board

 Combinational Logic Circuits Synthesis

 Basic Designs with FPGA Clock, etc.

Afternoon Session

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The first step of design is knowing the architecture of that system.

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Quick Details: 2021

The Cyclone IV device family offers
the following features:
Low-cost, low-power FPGA fabric:
• 6K to 150K logic elements
• Up to 6.3 Mb of embedded memory
• Up to 360 18 × 18 multipliers for
DSP processing intensive applications
• Protocol bridging applications for under
1.5 W total power

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Quick Details: 2021

• A USB port download cable that allows
PC users to program and configure
devices in-system.

• The USB-Blaster cable provides

configuration support for FPGA devices
and programming support for CPLD
devices, and other logic PLDs.

• The USB-Blaster cable provides

support for Passive Serial, JTAG, and
Active Serial Programming modes.

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This is where the fun starts. A demo in Intel-Altera Quartus.

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Examples and Demo

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HALF-ADDER 2021

module adder(A,B,S,C);
input A,B;
output S,C;
xor(S,A,B);
and(C,A,B);
endmodule

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FULL ADDER 2021

module FA(A,B,Cin,S,Cout);
input A,B,Cin;
output S,Cout;
wire U1out,U3out,U4out;

xor U1(U1out,A,B);
and U2(U2out,Cin,U1out);
and U3(U3out,A,B);
xor U4(S,U1out,Cin);
or U5(Cout,U2out,U3out);

endmodule
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Multiplexer 2021

module multiplexer41(sel,A,B,C,D,Q);
input [1:0]sel,A,B,C,D;
output Q;

not U1 (U1not,sel[1]);
not U2 (U2not,sel[0]);
and U3 (U3out,A,U2not,U1not);
and U4 (U4out,B,U2not,sel[1]);
and U5 (U5out,C,sel[0],U1not);
and U6 (U6out,D,sel[0],sel[1]);
or U7 (Q,U3out,U4out,U5out,U6out);
endmodule

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Binary Switch to Hex with 7

Segment (Behavioral) module binhex(bin,segment,DTenable);
2021

input [3:0]bin;
output [7:0]segment;
output DTenable;
reg [7:0] segment;
assign DTenable=1'b0;
always @(*)
case(bin)
4'b0000 : segment = ~(8'b00111111);
4'b0001 : segment = ~(8'b00000110);
4'b0010 : segment = ~(8'b01011011);
4'b0011 : segment = ~(8'b01001111);
4'b0100 : segment = ~(8'b01100110);
4'b0101 : segment = ~(8'b01101101);
4'b0110 : segment = ~(8'b01111101);
4'b0111 : segment = ~(8'b00000111);
4'b1000 : segment = ~(8'b01111111);
4'b1001 : segment = ~(8'b01101111);
4'b1010 : segment = ~(8'b01110111);
4'b1011 : segment = ~(8'b01111100);
4'b1100 : segment = ~(8'b00111001);
4'b1101 : segment = ~(8'b01011110);
4'b1110 : segment = ~(8'b01111001);
4'b1111 : segment = ~(8'b01110001);
default : segment = ~(8'b00000000);
endcase
endmodule
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Examples and Demo

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BLINK 2021

module blink(clk,led); always (@posedge clk)

input clk; begin
output led; clk_counter<=clk_counter+1’b1;
reg led_status; if(clk_counter>50000000)
reg [31:0] clk_counter; begin
led_status<=!led_status;
initial begin clk_counter<=32’b0;
clk_counter<=32’b0; end
led_status<=1’b0; end
end assign led=led_status;
endmodule

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always @(posedge clk)

4-bit BIN COUNTER begin
2021
counter<=counter+1'b1;
if(counter>50000000)
begin
module bincounter(clk,led);
input clk; led_status<=led_status+1'b1;
output [3:0]led; counter<=32'b0;
reg [31:0]counter; end
reg [3:0]led_status; end
assign led[0]=!led_status[0];
initial assign led[1]=!led_status[1];
begin assign led[2]=!led_status[2];
counter<=32'b0; assign led[3]=!led_status[3];
led_status<=4'b0000;
end endmodule

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BINARY COUNTER WITH HEX 2021

module BinCounterHex(clk,LED,ED1,D1); always@(posedge clk) end
input clk; begin /*Parallel Execution*/
output [3:0]LED; counter<=counter+1'b1; assign D1[0]=!D1_status[0];
output [6:0]D1; case(LED_status) assign D1[1]=!D1_status[1];
output ED1; 4'b0000 : D1_status = 8'b00111111; assign D1[2]=!D1_status[2];
reg [31:0]counter; 4'b0001 : D1_status = 8'b00000110; assign D1[3]=!D1_status[3];
reg [3:0]LED_status; 4'b0010 : D1_status = 8'b01011011; assign D1[4]=!D1_status[4];
reg [7:0]D1_status; 4'b0011 : D1_status = 8'b01001111; assign D1[5]=!D1_status[5];
reg ED1_status; 4'b0100 : D1_status = 8'b01100110; assign D1[6]=!D1_status[6];
4'b0101 : D1_status = 8'b01101101; assign LED[3]=!LED_status[0];
assign ED1=!ED1_status; 4'b0110 : D1_status = 8'b01111101; assign LED[2]=!LED_status[1];
4'b0111 : D1_status = 8'b00000111; assign LED[1]=!LED_status[2];
initial begin 4'b1000 : D1_status = 8'b01111111; assign LED[0]=!LED_status[3];
counter<=32'b0; 4'b1001 : D1_status = 8'b01101111;
LED_status<=4'b0; 4'b1010 : D1_status = 8'b01110111; endmodule
D1_status<=8'b0; 4'b1011 : D1_status = 8'b01111100;
ED1_status<=1'b1; 4'b1100 : D1_status = 8'b00111001;
end 4'b1101 : D1_status = 8'b01011110;
4'b1111 : D1_status = 8'b01110001;
default : D1_status = 8'b00000000;
endcase
if(counter>50000000)
begin
LED_status<=LED_status+1'b1;
counter<=32'b0;
end
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TRIP ALARM WITH RESET 2021

module tripalarm(trigger,reset,alarm); always @ (*)

input trigger,reset; begin
output alarm; if(trigger==1&&alarm_status==0)
alarm_status<=!alarm_status;
reg alarm_status;
else if(alarm_status==1&&reset==1)
alarm_status<=!alarm_status;
initial begin end
alarm_status<=1'b0;
end assign alarm=alarm_status;
endmodule

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2021

THANK YOU!
[email protected] // [email protected]

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