Lecture Overview

• Interrupts in AVR
Microprocessors & Interfacing – External interrupts
– Internal interrupts
• Timers/Counters
Interrupts (II)

Lecturer : Dr. Annie Guo

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External Interrupts External Interrupts (cont.)

• The external interrupts are triggered by the • To enable an interrupt, two bits must be set
INT7:0 pins. – I bit in SREG
– If enabled, the interrupts will trigger even if the – INTx bit in EIMSK
INT7:0 are configured as outputs • To activate an interrupt, the following must be
• This feature provides a way of generating a software
interrupt. met:
– Can be triggered by a falling or rising edge or a – The interrupt must be enabled
logic level – The associated external pin must have a designed
• Specified in External Interrupt Control Register signal asserted.
– EICRA (for INT3:0)
– EICRB (for INT7:4)

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 EIMSK EICRA
• External Interrupt Mask Register • External Interrupt Control Register A
– A bit is set to enable the related interrupt – For INT0-3
– Defines the type of signals that activates the
external Interrupt
• on rising or falling edge or level sensed.

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EICRB EIFR
• External Interrupt Control Register B • Interrupt flag register
– For INT4-7 – A bit is set when an event-triggered interrupt is
– Defines the type of signals that activates the enabled and the related event on the related INT
External Interrupt pin happens.
• on rising or falling edge or level sensed. • Event-triggered interrupt: signal edge activated.

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 Example 1 Example 1 (solution)
• Design a system, where the state of LEDs • Use an external interrupt
toggles under the control of the user. – Connect the external interrupt pin to a push button
– When the button pressed, the interrupt is
generated
• In the assembly code
– Set up the interrupt
• Set up the interrupt vector
• Enable the interrupt
– Write a service routine for this interrupt
• Change the display pattern
• Write the pattern to the port connected to the LEDs

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Code for Example 1 Code for Example 1

; continued
.include "m64def.inc“ ldi temp, (2 << ISC00) ; set INT0 as falling edge triggered interrupt
sts EICRA, temp
.def temp =r16
.def output = r17 in temp, EIMSK ; enable INT0
.def count = r18 ori temp, (1<<INT0)
.equ PATTERN = 0b01010101 out EIMSK, temp
; set up interrupt vectors sei ; enable Global Interrupt
jmp RESET jmp main
.org INT0addr
jmp EXT_INT0 EXT_INT0:
push temp ; save register
RESET: in temp, SREG ; save SREG
ldi temp, low(RAMEND) ; initialize stack push temp
out SPL, temp
ldi temp, high(RAMEND) com output ; flip the pattern
out SPH, temp out PORTC, output
inc count
ser temp ; set Port C as output
out DDRC, temp pop temp ; restore SREG
out PORTC, temp out SREG, temp
ldi output, PATTERN pop temp ; restore register
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reti COMP9032 Week7 12
 Code for Example 1 Timer/Counters
; continued
• Simply binary counters
main:
; main - does nothing but increment a counter • Used in two different modes:
clr count – Timer
clr temp
• Counting time periods
loop:
inc temp ; a dummy task in main – Counter
rjmp loop
• Counting the events or pulse or something of this nature
• Can be used to
– Measure time periods, speed, frequency
– Generate PWM signals
– Schedule real-time tasks
– etc.

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Timer/Counters in AVR 8-bit Timer/Counter Block Diagram

• In AVR, there are 8-bit and 16-bit
timer/counters.
– Timer 0 and Timer 2: 8-bit
– Timer 1 16-bit

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 8-bit Timer/Counter TIMSK
• The counter can be initialized with • Timer/Counter Interrupt Mask Register
– 0 (controlled by reset)
– a number (controlled by count signal)
– Set TOIEx (and I-bit in SREG) to enable the
Overflow Interrupt
• Can count up or down
– controlled by direction signal – Set OCIEx (and I bit in SREG) to enable Compare
• Those controlled signals are generated by hardware Match Interrupt
control logic
– The control logic is further controlled by programmer by
• Writing control bits into TCCRn
• Output
– Overflow interrupt request bit
– Output Compare interrupt request bit
– OCn bit: Output Compare bit for waveform generation 8 bit Timer/counters

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TIFR TIFR (cont.)

• Timer/Counter Interrupt Flag Register • Timer/Counter Interrupt Flag Register
– OCFx bit is set when a Compare Match between – TOVx bit is set when an overflow occurs in the
the counter and the data in OCRx (Output counter.
Compare Register). • When (I=1)&&(TOIEx=1)&&(TOVx=1), the related
• When (I=1)&&(OCIEx=1)&&(OCFx=1), the related Timer/Counter Overflow Interrupt is executed.
Timer/Counter Compare Match Interrupt is executed. • In PWM mode, this bit is set when the counter changes
– OCFx bit is cleared by hardware when the related counting direction at 0x00
interrupt is handled or can be cleared by writing a – OCFx bit is cleared by hardware when the related
logic 0 to the flag interrupt is handled or can be cleared by writing a
logic 0 to the flag

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Timer/Counters
Week7 19 S2, 2008 8 bitCOMP9032
Timer/counters
Week7 20
 TCCRx TCCR0 Bit Description
• Timer Counter Control Register • Bit 7:3:
– E.g. TCCR0 – control the mode of operation
• For Timer/Counter0 • the behavior of the Timer/Counter and the output, is defined by
the combination of the Waveform Generation mode (WGM01:0)
and Compare Output mode (COM01:0) bits.
• The simplest mode of operation is the Normal Mode
(WGM01:00 =00). In this mode the counting direction is always
up. The counter rolls over when it passes its maximum 8-bit
value (TOP = 0xFF) and then restarts from the bottom (0x00).
• Refer to Mega64 Data Sheet (pages 96~100) for
details.

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TCCR0 Bit Description (cont.) Example 2

• Bit 2:0 • Implement a scheduler that can execute a
– Control the clock selection task every one second.

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 Example 2 (solution) Example 2
; This program implements a timer that counts one second using
• Use Timer0 to count the time ; Timer0 interrupt
– Let’s set Timer0 prescaler to 8
• The time-out for the setting should be .include "m64def.inc"
– 256*(clock period) = 256*8/(7.3728 Mhz)
= 278 us .equ PATTERN=0b11110000
» Namely, we can set the Timer0 overflow interrupt that is to occur .def temp=r16
every 278 us. .def leds = r17
» Note, Clktos = 1/7.3728 Mhz (obtained from the data sheet)
• For one second, there are
– 1000000/278 = 3597 interrupts ; The macro clears a word (2 bytes) in a memory
• In code, ; the parameter @0 is the memory address for that word
.MACRO Clear
– Set Timer0 interrupt to occur every 278 microseconds
ldi r28, low(@0) ; load the memory address to Y
– Use a counter to count to 3597 interrupts for counting 1 ldi r29, high(@0)
second clr temp
– To observe the 1 second time period, use LEDs that toggles st y+, temp ; clear the two bytes at @0 in SRAM
every one second. st y, temp
.ENDMACRO
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Example 2 Example 2
; continued ; continued
.dseg
SecondCounter:
RESET: ldi temp, high(RAMEND) ; Initialize stack pointer
.byte 2 ; Two-byte counter for counting seconds.
TempCounter: out SPH, temp
.byte 2 ; Temporary counter. Used to determine ldi temp, low(RAMEND)
; if one second has passed out SPL, temp
.cseg
.org 0x0000
jmp RESET ser temp ; set Port C as output
jmp DEFAULT ; No handling for IRQ0. out DDRC, temp
jmp DEFAULT ; No handling for IRQ1.
… rjmp main
jmp Timer0OVF ; Jump to the interrupt handler for Timer0 overflow.
… ; continued
jmp DEFAULT ; default service for all other interrupts.
DEFAULT: reti ; no service
; continued

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 Example 2 Example 2
; continued
; continued
cpi r24, low(3597) ; Check if (r25:r24)=3597
ldi temp, high(3597) ; 3597= 106/278
Timer0OVF: ; interrupt subroutine to Timer0
cpc r25, temp
in temp, SREG
brne NotSecond
push temp ; Prologue starts.
com leds
push r29 ; Save all conflict registers in the prologue.
out PORTC, leds
push r28
Clear TempCounter ; Reset the temporary counter.
push r25
ldi r30, low(SecondCounter) ; Load the address of the second
push r24 ; Prologue ends.
ldi r31, high(SecondCounter) ; counter.
ldi r28, low(TempCounter) ; Load the address of the temporary
ld r24, z+ ; Load the value of the second counter.
ldi r29, high(TempCounter) ; counter.
ld r25, z
ld r24, y+ ; Load the value of the temporary counter.
adiw r25:r24, 1 ; Increase the second counter by one.
ld r25, y
; continued
adiw r25:r24, 1 ; Increase the temporary counter by one.
; continued

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Example 2 Example 2
; continued
; continued
st z, r25 ; Store the value of the second counter. main:
st -z, r24 ldi leds, 0xff
rjmp EndIF out PORTC, leds
NotSecond: ldi leds, PATTERN
st y, r25 ; Store the value of the temporary counter. Clear TempCounter ; Initialize the temporary counter to 0
st -y, r24 Clear SecondCounter ; Initialize the second counter to 0
EndIF: ldi temp, 0b00000010
pop r24 ; Epilogue starts; out TCCR0, temp ; Prescaling value=8
pop r25 ; Restore all conflict registers from the stack. ldi temp, 1<<TOIE0 ; =278 microseconds
pop r28 out TIMSK, temp ; T/C0 interrupt enable
pop r29 sei ; Enable global interrupt
pop temp loop: rjmp loop ; loop forever
out SREG, temp
reti ; Return from the interrupt.
; continued
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 Reading Material Homework
• Chapter 8: Interrupts and Real-Time Events. 1. What do you need to do to set up an Timer0
Microcontrollers and Microcomputers by Output Compare Match Interrupt?
Fredrick M. Cady.
• Mega64 Data Sheet.
– External Interrupts.
– Timer0

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Homework
2. Based on the Example 1 in this week lecture
slides, implement a software interrupt such
that when there is an overflow in the counter
that counts the number of LED toggles, all
LEDs are turned on.

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