A High Efficiency Bridgeless Flyback PFC Converter

for Adapter Application

Xiliang Chen, Tianyang Jiang, Xiucheng Huang, Junming Zhang
College of Electrical Engineering, Zhejiang University
38 Zheda Road, Hangzhou, China 310027
E-mail: [email protected]

Abstract—This paper proposes a high efficiency low cost AC/DC Another challenge to achieve high power density is related
converter for adapter application. In order to achieve high to the efficiency. Generally, adapters are required to operate
efficiency and low cost for adapter with universal AC input, a with universal input (90-264Vac); hence, in an effort to
single stage bridgeless flyback PFC converter with peak current achieve satisfactory thermal performance, it is important to
clamping technique was proposed. Compared with conventional achieve high efficiency over the entire input range. Typically,
flyback PFC converter, the conduction loss is reduced due to a boost PFC front end exhibits 1%-3% lower efficiency at
bridgeless structure. And the size of transformer can also be 100V line compared to that at 230V line [12]. The efficiency
significantly reduced due to lower peak current, which results in drop at low line is mainly caused by high conduction loss of
lower cost and higher power density. Detailed operation
power devices, such as the input rectifier bridge. In recent
principles and design considerations are illustrated.
years, many bridgeless PFC converters have been proposed to
Experimental results from a 90W prototype with universal input
and 20V/4.5A output are presented to verify the operation and eliminate the conduction loss caused by the bridge [6]-[11].
performance of the proposed converter. The minimum efficiency Reference [6] presents a systematic review of different kinds
at full load is above 91% over the entire input range. of bridgeless boost PFC rectifiers. Bridgeless buck [7] or
SEPIC [8][9] PFC front ends are also studied in related
I. INTRODUCTION literature. A bridgeless PFC converter based on flyback
topology was proposed in [10], but it requires additional
With the ever-present trend in size and cost reduction of driving circuits because the sources of the MOSFETs are not
portable equipment, even higher power density and efficiency connected to ground. Another bridgeless flyback converter
are required for their external power supply, such as adapters introduced in [11] is simpler, but the transformer size is big
for laptops, which creates new challenge for the power supply due to high peak current.
design.
In this paper, a high efficiency low cost flyback PFC
In order to achieve high power density, on one hand, the converter with peak current clamping for adapter application
size of components and components count must be reduced. In is proposed. Compared to conventional flyback PFC
most cases, magnetic components contribute a large portion of converter, one diode is eliminated from the current flowing
the converter’s weight and size. Hence, many magnetic path to reduce the conduction loss. Furthermore, the converter
integration techniques have been introduced to reduce both the is designed to operate in critical conduction mode (CRM) so
size and cost of magnetic components [1]. Another way for that the MOSFET switching loss can be minimized. By
size reduction is to adopt single stage topology with less applying the peak current clamping method [1], the size and
magnetic components. Conventional adapters with two stage weight of the transformer can be reduced while still meeting
structure consist of a power factor correction (PFC) front end the IEC-61000-3-2 class D regulation. As a result, the power
to achieve near unity power factor and a downstream DC/DC density of the system can be further improved, and the cost
stage to provide output voltage regulation and isolation. will be lower since a smaller magnetic core is used. Operation
Although the two stage scheme demonstrates excellent principles and design considerations of the converter are
performance in terms of power factor, total harmonic presented in the paper. Experimental results of a 90W
distortion (THD) and output voltage response, it requires high prototype with universal input and 20V/4.5A output are
components count and complex control circuit, which leads to presented to verify the operation and performance of the
increased cost and makes it less attractive for low power proposed converter.
application. In contrast, the single stage scheme integrates the
PFC stage with the DC/DC stage, leading to a low complexity II. PRINCIPLE OF OPERATION
and cost [2]-[5]. Therefore, it is quite suitable for adapter A. Power stage of the converter
application where the cost is a critical concern.
The bridgeless flyback converter shown in Fig. 1 was
adopted as the power stage of the converter [11]. The circuit

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can be regarded as two independent flyback converters that It should be noted that during positive half cycle, the
operate alternatively during positive and negative line cycle. on/off state of S2 will not affect the normal operation of the
During positive half of the line voltage, the operating flyback operating converter because D2 will prevent reverse current
converter consists of diode D1, switch S1, transformer T1 and from flowing through S2 and T2. It is the same for S1 during
output rectifier D3, as shown in Fig. 2(a). Similarly, during the negative half cycle. Therefore, in actual implementation,
negative half of the line voltage, the operating flyback switches S1 and S2 can be driven with the same signal. Due to
converter consists of diode D2, switch S2, transformer T2 and the symmetry of the topology, only half of the line cycle will
output rectifier D4, as shown in Fig. 2(b). Its operation be considered in the following analysis.
principle is identical to the conventional flyback converter.
The output voltage is regulated by the pulse-width-modulation B. Control scheme of the converter
(PWM) of switch S1 or S2. It can operate in continuous The control scheme for the proposed converter is shown in
conduction mode (CCM), critical conduction mode (CRM) Fig. 3. The converter is designed to operate in CRM, utilizing
and discontinuous conduction mode (DCM). a peak current mode PFC controller L6562 from ST. Detailed
operation principles and design equations for conventional
CRM flyback PFC converters were discussed in [13].
It can be seen that there are four parts that are different
from the conventional CRM flyback PFC converter, as
illustrated in Fig. 3: (1) Input voltage is sensed by adding two
signal diodes and a resistor divider. (2)The primary current of
both transformer T1 and T2 can be sensed by RCS. There is no
need to sense them separately. (3) Auxiliary windings are
added to T1 and T2 to achieve zero current detection (ZCD).
(4) A current reference vref is generated by the peak current
clamping circuit which clamps the peak value of a sinusoidal
Fig. 1 Topology of the converter waveform. The clamped value to the amplitude of the
sinusoidal waveform is determined by Rb2/(Rb1+Rb2). The
current shape vref will be multiplied by a coefficient in L6562
to control the primary side peak current. The clamping value
should be carefully designed to pass the related current
harmonic regulation and reduce the transformer size. Detailed
design consideration will be explained in the next Section.

(a) During positive cycle

(b) During negative cycle Fig. 3 Control scheme of the PFC converter

Fig. 2 Operation principle

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 III. DESIGN CONSIDERATIONS 2 ⋅ Pin ⋅ π
A=
π VPK sin(θ ) ⋅ i pk _ chopped (θ )
*
Design equations for the clamping value of sinusoid
current reference will be deduced in this section. Theoretical ∫0 V
dθ
analysis shows that the peak current and the magnetizing 1 + PK ⋅ sin(θ )
inductance of flyback transformer can be simultaneously n ⋅ Vo (7)
reduced with this method, which leads to a smaller
transformer size. Hence, we can plot the waveform of primary peak current
and average current with different θa, as shown in Fig. 5. In
Before the analysis, a normalized clamping sinusoid is fact, the traditional sinusoid peak current reference can be
defined, as shown by solid line in Fig. 4. It can be expressed regarded as a special case where θa=π/2. The harmonic
as components of i p _ ave _ chopped (θ ) can be calculated by Fourier
⎧sin(θ )
0 ≤ θ < θ a and π − θ a ≤ θ < π analysis. Before the design of the transformer, θa must be
i* pk _ chopped (θ )= ⎨ (1) determined first and guarantee that the harmonic components
⎩sin(θ a )
θ a ≤ θ < π − θa
can pass the related regulation, such as IEC61000-3-2 class D
Where θ=2πfL·t and fL is the line frequency.
for adapter application. Otherwise, θa should be modified to a
larger value and recalculate the harmonics.
The switching frequency is given by
1
f s _ chopped (θ ) =
Ton + Toff
(8)
1 ⎛ V ⋅ sin(θ ) ⋅ n ⋅ Vo ⎞
= ⋅ ⎜ PK ⎟
LP ⋅ i p _ pk _ chopped (θ ) ⎝ VPK ⋅ sin(θ ) + n ⋅ Vo ⎠

Fig. 4 Normalized chopped sinusoid

When the clamped sinusoid is taken as the peak current

reference, the primary peak current and average current can be
defined as:
i p _ pk _ chopped (θ ) = A ⋅ i* pk _ chopped (θ ) (2)
1 Fig. 5 Peak current and average current with different θa
i p _ ave _ chopped (θ ) = ⋅ D(θ ) ⋅ i p _ pk _ chopped (θ )
2 (3)
where D(θ) is the duty cycle. According to the volt-second
balance of the magnetizing inductor:
VPK ⋅ sin(θ ) ⋅ Ton = n ⋅Vo ⋅ Toff
(4)
where VPK is the peak value of input voltage, n is the
primary to secondary turns ratio of the transformer and Vo is
the output voltage. Duty cycle D(θ) is given as:
Ton 1
D(θ ) = =
Ton + Toff VPK
1+ ⋅ sin(θ ) Fig. 6 Switching frequency with different θa
n ⋅Vo
(5)
The frequency variation during half line cycle is shown in
The input power can be expressed as: Fig. 6. It is obvious that the minimum frequency appears at θa
with minimum input voltage. Therefore, by determining a
1 π
Pin =
π ∫ 0
VPK sin(θ ) ⋅ i p _ ave _ chopped (θ )dθ
(6)
minimum frequency fmin (typically above the range of audible
frequency, i.e. 20Hz-20kHz), the primary magnetizing
inductance can be calculated as:
Substituting (2) (3) (5) into (6) yields

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 1 Vgs:5V/div Time:4ms/div
⋅ VPK min ⋅ sin(θ a )
LP = π (9)
⎛ V ⎞
f min ⋅ i p _ pk _ chopped (θ a ) ⋅ ⎜ 1 + PK min ⎟
⎝ n ⋅ Vo ⎠
Vds1:100V/div Vds2:100V/div

It can be seen from Fig. 6 that based on the same minimum

frequency fmin, the case with clamped sinusoid reference
requires a smaller Lp compared to the conventional case. For
θa=π/6, the size reduction can be around 40%, which will be
calculated in the next section.
IV. EXPERIMENTAL RESULTS
Fig. 8 Experimental waveforms of the gate signal (Vgs) and drain-source
A 90W prototype with universal input and 20V/4.5A voltage (Vds1 and Vds2) of S1 and S2 (Vin=115Vac, Po=90W)
output was built to verify the performance of the proposed
converter. With θa=arcsin(0.5), i.e. Rb2/(Rb1+Rb2)=0.5 in Fig.
3, the primary peak current can be reduced from 6.1A to 4.9A,
and the magnetizing inductance can be reduced from 245μH
to 210μH based on the same minimum frequency fmin=40kHz.
Accordingly, the calculated area product (AP) of the flyback
transformer can be reduced from 0.81 to 0.5. The theroratical
transformer size reduction can be around 40%. Consequently,
the required core size can be reduced from PQ2625 to
PQ2620.
Fig. 7 shows the experimental waveforms of the input
voltage and input current at full load with Vin=115Vac, which
is in accordance with the analysis in Fig. 5. Correspondingly,
the measured harmonic components of the input current are (a)
shown in Fig. 10. It can be seen that the IEC61000-3-2 class D
requirements are satisfied. In Fig. 8, the gate signal for both
MOSFETs and their corresponding drain-source voltage are
illustrated. We can see that although the two switches share
the same driving signal, the two flyback converters can work
alternatively during positive and negative half of the line
cycle. The operation waveforms of switch S1 are shown in Fig.
9(a), (b). The waveform of S1’s current in Fig. 9(a) shows the
clamped sinusoid peak current. Detailed waveforms in Fig.9
(b) show the valley switching of S1. Due to the symmetry of
the circuit, the operation waveforms of switch S2 are not
shown here. Measured efficiency at full load with different
input voltage was shown in Fig. 11. Obviously, the minimum
efficiency at Vin=90Vac is above 91%, which is 1~2% higher (b)
than the conventional flyback PFC converter.
Fig. 9 Experimental waveforms of the gate signal (Vgs), drain-source voltage
(Vds1) and current (Is1) of S1 (Vin=115Vac, Po=90W)

350

300
ClassD
Measured
250
Harmonic Current (mA)

THD=30.13%
PF=0.957
200

150

100

50

Fig. 7 Experimental waveforms of the input voltage (Vin) and input current 0
(Iin) (Vin=115Vac, Po=90W) 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

Fig. 10 Measured harmonic components of the input current (Vin=115V,

Po=90W)

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