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DSD1

This document contains Verilog code for a digital system design (dsd1) module and a testbench module to test it. The dsd1 module implements a finite state machine with 5 states (S1, S0, S00, S000, S0001) that changes state based on the din input and sets the dout output to 1 when in the S0001 state. The testbench applies a test input sequence to the dsd1 module and monitors its operation over time.

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Phan Tan
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112 views3 pages

DSD1

This document contains Verilog code for a digital system design (dsd1) module and a testbench module to test it. The dsd1 module implements a finite state machine with 5 states (S1, S0, S00, S000, S0001) that changes state based on the din input and sets the dout output to 1 when in the S0001 state. The testbench applies a test input sequence to the dsd1 module and monitors its operation over time.

Uploaded by

Phan Tan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Name: Phan Le Nhat Tan

Verilog code:

module dsd1(clk, clr, din, dout,state);


input clk, clr, din;
output dout;
reg dout;
output [2:0] state;
reg[2:0] state;
parameter
S1 = 3'b000,
S0 = 3'b001,
S00 = 3'b010,
S000 = 3'b011,
S0001 = 3'b100;
always @(posedge clk or posedge clr)
begin
if (clr == 1)
state <= S1;
else
state <= state;
// Changing State
begin
case(state)
S1: if(din == 0)
state <= S0;
else state <= S1;
S0: if(din == 0)
state <= S00;
else state <= S1;
S00: if(din == 0)
state <= S000;
else state <= S1;
S000: if(din == 1)
state <= S0001;
else state <= S000;
S0001: if(din == 1)
state <= S1;
else state <= S0;
endcase
end
end
// Check Outputs
always @(state)
begin
if(state == S0001)
dout <=1;
else
dout <= 0;
end
endmodule

Testbench:

module testbench();
reg tdin;
reg tclk;
reg tclr;
wire tdout;
wire [2:0] tstate;
always #5 tclk = ~tclk;
dsd1 dut(tclk,tclr, tdin, tdout, tstate);
initial begin
$monitor($time," clk=%01d clr=%b din=%b dout=%b state=%b " ,tclk,tclr,tdin,tdout,tstate);
tclk = 0;
tdin = 0;
tclr = 1;
#10 tclr = 0;
#20 tdin = 1;
#10 tdin = 0;
#10 tdin = 0;
#10 tdin = 1;
#10 tdin = 1;
#10 tdin = 0;
#10 tdin = 0;
#10 tdin = 0;
#10 tdin = 0;
#10 tdin = 1;
#5 $finish;
end
endmodule

Simulation:

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