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Verilog Cheat Sheet: S Winberg and J Taylor

This document provides a cheat sheet for the Verilog hardware description language. It summarizes key concepts like comments, numeric constants, nets and variables, parameters, assignments, case statements, always blocks, generate statements, and state machines. The cheat sheet covers operators, module definitions, module instantiation, and functions. It provides examples of syntax for common Verilog constructs.

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Mohamed Elsahat
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673 views2 pages

Verilog Cheat Sheet: S Winberg and J Taylor

This document provides a cheat sheet for the Verilog hardware description language. It summarizes key concepts like comments, numeric constants, nets and variables, parameters, assignments, case statements, always blocks, generate statements, and state machines. The cheat sheet covers operators, module definitions, module instantiation, and functions. It provides examples of syntax for common Verilog constructs.

Uploaded by

Mohamed Elsahat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog Cheat Sheet

S Winberg and J Taylor

Comments Operators
// One-liner // These are in order of precedence...
/* Multiple // Select
lines */ A[N] A[N:M]
// Reduction
&A ~&A |A ~|A ^A ~^A
Numeric Constants // Compliment
// The 8-bit decimal number 106: !A ~A
8'b_0110_1010 // Binary // Unary
8'o_152 // Octal +A -A
8'd_106 // Decimal // Concatenate
8'h_6A // Hexadecimal {A, ..., B}
"j" // ASCII // Replicate
{N{A}}
78'bZ // 78-bit high-impedance // Arithmetic
A*B A/B A%B
Too short constants are padded with zeros A+B A-B
// Shift
on the left. Too long constants are A<<B A>>B
truncated from the left. // Relational
A>B A<B A>=B A<=B
Nets and Variables A==B A!=B
wire [3:0]w; // Assign outside always blocks // Bit-wise
reg [1:7]r; // Assign inside always blocks A&B
reg [7:0]mem[31:0]; A^B A~^B
A|B
integer j; // Compile-time variable // Logical
genvar k; // Generate variable A&&B
A||B
Parameters // Conditional
A ? B : C
parameter N = 8;
localparam State = 2'd3;
Module
Assignments module MyModule
#(parameter N = 8) // Optional parameter
assign Output = A * B;
(input Reset, Clk,
assign {C, D} = {D[5:2], C[1:9], E};
output [N-1:0]Output);
// Module implementation
endmodule

Module Instantiation
// Override default parameter: setting N = 13
MyModule #(13) MyModule1(Reset, Clk, Result);
Case Generate
always @(*) begin genvar j;
case(Mux) wire [12:0]Output[19:0];
2'd0: A = 8'd9;
2'd1, generate
2'd3: A = 8'd103; for(j = 0; j < 20; j = j+1)
2'd2: A = 8'd2; begin: Gen_Modules
default:; MyModule #(13) MyModule_Instance(
endcase Reset, Clk,
end Output[j]
);
always @(*) begin end
casex(Decoded) endgenerate
4'b1xxx: Encoded = 2'd0;
4'b01xx: Encoded = 2'd1;
4'b001x: Encoded = 2'd2;
State Machine
4'b0001: Encoded = 2'd3; reg [1:0]State;
default: Encoded = 2'd0; localparam Start = 2'b00;
endcase localparam Idle = 2'b01;
end localparam Work = 2'b11;
localparam Done = 2'b10;

Synchronous reg tReset;


always @(posedge Clk) begin
if(Reset) B <= 0; always @(posedge Clk) begin
else B <= B + 1'b1; tReset <= Reset;
end
if(tReset) begin
State <= Start;
Loop
always @(*) begin end else begin
Count = 0; case(State)
for(j = 0; j < 8; j = j+1) Start: begin
Count = Count + Input[j]; State <= Idle;
end end
Idle: begin
Function State <= Work;
end
function [6:0]F; Work: begin
input [3:0]A; State <= Done;
input [2:0]B; end
begin Done: begin
F = {A+1'b1, B+2'd2}; State <= Idle;
end end
endfunction default:;
endcase
end
end

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