Logic and Computer Design Fundamentals

Chapter 3 – Combinational
Logic Design
Part 1 – Implementation Technology and Logic
Design
Charles Kime & Thomas Kaminski
© 2008 Pearson Education, Inc.
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Overview
 Part 1 – Design Procedure
• Steps
 Specification
 Formulation
 Optimization
 Technology Mapping
• Beginning Hierarchical Design
• Technology Mapping - AND, OR, and NOT to NAND
or NOR
• Verification
 Manual
 Simulation

Chapter 3 - Part 1 2
Overview (continued)
 Part 2 – Combinational Logic
• Functions and functional blocks
• Rudimentary logic functions
• Decoding using Decoders
 Implementing Combinational Functions with
Decoders
• Encoding using Encoders
• Selecting using Multiplexers
 Implementing Combinational Functions with
Multiplexers

Chapter 3 - Part 1 3
 Combinational Circuits
 A combinational logic circuit has:
• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
 A block diagram:
Combinatorial
Logic
Circuit

m Boolean Inputs n Boolean Outputs

Chapter 3 - Part 1 4
Design Procedure
1. Specification
• Write a specification for the circuit if one is not
already available
2. Formulation
• Derive a truth table or initial Boolean equations
that define the required relationships between the
inputs and outputs, if not in the specification
• Apply hierarchical design if appropriate
3. Optimization
• Apply 2-level and multiple-level optimization
• Draw a logic diagram or provide a netlist for the
resulting circuit using ANDs, ORs, and inverters

Chapter 3 - Part 1 5
Design Procedure
4. Technology Mapping
• Map the logic diagram or netlist to the
implementation technology selected
5. Verification
• Verify the correctness of the final design
manually or using simulation

Chapter 3 - Part 1 6
 Design Example
1. Specification
• BCD to Excess-3 code converter
• Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
• BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively
• Excess-3 code words for digits 0 through 9: 4-
bit patterns consisting of 3 (binary 0011) added
to each BCD code word
• Implementation:
 multiple-level circuit
 NAND gates (including inverters)
Chapter 3 - Part 1 7
 Design Example (continued)
2. Formulation
• Conversion of 4-bit codes can be most easily
formulated by a truth table
• Variables I nput BCD Output Excess-3
- BCD: A BC D WXYZ
A,B,C,D 0000 0011
• Variables 0001 0100
0010 0101
- Excess-3 0011 0110
W,X,Y,Z 0100 0111
• Don’t Cares 0101 1000
- BCD 1010 0110 1001
0111 1010
to 1111 1000 1011
1001 1100
Chapter 3 - Part 1 8
Design Example (continued)
C C
3. Optimization z 1 1
y 1 1
0 1 3 2 0 1 3 2

a. 2-level using 1
4 5 7
1
6
1
4 5
1
7 6

K-maps X X X X B X X X X B
12 13 15 14 12 13 15 14

W = A + BC + BD A 1
8 9
X
11
X
10
A 1
8 9
X
11
X
10

X = B C + B D + BC D D D
Y = CD + CD
Z=D x C C
1 1 1
w
0 1 3 2 0 1 3 2

1 1 1 1
4 5 7 6 4 5 7 6

X X X X B X X X X B
12 13 15 14 12 13 15 14

A 8
1
9
X
11
X
10
A 1
8
1
9
X
11
X
10

D Chapter 3 - D
Part 1 9
Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
W = A + BC + BD
X = B C + B D + BC D
Y = CD + C D
Z= D G = 7 + 10 + 6 + 0 = 23
• Perform extraction, finding factor:
T1 = C + D
W = A + BT1
X = B T1 + BC D
Y = CD + C D
Z= D G = 2 + 1 + 4 + 7 + 6 + 0 = 19
Chapter 3 - Part 1 10
 Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
T1 = C + D
W = A + BT1
X = B T1 + BCD
Y = CD + C D
Z =D G = 19
• An additional extraction not shown in the text since it
uses a Boolean transformation: ( CD = C + D = T1 ):
W = A + BT1
X = B T1 + B T1
Y = CD + T1
Z= D G = 2 +1 + 4 + 6 + 4 + 0 = 16!
Chapter 3 - Part 1 11
 Design Example (continued)
4. Technology Mapping
• Mapping with a library containing inverters and 2-input
NAND, 2-input NOR, and 2-2 AOI gates
A A
W
W

B X
B

X
C

C Y
D D Y
Z

Z
Chapter 3 - Part 1 12
 Beginning Hierarchical Design
 To control the complexity of the function mapping inputs to
outputs:
• Decompose the function into smaller pieces called blocks
• Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
• Any block not decomposed is called a primitive block
• The collection of all blocks including the decomposed ones is a
hierarchy
 Example: 9-input parity tree (see next slide)
• Top Level: 9 inputs, one output
• 2nd Level: Four 3-bit odd parity trees in two levels
• 3rd Level: Two 2-bit exclusive-OR functions
• Primitives: Four 2-input NAND gates
• Design requires 4 X 2 X 4 = 32 2-input NAND gates

Chapter 3 - Part 1 13
Hierarchy for Parity Tree Example
X0
X1
X2
X3 9-Input
X4 odd ZO
X5 function
X6 X0 A0
X7 3-Input
X8 X1 A1 odd B O
function
(a) Symbol for circuit X2 A2

X3 A0 A0
3-Input 3-Input
X4 A 1 odd B O A1 odd B
O ZO
function function
X5 A2 A2

X6 A0
3-Input
X7 A1 odd B O
function
X8 A2

(b) Circuit as interconnected 3-input odd

function blocks
A0
A1 BO

A2

(c) 3-input odd function circuit as

interconnected exclusive-OR
blocks

(d) Exclusive-OR block as interconnected

NANDs Chapter 3 - Part 1 14
 Reusable Functions
 Whenever possible, we try to decompose
a complex design into common, reusable
function blocks
 These blocks are
• verified and well-documented
• placed in libraries for future use

Chapter 3 - Part 1 15
Top-Down versus Bottom-Up
 A top-down design proceeds from an abstract, high-
level specification to a more and more detailed design
by decomposition and successive refinement
 A bottom-up design starts with detailed primitive blocks
and combines them into larger and more complex
functional blocks
 Design usually proceeds top-down to known building
blocks ranging from complete CPUs to primitive logic
gates or electronic components.
 Much of the material in this chapter is devoted to
learning about combinational blocks used in top-down
design.

Chapter 3 - Part 1 16
Technology Mapping
 Mapping Procedures
• To NAND gates
• To NOR gates
• Mapping to multiple types of logic blocks in
covered in the reading supplement:
Advanced Technology Mapping.

Chapter 3 - Part 1 17
Mapping to NAND gates
 Assumptions:
• Gate loading and delay are ignored
• Cell library contains an inverter and n-input NAND
gates, n = 2, 3, …
• An AND, OR, inverter schematic for the circuit is
available
 The mapping is accomplished by:
• Replacing AND and OR symbols,
• Pushing inverters through circuit fan-out points,
and
• Canceling inverter pairs

Chapter 3 - Part 1 18
NAND Mapping Algorithm
1. Replace ANDs and ORs:
. .
. .
. .

. .
. .
. .

2. Repeat the following pair of actions until there

is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.

. .
. .
. .

Chapter 3 - Part 1 19
NAND Mapping Example

Chapter 3 - Part 1 20
Mapping to NOR gates
 Assumptions:
• Gate loading and delay are ignored
• Cell library contains an inverter and n-input NOR
gates, n = 2, 3, …
• An AND, OR, inverter schematic for the circuit is
available
 The mapping is accomplished by:
• Replacing AND and OR symbols,
• Pushing inverters through circuit fan-out points,
and
• Canceling inverter pairs

Chapter 3 - Part 1 21
NOR Mapping Algorithm
1. Replace ANDs and ORs:
. .
. .
. .

. .
. .
. .

2. Repeat the following pair of actions until there

is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.

. .
. .
. .

Chapter 3 - Part 1 22
 NOR Mapping Example

A A
B
B
2
X
F 1
C F
C
3
D
D
E
(a) A E
(b)
B

C
F
D
E
(c)

Chapter 3 - Part 1 23
Verification
 Verification - show that the final circuit
designed implements the original specification
 Simple specifications are:
• truth tables
• Boolean equations
• HDL code
 If the above result from formulation and are
not the original specification, it is critical that
the formulation process be flawless for the
verification to be valid!

Chapter 3 - Part 1 24
Basic Verification Methods
 Manual Logic Analysis
• Find the truth table or Boolean equations for the final circuit
• Compare the final circuit truth table with the specified truth
table, or
• Show that the Boolean equations for the final circuit are equal
to the specified Boolean equations
 Simulation
• Simulate the final circuit (or its netlist, possibly written as an
HDL) and the specified truth table, equations, or HDL
description using test input values that fully validate
correctness.
• The obvious test for a combinational circuit is application of all
possible “care” input combinations from the specification

Chapter 3 - Part 1 25
Verification Example: Manual Analysis
 BCD-to-Excess 3 Code Converter
• Find the SOP Boolean equations from the final
circuit.
• Find the truth table from these equations
• Compare to the formulation truth table
 Finding the Boolean Equations:
T1 = C + D = C + D
W = A (T1 B) = A + B T1
X = (T1 B) (B C D) = B T1 + B C D
Y = C D + C D = CD + CD

Chapter 3 - Part 1 26
Verification Example: Manual Analysis
 Find the circuit truth table from the equations and compare
to specification truth table:
Input BCD Output Excess-3
AB C D WXYZ
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0101 1000
0110 1001
0111 1010
1000 1011
1001 1011
The tables match! Chapter 3 - Part 1 27
Verification Example: Simulation

 Simulation procedure:
• Use a schematic editor or text editor to enter
a gate level representation of the final circuit
• Use a waveform editor or text editor to enter
a test consisting of a sequence of input
combinations to be applied to the circuit
 This test should guarantee the correctness of the
circuit if the simulated responses to it are correct
 Short of applying all possible “care” input
combinations, generation of such a test can be
difficult

Chapter 3 - Part 1 28
 Verification Example: Simulation
 Enter BCD-to-Excess-3 Code Converter Circuit Schematic

AOI symbol
not available

Chapter 3 - Part 1 29
 Verification Example: Simulation
 Enter waveform that applies all possible input combinations:

INPUTS
A
B
C
D

0 50 ns 100 ns

 Are all BCD input combinations present? (Low is a 0 and high

is a one)

Chapter 3 - Part 1 30
 Verification Example: Simulation
 Run the simulation of the circuit for 120 ns
INPUTS
A
B
C
D
OUTPUTS
W
X
Y
Z

0 50 ns 100 ns
 Do the simulation output combinations match the original
truth table?
Chapter 3 - Part 1 31
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Chapter 3 - Part 1 32