2368 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO.

3, MARCH 2021

High-Efficiency Two-Stage Three-Level

Grid-Connected Photovoltaic Inverter
Jun-Seok Kim, Jung-Min Kwon , Member, IEEE, and Bong-Hwan Kwon, Member, IEEE

Abstract—This paper proposes a high-efficiency two- the grid from the PV source’s dc power is essential [4]. Gen-
stage three-level grid-connected photovoltaic (PV) inverter. erally, conventional two-level configuration circuits have been
The proposed two-stage inverter comprises a three-level used as grid-connected inverters in various industrial environ-
step-up converter and a three-level inverter. The three-level
step-up converter not only improves the power-conversion ments because of their simplicity [5]–[7]. However, these two-
efficiency by lowering the voltage stress but also guaran- level inverters require large filter values and high-voltage-rated
tees the balancing of the dc-link capacitor voltages using a semiconductor devices; they demonstrate drawbacks associated
simple control algorithm; it also enables the proposed in- with their filter sizes and power losses [8], [9]. To overcome
verter to satisfy the VDE 0126-1-1 standard of leakage cur-
these drawbacks, various multilevel inverters have been intro-
rent. The three-level inverter minimizes the overall power
losses with zero reverse-recovery loss. Furthermore, it re- duced; we defined the name of multilevel inverter from divided
duces harmonic distortion, the voltage ratings of the semi- grid voltage level before filtering step during half-cycle of grid
conductor device, and the electromagnetic interference by period. Such circuit configurations not only have small filters
using a three-level circuit configuration; it also enables the but they also improve power-conversion efficiency and qual-
use of small and low-cost filters. To control the grid current
ity with their reduced voltage stress and harmonic components
effectively, we have used a feed-forward nominal voltage
compensator with a mode selector; this compensator im- [10]–[12]. However, this only multilevel inverters require a high
proves the control environment by presetting the operating input voltage that covers the grid peak voltage. Therefore, a large
point. The proposed high-efficiency two-stage three-level number of series-connected PV modules are used to generate
grid-connected PV inverter overcomes the low efficiency the required high voltage; inverters with such a configuration
problem of conventional two-stage inverters, and it provides
are called single-stage inverters. These lots of series-connected
high-power quality with maximum efficiency of 97.4%. Us-
ing a 3-kW prototype of the inverter, we have evaluated the PV module configurations have several drawbacks such as the
performance of the model and proved its feasibility. imbalance of hot spots during partial shading, low safety fea-
tures, and poor maximum power point tracking (MPPT) perfor-
Index Terms—Transformerless, multilevel, dc-ac power
conversion, single-phase. mance [13]. For this reason, a dc–dc power-conversion stage
that increases a low PV-source voltage to a high dc-link volt-
I. INTRODUCTION age was added to the single-stage inverter. Inverters with this
NERGY consumption rises with the increase in industri- configuration are called two-stage inverters; these inverters can
E alization worldwide, thereby leading to sustained use of
fossil-fuel consumption [1]. Increasing carbon dioxide emis-
use the MPPT algorithm efficiently [14]–[17]. Thus, two-stage
inverters have the advantage of fewer series-connected PV mod-
sions caused by the fossil fuels have stimulated global warm- ules and higher MPPT performances in comparison with single-
ing, leading to grave environmental concerns [2]. To replace the stage inverters. These two-stage inverters can step up the volt-
energy generated from fossil fuels, photovoltaic (PV) power- age using a transformer. However, it is more advantageous to
generation systems can be used [3]. For such systems, design- eliminate the transformer because this would reduce the pro-
ing a grid-connected inverter that provides reliable ac power to duction cost and size and increase power efficiency [18], [19].
Therefore, transformerless two-stage inverters have become a
typical object of study as a grid-connected inverter circuit con-
Manuscript received April 27, 2021; revised July 12, 2021; accepted figuration. However, such inverters have two problems: leak-
July 30, 2021. Date of publication August 17, 2021; date of current ver-
sion December 15, 2021. This work was supported by the National age current and low efficiency. Depending on the switching
Research Foundation of Korea (NRF) grant by the Korean Government strategy and the topology, the common mode voltage appears
(MISP) (NRF-2016R1C1B1014543). (Corresponding author: Jung-Min between the PV source and the ground, and it injects leakage
Kwon.)
J.-S. Kim and B.-H. Kwon are with the Department of Electronic and current through a parasitic capacitor, thereby causing power
Electrical Engineering, Pohang University of Science and Technology, losses, low grid-power quality, severe electromagnetic interfer-
Pohang 790-784, South Korea (e-mail: wnstjrdl1206@postech.ac.kr; ence (EMI), and personal-safety problems [20]. As such, the
bhkwon@postech.ac.kr).
J.-M. Kwon is with the Department of Electrical Engineering, Hanbat leakage current should be limited to below the VDE 0126-1-1
National University, Daejeon 305-719, South Korea (e-mail: jmkwon@ standard of 300 mA. Therefore, transformerless two-stage in-
hanbat.ac.kr). verters should be able to limit the leakage current to be less
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. than 300 mA, and the efficiency problem should also be im-
Digital Object Identifier 10.1109/TIE.2021.2740835 proved; two-stage inverters have low efficiency problem because

0278-0046 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
KIM et al.: HIGH-EFfiCIENCY TWO-STAGE THREE-LEVEL GRID-CONNECTED PHOTOVOLTAIC INVERTER 2369

Fig. 1. Proposed high-efficiency two-stage three-level grid-connected PV inverter circuit diagram.

tem, the use of a feed-forward nominal voltage compensator

with the mode selector algorithm ensures high-grid power qual-
ity without high computational burden or control complexity. In
this paper, the operational principles of the proposed two-stage
inverter are discussed in detail, and high-frequency analysis and
simulation results are presented. In addition, we use the experi-
mental results for a 3-kW prototype to demonstrate the validity
of the proposed system.

Fig. 2. Circuit diagram of dc–dc power conversion stage. (a) Proposed

converter. (b) Conventional converter.
II. OPERATIONAL PRINCIPLES AND CONTROL ALGORITHM OF
THE PROPOSED TWO-STAGE INVERTER

of their each low efficiencies of two separate power-processing The proposed two-stage inverter is composed of a three-level
stages. step-up converter and a three-level inverter, as shown in Fig. 1.
This paper proposes a high-efficiency two-stage three-level The proposed three-level step-up converter performs MPPT and
grid-connected PV inverter. The proposed inverter solves two balances the dc-link capacitor voltages Vdc1 and Vdc2 . Unlike
main problems of transformerless two-stage inverters; it not only conventional step-up converters, as shown in Fig. 2, the input
limits the leakage current to less than 300 mA, but also provides capacitor is split into two halves. The midpoints of the input
high power-conversion efficiency by ensuring high efficiency of capacitors and the dc-link capacitors are directly connected.
each stage. As shown in Fig. 1, the proposed two-stage inverter The proposed three-level inverter controls the grid current ig ;
comprises a three-level step-up converter and a three-level in- the reverse-recovery problems of the switches are reduced by
verter. The input capacitor of the three-level step-up converter the advantages of the proposed circuit configuration.
is split into two halves, and the midpoint of the input capacitors
and the midpoint of the dc-link capacitors are directly connected.
This connection enables the proposed two-stage inverter to limit A. Proposed Three-Level Step-Up Converter
the leakage current to less than 300 mA. Also, as dc–dc power For the proposed three-level step-up converter, Fig. 3
conversion stage, the proposed three-level step-up converter not shows the equivalent circuits of each operating mode, and
only improves the power-conversion efficiency with reduced Figs. 4 and 5 indicate block diagram of control algorithm
voltage stress but also guarantees the balancing of the dc-link and theoretical waveforms. The proposed step-up converter, as
capacitor voltages by means of a simple control algorithm. Fur- shown in Fig. 2(a), comprises two input capacitors C1 and C2 ,
thermore, as dc–ac power conversion stage, the proposed three- two input inductors L1 and L2 , two primary switches S1p and
level inverter minimizes the overall power loss by reducing the S2p , two primary diodes D1p and D2p , and two dc-link capacitors
reverse-recovery problems of the metal–oxide–semiconductor Cdc1 and Cdc2 . To simply analyze the converter, the half of dc-
field-effect transistor (MOSFET) body diodes; this inverter also link voltages Vdc1 and Vdc2 is given the same value Vdc /2 with
reduces voltage ratings, harmonic components, and EMI, and the steady-state condition. As shown in Fig. 5, S1p and S2p have
allows the use of small and low-cost filters. For the control sys- the same step-up duty ratio D with a 180◦ phase difference.
2370 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2021

The voltage vS 1 across S1p during one switching period is

defined as follows:
⎧
⎪
⎨ 0, for S1p on-time
vS 1 (t) = V (0 ≤ t < Ts ) (1)
⎪
⎩ dc , for S1p off-time
2
where Ts is switching period. The on-time is DTs , and the
off-time is (1 − D)Ts . In Fig. 1, by using (1) and Kirchhoff’s
voltage law, the following equation can be derived:
diL 1
L1 = vC 1 − v S 1 . (2)
dt
Here, L1 is the inductance for the input inductor L1 , iL 1 is the
inductor current for L1 , vC 1 is the capacitor voltage for the input
capacitor C1 . Given this dc–dc power-conversion condition, (2)
can be written as
 Ts
0= (vC 1 − vS 1 )dt. (3)
0
Fig. 3. Operation circuit diagrams of the proposed three-level step-up
converter.
Therefore, the average top input-capacitor voltage VC 1 for vC 1
over one switching period Ts can be calculated as
 Ts  Ts
1 1
VC 1 = vC 1 dt = vS 1 dt (4)
Ts 0 Ts 0
 Ts  Ts
1 1 Vdc Vdc
VC 1 = vS 1 dt = dt = (1 − D).
Ts 0 Ts D T s 2 2
(5)
Since both S1p and S2p have the same step-up duty ratio D,
the average bottom input-capacitor voltage VC 2 for vC 2 has the
same value as that in (5). The sum of VC 1 and VC 2 is equal to the
PV source voltage VPV ; therefore, the average input-capacitor
voltages VC 1 and VC 2 for the input capacitors C1 and C2 can be
expressed as
VPV
VC 1 = VC 2 = . (6)
2
From (6), it is seen that the PV source voltage is equally divided
between the input capacitors C1 and C2 . Thus, the step-up duty
ratio D of S1p and S2p is
VPV
D =1− . (7)
Vdc
As shown in Fig. 3, the converter can operate in four modes.
The four modes are described below, and the inductances L1
Fig. 4. Control algorithm block diagram of the three-level step-up and L2 have the same value Li for simple analysis.
converter. M ode 1 [t0 − t1 ]: During M ode 1, only S1p is turned on.
The energy from the PV source is stored in L1 . The current iL 1
flowing through L1 increases as follows:
VP V
iL 1 (t) = iL 1 (t0 ) + (t − t0 ). (8)
2Li
Whereas the current iL 2 flowing through L2 decreases as
follows:
Vdc − VP V
iL 2 (t) = iL 2 (t0 ) − (t − t0 ). (9)
2Li
Fig. 5. Theoretical waveforms of the proposed three-level step-up M ode 2 [t1 − t2 ]: In this mode, both S1p and S2p are turned
converter. (a) D < 0.5. (b) D > 0.5. OFF. The energy stored in L1 and L2 is transferred to the dc-link
KIM et al.: HIGH-EFfiCIENCY TWO-STAGE THREE-LEVEL GRID-CONNECTED PHOTOVOLTAIC INVERTER 2371

Fig. 6. Simple simulation result to verify the validity of balancing duty ratio Δd for balancing of v C 1 and v C 2 and V d c 1 and V d c 2 . (a) Control
algorithm result with balancing duty ratio Δd. (b) Control algorithm result without balancing duty ratio Δd.

capacitors Cdc1 and Cdc2 , respectively. In this mode, iL 1 and iL 2 Because C1 and C2 have the same value (C1 = C2 = Ci ) for
decrease with the slope given in (9). The converter can be in simple analysis, (12)–(14) can be rearranged as
M ode 2 only if D is less than 0.5.
iC 1 = − iC 2 (15)
M ode 3 [t2 − t3 ]: In this interval, only S2p is turned ON,
and the energy from the PV source is stored in L2 . Thus, the iL 1 + iL 2
iPV = . (16)
current iL 2 increases with the slope given in (8). The current 2
iL 1 decreases with the slope given in (9). By using (13) and (16), top input-capacitor current iC 1 is derived
M ode 4 is enacted only if D is greater than 0.5. Positive volt- as
ages are applied to both L1 and L2 during this mode; therefore,  
iL 2 − iL 1 dvC 1
the inductor currents increase with the slope VPV /2Li . iC 1 = = C1 . (17)
2 dt
Fig. 4 shows the control algorithm of the three-level step-up
converter. The converter performs MPPT with a step-up duty Also, by using (8), (9), and (17), the variation of top input-
ratio D and uses the balancing duty ratio Δd to balance the capacitor voltage ΔvC 1 during one switching period can be
dc-link capacitor voltages. The simple P&O method described calculated as
in [21] is used to extract the maximum power from the PV 1
ΔiC 1 = DTs (Vdc2 − Vdc1 ) + ΔdTs (−Vdc1 − Vdc2 )
sources. This MPPT algorithm directly provides the step-up 2Li
duty ratio D from the PV source voltage VPV and current iPV .

+ Ts (vC 2 − vC 1 + Vdc1 − Vdc2 ) . (18)

Meanwhile, the balancing duty ratio Δd is generated by the
dc-link balancing control component as follows: Ts ΔiC 1
ΔvC 1 = . (19)
C1
Δd  kp,balancing (Vdc1 − Vdc2 ) (10) These (18) and (19) mean that the balancing duty ratio Δd also
control the input-capacitor voltages, as shown in Fig. 6; we used
where kp,balancing is the proportional gain of the dc-link voltage the power simulator (PSIM). Therefore, by using the balancing
balancing controller, and Vdc1 and Vdc2 are the half of dc-link duty ratio Δd, the proposed balancing algorithm can balance
voltages. Thus, the switches S1p and S2p are driven by the duty not only Vdc1 and Vdc2 but also vC 1 and vC 2 .
ratios d1 and d2 , as shown in Fig. 4.
The PV source voltage VPV can be considered as constant B. Proposed Three-Level Inverter
during switching period Ts . Therefore, the primary differential
value of VPV can be calculated as The proposed inverter, for dc–ac power conversion stage, as
shown in Fig. 1, comprises two dc-link capacitors Cdc1 and Cdc2 ,
VPV = vC 1 + vC 2 (11) two diodes D1 and D2 , four high-frequency switches S1 –S4 ,
two hybrid switches S5 and S6 , and one filter inductor Lf . This
dvC 1 dvC 2 inverter’s topology comprises two legs: one leg has two hybrid
0= + . (12)
dt dt switches, and the other leg has a three-level voltage cell. The
two hybrid switches S5 and S6 are turned ON alternately during
Also, the input current iPV can be derived as follows by one grid period; the bottom hybrid switch S6 is turned ON during
using (12): the positive half-cycle of the grid voltage, and the top hybrid
switch S5 is turned ON during the negative half-cycle. A three-
dvC 1
iPV = iL 1 + C1 (13) level voltage cell operates at a high frequency and provides three
dt voltage levels.
dvC 2 dvC 1 S1 and S3 operate complementarily to each other. S2 and
iPV = iL 2 + C2 = iL 2 − C2 . (14)
dt dt S4 also operate in such a manner. Therefore, just two duty
2372 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2021

Fig. 7. Operation circuit diagrams of the proposed three-level inverter under the following conditions: (a) vc d = V d c at mode 1 (ig > 0).
(b) v c d = V d c /2 at mode 1 or mode 2 (ig > 0). (c) v c d = 0 at mode 2 (ig > 0). (d) v c d = −V d c at mode 4 (ig < 0). (e) v c d = −V d c /2 at mode 4 or
mode 3 (ig < 0). (f) v c d = 0 at mode 3 (ig < 0). Current flows only along the black lines.

ratios are required to control the proposed inverter; the nom-

inal duties Dn 1 and Dn 2 are the duty ratios of S1 and
S2 , respectively. As shown in Fig. 7, there are six possible
switching states. Since the repeated zero voltage level is counted
as one level, total five different voltage levels are provided at
vcd , namely Vdc , Vdc /2, 0, −Vdc /2, and −Vdc , where Vdc is the
dc-link voltage. Thus, the grid voltage vg can be divided into
four sections based on the five voltage levels, and these sections
determine the switching modes: mode 1, Vdc /2 ≤ vg < Vdc ;
mode 2, 0 ≤ vg < Vdc /2; mode 3, −Vdc /2 ≤ vg < 0; and mode
4, −Vdc < vg ≤ −Vdc /2. To select the mode, those voltages
need to be compared. This selection process is performed by the
mode selector shown in Fig. 8.
In mode 1, at a high frequency, S1 and S3 operate complemen-
tarily. Fig. 7(a) and (b) shows the operation circuit diagrams of
mode 1. During the ON and OFF states of S1 , the inductor voltage
vL is obtained as

vL = Vdc − vg , for the on-state of S1 (20)

Vdc
vL = − vg , for the off-state of S1 (21)
2

where vL > 0 in the on-state, and vL < 0 in the off-state; mode

1 has the operation voltage range Vdc /2 < vg < Vdc . By the
Fig. 8. Control algorithm block diagram of the three-level inverter.
principle of inductor volt-second balance, the nominal duty Dn 1
of S1 can be obtained as
In contrast, during mode 1, S2 has the fixed duty ratio Dn 2
 
Vdc tsw2on Ts
Dn 1 (Vdc − vg ) + (1 − Dn 1 ) − vg =0 (22) Dn 2 = = =1 (24)
2 Ts Ts
2vg where tsw2on is the S2 on-time during the switching period, and
Dn 1 = − 1. (23)
Vdc Ts is the switching period. By the same above processes, two
KIM et al.: HIGH-EFfiCIENCY TWO-STAGE THREE-LEVEL GRID-CONNECTED PHOTOVOLTAIC INVERTER 2373

duty ratios in all modes can be obtained as

2vg
Dn 1 = − 1, Dn 2 = 1, for mode 1 (25)
Vdc
2vg
Dn 1 = 0, Dn 2 = , for mode 2 (26)
Vdc
2vg
Dn 1 = + 1, Dn 2 = 1, for mode 3 (27)
Vdc
2vg
Dn 1 = 0, Dn 2 = + 2, for mode 4 (28)
Vdc
where the duty ratio Dn 3 of S5 is 0 at vg ≥ 0 and 1 at vg < 0.
To control the grid current ig , the control duty ΔD must be
added to the nominal duty. The switching frequency fs is much
higher than the grid frequency fg . Therefore, the grid voltage
vg can be considered to have a constant voltage during the
switching period Ts . In mode 1, the averaged current equation
for the filter inductor Lf over one switching period can be derived
as
 
Vdc Δig Fig. 9. High-frequency modeling equivalent circuit of the proposed two-
Df (Vdc − vg ) + (1 − Df ) − vg = Lf (29) stage inverter. (a) High-frequency equivalent circuit. (b) Thevenin model.
2 Ts
where Df is the final control duty, and Δig is the variation of
the grid current. The above averaged current equation can be
rearranged as
 
2vg 2Lf Δig
Df = −1 + . (30)
Vdc Vdc Ts
The first term in (30) is the same as the nominal Dn 1 during
mode 1 switching operation. Thus, the second term in the above
equation can be defined as
2Lf Δig
ΔD  . (31)
Vdc Ts
As a result of two re-expressed terms, (30) can be expressed as
the sum of two duty terms
Df = Dn 1 + ΔD. (32)
The second term ΔD directly contributes to grid current control; Fig. 10. Bode plot of LC filter circuit of Fig. 9(b) for open-circuit voltage
this term is used to track the grid current reference i∗g and is of voltage source v bn .
obtained from a current controller. For all the four modes, ΔD
is computed in exactly the same way.
reverse-recovery loss because of the characteristics of Schottky
In view of the overall inverter system, the control block di-
diodes; they do not have a recovery time. Therefore, the pro-
agram of the proposed inverter is shown in Fig. 8. The devel-
posed three-level inverter has only to consider the power losses
oped final control duty Df comprises the nominal duty Dn 1
without the consideration of reverse-recovery losses.
(or Dn 2 ) and the control duty ΔD. Dn 1 (or Dn 2 ) is used as
the feed-forward nominal voltage compensator, and it improves
III. HIGH-FREQUENCY MODEL AND SIMULATION RESULT FOR
the control environment by presetting the operating point. ΔD
directly contributes to grid current control and is used to track LEAKAGE CURRENT ANALYSIS
the grid current reference i∗g . As a result of these developed Limiting leakage current is an important factor to develop
controllers, the proposed inverter performs precise reference a high-performance transformerless PV inverter. Therefore, in
current tracking. Furthermore, the proposed three-level inverter this section, high-frequency models for the proposed two-stage
reduces the reverse-recovery loss problem by the advantages of inverters are analyzed to verify the validity of the proposed
the proposed circuit configuration. As shown in Fig. 7, S1 –S4 inverter. The value of the leakage current ip depends on the rate
have few reverse-recovery losses because they do not utilize the of change in the common mode voltage vp across the parasitic
body diodes in unity power factor. Also, two hybrid switches of capacitor Cp with respect to time, that is, dvP /dt.
S5 and S6 have no reverse-recovery losses since even they oper- A high-frequency modeling equivalent circuit for leakage cur-
ate at a grid frequency fg . Two diodes D1 and D2 also have zero rent analysis of the proposed inverter is obtained as shown in
2374 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2021

Fig. 12. Bode plot of filter circuit of Fig. 11(b) for open-circuit voltage
of voltage source v an .

Fig. 11. High-frequency modeling equivalent circuit of two-stage in-

verter using a conventional three-level step-up converter of Fig. 2(b)
as dc–dc power conversion stage. (a) High-frequency equivalent circuit.
(b) Thevenin model.

Fig. 9(a). The high-frequency voltage van between node a and

node n, which is the midpoint of the two dc-link capacitors,
is determined on the basis of the switching operations of the
primary switch S1p
⎧
⎨ 0, for S1p on-time
van = Vdc (33)
⎩ , for S1p off-time.
2

Also, the high-frequency voltage vbn between node b and node

n is determined based on the switching operation of the primary Fig. 13. Bode plot of filter circuit of Fig. 11(b) for open-circuit voltage
switch S2p of voltage source v bn .
⎧
⎨ 0, for S2p on-time
vbn = (34)
⎩ − Vdc , for S2p off-time.
TABLE I
PARAMETERS AND COMPONENTS OF PROTOTYPE
2

Meanwhile, in the inverter stage, the three-level high-frequency Parameters Symbols Value
voltage vnc between node n and node c is determined based Rated power Po 3 kW
on the three-level switching operation of four high-frequency PV voltage V PV 180–350 V
switches S1 –S4 DC-link voltage Vd c 350 V
Grid voltage vg 220 Vrms
⎧ Switching frequency fs 20 kHz
⎪ V
⎪ − dc , for S1 and S2 on-time
⎪ Grid frequency fg 60 Hz
⎪
⎨ 2 Input capacitances C1 , C2 6.6 µF
vnc (t) = 0, for S2 and S3 on-time (35) Input inductances L1 , L2 0.25 mH
⎪
⎪ DC-link capacitance Cd c 1 , Cd c 2 2.04 mF
⎪
⎪ V
⎩ dc , for S3 and S4 on-time.
Filter inductance Lf 1 mH
Components Symbols Part number
2 High-frequency switches S1p , S2p , and S1 –S4 IRFP4668PbF
Hybrid switches S5 , S6 FCA76N60N
Also, the hybrid voltage vnd between node n and node d is Diodes D1p , D2p , D1 , and D2 DSSK60-02A
determined based on the hybrid switching operation of the two
KIM et al.: HIGH-EFfiCIENCY TWO-STAGE THREE-LEVEL GRID-CONNECTED PHOTOVOLTAIC INVERTER 2375

Fig. 16. Experimental results for the input voltage V PV , three-level

Fig. 14. Simulation results for the leakage current of the proposed
voltage v c d , grid voltage v g , and grid current ig under the rated load
two-stage inverter.
condition.

Fig. 15. Simulation results for the leakage current using a conventional
three-level step-up converter of Fig. 2(b) as dc–dc power conversion Fig. 17. Experimental results for the dc-link voltage V d c and the dc-link
stage of two-stage inverter. capacitor voltages V d c 1 and V d c 2 during steady-state condition.

hybrid switches S5 and S6 The parasitic capacitances in the PV panel can be split into
⎧ three parts: cell-to-frame capacitance Ccf ; cell-to-rack capaci-
⎪ Vdc
⎨ , (vg > 0) tance Ccr ; and cell-to-ground capacitance Ccg . This paper uses
vnd (t) = 2 (36)
⎪ characteristics of these parasitic parameters of glass-faced pan-
⎩ − Vdc , (vg < 0). els. For a glass-faced panel with 50-mm cell-to-ground distance,
2
the total parasitic capacitance Cp is approximately 2.95 nF/kW
Unlike the high-frequency voltages van , vbn , and vnc , which [22]. The grounding resistance Rg is usually not zero; it is 15 Ω,
have the switching frequency, vnd has the grid frequency. By as considered in [23]. Thus, at the proposed two-stage inverter
the superposition principle and Thevenin’s theorem, the high- operation, the leakage current ip and the common mode voltage
frequency voltage sources van and vnc do not affect vp . Only vnd vp across the parasitic capacitor Cp can be simulated by using

and vbn affect the common mode voltage vp ; vbn is filtered by PSIM, as shown in Fig. 14. The simulation conditions are as
the LC low-pass filter and is obtained from the high-frequency follows: PV voltage VPV = 180 V, dc-link voltage Vdc = 350 V,
voltage vbn , as shown in Fig. 9(b). By using MATLAB, as shown parasitic capacitance CP = 10 nF, grounding resistance Rg =
in Fig. 10, it is checked that the open-circuit voltage of vbn is fil- 15 Ω, respective input and filter inductances Li = 0.25 mH and
tered by low-pass filter (Transfer function = 1/(1 + L2 C2 s2 )). Lf = 1 mH, rated power Prated = 3 kW, and grid voltage vg =
However, when a conventional three-level step-up converter in 220 Vrms . The detailed system conditions are listed in Table I. In
Fig. 2(b) operates at the dc–dc power conversion stage, the fil- this simulation result, the leakage current iP is quite low, with
ter cannot work as low-pass filter because there is no midpoint a measured rms value of 7 mA that satisfies the leakage current
connection. Thus, the high-frequency components of vbn and standards VDE-0126-1-1. However, as shown in Fig. 15, when a
even van is added to the common mode voltage vp , as shown in conventional three-level step-up converter in Fig. 2(b) operates
Fig. 11(b); it can be checked at bode plot of Fig. 12 at the dc–dc power conversion stage, vP changes rapidly on the
and Fig. 13. basis of the high-frequency switching operation. Therefore, a
2376 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2021

voltage Vdc and the half of dc-link voltages Vdc1 and Vdc2 during
steady-state condition. As shown in this figure, the dc-link volt-
age Vdc is divided equally between the input capacitors Cdc1 and
Cdc2 ; the difference between Vdc1 and Vdc2 is almost zero. From
Fig. 17, it can be observed that the proposed topology can well
balance the dc-link capacitor voltages with the proposed simple
balancing algorithm of the three-level step-up converter. Fig. 18
shows the experimental results of common mode voltage vP and
the leakage current iP . As shown in Fig. 18, the proposed in-
verter has only grid frequency voltage variation, which occurred
at the parasitic capacitor Cp . Consequently, the leakage current
iP is low with a maximum measured rms value of 70 mA, which
satisfies the leakage current standards VDE-0126-1-1. The ex-
Fig. 18. Experimental results for the common mode voltage v P and perimental results show that the high-frequency switching oper-
the leakage current iP .
ation of the proposed inverter does not affect the common mode
voltage vP . Therefore, the leakage current iP is significantly re-
duced; this feasibility is also verified in Section III. Finally, with
the rated PV voltage of 180 V, the measured efficiency of the
proposed inverter under each load condition is shown in Fig. 19.
This experimental results verify that the proposed inverter even
provides high efficiency. The measured maximum efficiency
is 97.4%.

V. CONCLUSION
A high-efficiency two-stage three-level grid-connected PV
inverter and control system were introduced. Also, a theoretical
analysis was provided along with the experimental results. By
using the novel circuit configuration, the proposed two-stage in-
verter performs power conversion with low leakage current and
high efficiency; in dc–dc power conversion stage, the connection
of midpoints of capacitors enables the proposed two-stage in-
Fig. 19. Measured efficiency of the proposed inverter under each load verter to limit the leakage current below 300 mA; in dc–ac power
condition.
conversion stage, the overall power losses were minimized by
eliminating the reverse-recovery problems of the MOSFET body
diodes. Besides, the proposed inverter with three voltage levels
severe leakage current occurs in this conventional circuit con- reduces the power losses, harmonic components, voltage ratings,
figuration, which cannot satisfy the standards VDE-0126-1-1. and EMI; it also enables using small and low-cost filters. For
the control system, the feedforward nominal voltage compen-
IV. EXPERIMENTAL RESULT sator also improves the control environment by presetting the
The prototype for the proposed inverter shown in Fig. 1 is operating point. This developed control algorithm makes the
implemented to show the validity of the system. The PV voltage proposed inverter feasible. Thus, the proposed high-efficiency
VPV , the dc-link voltage Vdc , the grid voltage vg , the switching two-stage three-level grid-connected PV inverter provides high-
frequency fs , the grid frequency fg , and the rated power Po power quality with high power-conversion efficiency. By using
are 180 V, 350 V, 220 Vrms , 20 kHz, 60 Hz, and 3 kW, respec- a 3-kW prototype, this experiment verified that the proposed
tively. For the glass-faced PV panel with 50-mm cell-to-ground inverter has high efficiency, and the developed control system is
distance, the total parasitic capacitance Cp is set to 10 nF. A suitable for the proposed inverter.
resistance of 15 Ω is connected in series with the leakage capac-
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