MITSUBISHI ICS (TV)

M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M64894 is a semiconductor integrated circuit consisting of
PLL frequency synthesizer for TV/VCR using I 2C BUS control. It
contains the prescaler with operating up to 1.3GHz, 4 band drivers
PRESCALER fin 1 16 Xin CRYSTAL
and tuning Amplifier for direct tuning. Built-in 4 band drivers. INPUT OSCILLATOR
GND GND 2 15 ADS CHIP ADDRESS
INPUT
SUPPLY

M64894FP/GP
FEATURES VOLTAGE 1
VCC1 3 14 SDA DATA INPUT
SUPPLY
• 4 integrated PNP band drivers VOLTAGE 2
VCC2 4 13 SCL CLOCK INPUT
(Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V)
BS4 5 12 ADC A/D INPUT
• Built-in high-withstanding voltage tuning Amplifier SUPPLY
BAND BS3 6 11 VCC3
• Low power dissipation (Icc=20mA, Vcc=5V) SWITCHING VOLTAGE 3
TUNING
• Built-in prescaler with input amplifier (Fmax=1.3GHz) OUTPUTS BS2 7 10 Vtu
OUTPUT
• I2C bus control (Read and write mode) BS1 8 9 Vin FILTER INPUT
• X’tal 4MHz is used to realize 3 type of tuning steps
(Division ratio 1/512, 1/640, 1/1024) Outline 16P2S-A (FP)
• Built-in 5-level A/D converter 16P2Z-A (GP)
• Programmable chip address
• 16-pin small SOP/SSOP package

APPLICATION
TV, VCR tuners

FUNCTION
RECOMMENDED OPERATING CONDITION • 2-modulus prescaler (1/32 and 1/33)
Supply voltage range..............................................V CC1=4.5 to 5.5V • Built-in 4MHz crystal oscillator and reference divider
VCC2=VCC1 to 13.2V • Programmable divider (10-bit M counter, 5-bit S counter)
VCC3=28 to 35V • Tri-state phase comparator
Rated supply voltage...........................................................V CC1=5V
• Lock detector
• Band switch driver
VCC2=12V
• Op. Amp for direct tuning
VCC3=33V • I2C bus receiver
• 5-level A/D converter

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 MITSUBISHI ICS (TV)

M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

BLOCK DIAGRAM
CRYSTAL CHIP ADDRESS CLOCK SUPPLY TUNING FILTER
OSCILLATOR INPUT DATA INPUT INPUT A/D INPUT VOLTAGE 3 OUTPUT INPUT

X in ADS SDA SCL ADC VCC3 Vtu Vin

16 15 14 13 12 11 10 9

5-LEVEL
A/D C
OSC I C RECEIVER
2

DIVIDER
10
LOCK
10-BIT M COUNTER DETECTOR AMP

1/32,1/33
5
PHASE CHARGE
5-BIT S COUNTER PUMP
COMPARATOR

4
1/8 P.O
BIAS BAND DRIVER
RESET

AMP

1 2 3 4 5 6 7 8
f in GND VCC1 VCC2 BS4 BS3 BS2 BS1

PRESCALER SUPPLY SUPPLY BAND SWITCHING

INPUT VOLTAGE 1 VOLTAGE 2 OUTPUTS

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 MITSUBISHI ICS (TV)

M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

DESCRIPTION OF PIN
Pin No. Symbol Pin name Function
1 fin Prescaler input Input for the VCO frequency.
2 GND GND Ground to 0V.
3 VCC1 Power supply voltage 1 Power supply voltage terminal. 5.0V ±0.5V
4 VCC2 Power supply voltage 2 Power supply for band switching, Vcc 1 to 13.2V
5 BS4
PNP open collector method is used.
6 BS3
Band switching outputs When the band switching data is "H", the output is ON.
7 BS2
When it is "L", the output is OFF.
8 BS1
This is the output terminal for the LPF input and charge pump output. When the
phase of the programmable divider output (f 1/N) is ahead compared to the
Filter input
9 Vin reference frequency (fref), the "source" current state becomes active.
(Charge pump output) If it is behind, the "sink" current becomes active.
If the phases are the same, the high impedance state becomes active.
10 Vtu Tuning output This supplies the tuning voltage.
11 VCC3 Power supply voltage 3 Power supply voltage for tuning voltage 28 to 35V
A/D conversion of the input voltage.
AD converter input/
12 ADC/ftest In control byte data input, the programmabule freq. Divider output and reference
Test port freq. output is selected by the test mode.
13 SCL Clock input Data is read into the shift register when the clock signal falls.
Input for band SW and programmable freq. divider set up.
14 SDA Data input In lead mode, itoutputs lock detector output and power down flagand a state of 5
level A/D converter.
15 ADS Address switching input Chip address sets it up with the input condition of terminal.
This is connected to the
16 Xin 4.0MHz crystal oscillator is connected.
crystal oscillator

ABSOLUTE MAXIMUM RATINGS (Ta=-20°C to +75°C, unless otherwise noted)

Symbol Parameter Conditions Ratings Unit
VCC1 Supply voltage 1 Pin3 6.0 V
VCC2 Supply voltage 2 Pin4 14.4 V
VCC3 Supply voltage 3 Pin11 36.0 V
VI Input voltage Not to exceed VCC1 6.0 V
VO Output voltage fREF output 6.0 V
Voltage applied when the band output is
VBSOFF 14.4 V
OFF
IBSON Band output current Per 1 band output circuit 50.0 mA
50mA per 1 band output circuit
tBSON ON the time when the band output is ON 10 sec
3circuit are pn at same time
Pd Power dissipation Ta=+75°C 450 (470) mW
Topr Operating temperature -20 to +75 °C
Tstg Storage temperature -40 to +125 °C

RECOMMENDED OPERATING CONDITIONS (Ta=-20°C to +75°C, unless otherwise noted)

Symbol Parameter Conditions Ratings Unit
VCC1 Supply voltage 1 Pin3 4.5 to 5.5 V
VCC2 Supply voltage 2 Pin4 VCC1 to 13.2 V
VCC3 Supply voltage 3 Pin11 28 to 35 V
fopr1 Operating frequency (1) Crystal oscillation circuit 4.0 MHz
fopr2 Operating frequency (2) 80 to 1,300 MHz
Normally 1 circuit is on. 2 circuits on at the
IBDL Band output current 5 to 8 same time is max. It is prohibited to have 0 to 40 mA
3 or more circuits turned on at the same time.

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 MITSUBISHI ICS (TV)

M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

ELECTRICAL CHARACTERISTICS (Ta=-20°C to +75°C, Vcc1=5.0V, Vcc2=12V, Vcc3=33V, unless otherwise noted)
Limits
Symbol Parameter Test pin Test conditions Unit
Min. Typ. Max.
VIH “H” input voltage 13 to 14 3.0 − VCC1+0.3 V
VIL “L” input voltage 13 to 14 − − 1.5 V
Input pin
IIH “H” input current 13 to 14 VCC1=5.5V, Vi=4.0V − − 10 µA
IIL “L” input current 13, 14 VCC1=5.5V, Vi=0.4V − -4/-14 -10/30 µA
VOL SDA “H” output voltage 14 VCC1=5.5V, Io=3mA − − 0.4 µA
VLO output “L” output voltage 14 VCC1=5.5V, Vo=5.5V − − 10 µA
VBS Band Output voltage 5 to 8 VCC2=12V, Io=-40mA 11.6 11.8 − V
IOLK1 SW Leak current 5 to 8 VCC2=12V band SW is OFF − − -10 µA
VTOH Tuning Output voltage “H” 10 VCC3=33V 32.5 − − V
VTOL output Output voltage “L” 10 VCC3=33V − 0.2 0.4 V
IOH “H” output current 9 VCC1=5.0V, Vo=2.5V − ±270 ±370 µA
Charge
IOL “L” output current 9 VCC1=5.0V, Vo=2.5V − ±70 ±110 µA
pump
ICPLK Leak current 9 VCC1=5.5V, Vo=2.5V − − ±50 nA
ICC1 Supply current 1 3 VCC1=5.5V − 20 30 mA
ICC2A 4 circuits: OFF 4 VCC2=12V − − 0.3 mA
Supply 1 circuits: ON,
ICC2B 4 VCC2=12V − 6.0 8.0 mA
current 2 Output: OPEN
ICC2C Output current 40mA 4 VCC2=12V Io=-40mA − 46.0 48.0 mA
ICC3 Supply current 3 11 VCC3=33V Output ON − 3.0 4.0 mA

Note. Typical values are measured at VCC1=5.0V, VCC2=12V, VCC3=33V, Ta=+25°C.

SWITCHING CHARACTERISTICS (Ta=-20°C to +75°C, VCC1=5.0V, VCC2=12V, VCC3=33V, unless otherwise noted)
Limits
Symbol Parameter Test pin Test conditions Unit
Min. Typ. Max.
VCC1=4.5 to 5.5V
fopr Prescaler operating frequency 1 80 − 1300 MHz
Vin=Vinmin to Vinmax
80 to 100MHz -24 − 4
100 to 200MHz -27 − 4
VCC1=4.5
Vin Operating input voltage 1 200 to 800MHz -30 − 4 dBm
to 5.5V
800 to 1000MHz -27 − 4
1000 to 1300MHz -18 − 4
tSCL Clock pulse frequency 13 VCC1=4.5 to 5.5V 0 − 100 kHz
tBUF Bus free time 14 VCC1=4.5 to 5.5V 4.7 − − µs
tHDSTA Data hold time 13 VCC1=4.5 to 5.5V 4 − − µs
tLOW SCL low hold time 13 VCC1=4.5 to 5.5V 4.7 − − µs
tHIGH SCL high hold time 13 VCC1=4.5 to 5.5V 4 − − µs
tSUSTA Set up time 13, 14 VCC1=4.5 to 5.5V 4.7 − − µs
tHDDAT Data hold time 13, 14 VCC1=4.5 to 5.5V 0 − − s
tSUDAT Data set up time 13, 14 VCC1=4.5 to 5.5V 250 − − ns
tr Rise time 13, 14 VCC1=4.5 to 5.5V − − 1000 ns
tf Fall time 13, 14 VCC1=4.5 to 5.5V − − 300 ns
tSUSTO Set up time 13, 14 VCC1=4.5 to 5.5V 4 − − µs

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 MITSUBISHI ICS (TV)

M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

METHOD OF SETTING DATA

The input information to consit of 2 or data of 4bytes to lead to Chip The information of 5 bytes necessary for circuit operation is chip
2
Address is received in I Cbus receiver. It shows a definition of bus address and control data, bandS.W. data of 2 bytes and divider byte
protocol admitted in the following. of 2 bytes. After the chip address input, 2 or data of 4 bytes are
1_STA CA CB BB STO received.
2_STA CA D1 D2 STO Function bit is contained the first and the third data byte to
3_STA CA CB BB D1 D2 STO distinguish between divider data and control data, band data, and
4_STA CA D1 D2 CB BB STO "0" goes ahead of divider data, and "1" goes ahead of control data,
STA : Start condition bandS.W. data.
STO : Stop condition
CA : Chip address
CB : Control data byte
BB : BandS.W. data byte
D1 : Divider data byte
D2 : Divider data byte

SDA

SCL 1-7 8 9 1-7 8 9 1-7 8 9

S P
ADDRESS 0 ACK DATA ACK DATA ACK
CA
STA STO

Write mode format

Byte MSB LSB

Address Byte 1 1 0 0 0 MA1 MA0 0 A
Devider Byte1 0 N14 N13 N12 N11 N10 N9 N8 A
Devider Byte2 N7 N6 N5 N4 N3 N2 N1 N0 A
Control Byte1 1 CP T2 T1 T0 RSa RSb OS A
Band SW Byte X X X X BS4 BS3 BS2 BS1 A

Read mode format

Byte MSB LSB

Address Byte 1 1 0 0 0 MA1 MA0 1 A
Status Byte1 POR FL X X X A2 A1 A0 A

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 MITSUBISHI ICS (TV)

M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

DATA CORDING EXAMPLE

Write mode format example

Byte MSB LSB Condotion in data setting

Address Byte 1 1 0 0 0 1 1 0 1 ADS input V CC1
Devider Byte1 0 1 0 0 0 0 0 0 1
Dividing ratio N=16544
Devider Byte2 1 0 1 0 0 0 0 0 1
C.P. current 270µA
Control Byte1 1 1 0 0 0 0 1 0 1
fREF division ratio 1/1024
Band SW Byte 0 0 0 0 1 0 0 0 1 BS4 output ON

fVCO=N×8×fREF=16544×8×(4MHz/1024)=517MHz

Read mode format example

Byte MSB LSB Condotion in divise

Address Byte 1 1 0 0 0 1 1 1 1
Status Byte1 input 1 1 1 1 1 1 1 1 1
Status Byte1 output 0 1 1 1 1 0 1 1 1 FL “1”output at locked ADC input at open

TEST MODE DATA SET UP METHOD RSa, RSb : Set up for the reference frequency division ratio
Test Mode Bit Set Up
RSa RSb Division ratio
X : Random, 0 or 1. normal "0"
1 1 1/512
MA1 ,MA0 : Programmabule Address Bit 0 1 1/1024
Address input voltage MA1 MA0 X 0 1/640
0 to 0.1∗VCC1 0 0
OS : Set up the tuning amplifier
Always valid 0 1
0.4∗VCC1 to 0.6*VCC1 1 0 OS Tuning voltage output Mode
0.9∗VCC1 to VCC1 1 1 0 ON Normal
1 OFF Test
N14 to N0 : How to set dividing ratio of the programable the divider
POR : Power on reset flag. “1” output at reset

Dividing ratio N=N14(2 14=16384)+ ⋅⋅⋅ +N0(20=1) FL : Lock detecter flag. “1” output at locked,

Therefore, the range of division N is 1,024 to 32,768 “0” output at unlocked

Example) fvco=fREF×8×N A2, A1, A0: 5level A/D converter output data
=3.90625×8×N ADC input voltage A2 A1 A0
=31.25×N (kHz) 0.6∗VCC1 to VCC1 1 0 0
0.45∗VCC1 to 0.6∗VCC1 0 1 1
CP: Setting up the charge pump current of the phase 0.3∗VCC1 to 0.45∗VCC1 0 1 0
comparator 0.15∗VCC1 to 0.3∗VCC1 0 0 1
CP Charge pump current Mode 0 to 0.15∗VCC1 0 0 0
0 70µA Test The voltage accuracy allowance range: ±0.03∗VCC1 (V)
1 270µA Normal

T2, T1, T0 : Setting up for the test mode POWER ON RESET OPERATION
T2 T1 T0 Charge pump Pin 12 condition Mode (Initial state the power is turned ON)
0 0 X Normal operation ADC input Normal operation BS4 to BS1 : OFF
0 1 X High impedance ADC input Test mode Charge pump : High impedance
1 1 0 Sink ADC input Test mode Tuning amplifier : OFF
1 1 1 Source ADC input Test mode Charge pump current : 270µA
1 0 0 High impedance fREF output Test mode Frequency division ratio : 1/1024
1 0 1 High impedance f1/N output Test mode

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 MITSUBISHI ICS (TV)

M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

TIMING DIAGRAM

START condition

SDA

tBUF
tLOW tr tf tHDSTA

SCL

tHDSTA tHDDAT tHIGH tSUDAT tSUSTA tSUSTO

STOP condition START condition STOP condition

CRYSTAL OSCILLATOR CONNECTION DIAGRAM

16

18pF Crystal oscillator characteristics

Actual resistance: less than 300Ω
Load capacitance : 20pF
4MHz

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 MITSUBISHI ICS (TV)

M64894FP/GP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

APPLICATION EXAMPLE

BUILT-IN PLL TUNER

+5V Vcc1 to 12V UHF VHF

1000p

10µ
- 3 M64894FP/GP

5 18
SW Vcc2 +B
15 ADS 4
47k
BS4 11
BS4
5
47k
BS3 12
BS3 IF IF
1 TEST 6
47k
BS2 13 4-BAND
BS2
M5493X 7 TUNER
series
47k
3 DATA BS1 14
14 BS1
8 1000p
fIN 17 Lo

4 CLK 1 AGC AGC

MCU GND 16
13 1000pF 1.5n
15
0.1µ
2 EN 10 VT
9 56k 56k
AFT
PD 2.2n
20 LD/f1/N 10
12 9
ADC 100p ∗
XIN XOUT GND
6 7 8

Note) Filter constant is

16 11 for reference.
18p
∗ Add a capacitor to stabilize
4MHz the circuit.
+33V

BT
Units Resistance : Ω
Capacitance : F

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