L2: Internal Organization of Memory Chip
L2: Internal Organization of Memory Chip
L2: Internal Organization of Memory Chip
Memory Subsystem
L2: Internal Organization of memory chip
• With the number of cells, the number of address lines required to enable one cell can
be determined.
Word Size
It is the maximum number of bits that a
CPU can process at a time and it depends
upon the processor.
Main Secondary
CPU MEMORY
Program and data are actually stored on MEMORY
secondary memory that is much larger.
• 4 address lines
required to access
16 locations.
• A Decoder is added
to select the
different words
(each 1 bit wide).
• For 16 words we
need a 4-to-16 line
Decoder
Cont..
A 128-bit memory chip organized as 16 x 8 is shown.
Every row of the cell array constitutes a memory word.
The rows of the cells are connected to the word lines.
Individual cells are connected to two bit lines. – Bit b and its complement b’. – are
required for reading and writing.
The Sense/Write circuits are activated by the chip select (CS) lines. The Sense/Write
circuits are connected to the data lines of the chip.
During a read operation, these circuits sense or read the information stored in the
cells selected by a word line and transmit this information to the data lines.
During a write operation, the Sense/Write circuits receive or write input information
from the data lines and store it in the selected cells.
Cells in each column are connected to a sense/write circuit by the two bit lines.
Other than address and data lines, there are two control lines: R/W’ and CS’ (Chip
Select). – CS is required to select one single chip in a multi-chip memory system.
More Examples
128x8 memory chip-1024 memory cells 1024x1 memory chip-1024 memory cells
128 memory word of size 8 bits 1024 memory word of size 1 bit only
Data bus size=8 bits Data bus size=1 bit
Address bus size=7 bits(2^7=128) Address bus size=10 bits(2^10=1024)
External Connection Requirements
Required 10-bit
address-divided
into 2 group of 5
bits each to form
a row and column
addresses for the
cell array
16
Example: Construct a large RAM-type memory of size 1K x 4 using smaller
RAM chips each of size 512 x 2
• larger 1K x 4 RAM memory requires
10 address lines and 4 data lines
• smaller RAMs of each 516 x 2 requires
9 address lines and 2 data lines
• Memory construction needs
1K/512= 1024/512 = 2 rows 1