Fundamentals of CMOS VLSI 10EC56

PART-A
UNIT-1 7 Hours
BASIC MOS TECHNOLOGY: Integrated circuit’s era. Enhancement and depletion mode
MOS transistors. nMOS fabrication. CMOS fabrication. Thermal aspects of processing.
BiCMOS technology. Production of E-beam masks. - 3Hrs
MOS TRANSISTOR THEORY: Introduction, MOS Device Design Equations, The
Complementary CMOS Inverter – DC Characteristics, Static Load MOS Inverters, The
Differential Inverter, The Transmission Gate, Tristate Inverter. - 4 Hrs

1. Explain the nMOS enhancement mode transistor operation for different values of V gs and Vds. (10M)
Jan 2015
2. Explain the CMOS inverter transfer characteristics highlighting the regions o0f operations of the
MOS transistor. (10M) Jan 2015
3. Explain the fabrication steps of CMOS P-well process with neat diagram and write the mask sequence.
(12M)
Jan 2014
4. List the threshold voltage equations and emphasize each term. (8M) Jan 2014
5. Explain the influence of βn/ βp on the DC transfer characteristics of inverter. (5M)Jun 2012
6. Discuss the difference in the thermal sequence between nMOS and CMOS process. (5M)Jun 2012
7. Explain the nMOS fabrication process with neat diagram. (10M) Jun 2012, Dec2012
8. Obtain the dc transfer characteristics of a CMOS inverter and mark the entire region showing the status of
PMOS and NMOS. (10M)Dec2012
9. Explain with structure the step-by-step flow of n-well fabrication process. (10M) Dec12
10. Explain the design equations of MOS devices and VI characteristics for n and p devices. (10M) Dec12
11. Describe in detail step-by-step procedure of P-well CMOS fabrication. (8M)Jun2011
12. Explain the transfer plot of CMOPS inverter with necessary expression for Vout in each region (8M)Jun2011
13. Write a note on transmission gate. (4M)Jun2011
14. Explain the nMOS enhancement mode transistor for different conditions of Vds. (8M)Dec 2011
15. Describe in detail BiCMOS fabrication in an n-well process. (8M)Dec 2011
16. What are the advantages of BiCMOS process over CMOS technology? (4M)Dec 2011
17. Explain the fabrication steps in P-well CMOS fabrication. (10M)Jun2010
18. Obtain the de transfer characteristics of a CMOS inverter and mark all the regions showing the status of
PMOS and NMOS. (10M)Jun2010
19. Distinguish between enhancement and depletion mode operation of MOSFET’s. (5M)Jan 2010
20. Explain with diagrams, the main steps in the twin-tub process. (10M)Jan 2010
21. Compare CMOS and Bipolar technologies. (5M)Jan 2010
UNIT-2 7 Hours
CIRCUIT DESIGN PROCESSES: MOS layers. Stick diagrams. Design rules and layout –
lambda-based design and other rules. Examples. Layout diagrams. Symbolic diagrams. Tutorial
exercises. 4 Hrs
Basic Physical Design of Simple logic gates. 3
Hrs

1. Draw the circuit and stick diagram for the nMOS and CMOS implementation of the Boolean

expression . (10M) Jan 2015

2. With neat diagram, explain λ based design rules for wired (nMOS and CMOS) and transistor design rules
(nMOS PMOS and CMOS). (10M) Jan 2015
3. Write the circuit and layout for Y= in CMOS style. (10M) Jan 2015

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Fundamentals of CMOS VLSI 10EC56

4. Write the CMOS inverter circuit and briefly explain. Write the CMOS VTC showing region A, B, C, D, E.
Derive the expressions for output voltage in region ‘B’. (10M)Jan 2014
5. Write the circuit and layout for in CMOS style. (10M)Jan 2014
6. Draw the circuit schematic and stick diagram for CMOS 2 input NOR gate. (7M)Jun 2012
7. With neat sketches, explain λ based design rules for pMOS, nMOS and nMOS depletion mode transistor.
(6M)Jun 2012
8. List the colour, stick encoding, mask layout encoding, layers for a simple metal nMOS process. (7M)Jun 2012
9. Compare CMOS and bipolar technologies. (4M)Dec2012
10. Draw the circuit schematic and stick diagram of CMOS 2 input NAND gate. (6M)Dec2012
11. A NMOS transistor has a threshold voltage of 0.75V, the body effect co-efficient equal to 0.54 compute the
threshold voltage of 0.75V, the body effect co-efficient equal to 0.54 compute the threshold voltage for V SB=
5V and 2ϕF= -0.6V. (5M)Dec2012
12. Draw the layout for the schematic shown in the Fig 9. (10M)Dec2012

Fig 9 Fig 10
13. Draw circuit diagram and stick diagram of two NOR gate using CMOS logic use standard
colour/monochrome codes (8M)Jun2011
14. Explain λ-based design rules applicable to MOS layers and transmission (8M)Jun2011, (7M) Dec2012
15. Write a note on Double metal MOS process rules for contact cut. (4M)Jun2011
16. What is body effect? Which parameters are responsible for it? (8M)Dec 2011
17. An nMOS transistor is operating in active region with following parameters V GS=3.9V, Vth=1V, W/L=100,
μnC0x=90μA/r2, Find ID and drain to source resistance. (5M)Dec 2011
18. Explain in detail regions of operation and mid-point voltage equation for CMOS inverter. (7M)Dec 2011
19. Compare CMOS and bipolar technologies. (4M)Jun2010
20. Explain the transmission gate operation. (4M)Jun2010
21. Draw λ-based design rules for double metal CMOS process for layers and transistors.
(8M)Jun2010,
22. Draw the circuit diagram and stick diagram for NAND gate (4M)Jun2010

UNIT-3 6 Hours
CMOS LOGIC STRUCTURES: CMOS Complementary Logic, Bi CMOS Logic, Pseudo-nMOS
Logic, Dynamic CMOS Logic, Clocked CMOS Logic, Pass Transistor Logic, CMOS Domino
Logic Cascaded Voltage Switch Logic (CVSL).

1. Explain the differences between CMOS complementary logic and BICMOS logic. (8M) Jan 2015
2. Explain the following : i) Dynamic logic; ii) Clocked CMOS logic. (12M) Jan 2015
3. Write circuit and stick diagram for CMOS tristate inverter. (4M) Jan 2014
4. Write the circuit of BICMOS NAND and NOR gate and briefly explain. (8M) Jan 2014
5. Explain the circuit of dynamic CMOS logic by taking an example of the function
(8M) Jan 2014

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Fundamentals of CMOS VLSI 10EC56

6. Explain the operation of CMOS dynamic logic. Discuss the merits and demerits. (7M)Jun 2012
7. What are the properties of nMOS and pMOS switches? How is transmission gate useful? (8M) Jun
2012
8. Explain the operation of CMOS dynamic logic. Also discuss the cascading problem of dynamic CMOS logic.
(10M)Dec2012
9. Realize for clocked CMOS logic. (5M)Dec2012,Jun 2012
10. Explain the pseudo-NMOS logic, structure and their salient features with example. (8M)Dec2012
11. Explain the circuit the working principle of Bi-CMOS not gate and show the sub circuits of the output voltage.

(8M)Dec2012
12. Find the equation for the node voltages V1, V2, V3 during logic “1” transfer, when each pass transistor, as
shown in Fig 10. Assume threshold voltage of each transistor is Vtn. (5M)Dec2012
13. Explain the following logic structures with salient features:
a. BiCMOS logic b. Pseudo-nMOS logic c. Pass transistor logic d. C2MOS logic. (20M)Jun2011
14. Explain different types of pseudo - NMOS logic. (7M)Jun 2010
15. Explain CMOS domain logic and derive the evaluation voltage equation. (8M)Jun 2010
16. Explain 2-input x-nor gate in pass transistor logic. (5M)Jun 2010

UNIT-4 6 Hours
BASIC CIRCUIT CONCEPTS: Sheet resistance. Area c a p a c i t a n c e . Capacitance
calculations. The delay unit. Inverter delays. Driving capacitive loads. Propagation delays. Wiring
capacitances. 3 Hrs
SCALING OF MOS CIRCUITS: Scaling models and factors. Limits on scaling. Limits due
to current density and noise. 3 Hrs

1. Provide scaling factors for:

i) Saturation current. ii) Current density iii) Power dissipation/ unit area. iv) Maximum operating frequency.
(10M) Jan 2015
2. Discuss the following in scaling of MOS circuits:
i) Limits of miniaturaization.
ii) Limits of interconnect and contact resistance. (10M) Jan 2015
3. Define sheet resistance (Rs) and standard unit of capacitance ( ) . Calculate the on resistance of 4:1 nmos

inverter with Rs=10kΩ/ , . Also estimate the total power dissipated if V DD=5.
(8M)
Jan 2014
4. Calculate the capacitance in Cg for the given metal layer shown in fig 4.2, if feature size=5μm and relative
value of metal to substrate= 0.075. (5M) Jan 2014

Fig 4.2
5. Explain briefly the circuit of inverting and non-inverting super buffer. (7M) Jan 2014
6. What are the scaling factors of (i)Parasitic capacitance Cx (ii) Power dissipation per unit area Pa.(4M)Jun 2012
7. Calculate the ON resistance for nMOS inverter with Rsn=10KΩ, Zpu=8 and Zpd=1. (4M) Jun 2012
8. What are the possible effects of propagation delay in cascade pass transistor chain and long polysilicon wires?
(12M)Jun 2012
9. With a neat circuit diagram and waveform, explain the principle of operation of a dynamic logic and what are
the advantages and disadvantages. (10M)Dec2012
10. Explain with circuit diagram the super buffers with inverting type and non-inverting type of nmos.

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Fundamentals of CMOS VLSI 10EC56

(10M)Dec2012
11. Find the scaling factors for:
a. Channel Resistance Ron
b. Current density J. (6M) Dec 2012
12. Derive the equation for rise time and fall time for CMOS inverter . (8M) Dec 2012
13. Write a note on limitations of scaling. (6M) Dec 2012
14. Define sheet resistance, standard unit capacitance and delay unit of time. (6M)Jun2011
15. Explain cascaded inverters to drive large capacitive loads. Obtain an equation to find number of stages.

(8M)Jun2011
16. Discuss the following in scaling of MOS circuits: i) Limit of miniaturization ii) Limits of interconnect and
contact resistance. (6M)Jun2011
17. Explain the terms: i) Rise time ii) Fall time iii) Delay time. Derive the equations for fall time of
CMOS inverter. (8M)Jun 2010
18. Provide scaling factors for gate area, gate delay, sat current. (6M)Jun 2010
19. Explain in brief the wiring capacitances. (6M)Jun 2010
20. Discuss the limits of scaling on: i) supply voltage due to noise ii) Sub threshold current iii) Interconnects.

(10M)Jan 2010
21. Realize a 2-input NAND gate for a clocked CMOS logic and also for CMOS domino logic. (10M)Jan 2010

PART-B
UNIT-5 7 Hours
CMOS SUBSYSTEM DESIGN: Architectural issues. Switch logic. Gate logic. Design examples –
combinational logic. Clocked circuits. Other system considerations. 5 Hrs
Clocking Strategies 2 Hrs

1. Discuss the architectural issues related to sub system design. (08M) Jan 2015
2. Explain switch logic (nMOS and CMOS) implementation for 4-way multiplexer. (12M) Jan 2015
3. Calculate the O/P voltage Vout in the circuit given in fig 1 for different values of Va, Vb. (4M) Jan 2014

Fig 1 Fig 15
4. Explain how to implement the switch logic of four way multiplexer, using transmission gate. (10M) Jun 2012
5. Explain the dynamic 4-bit shift register, using nMOS logic. (10M) Jun 2012
6. Explain structured design of bus arbitration logic for n-line bus. (10M)Dec 2012
7. Discuss the architectural issues to be followed in the design of a VLSI subsystem. (10M)Dec2012
8. Explain dynamic 4-bit shift register using CMOS logic. (10M)Dec 2012
9. Design a 4:1 multiplexer using nmos logic and CMOS logic. (10M)Dec2012
10. Explain the structured design of a parity generator with necessary blocks and stick diagram. (10M)Jun2011
11. Explain domino CMOS logic with neat circuit. (10M)Jun2011
12. Explain the restoring logic, in detail. (4M)Jun 2010
13. How to implement the switch logic for 4-way multiplexer? Explain. (8M)Jun 2010
14. Explain the pre charge bus approach, used in system design. (8M)Jun 2010

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Fundamentals of CMOS VLSI 10EC56

15. Calculate the area capacitance of a multi-layer structure shown in fig 15. (8M)Jan 2010
16. Narrate the steps involved in calculating the sheet resistance of:
i) Transistor channels ii) nMOS inverter iii) CMOS inverter. (6M)Jan 2010
17. Derive expressions for rise time fall time for 1:1 CMOS inverter. (6M)Jan 2010

UNIT-6 6 Hours
CMOS SUBSYSTEM DESIGN PROCESSES: General considerations. Process illustration. ALU
subsystem. Adders. Multipliers. .
1. Discuss the general arrangements of a 4-bit arithmetic processor. (12M) Jan 2015
2. Explain 4X4 barrel shifter with neat diagram. (8M) Jan 2015
3. Discuss the 4 phase clocking scheme to avoid the problem of cascading in dynamic CMOS logic.
(6M) Jan 2014
4. What are the adder enhancement techniques? Briefly explain. (4M) Jan 2014
5. Write and explain 6-bit carry select adder. (10M) Jan 2014
6. Discuss the problem associated in VLSI design. (4M) Jun 2012
7. Explain the design steps for a 4-bit adder. (6M) Jun 2012, Jun 2010
8. Explain 4-bit Braun multiplier, with neat diagram. (10M) Jun 2012
9. Design 4-bit ALU to implement addition, subtraction, EXOR, EXNOR, OR and AND operations.
(10M)Dec 2012
10. With the neat diagram, explain Braun array multiplier. (10M)Dec2012
11. Define regularity in process illustration. (5M)Dec2012
12. Explain the implementation of ALU functions with a standard adder. (8M)Dec2012
13. Explain the important general consideration in CMOS design process. (7M)Dec2012
14. List and explain the general considerations to be consider in digital system design. (6M)Jun2011
15. Explain the design of datapath in 4-bit arithmetic processor with floor plan for 4-bit datapath. (10M)Jun2011
16. Write MOS switch implementation of 4x4 crossbar switch. (4M)Jun2011
17. Explain the 4 x 4 cross bar switch operation. Mention the salient features of sub system design process.

(8M)Jun 2010
18. How can 4-bit ALU architecture be used to implement an adder? (6M)Jun 2010
19. Discuss the architectural issues to be followed in the design of a VLSI subsystem. (6M)Jan 2010
20. Design 4:1 MUX using transmission gates. (6M)Jan 2010
21. Discuss the timing constraints for both flip flops and latches. (8M)Jan 2010

UNIT-7 6 Hours
MEMORY, REGISTERS AND CLOCK: Timing considerations. Memory elements. Memory cell arrays.

1. Explain 3-transistor dynamic RAM-cell. (10M) Jan 2015

2. Explain write operation, read operation for four transistor dynamic and six transistor static CMOS memory
cell. (10M) Jan 2015
3. Write and explain 4 transistors dynamic and 6 transistor static CMOS memory cell with sense amplifier.
(12M)Jan 2014
4. Explain the one transistor dynamic memory cell emphasizing three plate capacitor. (8M) Jan 2014, Dec 2012
5. Explain the working of one transistor dynamic memory cell, with schematic and stick diagram. (6M)Jun 2012
6. Explain nMOS pseudo static memory cell, with stick diagram. (8M)Jun 2012
7. Explain the concept of system partitioning in VLSI chip testing. (6M)Jun 2012
8. Explain the working of three-transistor dynamic RAM cell. (10M)Dec 2012
9. Discuss CMOS pseudo-static memory cell with stick diagram. (10M)Dec 2012
10. Discuss the important factors of system timing consideration. (10M)Dec2012
11. Draw the circuit and stick diagram. Explain n-MOS pseudo-static memory cell. (10M)Dec2012

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Fundamentals of CMOS VLSI 10EC56

12. What are timing considerations in system design? (6M)Jun2011

13. Draw one-transistor dynamic memory cell circuit arrangement. What is the significance of creating capacitor
by using a polysilicon plate over the diffusion area? (8M)Jun2011
14. Explain six transistor static CMOS memory cell arrangement. (6M)Jun2011
15. Explain the read and write operations in dynamic m e m o r y cell. (6M)Jun 2010
16. Explain b o o t h multiplier, with an example. (8M)Jun 2010
17. Explain different types of I /O pads. (6M)Jun 2010
18. Discuss Baugh-Worely method used for two’s complement multiplication. (12M)Jan 2010
19. Explain the working of 3TDRAM cell. (8M)Jan 2010

UNIT-8 7 Hours
TESTABILITY: Performance parameters. Layout issues. I/O pads. Real estate. System delays. Ground rules
for design. Test and testability.

1. Explain the scan design techniques. (10M) Jan 2015

2. Wruite a note on testability and testing. (10M) Jan 2015
3. Write short notes on:
a. Latch up. (7M)Jan 2014
b. Nature of failure in CMOS. (6M)Jan 2014
c. I/O pads. (7M)Jan 2014
4. Write short notes on:
a. BICMOS logic b. CMOS inverter noise margin c. Built in self-test (BIST)
b. Input/output pads. (20M)Jun 2012
5. Explain sensitized path based testing for combinational logic. (10M)Dec 2012
6. Write a note on ground rules for successful design. (10M)Dec 2012
7. Write short notes on:
a) I/O pads b)Test and testability c) LSSD d) BIST (20M)Dec2012
8. Discuss the requirements of I/O pads in a chip. (5M)Jun2011
9. Explain the sensitized path based testing applied to combinational logic as an example. (10M)Jun2011
10. Write a note on scan design technique. (5M)Jun2011
11. Write a note on testability and testing. (10M)Jun 2010
12. Explain the ground rubs for a system design. (10M)Jun 2010
13. Define noise margin for both high and low levels. (4M)Jan 2010
14. Discuss the meaning of “REAL ESTATE” in VLSI design. (8M)Jan 2010
15. Narrate the meaning of controllability and observability in VLSI chip testing. (8M)Jan 2010

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