32-Bit AVR Microcontroller
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fabio305532-Bit AVR Microcontroller
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fabio3055Features
• High Performance, Low Power 32-bit Atmel® AVR® Microcontroller
– Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing up to 1.51DMIPS/MHz
• Up to 126 DMIPS Running at 84MHz from Flash (1 Wait-State)
• Up to 63 DMIPS Running at 42MHz from Flash (0 Wait-State)
– Memory Protection Unit
• Multi-Layer Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance 32-bit AVR
– 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral
Communication Microcontroller
– 4 generic DMA Channels for High Bandwidth Data Paths
• Internal High-Speed Flash
– 256KBytes, 128KBytes, 64KBytes versions AT32UC3A3256S
– Single-Cycle Flash Access up to 36MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
AT32UC3A3256
– 4 ms Page Programming Time and 8ms Full-Chip Erase Time AT32UC3A3128S
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area AT32UC3A3128
• Internal High-Speed SRAM AT32UC3A364S
– 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus
– 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System AT32UC3A364
• Interrupt Controller AT32UC3A4256S
– Autovectored Low Latency Interrupt Service with Programmable Priority
• System Functions AT32UC3A4256
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL),
AT32UC3A4128S
– Watchdog Timer, Real-Time Clock Timer AT32UC3A4128
• External Memories
– Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash
AT32UC3A464S
– Up to 66 MHz AT32UC3A464
• External Storage device support
– MultiMediaCard (MMC V4.3), Secure-Digital (SD V2.0), SDIO V1.1
– CE-ATA V1.1, FastSD, SmartMedia, Compact Flash
– Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro
– IDE Interface
• One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S,
AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S
– 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
– Buffer Encryption/Decryption Capabilities
• Universal Serial Bus (USB)
– High-Speed USB 2.0 (480Mbit/s) Device and Embedded Host
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-Chip Transceivers Including Pull-Ups
• One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs.
• Two Three-Channel 16-bit Timer/Counter (TC)
• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Fractionnal Baudrate Generator
32072H-AVR32–10/2012
AT32UC3A3
– Support for SPI and LIN
– Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line
• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
• One Synchronous Serial Protocol Controller
– Supports I2S and Generic Frame-Based Protocols
• Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible
• 16-bit Stereo Audio Bitstream
– Sample Rate Up to 50 KHz
• QTouch® Library Support
– Capacitive Touch Buttons, Sliders, and Wheels
– QTouch and QMatrix Acquisition
• On-Chip Debug System (JTAG interface)
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
• 110 General Purpose Input/Output (GPIOs)
– Standard or High Speed mode
– Toggle capability: up to 84MHz
• Packages
– 144-ball TFBGA, 11x11 mm, pitch 0.8 mm
– 144-pin LQFP, 22x22 mm, pitch 0.5 mm
– 100-ball VFBGA, 7x7 mm, pitch 0.65 mm
• Single 3.3V Power Supply
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32072H–AVR32–10/2012
AT32UC3A3
1. Description
The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC
RISC processor running at frequencies up to 84MHz. AVR32 UC is a high-performance 32-bit
RISC microprocessor core, designed for cost-sensitive embedded applications, with particular
emphasis on low power consumption, high code density and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern operating systems and real-time operating systems. Higher
computation capabilities are achievable using a rich set of DSP instructions.
The AT32UC3A3/A4 incorporates on-chip Flash and SRAM memories for secure and fast
access. 64 KBytes of SRAM are directly coupled to the AVR32 UC for performances optimiza-
tion. Two blocks of 32 Kbytes SRAM are independently attached to the High Speed Bus Matrix,
allowing real ping-pong management.
The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between
peripherals and memories without processor involvement. The PDCA drastically reduces pro-
cessing overhead when transferring continuous and large data streams.
The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector
monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external
oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.
The device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each chan-
nel can be independently programmed to perform frequency measurement, event counting,
interval measurement, pulse generation, delay timing and pulse width modulation. 16-bit chan-
nels are combined to operate as 32-bit channels.
The AT32UC3A3/A4 also features many communication interfaces for communication intensive
applications like UART, SPI or TWI. The USART supports different communication modes, like
SPI Mode and LIN Mode. Additionally, a flexible Synchronous Serial Controller (SSC) is avail-
able. The SSC provides easy access to serial communication protocols and audio standards like
I2S.
The AT32UC3A3/A4 includes a powerfull External Bus Interface to interface all standard mem-
ory device like SRAM, SDRAM, NAND Flash or parallel interfaces like LCD Module.
The peripheral set includes a High Speed MCI for SDIO/SD/MMC and a hardware encryption
module based on AES algorithm.
The device embeds a 10-bit ADC and a Digital Audio bistream DAC.
The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high
speed peripherals (USB, External Memories, MMC, SDIO, ...) and through high speed internal
features (AES, internal memories).
The High-Speed (480MBit/s) USB 2.0 Device and Host interface supports several USB Classes
at the same time thanks to the rich Endpoint configuration. The Embedded Host interface allows
device like a USB Flash disk or a USB printer to be directly connected to the processor. This
periphal has its own dedicated DMA and is perfect for Mass Storage application.
AT32UC3A3/A4 integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intru-
sive real-time trace, full-speed read/write memory access in addition to basic runtime control.
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32072H–AVR32–10/2012
AT32UC3A3
2. Overview
2.1 Block Diagram
Figure 2-1. Block Diagram
TCK
TDO JTAG AVR32UC LOCAL BUS FAST GPIO
MEMORY INTERFACE
INTERFACE
TDI INTERFACE
TMS
NEXUS
CPU
MCKO CLASS 2+
MDO[5..0] MEMORY PROTECTION UNIT
OCD 64 KB
MSEO[1..0]
EVTI_N INSTR DATA SRAM
EVTO_N INTERFACE INTERFACE
USB_VBIAS
USB_VBUS
DMFS, DMHS USB HS PBB
DPFS, DPHS INTERFACE
CONTROLLER
ID
VBOF 256/128/64
FLASH
S M M M S
DMA KB
M S FLASH
HRAM0/1
32KB RAM S
32KB RAM S
HIGH SPEED DATA[15..0]
(SDRAM, STATIC MEMORY, COMPACT
BUS MATRIX S ADDR[23..0]
DMACA M
NCS[5..0]
EXTERNAL BUS INTERFACE
M NRD
FLASH & NAND FLASH)
NWAIT
GENERAL PURPOSE IOs
NWE0
NWE1
DMA
AES S S S M NWE3
RAS
CAS
CONFIGURATION REGISTERS BUS
SDA10
SDCK
PB HSB HSB
PERIPHERAL SDCKE
HSB-PB HSB-PB
DMA
BRIDGE B BRIDGE A SDWE
CONTROLLER
PB CFCE1
CFCE2
CFRW
PBA
NANDOE
CLK MULTIMEDIA CARD NANDWE
DMA
CMD[1..0] & MEMORY STICK RXD
INTERFACE TXD
PA DATA[15..0]
DMA
GENERAL PURPOSE IOs
PB USART1 CLK
RTS, CTS PA
PC PB
PX DSR, DTR, DCD, RI
PC
INTERRUPT PX
RXD
CONTROLLER USART0 TXD
DMA
USART2 CLK
RTS, CTS
EXTINT[7..0] EXTERNAL
SCAN[7..0] INTERRUPT RXD
NMI CONTROLLER
DMA
USART3 TXD
CLK
REAL TIME
COUNTER SPCK
SERIAL
DMA
MISO, MOSI
PERIPHERAL
VDDIN NPCS0
1V8
INTERFACE 0/1 NPCS[3..1]
GNDCORE Regulator WATCHDOG
VDDCORE TIMER TX_CLOCK, TX_FRAME_SYNC
SYNCHRONOUS
DMA
TX_DATA
SERIAL
RX_CLOCK, RX_FRAME_SYNC
115 kHz CONTROLLER
POWER RX_DATA
RCSYS
MANAGER
TWCK
XIN32 32 KHz TWO-WIRE
DMA
XOUT32 OSC TWD
CLOCK INTERFACE 0/1
GENERATOR TWALM
XIN0
OSC0
XOUT0
CLOCK ANALOG TO AD[7..0]
CONTROLLER
DMA
XIN1 DIGITAL
OSC1
XOUT1 CONVERTER
SLEEP
PLL0 CONTROLLER
PLL1 AUDIO DATA[1..0]
DMA
RESET BITSTREAM DATAN[1..0]
GCLK[3..0] CONTROLLER DAC
RESET_N
A[2..0]
TIMER/COUNTER
B[2..0]
CLK[2..0] 0/1
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32072H–AVR32–10/2012
AT32UC3A3
2.2 Configuration Summary
The table below lists all AT32UC3A3/A4 memory and package configurations:
Table 2-1. Configuration Summary
Feature AT32UC3A3256/128/64 AT32UC3A4256/128/64
Flash 256/128/64 KB
SRAM 64 KB
HSB RAM 64 KB
EBI Full Nand flash only
GPIO 110 70
External Interrupts 8
TWI 2
USART 4
Peripheral DMA Channels 8
Generic DMA Channels 4
SPI 2
1 MMC/SD slot
MCI slots 2 MMC/SD slots
+ 1 SD slot
High Speed USB 1
AES (S option) 1
SSC 1
Audio Bitstream DAC 1
Timer/Counter Channels 6
Watchdog Timer 1
Real-Time Clock Timer 1
Power Manager 1
PLL 80-240 MHz (PLL0/PLL1)
Crystal Oscillators 0.4-20 MHz (OSC0/OSC1)
Oscillators
Crystal Oscillator 32 KHz (OSC32K)
RC Oscillator 115 kHz (RCSYS)
10-bit ADC 1
number of channels 8
JTAG 1
Max Frequency 84 MHz
Package LQFP144, TFBGA144 VFBGA100
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32072H–AVR32–10/2012
AT32UC3A3
3. Package and Pinout
3.1 Package
The device pins are multiplexed with peripheral functions as described in the Peripheral Multi-
plexing on I/O Line section.
Figure 3-1. TFBGA144 Pinout (top view)
1 2 3 4 5 6 7 8 9 10 11 12
A
PX40 PB00 PA28 PA27 PB03 PA29 PC02 PC04 PC05 DPHS DMHS USB_VBUS
B
PX10 PB11 PA31 PB02 VDDIO PB04 PC03 VDDIO USB_VBIAS DMFS GNDPLL PA09
C
PX09 PX35 GNDIO PB01 PX16 PX13 PA30 PB08 DPFS GNDCORE PA08 PA10
D
PX08 PX37 PX36 PX47 PX19 PX12 PB10 PA02 PA26 PA11 PB07 PB06
E
PX38 VDDIO PX54 PX53 VDDIO PX15 PB09 VDDIN PA25 PA07 VDDCORE PA12
F
PX39 PX07 PX06 PX49 PX48 GNDIO GNDIO PA06 PA04 PA05 PA13 PA16
G
PX00 PX05 PX59 PX50 PX51 GNDIO GNDIO PA23 PA24 PA03 PA00 PA01
H
PX01 VDDIO PX58 PX57 VDDIO PC01 PA17 VDDIO PA21 PA22 VDDANA PB05
J
PX04 PX02 PX34 PX56 PX55 PA14 PA15 PA19 PA20 TMS TDO RESET_N
K
PX03 PX44 GNDIO PX46 PC00 PX17 PX52 PA18 PX27 GNDIO PX29 TCK
L
PX11 GNDIO PX45 PX20 VDDIO PX18 PX43 VDDIN PX26 PX28 GNDANA TDI
M
PX22 PX41 PX42 PX14 PX21 PX23 PX24 PX25 PX32 PX31 PX30 PX33
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32072H–AVR32–10/2012
AT32UC3A3
Figure 3-2. LQFP144 Pinout
RESET_N
GNDIO
GNDIO
VDDIO
VDDIO
PC01
PC00
PA15
PA14
PX31
PX30
PX33
PX29
PX32
PX25
PX28
PX26
PX27
PX43
PX52
PX24
PX23
PX18
PX17
PX21
PX55
PX56
PX51
PX57
PX50
PX46
PX20
TDO
TMS
TCK
TDI
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PA21 109 72 PX22
PA22 110 71 PX41
PA23 111 70 PX45
PA24 112 69 PX42
PA20 113 68 PX14
PA19 114 67 PX11
PA18 115 66 PX44
PA17 116 65 GNDIO
GNDANA 117 64 VDDIO
VDDANA 118 63 PX03
PA25 119 62 PX02
PA26 120 61 PX34
PB05 121 60 PX04
PA00 122 59 PX01
PA01 123 58 PX05
PA05 124 57 PX58
PA03 125 56 PX59
PA04 126 55 PX00
PA06 127 54 PX07
PA16 128 53 PX06
PA13 129 52 PX39
VDDIO 130 51 PX38
GNDIO 131 50 PX08
PA12 132 49 PX09
PA07 133 48 VDDIO
PB06 134 47 GNDIO
PB07 135 46 PX54
PA11 136 45 PX37
PA08 137 44 PX36
PA10 138 43 PX49
PA09 139 42 PX53
GNDCORE 140 41 PX48
VDDCORE 141 40 PX15
VDDIN 142 39 PX47
VDDIN 143 38 PX35
GNDPLL 144 37 PX10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
USB_VBUS
VDDIO
USB_VBIAS
GNDIO
DMHS
DPHS
GNDIO
DMFS
DPFS
VDDIO
PB08
PC05
PC04
PA30
PA02
PB10
PB09
PC02
PC03
GNDIO
VDDIO
PB04
PA29
PB03
PB02
PA27
PB01
PA28
PA31
PB00
PB11
PX16
PX13
PX12
PX19
PX40
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32072H–AVR32–10/2012
AT32UC3A3
Figure 3-3. VFBGA100 Pinout (top view)
1 2 3 4 5 6 7 8 9 10
A
PA28 PA27 PB04 PA30 PC02 PC03 PC05 DPHS DMHS USB_VBUS
B
PB00 PB01 PB02 PA29 VDDIO VDDIO PC04 DPFS DMFS GNDPLL
C
PB11 PA31 GNDIO PB03 PB09 PB08 USB_VBIAS GNDIO PA11 PA10
D PX16/
PX12 PX10 PX13 PX53(1)
PB10 PB07 PB06 PA09 VDDIN VDDIN
E PA02/ PA06/
PX47(1)
GNDIO PX08 PX09 VDDIO GNDIO PA16 PA13(1)
PA04 VDDCORE
F PX19/ PA26/
VDDIO PX06 PX07 GNDIO VDDIO PA08 PA03 GNDCORE
PX59(1) PB05(1)
G PA23/ PA12/ PA00/ PA01/
PX05 PX01 PX02 PX00 PX30 PX46(1) PA25(1) PA18(1)
PA05 PA17(1)
H PA22/ PA20/ PA07/
PX04 PX21 GNDIO PX25 PX31 PX20(1)
TMS GNDANA
PX18(1) PA19(1)
J PA15/ PA24/
PX03 PX24 PX26 PX29 VDDIO VDDANA
PX45(1)
TDO RESET_N
PX17(1)
K PX15/ PC00/ PA14/ PA21/
PX23 PX27 PX28 PX32(1) PX14(1)
PC01 PX11(1)
TDI TCK PX22(1)
Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO
configuration to avoid electrical conflict
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32072H–AVR32–10/2012
AT32UC3A3
3.2 Peripheral Multiplexing on I/O lines
3.2.1 Multiplexed Signals
Each GPIO line can be assigned to one of the peripheral functions. The following table
describes the peripheral signals multiplexed to the GPIO lines.
Note that GPIO 44 is physically implemented in silicon but it must be kept unused and config-
ured in input mode.
Table 3-1. GPIO Controller Function Multiplexing
G GPIO function
P PIN
BGA QFP BGA I Type
(2)
144 144 100 PIN O Supply A B C D
(1)
G11 122 G8 PA00 0 VDDIO x3 USART0 - RTS TC0 - CLK1 SPI1 - NPCS[3]
(1)
G12 123 G10 PA01 1 VDDIO x1 USART0 - CTS TC0 - A1 USART2 - RTS
(1)
D8 15 E1 PA02 2 VDDIO x1 USART0 - CLK TC0 - B1 SPI0 - NPCS[0]
G10 125 F9 PA03 3 VDDIO x1 USART0 - RXD EIC - EXTINT[4] ABDAC - DATA[0]
F9 126 E9 PA04 4 VDDIO x1 USART0 - TXD EIC - EXTINT[5] ABDAC - DATAN[0]
F10 124 G9 PA05 5 VDDIO x1 USART1 - RXD TC1 - CLK0 USB - ID
(1)
F8 127 E8 PA06 6 VDDIO x1 USART1 - TXD TC1 - CLK1 USB - VBOF
E10 133 H10(1) PA07 7 VDDIO x1 SPI0 - NPCS[3] ABDAC - DATAN[0] USART1 - CLK
C11 137 F8 PA08 8 VDDIO x3 SPI0 - SPCK ABDAC - DATA[0] TC1 - B1
B12 139 D8 PA09 9 VDDIO x2 SPI0 - NPCS[0] EIC - EXTINT[6] TC1 - A1
C12 138 C10 PA10 10 VDDIO x2 SPI0 - MOSI USB - VBOF TC1 - B0
D10 136 C9 PA11 11 VDDIO x2 SPI0 - MISO USB - ID TC1 - A2
(1)
E12 132 G7 PA12 12 VDDIO x1 USART1 - CTS SPI0 - NPCS[2] TC1 - A0
(1)
F11 129 E8 PA13 13 VDDIO x1 USART1 - RTS SPI0 - NPCS[1] EIC - EXTINT[7]
(1)
J6 100 K7 PA14 14 VDDIO x1 SPI0 - NPCS[1] TWIMS0 - TWALM TWIMS1 - TWCK
J7 101 J7(1) PA15 15 VDDIO x1 MCI - CMD[1] SPI1 - SPCK TWIMS1 - TWD
F12 128 E7 PA16 16 VDDIO x1 MCI - DATA[11] SPI1 - MOSI TC1 - CLK2
(1)
H7 116 G10 PA17 17 VDDANA x1 MCI - DATA[10] SPI1 - NPCS[1] ADC - AD[7]
(1)
K8 115 G8 PA18 18 VDDANA x1 MCI - DATA[9] SPI1 - NPCS[2] ADC - AD[6]
J8 114 H10(1) PA19 19 VDDANA x1 MCI - DATA[8] SPI1 - MISO ADC - AD[5]
J9 113 H9(1) PA20 20 VDDANA x1 EIC - NMI SSC - RX_FRAME_SYNC ADC - AD[4]
(1)
H9 109 K10 PA21 21 VDDANA x1 ADC - AD[0] EIC - EXTINT[0] USB - ID
(1)
H10 110 H6 PA22 22 VDDANA x1 ADC - AD[1] EIC - EXTINT[1] USB - VBOF
G8 111 G6(1) PA23 23 VDDANA x1 ADC - AD[2] EIC - EXTINT[2] ABDAC - DATA[1]
G9 112 J10(1) PA24 24 VDDANA x1 ADC - AD[3] EIC - EXTINT[3] ABDAC - DATAN[1]
(1)
E9 119 G7 PA25 25 VDDIO x1 TWIMS0 - TWD TWIMS1 - TWALM USART1 - DCD
(1)
D9 120 F7 ) PA26 26 VDDIO x1 TWIMS0 - TWCK USART2 - CTS USART1 - DSR
A4 26 A2 PA27 27 VDDIO x2 MCI - CLK SSC - RX_DATA USART3 - RTS MSI - SCLK
A3 28 A1 PA28 28 VDDIO x1 MCI - CMD[0] SSC - RX_CLOCK USART3 - CTS MSI - BS
A6 23 B4 PA29 29 VDDIO x1 MCI - DATA[0] USART3 - TXD TC0 - CLK0 MSI - DATA[0]
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32072H–AVR32–10/2012
AT32UC3A3
Table 3-1. GPIO Controller Function Multiplexing
G GPIO function
P PIN
BGA QFP BGA I Type
(2)
144 144 100 PIN O Supply A B C D
C7 14 A4 PA30 30 VDDIO x1 MCI - DATA[1] USART3 - CLK DMACA - DMAACK[0] MSI - DATA[1]
B3 29 C2 PA31 31 VDDIO x1 MCI - DATA[2] USART2 - RXD DMACA - DMARQ[0] MSI - DATA[2]
A2 30 B1 PB00 32 VDDIO x1 MCI - DATA[3] USART2 - TXD ADC - TRIGGER MSI - DATA[3]
C4 27 B2 PB01 33 VDDIO x1 MCI - DATA[4] ABDAC - DATA[1] EIC - SCAN[0] MSI - INS
B4 25 B3 PB02 34 VDDIO x1 MCI - DATA[5] ABDAC - DATAN[1] EIC - SCAN[1]
A5 24 C4 PB03 35 VDDIO x1 MCI - DATA[6] USART2 - CLK EIC - SCAN[2]
B6 22 A3 PB04 36 VDDIO x1 MCI - DATA[7] USART3 - RXD EIC - SCAN[3]
H12 121 F7(1) PB05 37 VDDIO x3 USB - ID TC0 - A0 EIC - SCAN[4]
D12 134 D7 PB06 38 VDDIO x1 USB - VBOF TC0 - B0 EIC - SCAN[5]
D11 135 D6 PB07 39 VDDIO x3 SPI1 - SPCK SSC - TX_CLOCK EIC - SCAN[6]
C8 11 C6 PB08 40 VDDIO x2 SPI1 - MISO SSC - TX_DATA EIC - SCAN[7]
E7 17 C5 PB09 41 VDDIO x2 SPI1 - NPCS[0] SSC - RX_DATA EBI - NCS[4]
D7 16 D5 PB10 42 VDDIO x2 SPI1 - MOSI SSC - RX_FRAME_SYNC EBI - NCS[5]
B2 31 C1 PB11 43 VDDIO x1 USART1 - RXD SSC - TX_FRAME_SYNC PM - GCLK[1]
(1)
K5 98 K5 PC00 45 VDDIO x1
H6 99 K6 PC01 46 VDDIO x1
A7 18 A5 PC02 47 VDDIO x1
B7 19 A6 PC03 48 VDDIO x1
A8 13 B7 PC04 49 VDDIO x1
A9 12 A7 PC05 50 VDDIO x1
G1 55 G4 PX00 51 VDDIO x2 EBI - DATA[10] USART0 - RXD USART1 - RI
H1 59 G2 PX01 52 VDDIO x2 EBI - DATA[9] USART0 - TXD USART1 - DTR
J2 62 G3 PX02 53 VDDIO x2 EBI - DATA[8] USART0 - CTS PM - GCLK[0]
K1 63 J1 PX03 54 VDDIO x2 EBI - DATA[7] USART0 - RTS
J1 60 H1 PX04 55 VDDIO x2 EBI - DATA[6] USART1 - RXD
G2 58 G1 PX05 56 VDDIO x2 EBI - DATA[5] USART1 - TXD
F3 53 F3 PX06 57 VDDIO x2 EBI - DATA[4] USART1 - CTS
F2 54 F4 PX07 58 VDDIO x2 EBI - DATA[3] USART1 - RTS
D1 50 E3 PX08 59 VDDIO x2 EBI - DATA[2] USART3 - RXD
C1 49 E4 PX09 60 VDDIO x2 EBI - DATA[1] USART3 - TXD
B1 37 D2 PX10 61 VDDIO x2 EBI - DATA[0] USART2 - RXD
L1 67 K7(1) PX11 62 VDDIO x2 EBI - NWE1 USART2 - TXD
D6 34 D1 PX12 63 VDDIO x2 EBI - NWE0 USART2 - CTS MCI - CLK
C6 33 D3 PX13 64 VDDIO x2 EBI - NRD USART2 - RTS MCI - CLK
(1)
M4 68 K5 PX14 65 VDDIO x2 EBI - NCS[1] TC0 - A0
E6 40 K4(1) PX15 66 VDDIO x2 EBI - ADDR[19] USART3 - RTS TC0 - B0
C5 32 D4(1) PX16 67 VDDIO x2 EBI - ADDR[18] USART3 - CTS TC0 - A1
(1)
K6 83 J10 PX17 68 VDDIO x2 EBI - ADDR[17] DMACA - DMARQ[1] TC0 - B1
10
32072H–AVR32–10/2012
AT32UC3A3
Table 3-1. GPIO Controller Function Multiplexing
G GPIO function
P PIN
BGA QFP BGA I Type
(2)
144 144 100 PIN O Supply A B C D
(1)
L6 84 H9 PX18 69 VDDIO x2 EBI - ADDR[16] DMACA - DMAACK[1] TC0 - A2
(1)
D5 35 F1 PX19 70 VDDIO x2 EBI - ADDR[15] EIC - SCAN[0] TC0 - B2
(1)
L4 73 H6 PX20 71 VDDIO x2 EBI - ADDR[14] EIC - SCAN[1] TC0 - CLK0
M5 80 H2 PX21 72 VDDIO x2 EBI - ADDR[13] EIC - SCAN[2] TC0 - CLK1
M1 72 K10(1) PX22 73 VDDIO x2 EBI - ADDR[12] EIC - SCAN[3] TC0 - CLK2
M6 85 K1 PX23 74 VDDIO x2 EBI - ADDR[11] EIC - SCAN[4] SSC - TX_CLOCK
M7 86 J2 PX24 75 VDDIO x2 EBI - ADDR[10] EIC - SCAN[5] SSC - TX_DATA
M8 92 H4 PX25 76 VDDIO x2 EBI - ADDR[9] EIC - SCAN[6] SSC - RX_DATA
L9 90 J3 PX26 77 VDDIO x2 EBI - ADDR[8] EIC - SCAN[7] SSC - RX_FRAME_SYNC
K9 89 K2 PX27 78 VDDIO x2 EBI - ADDR[7] SPI0 - MISO SSC - TX_FRAME_SYNC
L10 91 K3 PX28 79 VDDIO x2 EBI - ADDR[6] SPI0 - MOSI SSC - RX_CLOCK
K11 94 J4 PX29 80 VDDIO x2 EBI - ADDR[5] SPI0 - SPCK
M11 96 G5 PX30 81 VDDIO x2 EBI - ADDR[4] SPI0 - NPCS[0]
M10 97 H5 PX31 82 VDDIO x2 EBI - ADDR[3] SPI0 - NPCS[1]
(1)
M9 93 K4 PX32 83 VDDIO x2 EBI - ADDR[2] SPI0 - NPCS[2]
M12 95 PX33 84 VDDIO x2 EBI - ADDR[1] SPI0 - NPCS[3]
J3 61 PX34 85 VDDIO x2 EBI - ADDR[0] SPI1 - MISO PM - GCLK[0]
C2 38 PX35 86 VDDIO x2 EBI - DATA[15] SPI1 - MOSI PM - GCLK[1]
D3 44 PX36 87 VDDIO x2 EBI - DATA[14] SPI1 - SPCK PM - GCLK[2]
D2 45 PX37 88 VDDIO x2 EBI - DATA[13] SPI1 - NPCS[0] PM - GCLK[3]
E1 51 PX38 89 VDDIO x2 EBI - DATA[12] SPI1 - NPCS[1] USART1 - DCD
F1 52 PX39 90 VDDIO x2 EBI - DATA[11] SPI1 - NPCS[2] USART1 - DSR
A1 36 PX40 91 VDDIO x2 MCI - CLK
M2 71 PX41 92 VDDIO x2 EBI - CAS
M3 69 PX42 93 VDDIO x2 EBI - RAS
L7 88 PX43 94 VDDIO x2 EBI - SDA10 USART1 - RI
K2 66 PX44 95 VDDIO x2 EBI - SDWE USART1 - DTR
L3 70 J7(1) PX45 96 VDDIO x3 EBI - SDCK
K4 74 G6(1) PX46 97 VDDIO x2 EBI - SDCKE
(1)
D4 39 E1 PX47 98 VDDIO x2 EBI - NANDOE ADC - TRIGGER MCI - DATA[11]
F5 41 PX48 99 VDDIO x2 EBI - ADDR[23] USB - VBOF MCI - DATA[10]
F4 43 PX49 100 VDDIO x2 EBI - CFRNW USB - ID MCI - DATA[9]
G4 75 PX50 101 VDDIO x2 EBI - CFCE2 TC1 - B2 MCI - DATA[8]
G5 77 PX51 102 VDDIO x2 EBI - CFCE1 DMACA - DMAACK[0] MCI - DATA[15]
K7 87 PX52 103 VDDIO x2 EBI - NCS[3] DMACA - DMARQ[0] MCI - DATA[14]
E4 42 D4(1) PX53 104 VDDIO x2 EBI - NCS[2] MCI - DATA[13]
E3 46 PX54 105 VDDIO x2 EBI - NWAIT USART3 - TXD MCI - DATA[12]
J5 79 PX55 106 VDDIO x2 EBI - ADDR[22] EIC - SCAN[3] USART2 - RXD
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Table 3-1. GPIO Controller Function Multiplexing
G GPIO function
P PIN
BGA QFP BGA I Type
(2)
144 144 100 PIN O Supply A B C D
J4 78 PX56 107 VDDIO x2 EBI - ADDR[21] EIC - SCAN[2] USART2 - TXD
H4 76 PX57 108 VDDIO x2 EBI - ADDR[20] EIC - SCAN[1] USART3 - RXD
H3 57 PX58 109 VDDIO x2 EBI - NCS[0] EIC - SCAN[0] USART3 - TXD
G3 56 F1(1) PX59 110 VDDIO x2 EBI - NANDWE MCI - CMD[1]
Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO
configuration to avoid electrical conflict.
2. Refer to ”Electrical Characteristics” on page 960 for a description of the electrical properties of
the pad types used..
3.2.2 Peripheral Functions
Each GPIO line can be assigned to one of several peripheral functions. The following table
describes how the various peripheral functions are selected. The last listed function has priority
in case multiple functions are enabled on the same pin.
Table 3-2. Peripheral Functions
Function Description
GPIO Controller Function multiplexing GPIO and GPIO peripheral selection A to D
Nexus OCD AUX port connections OCD trace system
JTAG port connections JTAG debug port
Oscillators OSC0, OSC1, OSC32
3.2.3 Oscillator Pinout
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled
by registers in the Power Mananger (PM). Please refer to the PM chapter for more information
about this.
Table 3-3.Oscillator Pinout
TFBGA144 QFP144 VFBGA100 Pin name Oscillator pin
A7 18 A5 PC02 XIN0
B7 19 A6 PC03 XOUT0
A8 13 B7 PC04 XIN1
A9 12 A7 PC05 XOUT1
(1)
K5 98 K5 PC00 XIN32
H6 99 K6 PC01 XOUT32
Note: 1. This ball is physically connected to 2 GPIOs. Software must managed carrefully the GPIO con-
figuration to avoid electrical conflict
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3.2.4 JTAG port connections
Table 3-4. JTAG Pinout
TFBGA144 QFP144 VFBGA100 Pin name JTAG pin
K12 107 K9 TCK TCK
L12 108 K8 TDI TDI
J11 105 J8 TDO TDO
J10 104 H7 TMS TMS
3.2.5 Nexus OCD AUX port connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spective of the GPIO configuration. Three differents OCD trace pin mappings are possible,
depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Tech-
nical Reference Manual.
Table 3-5. Nexus OCD AUX port connections
Pin AXS=0 AXS=1 AXS=2
EVTI_N PB05 PA08 PX00
MDO[5] PA00 PX56 PX06
MDO[4] PA01 PX57 PX05
MDO[3] PA03 PX58 PX04
MDO[2] PA16 PA24 PX03
MDO[1] PA13 PA23 PX02
MDO[0] PA12 PA22 PX01
MSEO[1] PA10 PA07 PX08
MSEO[0] PA11 PX55 PX07
MCKO PB07 PX00 PB09
EVTO_N PB06 PB06 PB06
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3.3 Signal Descriptions
The following table gives details on signal name classified by peripheral.
Table 3-6. Signal Description List
Active
Signal Name Function Type Level Comments
Power
VDDIO I/O Power Supply Power 3.0 to 3.6V
VDDANA Analog Power Supply Power 3.0 to 3.6V
VDDIN Voltage Regulator Input Supply Power 3.0 to 3.6V
Power
VDDCORE Voltage Regulator Output for Digital Supply 1.65 to 1.95 V
Output
GNDANA Analog Ground Ground
GNDIO I/O Ground Ground
GNDCORE Digital Ground Ground
GNDPLL PLL Ground Ground
Clocks, Oscillators, and PLL’s
XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog
XOUT0, XOUT1,
Crystal 0, 1, 32 Output Analog
XOUT32
JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
Auxiliary Port - AUX
MCKO Trace Data Output Clock Output
MDO[5:0] Trace Data Output Output
MSEO[1:0] Trace Frame Control Output
EVTI_N Event In Input Low
EVTO_N Event Out Output Low
Power Manager - PM
GCLK[3:0] Generic Clock Pins Output
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Table 3-6. Signal Description List
Active
Signal Name Function Type Level Comments
RESET_N Reset Pin Input Low
DMA Controller - DMACA (optional)
DMAACK[1:0] DMA Acknowledge Output
DMARQ[1:0] DMA Requests Input
External Interrupt Controller - EIC
EXTINT[7:0] External Interrupt Pins Input
SCAN[7:0] Keypad Scan Pins Output
NMI Non-Maskable Interrupt Pin Input Low
General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX
PA[31:0] Parallel I/O Controller GPIO port A I/O
PB[11:0] Parallel I/O Controller GPIO port B I/O
PC[5:0] Parallel I/O Controller GPIO port C I/O
PX[59:0] Parallel I/O Controller GPIO port X I/O
External Bus Interface - EBI
ADDR[23:0] Address Bus Output
CAS Column Signal Output Low
CFCE1 Compact Flash 1 Chip Enable Output Low
CFCE2 Compact Flash 2 Chip Enable Output Low
CFRNW Compact Flash Read Not Write Output
DATA[15:0] Data Bus I/O
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NCS[5:0] Chip Select Output Low
NRD Read Signal Output Low
NWAIT External Wait Signal Input Low
NWE0 Write Enable 0 Output Low
NWE1 Write Enable 1 Output Low
RAS Row Signal Output Low
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Table 3-6. Signal Description List
Active
Signal Name Function Type Level Comments
SDA10 SDRAM Address 10 Line Output
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output
SDWE SDRAM Write Enable Output Low
MultiMedia Card Interface - MCI
CLK Multimedia Card Clock Output
CMD[1:0] Multimedia Card Command I/O
DATA[15:0] Multimedia Card Data I/O
Memory Stick Interface - MSI
SCLK Memory Stick Clock Output
BS Memory Stick Command I/O
DATA[3:0] Multimedia Card Data I/O
Serial Peripheral Interface - SPI0, SPI1
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
NPCS[3:0] SPI Peripheral Chip Select I/O Low
SPCK Clock Output
Synchronous Serial Controller - SSC
RX_CLOCK SSC Receive Clock I/O
RX_DATA SSC Receive Data Input
RX_FRAME_SYNC SSC Receive Frame Sync I/O
TX_CLOCK SSC Transmit Clock I/O
TX_DATA SSC Transmit Data Output
TX_FRAME_SYNC SSC Transmit Frame Sync I/O
Timer/Counter - TC0, TC1
A0 Channel 0 Line A I/O
A1 Channel 1 Line A I/O
A2 Channel 2 Line A I/O
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Table 3-6. Signal Description List
Active
Signal Name Function Type Level Comments
B0 Channel 0 Line B I/O
B1 Channel 1 Line B I/O
B2 Channel 2 Line B I/O
CLK0 Channel 0 External Clock Input Input
CLK1 Channel 1 External Clock Input Input
CLK2 Channel 2 External Clock Input Input
Two-wire Interface - TWI0, TWI1
TWCK Serial Clock I/O
TWD Serial Data I/O
TWALM SMBALERT signal I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3
CLK Clock I/O
CTS Clear To Send Input
DCD Data Carrier Detect Only USART1
DSR Data Set Ready Only USART1
DTR Data Terminal Ready Only USART1
RI Ring Indicator Only USART1
RTS Request To Send Output
RXD Receive Data Input
TXD Transmit Data Output
Analog to Digital Converter - ADC
Analog
AD0 - AD7 Analog input pins
input
Audio Bitstream DAC (ABDAC)
DATA0-DATA1 D/A Data out Output
DATAN0-DATAN1 D/A Data inverted out Output
Universal Serial Bus Device - USB
DMFS USB Full Speed Data - Analog
DPFS USB Full Speed Data + Analog
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Table 3-6. Signal Description List
Active
Signal Name Function Type Level Comments
DMHS USB High Speed Data - Analog
DPHS USB High Speed Data + Analog
Connect to the ground through a
6810 ohms (+/- 1%) resistor in
parallel with a 10pf capacitor.
USB_VBIAS USB VBIAS reference Analog
If USB hi-speed feature is not
required, leave this pin
unconnected to save power
USB_VBUS USB VBUS signal Output
VBOF USB VBUS on/off bus power control port Output
ID ID Pin fo the USB bus Input
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3.4 I/O Line Considerations
3.4.1 JTAG Pins
TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has
no pull-up resistor.
3.4.2 RESET_N Pin
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As
the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case
no reset from the system needs to be applied to the product.
3.4.3 TWI Pins
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the
pins have the same characteristics as other GPIO pins.
3.4.4 GPIO Pins
All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is
performed independently for each I/O line through the I/O Controller. After reset, I/O lines default
as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset
State” of the I/O Controller multiplexing tables.
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3.5 Power Considerations
3.5.1 Power Supplies
The AT32UC3A3 has several types of power supply pins:
• VDDIO: Powers I/O lines. Voltage is 3.3V nominal
• VDDANA: Powers the ADC. Voltage is 3.3V nominal
• VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal
• VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the
core, memories, and peripherals. Voltage is 1.8V nominal
The ground pin GNDCORE is common to VDDCORE and VDDIN. The ground pin for VDDANA
is GNDANA. The ground pins for VDDIO are GNDIO.
Refer to Electrical Characteristics chapter for power consumption on the various supply pins.
3.5.2 Voltage Regulator
The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up
to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on
VDDCORE and powers the core, memories and peripherals.
Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid
oscillations.
The best way to achieve this is to use two capacitors in parallel between VDDCORE and
GNDCORE:
• One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the
chip as possible.
• One external 2.2µF (or 3.3µF) X7R capacitor (COUT2).
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce source voltage drop.
The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be
used in parallel (1nF NPO and 4.7µF X7R).
3.3V VDDIN
CIN2 CIN1
1.8V
Regulator
1.8V VDDCORE
COUT2 COUT1
For decoupling recommendations for VDDIO and VDDANA please refer to the Schematic
checklist.
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4. Processor and Architecture
Rev: 1.4.2.0
This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the
AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-
sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical
Reference Manual.
4.1 Features
• 32-bit load/store AVR32A RISC architecture
– 15 general-purpose 32-bit registers
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file
– Fully orthogonal instruction set
– Privileged and unprivileged modes enabling efficient and secure Operating Systems
– Innovative instruction set together with variable instruction length ensuring industry leading
code density
– DSP extention with saturating arithmetic, and a wide variety of multiply instructions
• 3-stage pipeline allows one instruction per clock cycle for most instructions
– Byte, halfword, word and double word memory access
– Multiple interrupt priority levels
• MPU allows for operating systems with memory protection
4.2 AVR32 Architecture
AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensi-
tive embedded applications, with particular emphasis on low power consumption and high code
density. In addition, the instruction set architecture has been tuned to allow a variety of micro-
architectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance
processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.
Through a quantitative approach, a large set of industry recognized benchmarks has been com-
piled and analyzed to achieve the best code density in its class. In addition to lowering the
memory requirements, a compact code size also contributes to the core’s low power characteris-
tics. The processor supports byte and halfword data types without penalty in code size and
performance.
Memory load and store operations are provided for byte, halfword, word, and double word data
with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely
linked to the architecture and is able to exploit code optimization features, both for size and
speed.
In order to reduce code size to a minimum, some instructions have multiple addressing modes.
As an example, instructions with immediates often have a compact format with a smaller imme-
diate, and an extended format with a larger immediate. In this way, the compiler is able to use
the format giving the smallest code size.
Another feature of the instruction set is that frequently used instructions, like add, have a com-
pact format with two operands as well as an extended format with three operands. The larger
format increases performance, allowing an addition and a data move in the same instruction in a
single cycle. Load and store instructions have several different formats in order to reduce code
size and speed up execution.
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The register file is organized as sixteen 32-bit registers and includes the Program Counter, the
Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values
from function calls and is used implicitly by some instructions.
4.3 The AVR32UC CPU
The AVR32UC CPU targets low- and medium-performance applications, and provides an
advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration
hardware is not implemented.
AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch,
one High Speed Bus master for data access, and one High Speed Bus slave interface allowing
other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the
CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing.
Also, power consumption is reduced by not needing a full High Speed Bus access for memory
accesses. A dedicated data RAM interface is provided for communicating with the internal data
RAMs.
A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the
LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the
CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory
range allocated to it, and data transfers are performed using regular load and store instructions.
Details on which devices that are mapped into the local bus space is given in the Memories
chapter of this data sheet.
Figure 4-1 on page 23 displays the contents of AVR32UC.
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Figure 4-1. Overview of the AVR32UC CPU
Reset interface
OCD interface
Interrupt controller interface
Power/
OCD
Reset
system
control
AVR32UC CPU pipeline
MPU
Instruction memory controller Data memory controller
High
High CPU Local
Speed
High Speed Bus master Speed Bus
Bus
Bus slave master
Data RAM interface
master
High Speed Bus
High Speed Bus
High Speed Bus
4.3.1 Pipeline Overview CPU Local Bus
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 24 shows an overview of the AVR32UC pipeline stages.
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Figure 4-2. The AVR32UC Pipeline
MUL Multiply unit
Regf ile Regf ile
IF ID A LU A LU unit
Read w rite
Pref etch unit Decode unit
Load-store
LS
unit
4.3.2 AVR32A Microarchitecture Compliance
AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-
geted at cost-sensitive, lower-end applications like smaller microcontrollers. This
microarchitecture does not provide dedicated hardware registers for shadowing of register file
registers in interrupt contexts. Additionally, it does not provide hardware registers for the return
address registers and return status registers. Instead, all this information is stored on the system
stack. This saves chip area at the expense of slower interrupt handling.
Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These
registers are pushed regardless of the priority level of the pending interrupt. The return address
and status register are also automatically pushed to stack. The interrupt handler can therefore
use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are
restored, and execution continues at the return address stored popped from stack.
The stack is also used to store the status register and return address for exceptions and scall.
Executing the rete or rets instruction at the completion of an exception or system call will pop
this status register and continue execution at the popped return address.
4.3.3 Java Support
AVR32UC does not provide Java hardware acceleration.
4.3.4 Memory Protection
The MPU allows the user to check all memory accesses for privilege violations. If an access is
attempted to an illegal memory address, the access is aborted and an exception is taken. The
MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.
4.3.5 Unaligned Reference Handling
AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is
able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an
address exception. Doubleword-sized accesses with word-aligned pointers will automatically be
performed as two word-sized accesses.
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The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses.
Table 4-1. Instructions with Unaligned Reference Support
Instruction Supported alignment
ld.d Word
st.d Word
4.3.6 Unimplemented Instructions
The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:
• All SIMD instructions
• All coprocessor instructions if no coprocessors are present
• retj, incjosp, popjc, pushjc
• tlbr, tlbs, tlbw
• cache
4.3.7 CPU and Architecture Revision
Three major revisions of the AVR32UC CPU currently exist.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.
AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled
for revision 1 or 2 is binary-compatible with revision 3 CPUs.
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4.4 Programming Model
4.4.1 Register File Configuration
The AVR32UC register file is shown below.
Figure 4-3. The AVR32UC Register File
Application Supervisor INT0 INT1 INT2 INT3 Exception NMI Secure
Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0
PC PC PC PC PC PC PC PC PC
LR LR LR LR LR LR LR LR LR
SP_APP SP_SYS SP_SYS SP_SYS SP_SYS SP_SYS SP_SYS SP_SYS SP_SEC
R12 R12 R12 R12 R12 R12 R12 R12 R12
R11 R11 R11 R11 R11 R11 R11 R11 R11
R10 R10 R10 R10 R10 R10 R10 R10 R10
R9 R9 R9 R9 R9 R9 R9 R9 R9
R8 R8 R8 R8 R8 R8 R8 R8 R8
INT0PC
R7 INT0PC
R7 INT0PC
R7 INT0PC
R7 INT0PC
R7 INT0PC
R7 INT0PC
R7 INT0PC
R7 INT0PC
R7
INT1PC
R6 INT1PC
R6 INT1PC
R6 INT1PC
R6 INT1PC
R6 INT1PC
R6 INT1PC
R6 INT1PC
R6 INT1PC
R6
FINTPC
R5 FINTPC
R5 FINTPC
R5 FINTPC
R5 FINTPC
R5 FINTPC
R5 FINTPC
R5 FINTPC
R5 FINTPC
R5
SMPC
R4 SMPC
R4 SMPC
R4 SMPC
R4 SMPC
R4 SMPC
R4 SMPC
R4 SMPC
R4 SMPC
R4
R3 R3 R3 R3 R3 R3 R3 R3 R3
R2 R2 R2 R2 R2 R2 R2 R2 R2
R1 R1 R1 R1 R1 R1 R1 R1 R1
R0 R0 R0 R0 R0 R0 R0 R0 R0
SR SR SR SR SR SR SR SR SR
SS_STATUS
SS_ADRF
SS_ADRR
SS_ADR0
SS_ADR1
SS_SP_SYS
SS_SP_APP
SS_RAR
SS_RSR
4.4.2 Status Register Configuration
The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4 on
page 26 and Figure 4-5 on page 27. The lower word contains the C, Z, N, V, and Q condition
code flags and the R, T, and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 4-4. The Status Register High Halfword
Bit 31 Bit 16
LC
- - - - DM D - M2 M1 M0 EM I3M I2M
FE I1M I0M GM Bit name
1
0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Initial value
Global Interrupt Mask
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 2 Mask
Interrupt Level 3 Mask
Exception Mask
Mode Bit 0
Mode Bit 1
Mode Bit 2
Reserved
Debug State
Debug State Mask
Reserved
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Figure 4-5. The Status Register Low Halfword
Bit 15 Bit 0
- T - - - - - - - - L Q V N Z C Bit name
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value
Carry
Zero
Sign
Overflow
Saturation
Lock
Reserved
Scratch
Reserved
4.4.3 Processor States
4.4.3.1 Normal RISC State
The AVR32 processor supports several different execution contexts as shown in Table 4-2 on
page 27.
Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
Priority Mode Security Description
1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode
2 Exception Privileged Execute exceptions
3 Interrupt 3 Privileged General purpose interrupt mode
4 Interrupt 2 Privileged General purpose interrupt mode
5 Interrupt 1 Privileged General purpose interrupt mode
6 Interrupt 0 Privileged General purpose interrupt mode
N/A Supervisor Privileged Runs supervisor calls
N/A Application Unprivileged Normal program execution mode
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
4.4.3.2 Debug State
The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
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All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
Debug state can be entered as described in the AVR32UC Technical Reference Manual.
Debug state is exited by the retd instruction.
4.4.4 System Registers
The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions. The table below lists the system registers speci-
fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is
responsible for maintaining correct sequencing of any instructions following a mtsr instruction.
For detail on the system registers, refer to the AVR32UC Technical Reference Manual.
Table 4-3. System Registers
Reg # Address Name Function
0 0 SR Status Register
1 4 EVBA Exception Vector Base Address
2 8 ACBA Application Call Base Address
3 12 CPUCR CPU Control Register
4 16 ECR Exception Cause Register
5 20 RSR_SUP Unused in AVR32UC
6 24 RSR_INT0 Unused in AVR32UC
7 28 RSR_INT1 Unused in AVR32UC
8 32 RSR_INT2 Unused in AVR32UC
9 36 RSR_INT3 Unused in AVR32UC
10 40 RSR_EX Unused in AVR32UC
11 44 RSR_NMI Unused in AVR32UC
12 48 RSR_DBG Return Status Register for Debug mode
13 52 RAR_SUP Unused in AVR32UC
14 56 RAR_INT0 Unused in AVR32UC
15 60 RAR_INT1 Unused in AVR32UC
16 64 RAR_INT2 Unused in AVR32UC
17 68 RAR_INT3 Unused in AVR32UC
18 72 RAR_EX Unused in AVR32UC
19 76 RAR_NMI Unused in AVR32UC
20 80 RAR_DBG Return Address Register for Debug mode
21 84 JECR Unused in AVR32UC
22 88 JOSP Unused in AVR32UC
23 92 JAVA_LV0 Unused in AVR32UC
24 96 JAVA_LV1 Unused in AVR32UC
25 100 JAVA_LV2 Unused in AVR32UC
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Table 4-3. System Registers (Continued)
Reg # Address Name Function
26 104 JAVA_LV3 Unused in AVR32UC
27 108 JAVA_LV4 Unused in AVR32UC
28 112 JAVA_LV5 Unused in AVR32UC
29 116 JAVA_LV6 Unused in AVR32UC
30 120 JAVA_LV7 Unused in AVR32UC
31 124 JTBA Unused in AVR32UC
32 128 JBCR Unused in AVR32UC
33-63 132-252 Reserved Reserved for future use
64 256 CONFIG0 Configuration register 0
65 260 CONFIG1 Configuration register 1
66 264 COUNT Cycle Counter register
67 268 COMPARE Compare register
68 272 TLBEHI Unused in AVR32UC
69 276 TLBELO Unused in AVR32UC
70 280 PTBR Unused in AVR32UC
71 284 TLBEAR Unused in AVR32UC
72 288 MMUCR Unused in AVR32UC
73 292 TLBARLO Unused in AVR32UC
74 296 TLBARHI Unused in AVR32UC
75 300 PCCNT Unused in AVR32UC
76 304 PCNT0 Unused in AVR32UC
77 308 PCNT1 Unused in AVR32UC
78 312 PCCR Unused in AVR32UC
79 316 BEAR Bus Error Address Register
80 320 MPUAR0 MPU Address Register region 0
81 324 MPUAR1 MPU Address Register region 1
82 328 MPUAR2 MPU Address Register region 2
83 332 MPUAR3 MPU Address Register region 3
84 336 MPUAR4 MPU Address Register region 4
85 340 MPUAR5 MPU Address Register region 5
86 344 MPUAR6 MPU Address Register region 6
87 348 MPUAR7 MPU Address Register region 7
88 352 MPUPSR0 MPU Privilege Select Register region 0
89 356 MPUPSR1 MPU Privilege Select Register region 1
90 360 MPUPSR2 MPU Privilege Select Register region 2
91 364 MPUPSR3 MPU Privilege Select Register region 3
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Table 4-3. System Registers (Continued)
Reg # Address Name Function
92 368 MPUPSR4 MPU Privilege Select Register region 4
93 372 MPUPSR5 MPU Privilege Select Register region 5
94 376 MPUPSR6 MPU Privilege Select Register region 6
95 380 MPUPSR7 MPU Privilege Select Register region 7
96 384 MPUCRA Unused in this version of AVR32UC
97 388 MPUCRB Unused in this version of AVR32UC
98 392 MPUBRA Unused in this version of AVR32UC
99 396 MPUBRB Unused in this version of AVR32UC
100 400 MPUAPRA MPU Access Permission Register A
101 404 MPUAPRB MPU Access Permission Register B
102 408 MPUCR MPU Control Register
103-191 448-764 Reserved Reserved for future use
192-255 768-1020 IMPL IMPLEMENTATION DEFINED
4.5 Exceptions and Interrupts
AVR32UC incorporates a powerful exception handling scheme. The different exception sources,
like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well-
defined behavior when multiple exceptions are received simultaneously. Additionally, pending
exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower pri-
ority class.
When an event occurs, the execution of the instruction stream is halted, and execution control is
passed to an event handler at an address specified in Table 4-4 on page 33. Most of the han-
dlers are placed sequentially in the code space starting at the address specified by EVBA, with
four bytes between each handler. This gives ample space for a jump instruction to be placed
there, jumping to the event routine itself. A few critical handlers have larger spacing between
them, allowing the entire event routine to be placed directly at the address specified by the
EVBA-relative offset generated by hardware. All external interrupt sources have autovectored
interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify
the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giv-
ing an offset of maximum 16384 bytes. The target address of the event handler is calculated as
(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception
code segments must be set up appropriately. The same mechanisms are used to service all dif-
ferent types of events, including external interrupt requests, yielding a uniform event handling
scheme.
An interrupt controller does the priority handling of the external interrupts and provides the
autovector offset to the CPU.
4.5.1 System Stack Issues
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
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The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
4.5.2 Exceptions and Interrupt Requests
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and
Bus Error) can not be masked. When an event is accepted, hardware automatically
sets the mask bits corresponding to all sources with equal or lower priority. This inhibits
acceptance of other events of the same or lower priority, except for the critical events
listed above. Software may choose to clear some or all of these bits after saving the
necessary state if other priority schemes are desired. It is the event source’s respons-
ability to ensure that their events are left pending until accepted by the CPU.
2. When a request is accepted, the Status Register and Program Counter of the current
context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-
isters R8-R12 and LR are also automatically stored to stack. Storing the Status
Register ensures that the core is returned to the previous execution mode when the
current event handling is completed. When exceptions occur, both the EM and GM bits
are set, and the application may manually enable nested exceptions if desired by clear-
ing the appropriate bit. Each exception handler has a dedicated handler address, and
this address uniquely identifies the exception source.
3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
ter file bank is selected. The address of the event handler, as shown in Table 4-4, is
loaded into the Program Counter.
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.
4.5.3 Supervisor Calls
The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is
designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. The scall mechanism is designed so that a minimal
execution cycle overhead is experienced when performing supervisor routine calls from time-
critical event handlers.
The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set reference. In order to allow the scall routine to return to the
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.
4.5.4 Debug Requests
The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the
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status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the
Debug Exception handler. By default, Debug mode executes in the exception context, but with
dedicated Return Address Register and Return Status Register. These dedicated registers
remove the need for storing this data to the system stack, thereby improving debuggability. The
mode bits in the status register can freely be manipulated in Debug mode, to observe registers
in all contexts, while retaining full privileges.
Debug mode is exited by executing the retd instruction. This returns to the previous context.
4.5.5 Entry Points for Events
Several different event handler entry points exists. In AVR32UC, the reset address is
0x8000_0000. This places the reset address in the boot flash memory area.
TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-
dler can be placed. This speeds up execution by removing the need for a jump instruction placed
at the program address jumped to by the event hardware. All other exceptions have a dedicated
event routine entry point located relative to EVBA. The handler routine address identifies the
exception source directly.
AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.
ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of
the entries in the MPU. TLB multiple hit exception indicates that an access address did map to
multiple TLB entries, signalling an error.
All external interrupt requests have entry points located at an offset relative to EVBA. This
autovector offset is specified by an external Interrupt Controller. The programmer must make
sure that none of the autovector offsets interfere with the placement of other code. The autovec-
tor offset has 14 address bits, giving an offset of maximum 16384 bytes.
Special considerations should be made when loading EVBA with a pointer. Due to security con-
siderations, the event handlers should be located in non-writeable flash memory, or optionally in
a privileged memory protection region if an MPU is present.
If several events occur on the same instruction, they are handled in a prioritized way. The priority
ordering is presented in Table 4-4. If events occur on several instructions at different locations in
the pipeline, the events on the oldest instruction are always handled before any events on any
younger instruction, even if the younger instruction has events of higher priority than the oldest
instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later
than A.
The addresses and priority of simultaneous events are shown in Table 4-4. Some of the excep-
tions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-point unit.
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Table 4-4. Priority and Handler Addresses for Events
Priority Handler Address Name Event source Stored Return Address
1 0x8000_0000 Reset External input Undefined
2 Provided by OCD system OCD Stop CPU OCD system First non-completed instruction
3 EVBA+0x00 Unrecoverable exception Internal PC of offending instruction
4 EVBA+0x04 TLB multiple hit MPU
5 EVBA+0x08 Bus error data fetch Data bus First non-completed instruction
6 EVBA+0x0C Bus error instruction fetch Data bus First non-completed instruction
7 EVBA+0x10 NMI External input First non-completed instruction
8 Autovectored Interrupt 3 request External input First non-completed instruction
9 Autovectored Interrupt 2 request External input First non-completed instruction
10 Autovectored Interrupt 1 request External input First non-completed instruction
11 Autovectored Interrupt 0 request External input First non-completed instruction
12 EVBA+0x14 Instruction Address CPU PC of offending instruction
13 EVBA+0x50 ITLB Miss MPU
14 EVBA+0x18 ITLB Protection MPU PC of offending instruction
15 EVBA+0x1C Breakpoint OCD system First non-completed instruction
16 EVBA+0x20 Illegal Opcode Instruction PC of offending instruction
17 EVBA+0x24 Unimplemented instruction Instruction PC of offending instruction
18 EVBA+0x28 Privilege violation Instruction PC of offending instruction
19 EVBA+0x2C Floating-point UNUSED
20 EVBA+0x30 Coprocessor absent Instruction PC of offending instruction
21 EVBA+0x100 Supervisor call Instruction PC(Supervisor Call) +2
22 EVBA+0x34 Data Address (Read) CPU PC of offending instruction
23 EVBA+0x38 Data Address (Write) CPU PC of offending instruction
24 EVBA+0x60 DTLB Miss (Read) MPU
25 EVBA+0x70 DTLB Miss (Write) MPU
26 EVBA+0x3C DTLB Protection (Read) MPU PC of offending instruction
27 EVBA+0x40 DTLB Protection (Write) MPU PC of offending instruction
28 EVBA+0x44 DTLB Modified UNUSED
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4.6 Module Configuration
All AT32UC3A3 parts implement the CPU and Architecture Revision 2.
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5. Memories
5.1 Embedded Memories
• Internal High-Speed Flash
– 256KBytes (AT32UC3A3256/S)
– 128Kbytes (AT32UC3A3128/S)
– 64Kbytes (AT32UC3A364/S)
• 0 wait state access at up to 42MHz in worst case conditions
• 1 wait state access at up to 84MHz in worst case conditions
• Pipelined Flash architecture, allowing burst reads from sequential Flash locations, hiding
penalty of 1 wait state access
• Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation
to only 15% compared to 0 wait state operation
• 100 000 write cycles, 15-year data retention capability
• Sector lock capabilities, Bootloader protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User page for data to be preserved during Chip Erase
• Internal High-Speed SRAM
– 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the
High Speed Bud (HSB) matrix
– 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix
5.2 Physical Memory Map
The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot.
Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Techni-
cal Architecture Manual.
The 32-bit physical address space is mapped as follows:
Table 5-1. AT32UC3A3A4 Physical Memory Map
Size Size Size
AT32UC3A3256S AT32UC3A3128S AT32UC3A364S
Start
Device AT32UC3A3256 AT32UC3A3128 AT32UC3A364
Address
AT32UC3A4256S AT32UC3A4128S AT32UC3A464S
AT32UC3A4256 AT32UC3A4128 AT32UC3A464
Embedded CPU SRAM 0x00000000 64KByte 64KByte 64KByte
Embedded Flash 0x80000000 256KByte 128KByte 64KByte
EBI SRAM CS0 0xC0000000 16MByte 16MByte 16MByte
EBI SRAM CS2 0xC8000000 16MByte 16MByte 16MByte
EBI SRAM CS3 0xCC000000 16MByte 16MByte 16MByte
EBI SRAM CS4 0xD8000000 16MByte 16MByte 16MByte
EBI SRAM CS5 0xDC000000 16MByte 16MByte 16MByte
EBI SRAM CS1
0xD0000000 128MByte 128MByte 128MByte
/SDRAM CS0
USB Data 0xE0000000 64KByte 64KByte 64KByte
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Table 5-1. AT32UC3A3A4 Physical Memory Map
Size Size Size
AT32UC3A3256S AT32UC3A3128S AT32UC3A364S
Start
Device AT32UC3A3256 AT32UC3A3128 AT32UC3A364
Address
AT32UC3A4256S AT32UC3A4128S AT32UC3A464S
AT32UC3A4256 AT32UC3A4128 AT32UC3A464
HRAMC0 0xFF000000 32KByte 32KByte 32KByte
HRAMC1 0xFF008000 32KByte 32KByte 32KByte
HSB-PB Bridge A 0xFFFF0000 64KByte 64KByte 64KByte
HSB-PB Bridge B 0xFFFE0000 64KByte 64KByte 64KByte
5.3 Peripheral Address Map
Table 5-2. Peripheral Address Mapping
Address Peripheral Name
0xFF100000
DMACA DMA Controller - DMACA
0xFFFD0000
AES Advanced Encryption Standard - AES
0xFFFE0000
USB USB 2.0 Device and Host Interface - USB
0xFFFE1000
HMATRIX HSB Matrix - HMATRIX
0xFFFE1400
FLASHC Flash Controller - FLASHC
0xFFFE1C00
SMC Static Memory Controller - SMC
0xFFFE2000
SDRAMC SDRAM Controller - SDRAMC
0xFFFE2400 Error code corrector Hamming and Reed Solomon -
ECCHRS
ECCHRS
0xFFFE2800
BUSMON Bus Monitor module - BUSMON
0xFFFE4000
MCI Mulitmedia Card Interface - MCI
0xFFFE8000
MSI Memory Stick Interface - MSI
0xFFFF0000
PDCA Peripheral DMA Controller - PDCA
0xFFFF0800
INTC Interrupt controller - INTC
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Table 5-2. Peripheral Address Mapping
0xFFFF0C00
PM Power Manager - PM
0xFFFF0D00
RTC Real Time Counter - RTC
0xFFFF0D30
WDT Watchdog Timer - WDT
0xFFFF0D80
EIC External Interrupt Controller - EIC
0xFFFF1000
GPIO General Purpose Input/Output Controller - GPIO
0xFFFF1400 Universal Synchronous/Asynchronous
USART0
Receiver/Transmitter - USART0
0xFFFF1800 Universal Synchronous/Asynchronous
USART1
Receiver/Transmitter - USART1
0xFFFF1C00 Universal Synchronous/Asynchronous
USART2
Receiver/Transmitter - USART2
0xFFFF2000 Universal Synchronous/Asynchronous
USART3
Receiver/Transmitter - USART3
0xFFFF2400
SPI0 Serial Peripheral Interface - SPI0
0xFFFF2800
SPI1 Serial Peripheral Interface - SPI1
0xFFFF2C00
TWIM0 Two-wire Master Interface - TWIM0
0xFFFF3000
TWIM1 Two-wire Master Interface - TWIM1
0xFFFF3400
SSC Synchronous Serial Controller - SSC
0xFFFF3800
TC0 Timer/Counter - TC0
0xFFFF3C00
ADC Analog to Digital Converter - ADC
0xFFFF4000
ABDAC Audio Bitstream DAC - ABDAC
0xFFFF4400
TC1 Timer/Counter - TC1
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Table 5-2. Peripheral Address Mapping
0xFFFF5000
TWIS0 Two-wire Slave Interface - TWIS0
0xFFFF5400
TWIS1 Two-wire Slave Interface - TWIS1
5.4 CPU Local Bus Mapping
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bus, and by accesses on the local bus.
Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
The following GPIO registers are mapped on the local bus:
Table 5-3. Local Bus Mapped GPIO Registers
Local Bus
Port Register Mode Address Access
0 Output Driver Enable Register (ODER) WRITE 0x40000040 Write-only
SET 0x40000044 Write-only
CLEAR 0x40000048 Write-only
TOGGLE 0x4000004C Write-only
Output Value Register (OVR) WRITE 0x40000050 Write-only
SET 0x40000054 Write-only
CLEAR 0x40000058 Write-only
TOGGLE 0x4000005C Write-only
Pin Value Register (PVR) - 0x40000060 Read-only
1 Output Driver Enable Register (ODER) WRITE 0x40000140 Write-only
SET 0x40000144 Write-only
CLEAR 0x40000148 Write-only
TOGGLE 0x4000014C Write-only
Output Value Register (OVR) WRITE 0x40000150 Write-only
SET 0x40000154 Write-only
CLEAR 0x40000158 Write-only
TOGGLE 0x4000015C Write-only
Pin Value Register (PVR) - 0x40000160 Read-only
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Table 5-3. Local Bus Mapped GPIO Registers
Local Bus
Port Register Mode Address Access
2 Output Driver Enable Register (ODER) WRITE 0x40000240 Write-only
SET 0x40000244 Write-only
CLEAR 0x40000248 Write-only
TOGGLE 0x4000024C Write-only
Output Value Register (OVR) WRITE 0x40000250 Write-only
SET 0x40000254 Write-only
CLEAR 0x40000258 Write-only
TOGGLE 0x4000025C Write-only
Pin Value Register (PVR) - 0x40000260 Read-only
3 Output Driver Enable Register (ODER) WRITE 0x40000340 Write-only
SET 0x40000344 Write-only
CLEAR 0x40000348 Write-only
TOGGLE 0x4000034C Write-only
Output Value Register (OVR) WRITE 0x40000350 Write-only
SET 0x40000354 Write-only
CLEAR 0x40000358 Write-only
TOGGLE 0x4000035C Write-only
Pin Value Register (PVR) - 0x40000360 Read-only
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6. Boot Sequence
This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after power-
up is controlled by the Power Manager. For specific details, refer to Section 7. ”Power Manager
(PM)” on page 41.
6.1 Starting of Clocks
After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the
power has stabilized throughout the device. Once the power has stabilized, the device will use
the internal RC Oscillator as clock source.
On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have
a divided frequency, all parts of the system receives a clock with the same frequency as the
internal RC Oscillator.
6.2 Fetching of Initial Instructions
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset
address, which is 0x8000_0000. This address points to the first address in the internal Flash.
The internal Flash uses VDDIO voltage during read and write operations. BOD33 monitors this
voltage and maintains the device under reset until VDDIO reaches the minimum voltage, pre-
venting any spurious execution from flash.
The code read from the internal Flash is free to configure the system to use for example the
PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
When powering up the device, there may be a delay before the voltage has stabilized, depend-
ing on the rise time of the supply used. The CPU can start executing code as soon as the supply
is above the POR threshold, and before the supply is stable. Before switching to a high-speed
clock source, the user should use the BOD to make sure the VDDCORE is above the minimum-
level (1.62V).
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7. Power Manager (PM)
Rev: 2.3.1.0
7.1 Features
• Controls integrated oscillators and PLLs
• Generates clocks and resets for digital logic
• Supports 2 crystal oscillators 0.4-20MHz
• Supports 2 PLLs 40-240MHz
• Supports 32KHz ultra-low power oscillator
• Integrated low-power RC oscillator
• On-the fly frequency change of CPU, HSB, PBA, and PBB clocks
• Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators
• Module-level clock gating through maskable peripheral clocks
• Wake-up from internal or external interrupts
• Generic clocks with wide frequency range provided
• Automatic identification of reset sources
• Controls brownout detector (BOD and BOD33), RC oscillator, and bandgap voltage reference
through control and calibration registers
7.2 Overview
The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and
resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can
multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power
32KHz oscillator is used to generate the real-time counter clock for high accuracy real-time mea-
surements. The PM also contains a low-power RC oscillator with fast start-up time, which can be
used to clock the digital logic.
The provided clocks are divided into synchronous and generic clocks. The synchronous clocks
are used to clock the main digital logic in the device, namely the CPU, and the modules and
peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous
clocks, which can be tuned precisely within a wide frequency range, which makes them suitable
for peripherals that require specific frequencies, such as timers and communication modules.
The PM also contains advanced power-saving features, allowing the user to optimize the power
consumption for an application. The synchronous clocks are divided into three clock domains,
one for the CPU and HSB, one for modules on the PBA bus, and one for modules on the PBB
bus.The three clocks can run at different speeds, so the user can save power by running periph-
erals at a relatively low clock, while maintaining a high CPU performance. Additionally, the
clocks can be independently changed on-the-fly, without halting any peripherals. This enables
the user to adjust the speed of the CPU and memories to the dynamic load of the application,
without disturbing or re-configuring active peripherals.
Each module also has a separate clock, enabling the user to switch off the clock for inactive
modules, to save further power. Additionally, clocks and oscillators can be automatically
switched off during idle periods by using the sleep instruction on the CPU. The system will return
to normal on occurrence of interrupts.
The Power Manager also contains a Reset Controller, which collects all possible reset sources,
generates hard and soft resets, and allows the reset source to be identified by software.
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7.3 Block Diagram
Figure 7-1. Power Manager Block Diagram
Synchronous
RCSYS Synchronous clocks
Clock Generator CPU, HSB,
PBA, PBB
O scillator 0
PLL0
O scillator 1 PLL1
G eneric Clock
Generic clocks
G enerator
32 KHz
CLK_32
O scillator
OSC /PLL
Control signals RC
O scillator
Slow clock
O scillator and Startup
PLL Control Counter
Voltage Regulator
Sleep
Interrupts Sleep Controller instruction
Calibration
fuses
Registers
Brown-O ut
Reset Controller resets
Detector
Power-O n
Detector
Other reset
sources
External Reset Pad
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7.4 Product Dependencies
7.4.1 I/O Lines
The PM provides a number of generic clock outputs, which can be connected to output pins,
multiplexed with I/O lines. The user must first program the I/O controller to assign these pins to
their peripheral function. If the I/O pins of the PM are not used by the application, they can be
used for other purposes by the I/O controller.
7.4.2 Interrupt
The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using
the PM interrupt requires the interrupt controller to be programmed first.
7.5 Functional Description
7.5.1 Slow Clock
The slow clock is generated from an internal RC oscillator which is always running, except in
Static mode. The slow clock can be used for the main clock in the device, as described in Sec-
tion 7.5.5. The slow clock is also used for the Watchdog Timer and measuring various delays in
the Power Manager.
The RC oscillator has a 3 cycles startup time, and is always available when the CPU is running.
The RC oscillator operates at approximately 115 kHz. Software can change RC oscillator cali-
bration through the use of the RCCR register. Please see the Electrical Characteristics section
for details.
RC oscillator can also be used as the RTC clock when crystal accuracy is not required.
7.5.2 Oscillator 0 and 1 Operation
The two main oscillators are designed to be used with an external crystal and two biasing capac-
itors, as shown in Figure 7-2 on page 44. Oscillator 0 can be used for the main clock in the
device, as described in Section 7.5.5. Both oscillators can be used as source for the generic
clocks, as described in Section 7.5.8.
The oscillators are disabled by default after reset. When the oscillators are disabled, the XIN and
XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an
external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a
general purpose I/O.
The oscillators can be enabled by writing to the OSCnEN bits in MCCTRL. Operation mode
(external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are
automatically switched off in certain sleep modes to reduce power consumption, as described in
Section 7.5.7.
After a hard reset, or when waking up from a sleep mode that disabled the oscillators, the oscil-
lators may need a certain amount of time to stabilize on the correct frequency. This start-up time
can be set in the OSCCTRLn register.
The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks
propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared
according to the status of the oscillators. A zero to one transition on these bits can also be con-
figured to generate an interrupt, as described in Section 7.6.7.
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Figure 7-2. Oscillator Connections
C2
XO UT
XIN
C1
7.5.3 32 KHz Oscillator Operation
The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator
is used as source clock for the Real-Time Counter.
The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32.
The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static
mode.
While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general
purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in
OSCCTRL32 register), the external clock must be connected to XIN32 while the XOUT32 pin
can be used as a general purpose I/O.
The startup time of the 32 KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY
in POSCSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY.
As a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 KHz
oscillator will keep running across resets, except Power-On-Reset.
7.5.4 PLL Operation
The device contains two PLLs, PLL0 and PLL1. These are disabled by default, but can be
enabled to provide high frequency source clocks for synchronous or generic clocks. The PLLs
can take either Oscillator 0 or 1 as reference clock. The PLL output is divided by a multiplication
factor, and the PLL compares the resulting clock to the reference clock. The PLL will adjust its
output frequency until the two compared clocks are equal, thus locking the output frequency to a
multiple of the reference clock frequency.
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from
receiving a too high frequency and thus become unstable.
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Figure 7-3. PLL with Control Logic and Filters
PLLMUL
Output
Mask PLL clock
Divider
Osc0 clock 0
Input Fin PLL LOCK
1
Divider
Osc1 clock
PLLEN
PLLOSC PLLOPT
PLLDIV
7.5.4.1 Enabling the PLL
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and
division factors, respectively, creating the voltage controlled ocillator frequency fVCO and the PLL
frequency fPLL :
if PLLDIV > 0
fIN = fOSC/2 • PLLDIV
fVCO = (PLLMUL+1)/(PLLDIV) • fOSC
if PLLDIV = 0
fIN = fOSC
fVCO = 2 • (PLLMUL+1) • fOSC
Note: Refer to Electrical Characteristics section for FIN and FVCO frequency range.
If PLLOPT[1] field is set to 0:
fPLL = fVCO.
If PLLOPT[1] field is set to 1:
fPLL = fVCO / 2.
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The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
7.5.5 Synchronous Clocks
The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the
common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main
clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from
any tapping of this prescaler, or the undivided main clock, as long as fCPU ≥ fPBA,B,. The synchro-
nous clock source can be changed on-the fly, responding to varying load in the application. The
clock domains can be shut down in sleep mode, as described in Section 7.5.7. Additionally, the
clocks for each module in the four domains can be individually masked, to avoid power con-
sumption in inactive modules.
Figure 7-4. Synchronous Clock Generation
Sleep Sleep
instruction Controller
0
Main clock Mask CPU clocks
Slow clock
1
Osc0 clock HSB clocks
PLL0 clock
Prescaler
PBAclocks
CPUMASK
CPUDIV
PBB clocks
MCSEL CPUSEL
7.5.5.1 Selecting PLL or oscillator for the main clock
The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default,
the main clock will be connected to the slow clock. The user can connect the main clock to Oscil-
lator 0 or PLL0 by writing the MCSEL field in the Main Clock Control Register (MCCTRL). This
must only be done after that unit has been enabled, otherwise a deadlock will occur. Care
should also be taken that the new frequency of the synchronous clocks does not exceed the
maximum frequency for each clock domain.
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7.5.5.2 Selecting synchronous clock division ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CKSEL.CPUDIV to 1 and CPUSEL to the prescaling
value, resulting in a CPU clock frequency:
( CPUSEL + 1 )
f CPU = f main ⁄ 2
Similarly, the clock for the PBA, and PBB can be divided by writing their respective fields. To
ensure correct operation, frequencies must be selected so that fCPU ≥ fPBA,B. Also, frequencies
must never exceed the specified maximum frequency for each clock domain.
CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a
new clock setting to be written to all synchronous clocks at the same time. It is possible to keep
one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL
fields. This way, it is possible to e.g. scale CPU and HSB speed according to the required perfor-
mance, while keeping the PBA and PBB frequency constant.
For modules connected to the HSB bus, the PB clock frequency must be set to the same fre-
quency than the CPU clock.
7.5.5.3 Clock ready flag
There is a slight delay from CKSEL is written and the new clock setting becomes effective. Dur-
ing this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER.CKRDY is written to
one, the Power Manager interrupt can be triggered when the new clock setting is effective.
CKSEL must not be re-written while CKRDY is zero, or the system may become unstable or
hang.
7.5.6 Peripheral Clock Masking
By default, the clock for all modules are enabled, regardless of which modules are actually being
used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock
domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0.
When a module is not clocked, it will cease operation, and its registers cannot be read or written.
The module can be re-enabled later by writing the corresponding mask bit to 1.
A module may be connected to several clock domains, in which case it will have several mask
bits.
Table 7-7 on page 58 contains the list of implemented maskable clocks.
7.5.6.1 Cautionary note
The OCD clock must never be switched off if the user wishes to debug the device with a JTAG
debugger.
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the internal RAM will cause a problem if the stack is mapped there.
Switching off the clock to the Power Manager (PM), which contains the mask registers, or the
corresponding PBx bridge, will make it impossible to write the mask registers again. In this case,
they can only be re-enabled by a system reset.
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7.5.6.2 Mask ready flag
Due to synchronization in the clock generator, there is a slight delay from a mask register is writ-
ten until the new mask setting goes into effect. When clearing mask bits, this delay can usually
be ignored. However, when setting mask bits, the registers in the corresponding module must
not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR pro-
vides the required mask status information. When writing either mask register with any value,
this bit is cleared. The bit is set when the clocks have been enabled and disabled according to
the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the
MSKRDY bit in IER.
7.5.7 Sleep Modes
In normal operation, all clock domains are active, allowing software execution and peripheral
operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other
clock domains to save power. This is activated by the sleep instruction, which takes the sleep
mode index number as argument.
7.5.7.1 Entering and exiting sleep modes
The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.
The modules will be halted regardless of the bit settings of the mask registers.
Oscillators and PLLs can also be switched off to save power. Some of these modules have a rel-
atively long start-up time, and are only switched off when very low power consumption is
required.
The CPU and affected modules are restarted when the sleep mode is exited. This occurs when
an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if
the source module is not clocked.
7.5.7.2 Supported sleep modes
The following sleep modes are supported. These are detailed in Table 7-1 on page 49.
• Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any
interrupt.
• Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up
sources are any interrupt from PB modules.
• Standby: All synchronous clocks are stopped, but oscillators and PLLs are running, allowing
quick wake-up to normal mode. Wake-up sources are RTC or external interrupt.
• Stop: As Standby, but Oscillator 0 and 1, and the PLLs are stopped. 32 KHz (if enabled) and
RC oscillators and RTC/WDT still operate. Wake-up sources are RTC, external interrupt, or
external reset pin.
• DeepStop: All synchronous clocks, Oscillator 0 and 1 and PLL 0 and 1 are stopped. 32 KHz
oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference, BOD
and BOD33 are turned off. Wake-up sources are RTC, external interrupt (EIC) or external
reset pin.
• Static: All oscillators, including 32 KHz and RC oscillator are stopped. Bandgap voltage
reference, BOD and BOD33 detectors are turned off. Wake-up sources are external interrupt
(EIC) in asynchronous mode only or external reset pin.
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Table 7-1. Sleep Modes
Osc0,1 BOD &
PBA,B PLL0,1, BOD33 & Voltage
Index Sleep Mode CPU HSB GCLK SYSTIMER Osc32 RCSYS Bandgap Regulator
0 Idle Stop Run Run Run Run Run On Full power
1 Frozen Stop Stop Run Run Run Run On Full power
2 Standby Stop Stop Stop Run Run Run On Full power
3 Stop Stop Stop Stop Stop Run Run On Low power
4 DeepStop Stop Stop Stop Stop Run Run Off Low power
5 Static Stop Stop Stop Stop Stop Stop Off Low power
The power level of the internal voltage regulator is also adjusted according to the sleep mode to
reduce the internal regulator power consumption.
7.5.7.3 Precautions when entering sleep mode
Modules communicating with external circuits should normally be disabled before entering a
sleep mode that will stop the module operation. This prevents erratic behavior when entering or
exiting sleep mode. Please refer to the relevant module documentation for recommended
actions.
Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. This means that bus transactions are not allowed between clock domains affected
by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus
transaction.
The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are com-
plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is
necessary.
When entering a sleep mode (except Idle mode), all HSB masters must be stopped before
entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete,
the CPU should perform a read operation from any register on the PB bus before executing the
sleep instruction. This will stall the CPU while waiting for any pending PB operations to
complete.
When entering a sleep mode deeper or equal to DeepStop, the VBus asynchronous interrupt
should be disabled (USBCON.VBUSTE = 0).
7.5.7.4 Wake Up
The USB can be used to wake up the part from sleep modes through register AWEN of the
Power Manager.
7.5.8 Generic Clocks
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The Power Manager contains an implementation
defined number of generic clocks that can provide a wide range of accurate clock frequencies.
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Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source
can optionally be divided by any even integer up to 512. Each clock can be independently
enabled and disabled, and is also automatically disabled along with peripheral clocks by the
Sleep Controller.
Figure 7-5. Generic Clock Generation
Sleep
Controller
0
Osc0 clock 0 Mask Generic Clock
Osc1 clock
PLL0 clock
Divider 1
PLL1 clock 1
PLLSEL DIVEN CEN
OSCSEL DIV
7.5.8.1 Enabling a generic clock
A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use
either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV,
resulting in the output frequency:
f GCLK = f SRC ⁄ ( 2 × ( DIV + 1 ) )
7.5.8.2 Disabling a generic clock
The generic clock can be disabled by writing CEN to zero or entering a sleep mode that disables
the PB clocks. In either case, the generic clock will be switched off on the first falling edge after
the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as
1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0,
the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the
generic clock.
When the clock is disabled, both the prescaler and output are reset.
7.5.8.3 Changing clock frequency
When changing generic clock frequency by writing GCCTRL, the clock should be switched off by
the procedure above, before being re-enabled with the new clock source or division setting. This
prevents glitches during the transition.
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7.5.8.4 Generic clock implementation
The generic clocks are allocated to different functions as shown in Table 7-2 on page 51.
Table 7-2. Generic Clock Allocation
Clock number Function
0 GCLK0 pin
1 GCLK1 pin
2 GCLK2 pin
3 GCLK3 pin
4 GCLK_USBB
5 GCLK_ABDAC
7.5.9 Divided PB Clocks
The clock generator in the Power Manager provides divided PBA and PBB clocks for use by
peripherals that require a prescaled PBx clock. This is described in the documentation for the
relevant modules.
The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx
clocks are stopped.
7.5.10 Debug Operation
The OCD clock must never be switched off if the user wishes to debug the device with a JTAG
debugger.
During a debug session, the user may need to halt the system to inspect memory and CPU reg-
isters. The clocks normally keep running during this debug operation, but some peripherals may
require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program
to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx
clocks. This is described in the documentation for the relevant modules. The divided PBx clocks
are always debug qualified clocks.
Debug qualified PBx clocks are stopped during debug operation. The debug system can option-
ally keep these clocks running during the debug operation. This is described in the
documentation for the On-Chip Debug system.
7.5.11 Reset Controller
The Reset Controller collects the various reset sources in the system and generates hard and
soft resets for the digital logic.
The device contains a Power-On Detector, which keeps the system reset until power is stable.
This eliminates the need for external reset circuitry to guarantee stable operation when powering
up the device.
It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pul-
lup, and does not need to be driven externally when negated. Table 7-4 on page 53 lists these
and other reset sources supported by the Reset Controller.
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Figure 7-6. Reset Controller Block Diagram
R C _R CAU SE
RESET_N
P o w e r-O n CPU, HSB,
D e te c to r PBA, PBB
R eset
B ro w n o u t C o n tro lle r O C D , R T C /W D T ,
D e te c to r C lo c k G e n e ra to r
JTA G
OCD
WDT
In addition to the listed reset types, the JTAG can keep parts of the device statically reset
through the JTAG Reset Register. See JTAG documentation for details.
Table 7-3. Reset Description
Reset source Description
Power-on Reset Supply voltage below the power-on reset detector
threshold voltage
External Reset RESET_N pin asserted
Brownout Reset Supply voltage below the brownout reset detector
threshold voltage
CPU Error Caused by an illegal CPU access to external memory
while in Supervisor mode
Watchdog Timer See watchdog timer documentation.
OCD See On-Chip Debug documentation
When a reset occurs, some parts of the chip are not necessarily reset, depending on the reset
source. Only the Power On Reset (POR) will force a reset of the whole chip.
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Table 7-4 on page 53 lists parts of the device that are reset, depending on the reset source.
Table 7-4. Effect of the Different Reset Events
CPU
Power-On External Watchdog BOD BOD33 Error OCD
Reset Reset Reset Reset Reset Reset Reset
CPU/HSB/PBA/PBB Y Y Y Y Y Y Y
(excluding Power Manager)
32 KHz oscillator Y N N N N N N
RTC control register Y N N N N N N
GPLP registers Y N N N N N N
Watchdog control register Y Y N Y Y Y Y
Voltage calibration register Y N N N N N N
RCSYS Calibration register Y N N N N N N
BOD control register Y Y N N N N N
BOD33 control register Y Y N N N N N
Bandgap control register Y Y N N N N N
Clock control registers Y Y Y Y Y Y Y
Osc0/Osc1 and control registers Y Y Y Y Y Y Y
PLL0/PLL1 and control registers Y Y Y Y Y Y Y
OCD system and OCD registers Y Y N Y Y Y N
The cause of the last reset can be read from the RCAUSE register. This register contains one bit
for each reset source, and can be read during the boot sequence of an application to determine
the proper action to be taken.
7.5.11.1 Power-On detector
The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the
device is powered on. The reset is active until the supply voltage from the linear regulator is
above the power-on threshold level. The reset will be re-activated if the voltage drops below the
power-on threshold level. See Electrical Characteristics for parametric details.
7.5.11.2 Brown-Out detector
The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply
voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD is disabled by default,
but can be enabled either by software or by flash fuses. The Brown-Out Detector can either gen-
erate an interrupt or a reset when the supply voltage is below the brown-out detection level. In
any case, the BOD output is available in bit POSCSR.BODDET bit.
Note that any change to the BOD.LEVEL field of the BOD register should be done with the BOD
deactivated to avoid spurious reset or interrupt.
See Electrical Characteristics chapter for parametric details.
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7.5.11.3 Brown-Out detector 3V3
The Brown-Out Detector 3V3 (BOD33) monitors one VDDIO supply pin and compares the sup-
ply voltage to the brown-out detection 3V3 level, which is typically calibrated at 2V7. The BOD33
is enabled by default, but can be disabled by software. The Brown-Out Detector 3V3 can either
generate an interrupt or a reset when the supply voltage is below the brown-out detection3V3
level. In any case, the BOD33 output is available in bit POSCSR.BOD33DET bit.
Note that any change to the BOD33.LEVEL field of the BOD33 register should be done with the
BOD33 deactivated to avoid spurious reset or interrupt.
The BOD33.LEVEL default value is calibrated to 2V7
See Electrical Characteristics chapter for parametric details.
Table 7-5. VDDIO pin monitored by BOD33
TFBGA144 QFP144 VFBGA100
H5 81 E5
7.5.11.4 External reset
The external reset detector monitors the state of the RESET_N pin. By default, a low level on
this pin will generate a reset.
7.5.12 Calibration Registers
The Power Manager controls the calibration of the RC oscillator, voltage regulator, bandgap
voltage reference through several calibrations registers.
Those calibration registers are loaded after a Power On Reset with default values stored in fac-
tory-programmed flash fuses.
Although it is not recommended to override default factory settings, it is still possible to override
these default values by writing to those registers. To prevent unexpected writes due to software
bugs, write access to these registers is protected by a “key”. First, a write to the register must be
made with the field “KEY” equal to 0x55 then a second write must be issued with the “KEY” field
equal to 0xAA.
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7.6 User Interface
Table 7-6. PM Register Memory Map
Offset Register Register Name Access Reset State
0x000 Main Clock Control MCCTRL Read/Write 0x00000000
0x0004 Clock Select CKSEL Read/Write 0x00000000
0x008 CPU Mask CPUMASK Read/Write 0x00000003
0x00C HSB Mask HSBMASK Read/Write 0x00000FFF
0x010 PBA Mask PBAMASK Read/Write 0x001FFFFF
0x014 PBB Mask PBBMASK Read/Write 0x000003FF
0x020 PLL0 Control PLL0 Read/Write 0x00000000
0x024 PLL1 Control PLL1 Read/Write 0x00000000
0x028 Oscillator 0 Control Register OSCCTRL0 Read/Write 0x00000000
0x02C Oscillator 1 Control Register OSCCTRL1 Read/Write 0x00000000
0x030 Oscillator 32 Control Register OSCCTRL32 Read/Write 0x00000000
0x040 PM Interrupt Enable Register IER Write-only 0x00000000
0x044 PM Interrupt Disable Register IDR Write-only 0x00000000
0x048 PM Interrupt Mask Register IMR Read-only 0x00000000
0x04C PM Interrupt Status Register ISR Read-only 0x00000000
00050 PM Interrupt Clear Register ICR Write-only 0x00000000
0x054 Power and Oscillators Status Register POSCSR Read/Write 0x00000000
0x060 Generic Clock Control 0 GCCTRL0 Read/Write 0x00000000
0x064 Generic Clock Control 1 GCCTRL1 Read/Write 0x00000000
0x068 Generic Clock Control 2 GCCTRL2 Read/Write 0x00000000
0x06C Generic Clock Control 3 GCCTRL3 Read/Write 0x00000000
0x070 Generic Clock Control 4 GCCTRL4 Read/Write 0x00000000
0x074 Generic Clock Control 5 GCCTRL5 Read/Write 0x00000000
0x0C0 RC Oscillator Calibration Register RCCR Read/Write Factory settings
0x0C4 Bandgap Calibration Register BGCR Read/Write Factory settings
0x0C8 Linear Regulator Calibration Register VREGCR Read/Write Factory settings
0x0D0 BOD Level Register BOD Read/Write BOD fuses in Flash
BOD33 reset enable
0x0D4 BOD33 Level Register BOD33 Read/Write
BOD33 LEVEL=2V7
0x0140 Reset Cause Register RCAUSE Read/Write Latest Reset Source
0x0144 Asynchronous Wake Enable Register AWEN Read/Write 0x00000000
0x200 General Purpose Low-Power register GPLP Read/Write 0x00000000
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7.6.1 Main Clock Control Register
Name: MCCTRL
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - OSC1EN OSC0EN MCSEL
• OSC1EN: Oscillator 1 Enable
1: Oscillator 1 is enabled
0: Oscillator 1 is disabled
• OSC0EN: Oscillator 0 Enable
1: Oscillator 0 is enabled
0: Oscillator 0 is disabled
• MCSEL: Main Clock Select
This field contains the clock selected as the main clock.
MCSEL Selected Clock
0b00 Slow Clock
0b01 Oscillator 0
0b10 PLL 0
0b11 Reserved
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7.6.2 Clock Select Register
Name: CKSEL
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
PBBDIV - - - - PBBSEL
23 22 21 20 19 18 17 16
PBADIV - - - - PBASEL
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
CPUDIV - - - - CPUSEL
• PBBDIV: PBB Division Enable
PBBDIV = 0: PBB clock equals main clock.
PBBDIV = 1: PBB clock equals main clock divided by 2(PBBSEL+1).
• PBADIV, PBASEL: PBA Division and Clock Select
PBADIV = 0: PBA clock equals main clock.
PBADIV = 1: PBA clock equals main clock divided by 2(PBASEL+1).
• CPUDIV, CPUSEL: CPU/HSB Division and Clock Select
CPUDIV = 0: CPU/HSB clock equals main clock.
CPUDIV = 1: CPU/HSB clock equals main clock divided by 2(CPUSEL+1).
Note that if xxxDIV is written to 0, xxxSEL should also be written to 0 to ensure correct operation.
Also note that writing this register clears POSCSR.CKRDY. The register must not be re-written until CKRDY goes high.
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7.6.3 Clock Mask Registers
Name: CPU/HSB/PBA/PBBMASK
Access Type: Read/Write
Offset: 0x08-0x14
Reset Value: 0x00000003/0x00000FFF/0x001FFFFF/0x000003FF
31 30 29 28 27 26 25 24
MASK[31:24]
23 22 21 20 19 18 17 16
MASK[23:16]
15 14 13 12 11 10 9 8
MASK[15:8]
7 6 5 4 3 2 1 0
MASK[7:0]
• MASK: Clock Mask
If bit n is written to zero, the clock for module n is stopped. If bit n is writen to one, the clock for module n is enabled according to
the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by
each bit, is shown in Table 7-7 on page 58.
Table 7-7. Maskable module clocks in AT32UC3A3.
Bit CPUMASK HSBMASK PBAMASK PBBMASK
0 - FLASHC INTC HMATRIX
1 OCD(1) PBA Bridge I/O USBB
2 - PBB Bridge PDCA FLASHC
3 - USBB PM/RTC/EIC SMC
4 - PDCA ADC SDRAMC
5 - EBI SPI0 ECCHRS
6 - PBC Bridge SPI1 MCI
7 - DMACA TWIM0 BUSMON
8 - BUSMON TWIM1 MSI
9 - HRAMC0 TWIS0 AES
10 - HRAMC1 TWIS1 -
(2)
11 - USART0 -
12 - - USART1 -
13 - - USART2 -
14 - - USART3 -
15 - - SSC -
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Table 7-7. Maskable module clocks in AT32UC3A3.
Bit CPUMASK HSBMASK PBAMASK PBBMASK
16 SYSTIMER - TC0 -
(compare/count
registers clk)
17 - - TC1 -
18 - - ABDAC -
(2)
19 - - -
(2)
20 - - -
31:21 - - - -
Note: 1. This bit must be set to one if the user wishes to debug the device with a JTAG debugger.
2. This bits must be set to one
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7.6.4 PLL Control Registers
Name: PLL0,1
Access Type: Read/Write
Offset: 0x20-0x24
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
PLLTEST - PLLCOUNT
23 22 21 20 19 18 17 16
- - - - PLLMUL
15 14 13 12 11 10 9 8
- - - - PLLDIV
7 6 5 4 3 2 1 0
- - - PLLOPT PLLOSC PLLEN
• PLLTEST: PLL Test
Reserved for internal use. Always write to 0.
• PLLCOUNT: PLL Count
Specifies the number of slow clock cycles before ISR.LOCKn will be set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiting a sleep mode.
• PLLMUL: PLL Multiply Factor
• PLLDIV: PLL Division Factor
These fields determine the ratio of the PLL output frequency to the source oscillator frequency. Formula is detallied in Section
7.5.4.1
• PLLOPT: PLL Option
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range
PLLOPT[1]: Enable the extra output divider
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time)
Description
PLLOPT[0]: VCO frequency 0 80MHz<fvco<180MHz
1 160MHz<fvco<240MHz
PLLOPT[1]: Output divider 0 fPLL = fvco
1 fPLL = fvco/2
PLLOPT[2] 0 Wide Bandwidth Mode enabled
1 Wide Bandwidth Mode disabled
• PLLOSC: PLL Oscillator Select
0: Oscillator 0 is the source for the PLL.
1: Oscillator 1 is the source for the PLL.
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• PLLEN: PLL Enable
0: PLL is disabled.
1: PLL is enabled.
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7.6.5 Oscillator 0/1 Control Registers
Name: OSCCTRL0,1
Access Type: Read/Write
Offset: 0x28-0x2C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - STARTUP
7 6 5 4 3 2 1 0
- - - - - MODE
• STARTUP: Oscillator Startup Time
Select startup time for the oscillator.
Number of RC oscillator Approximative Equivalent time
STARTUP clock cycle (RCSYS = 115 kHz)
0 0 0
1 64 560 us
2 128 1.1 ms
3 2048 18 ms
4 4096 36 ms
5 8192 71 ms
6 16384 142 ms
7 Reserved Reserved
• MODE: Oscillator Mode
Choose between crystal, or external clock
0: External clock connected on XIN, XOUT can be used as an I/O (no crystal)
1 to 3: reserved
4: Crystal is connected to XIN/XOUT - Oscillator is used with gain G0 ( XIN from 0.4 MHz to 0.9 MHz ).
5: Crystal is connected to XIN/XOUT - Oscillator is used with gain G1 ( XIN from 0.9 MHz to 3.0 MHz ).
6: Crystal is connected to XIN/XOUT - Oscillator is used with gain G2 ( XIN from 3.0 MHz to 8.0 MHz ).
7: Crystal is connected to XIN/XOUT - Oscillator is used with gain G3 ( XIN from 8.0 Mhz).
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7.6.6 32 KHz Oscillator Control Register
Name: OSCCTRL32
Access Type: Read/Write
Offset: 0x30
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - STARTUP
15 14 13 12 11 10 9 8
- - - - - MODE
7 6 5 4 3 2 1 0
- - - - - - - OSC32EN
• STARTUP: Oscillator Startup Time
Select startup time for 32 KHz oscillator
Number of RC oscillator Approximative Equivalent time
STARTUP clock cycle (RCSYS = 115 kHz)
0 0 0
1 128 1.1 ms
2 8192 72.3 ms
3 16384 143 ms
4 65536 570 ms
5 131072 1.1 s
6 262144 2.3 s
7 524288 4.6 s
Note: This register is only reset by Power-On Reset
• MODE: Oscillator Mode
Choose between crystal, or external clock
0: External clock connected on XIN32, XOUT32 can be used as a I/O (no crystal)
1: Crystal is connected to XIN32/XOUT32 - Oscillator is used with automatic gain control
2 to 7: Reserved
• OSC32EN: Enable the 32 KHz oscillator
0: 32 KHz Oscillator is disabled
1: 32 KHz Oscillator is enabled
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7.6.7 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
7 6 5 4 3 2 1 0
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
Writing a one to a bit in this register will set the corresponding bit in IMR.
Writing a zero to a bit in this register has no effect.
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7.6.8 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x44
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
7 6 5 4 3 2 1 0
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
Writing a one to a bit in this register will clear the corresponding bit in IMR.
Writing a zero to a bit in this register has no effect.
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7.6.9 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x48
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
7 6 5 4 3 2 1 0
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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7.6.10 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x4C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
7 6 5 4 3 2 1 0
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
• BOD33DET: Brown out detection
This bit is set when a 0 to 1 transition on POSCSR.BOD33DET bit is detected: BOD33 has detected that power supply is
going below BOD33 reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
• BODDET: Brown out detection
This bit is set when a 0 to 1 transition on POSCSR.BODDET bit is detected: BOD has detected that power supply is going
below BOD reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
• OSC32RDY: 32 KHz oscillator Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC32RDY bit is detected: The 32 KHz oscillator is stable and
ready to be used as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
• OSC1RDY: Oscillator 1 Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected: Oscillator 1 is stable and ready to be used
as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
• OSC0RDY: Oscillator 0 Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected: Oscillator 1 is stable and ready to be used
as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
• MSKRDY: Mask Ready
This bit is set when a 0 to 1 transition on the POSCSR.MSKRDY bit is detected: Clocks are now masked according to the
(CPU/HSB/PBA/PBB)_MASK registers.
This bit is cleared when the corresponding bit in ICR is written to one.
• CKRDY: Clock Ready
0: The CKSEL register has been written, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register.
Note: Writing a one to ICR.CKRDY has no effect.
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• LOCK1: PLL1 locked
This bit is set when a 0 to 1 transition on the POSCSR.LOCK1 bit is detected: PLL 1 is locked and ready to be selected as
clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
• LOCK0: PLL0 locked
This bit is set when a 0 to 1 transition on the POSCSR.LOCK0 bit is detected: PLL 0 is locked and ready to be selected as
clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
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7.6.11 Interrupt Clear Register
Name: ICR
Access Type: Write-only
Offset: 0x50
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
7 6 5 4 3 2 1 0
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request.
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7.6.12 Power and Oscillators Status Register
Name: POSCSR
Access Type: Read-only
Offset: 0x54
Reset Value: 0x00000020
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
7 6 5 4 3 2 1 0
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
• BOD33DET: Brown out 3V3 detection
0: No BOD33 event
1: BOD33 has detected that power supply is going below BOD33 reference value.
• BODDET: Brown out detection
0: No BOD event
1: BOD has detected that power supply is going below BOD reference value.
• OSC32RDY: 32 KHz oscillator Ready
0: The 32 KHz oscillator is not enabled or not ready.
1: The 32 KHz oscillator is stable and ready to be used as clock source.
• OSC1RDY: OSC1 ready
0: Oscillator 1 not enabled or not ready.
1: Oscillator 1 is stable and ready to be used as clock source.
• OSC0RDY: OSC0 ready
0: Oscillator 0 not enabled or not ready.
1: Oscillator 0 is stable and ready to be used as clock source.
• MSKRDY: Mask ready
0: Mask register has been changed, masking in progress.
1: Clock are masked according to xxx_MASK
• CKRDY:
0: The CKSEL register has been written, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register.
• LOCK1: PLL 1 locked
0:PLL 1 is unlocked
1:PLL 1 is locked, and ready to be selected as clock source.
• LOCK0: PLL 0 locked
0: PLL 0 is unlocked
1: PLL 0 is locked, and ready to be selected as clock source.
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7.6.13 Generic Clock Control Register
Name: GCCTRLx
Access Type: Read/Write
Offset: 0x60 - 0x74
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
DIV[7:0]
7 6 5 4 3 2 1 0
- - - DIVEN - CEN PLLSEL OSCSEL
There is one GCCTRL register per generic clock in the design.
• DIV: Division Factor
• DIVEN: Divide Enable
0: The generic clock equals the undivided source clock.
1: The generic clock equals the source clock divided by 2*(DIV+1).
• CEN: Clock Enable
0: Clock is stopped.
1: Clock is running.
• PLLSEL: PLL Select
0: Oscillator is source for the generic clock.
1: PLL is source for the generic clock.
• OSCSEL: Oscillator Select
0: Oscillator (or PLL) 0 is source for the generic clock.
1: Oscillator (or PLL) 1 is source for the generic clock.
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7.6.14 RC Oscillator Calibration Register
Name: RCCR
Access Type: Read/Write
Offset: 0xC0
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
- - - - - - - FCD
15 14 13 12 11 10 9 8
- - - - - - CALIB
7 6 5 4 3 2 1 0
CALIB
• KEY: Register Write protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
• FCD: Flash Calibration Done
Set to 1 when CTRL, HYST, and LEVEL fields have been updated by the Flash fuses after power-on reset, or after Flash fuses
are reprogrammed. The CTRL, HYST and LEVEL values will not be updated again by the Flash fuses until a new power-on
reset or the FCD field is written to zero.
• CALIB: Calibration Value
Calibration Value for the RC oscillator.
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7.6.15 Bandgap Calibration Register
Name: BGCR
Access Type: Read/Write
Offset: 0xC4
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
- - - - - - - FCD
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - CALIB
• KEY: Register Write protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
• FCD: Flash Calibration Done
Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are
reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is
written to zero.
• CALIB: Calibration value
Calibration value for Bandgap. See Electrical Characteristics for voltage values.
It is not recommended to override default factory settings in the BGCR register. Flash reliability is not guaranted if this value is
modified by the user
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7.6.16 PM Voltage Regulator Calibration Register
Name: VREGCR
Access Type: Read/Write
Offset: 0xC8
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
- - - - - - - FCD
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - CALIB
• KEY: Register Write protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
Calibration value for Voltage Regulator. See Electrical Characteristics for voltage values.
• FCD: Flash Calibration Done
Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are
reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is
written to zero.
• CALIB: Calibration value
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7.6.17 BOD Control Register
Name: BOD
Access Type: Read/Write
Offset: 0xD0
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
- - - - - - - FCD
15 14 13 12 11 10 9 8
- - - - - - CTRL
7 6 5 4 3 2 1 0
- HYST LEVEL
• KEY: Register Write protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
• FCD: BOD Fuse calibration done
Set to 1 when CTRL, HYST and LEVEL fields has been updated by the Flash fuses after power-on reset or Flash fuses update
If one, the CTRL, HYST and LEVEL values will not be updated again by Flash fuses
Can be cleared to allow subsequent overwriting of the value by Flash fuses
• CTRL: BOD Control
0: BOD is off
1: BOD is enabled and can reset the chip
2: BOD is enabled and but cannot reset the chip. Only interrupt will be sent to interrupt controller, if enabled in the IMR register.
3: BOD is off
• HYST: BOD Hysteresis
0: No hysteresis
1: Hysteresis On
• LEVEL: BOD Level
This field sets the triggering threshold of the BOD. See Electrical Characteristics for actual voltage levels.
Note that any change to the LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset
or interrupt.
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7.6.18 BOD33 Control Register
Name: BOD33
Access Type: Read/Write
Offset: 0xD4
Reset Value: 0x0000010X
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
- - - - - - - FCD
15 14 13 12 11 10 9 8
- - - - - - CTRL
7 6 5 4 3 2 1 0
- - LEVEL
• KEY: Register Write protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
• FCD: BOD33 Fuse calibration done
Set to 1 when LEVEL field has been updated by the Flash fuses after power-on reset or Flash fuses update
If one, the LEVEL value will not be updated again by Flash fuses
Can be cleared to allow subsequent overwriting of the value by Flash fuses
• CTRL: BOD33 Control
0: BOD33 is off
1: BOD33 is enabled and can reset the chip
2: BOD33 is enabled and but cannot reset the chip. Only interrupt will be sent to interrupt controller, if enabled in the IMR
register.
3: BOD33 is off
• LEVEL: BOD33 Level
This field sets the triggering threshold of the BOD33. See Electrical Characteristics for actual voltage levels.
Note that any change to the LEVEL field of the BOD33 register should be done with the BOD33 deactivated to avoid spurious
reset or interrupt.
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7.6.19 Reset Cause Register
Name: RCAUSE
Access Type: Read-only
Offset: 0x140
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - BOD33 - OCDRST
7 6 5 4 3 2 1 0
CPUERR - - JTAG WDT EXT BOD POR
• BOD33: Brown-out 3V3 Reset
The CPU was reset due to the supply voltage 3V3 being lower than the brown-out threshold level.
• OCDRST: OCD Reset
The CPU was reset because the RES strobe in the OCD Development Control register has been written to one.
• CPUERR: CPU Error
The CPU was reset because it had detected an illegal access.
• JTAG: JTAG reset
The CPU was reset by setting the bit RC_CPU in the JTAG reset register.
• WDT: Watchdog Reset
The CPU was reset because of a watchdog timeout.
• EXT: External Reset Pin
The CPU was reset due to the RESET pin being asserted.
• BOD: Brown-out Reset
The CPU was reset due to the supply voltage 1V8 being lower than the brown-out threshold level.
• POR Power-on Reset
The CPU was reset due to the supply voltage being lower than the power-on threshold level.
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7.6.20 Asynchronous Wake Up Enable
Name: AWEN
Access Type: Read/Write
Offset: 0x144
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - USB_WAKEN
• USB_WAKEN : Wake Up Enable Register
Writing a zero to this bit will disable the USB wake up.
Writing a one to this bit will enable the USB wake up.
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7.6.21 General Purpose Low-power Register
Name: GPLP
Access Type: Read/Write
Offset: 0x200
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
GPLP
23 22 21 20 19 18 17 16
GPLP
15 14 13 12 11 10 9 8
GPLP
7 6 5 4 3 2 1 0
GPLP
These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will keep the content
of these registers untouched. User software can use these register to save context variables in a very low power mode.
Two GPLP register are implemented in AT32UC3A3.
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8. Real Time Counter (RTC)
Rev: 2.4.0.1
8.1 Features
• 32-bit real-time counter with 16-bit prescaler
• Clocked from RC oscillator or 32KHz oscillator
• Long delays
– Max timeout 272years
• High resolution: Max count frequency 16KHz
• Extremely low power consumption
• Available in all sleep modes except Static
• Interrupt on wrap
8.2 Overview
The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate mea-
surement of real-time sequences. The RTC is fed from a 16-bit prescaler, which is clocked from
the system RC oscillator or the 32KHz crystal oscillator. Any tapping of the prescaler can be
selected as clock source for the RTC, enabling both high resolution and long timeouts. The pres-
caler cannot be written directly, but can be cleared by the user.
The RTC can generate an interrupt when the counter wraps around the value stored in the top
register (TOP), producing accurate periodic interrupts.
8.3 Block Diagram
Figure 8-1. Real Time Counter Block Diagram
CTRL TOP
CLK32 EN PSEL
CLK_32 1
16-bit Prescaler 32-bit counter TOPI IRQ
RCSYS 0
VAL
8.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
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8.4.1 Power Management
The RTC remains operating in all sleep modes except Static mode. Interrupts are not available
in DeepStop mode.
8.4.2 Clocks
The RTC can use the system RC oscillator as clock source. This oscillator is always enabled
whenever this module is active. Please refer to the Electrical Characteristics chapter for the
characteristic frequency of this oscillator (fRC).
The RTC can also use the 32 KHz crystal oscillator as clock source. This oscillator must be
enabled before use. Please refer to the Power Manager chapter for details.
The clock for the RTC bus interface (CLK_RTC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
RTC before disabling the clock, to avoid freezing the RTC in an undefined state.
8.4.3 Interrupts
The RTC interrupt request line is connected to the interrupt controller. Using the RTC interrupt
requires the interrupt controller to be programmed first.
8.4.4 Debug Operation
The RTC prescaler is frozen during debug operation, unless the OCD system keeps peripherals
running in debug operation.
8.5 Functional Description
8.5.1 RTC Operation
8.5.1.1 Source clock
The RTC is enabled by writing a one to the Enable bit in the Control Register (CTRL.EN). The
16-bit prescaler will then increment on the selected clock. The prescaler cannot be read or writ-
ten, but it can be reset by writing a one to the Prescaler Clear bit in CTRL register (CTRL.PCLR).
The 32KHz Oscillator Select bit in CTRL register (CTRL.CLK32) selects either the RC oscillator
or the 32 KHz oscillator as clock source (defined as INPUT in the formula below) for the
prescaler.
The Prescale Select field in CTRL register (CTRL.PSEL) selects the prescaler tapping, selecting
the source clock for the RTC:
( PSEL + 1 )
f RTC = f INPUT ⁄ 2
8.5.1.2 Counter operation
When enabled, the RTC will increment until it reaches TOP, and then wraps to 0x0. The status
bit TOPI in Interrupt Status Register (ISR) is set to one when this occurs. From 0x0 the counter
will count TOP+1 cycles of the source clock before it wraps back to 0x0.
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The RTC count value can be read from or written to the Value register (VAL). Due to synchroni-
zation, continuous reading of the VAL register with the lowest prescaler setting will skip every
other value.
8.5.1.3 RTC interrupt
The RTC interrupt is enabled by writing a one to the Top Interrupt bit in the Interrupt Enable Reg-
ister (IER.TOPI), and is disabled by writing a one to the Top Interrupt bit in the Interrupt Disable
Register (IDR.TOPI). The Interrupt Mask Register (IMR) can be read to see whether or not the
interrupt is enabled. If enabled, an interrupt will be generated if the TOPI bit in the Interrupt Sta-
tus Register (ISR) is set. The TOPI bit in ISR can be cleared by writing a one to the TOPI bit in
the Interrupt Clear Register (ICR.TOPI).
The RTC interrupt can wake the CPU from all sleep modes except DeepStop and Static modes.
8.5.1.4 RTC wakeup
The RTC can also wake up the CPU directly without triggering an interrupt when the ISR.TOPI
bit is set. In this case, the CPU will continue executing from the instruction following the sleep
instruction.
This direct RTC wake-up is enabled by writing a one to the Wake Enable bit in the CTRL register
(CTRL.WAKEN). When the CPU wakes from sleep, the CTRL.WAKEN bit must be written to
zero to clear the internal wake signal to the sleep controller, otherwise a new sleep instruction
will have no effect.
The RTC wakeup is available in all sleep modes except Static mode. The RTC wakeup can be
configured independently of the RTC interrupt.
8.5.1.5 Busy bit
Due to the crossing of clock domains, the RTC uses a few clock cycles to propagate the values
stored in CTRL, TOP, and VAL to the RTC. The RTC Busy bit in CTRL (CTRL.BUSY) indicates
that a register write is still going on and all writes to TOP, CTRL, and VAL will be discarded until
the CTRL.BUSY bit goes low again.
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8.6 User Interface
Table 8-1. RTC Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CTRL Read/Write 0x00010000
0x04 Value Register VAL Read/Write 0x00000000
0x08 Top Register TOP Read/Write 0xFFFFFFFF
0x10 Interrupt Enable Register IER Write-only 0x00000000
0x14 Interrupt Disable Register IDR Write-only 0x00000000
0x18 Interrupt Mask Register IMR Read-only 0x00000000
0x1C Interrupt Status Register ISR Read-only 0x00000000
0x20 Interrupt Clear Register ICR Write-only 0x00000000
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8.6.1 Control Register
Name: CTRL
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00010000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - CLKEN
15 14 13 12 11 10 9 8
- - - - PSEL
7 6 5 4 3 2 1 0
- - - BUSY CLK32 WAKEN PCLR EN
• CLKEN: Clock Enable
1: The clock is enabled.
0: The clock is disabled.
• PSEL: Prescale Select
Selects prescaler bit PSEL as source clock for the RTC.
• BUSY: RTC Busy
This bit is set when the RTC is busy and will discard writes to TOP, VAL, and CTRL.
This bit is cleared when the RTC accepts writes to TOP, VAL, and CTRL.
• CLK32: 32 KHz Oscillator Select
1: The RTC uses the 32 KHz oscillator as clock source.
0: The RTC uses the RC oscillator as clock source.
• WAKEN: Wakeup Enable
1: The RTC wakes up the CPU from sleep modes.
0: The RTC does not wake up the CPU from sleep modes.
• PCLR: Prescaler Clear
Writing a one to this bit clears the prescaler.
Writing a zero to this bit has no effect.
This bit always reads as zero.
• EN: Enable
1: The RTC is enabled.
0: The RTC is disabled.
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8.6.2 Value Register
Name: VAL
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
VAL[31:24]
23 22 21 20 19 18 17 16
VAL[23:16]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]
• VAL[31:0]: RTC Value
This value is incremented on every rising edge of the source clock.
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8.6.3 Top Register
Name: TOP
Access Type: Read/Write
Offset: 0x08
Reset Value: 0xFFFFFFFF
31 30 29 28 27 26 25 24
VAL[31:24]
23 22 21 20 19 18 17 16
VAL[23:16]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]
• VAL[31:0]: RTC Top Value
VAL wraps at this value.
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8.6.4 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - TOPI
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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8.6.5 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - TOPI
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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8.6.6 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - TOPI
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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8.6.7 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - TOPI
• TOPI: Top Interrupt
This bit is set when VAL has wrapped at its top value.
This bit is cleared when the corresponding bit in ICR is written to one.
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8.6.8 Interrupt Clear Register
Name: ICR
Access Type: Write-only
Offset: 0x20
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - TOPI
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
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9. Watchdog Timer (WDT)
Rev: 2.4.0.1
9.1 Features
• Watchdog timer counter with 32-bit prescaler
• Clocked from the system RC oscillator (RCSYS)
9.2 Overview
The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is
clocked from the RC oscillator. The watchdog timer must be periodically reset by software within
the time-out period, otherwise, the device is reset and starts executing from the boot vector. This
allows the device to recover from a condition that has caused the system to be unstable.
9.3 Block Diagram
Figure 9-1. WDT Block Diagram
CLR
32-bit Watchdog
RCSYS Watchdog Reset
Prescaler Detector
EN CTRL
9.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
9.4.1 Power Management
When the WDT is enabled, the WDT remains clocked in all sleep modes, and it is not possible to
enter Static mode.
9.4.2 Clocks
The WDT can use the system RC oscillator (RCSYS) as clock source. This oscillator is always
enabled whenever these modules are active. Please refer to the Electrical Characteristics chap-
ter for the characteristic frequency of this oscillator (fRC).
9.4.3 Debug Operation
The WDT prescaler is frozen during debug operation, unless the On-Chip Debug (OCD) system
keeps peripherals running in debug operation.
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9.5 Functional Description
The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This
also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field
(PSEL) in the CTRL register selects the watchdog time-out period:
TWDT = 2(PSEL+1) / fRC
The next time-out period will begin as soon as the watchdog reset has occurred and count down
during the reset sequence. Care must be taken when selecting the PSEL field value so that the
time-out period is greater than the startup time of the chip, otherwise a watchdog reset can reset
the chip before any code has been run.
To avoid accidental disabling of the watchdog, the CTRL register must be written twice, first with
the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to do so will cause
the write operation to be ignored, and the CTRL register value will not change.
The Clear register (CLR) must be written with any value with regular intervals shorter than the
watchdog time-out period. Otherwise, the device will receive a soft reset, and the code will start
executing from the boot vector.
When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result
in entering Shutdown mode, leaving the WDT operational.
9.6 User Interface
Table 9-1. WDT Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CTRL Read/Write 0x00000000
0x04 Clear Register CLR Write-only 0x00000000
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9.6.1 Control Register
Name: CTRL
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - PSEL
7 6 5 4 3 2 1 0
- - - - - - - EN
• KEY: Write protection key
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective.
This field always reads as zero.
• PSEL: Prescale Select
PSEL is used as watchdog timeout period.
• EN: WDT Enable
1: WDT is enabled.
0: WDT is disabled.
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9.6.2 Clear Register
Name: CLR
Access Type: Write-only
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
CLR[31:24]
23 22 21 20 19 18 17 16
CLR[23:16]
15 14 13 12 11 10 9 8
CLR[15:8]
7 6 5 4 3 2 1 0
CLR[7:0]
• CLR:
Writing periodically any value to this field when the WDT is enabled, within the watchdog time-out period, will prevent a
watchdog reset.
This field always reads as zero.
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10. Interrupt Controller (INTC)
Rev: 1.0.1.5
10.1 Features
• Autovectored low latency interrupt service with programmable priority
– 4 priority levels for regular, maskable interrupts
– One Non-Maskable Interrupt
• Up to 64 groups of interrupts with up to 32 interrupt requests in each group
10.2 Overview
The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an inter-
rupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for
regular, maskable interrupts, and a Non-Maskable Interrupt (NMI).
The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request
lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register
(IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and
an autovector to each group, and the IRRs are used to identify the active interrupt request within
each group. If a group has only one interrupt request line, an active interrupt group uniquely
identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC
also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the
group that has a pending interrupt of the corresponding priority level. If several groups have a
pending interrupt of the same level, the group with the lowest number takes priority.
10.3 Block Diagram
Figure 10-1 gives an overview of the INTC. The grey boxes represent registers that can be
accessed via the user interface. The interrupt requests from the peripherals (IREQn) and the
NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of
the figure.
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Figure 10-1. INTC Block Diagram
Interrupt Controller CPU
NMIREQ
Masks SREG
Masks
I[3-0]M
GrpReqN ValReqN GM
OR
. IPRn INT_level,
offset
. . .
IRRn INTLEVEL
. Request . .
Prioritizer
IREQ63 .
Masking ValReq1 .
GrpReq1
IREQ34 OR
IREQ33 INT_level,
IREQ32 IPR1 AUTOVECTOR
offset
IRR1
IREQ31 ValReq0
GrpReq0
IREQ2 OR
IREQ1 INT_level,
IREQ0 IPR0 offset
IRR0
IRR Registers IPR Registers ICR Registers
10.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
10.4.1 Power Management
If the CPU enters a sleep mode that disables CLK_SYNC, the INTC will stop functioning and
resume operation after the system wakes up from sleep mode.
10.4.2 Clocks
The clock for the INTC bus interface (CLK_INTC) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager.
The INTC sampling logic runs on a clock which is stopped in any of the sleep modes where the
system RC oscillator is not running. This clock is referred to as CLK_SYNC. This clock is
enabled at reset, and only turned off in sleep modes where the system RC oscillator is stopped.
10.4.3 Debug Operation
When an external debugger forces the CPU into debug mode, the INTC continues normal
operation.
10.5 Functional Description
All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt
Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that
is active. If several IREQs within the same group are active, the interrupt service routine must
prioritize between them. All of the input lines in each group are logically ORed together to form
the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.
The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to
INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding
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Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the
CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not
masked by the CPU status register, gets its corresponding ValReq line asserted.
Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status
register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Inter-
rupt Mask (GM). An interrupt request is masked if either the GM or the corresponding interrupt
level mask bit is set.
The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the
pending interrupt of the highest priority. If an NMI interrupt request is pending, it automatically
gets the highest priority of any pending interrupt. If several interrupt groups of the highest pend-
ing interrupt level have pending interrupts, the interrupt group with the lowest number is
selected.
The INTLEVEL and handler autovector offset (AUTOVECTOR) of the selected interrupt are
transmitted to the CPU for interrupt handling and context switching. The CPU does not need to
know which interrupt is requesting handling, but only the level and the offset of the handler
address. The IRR registers contain the interrupt request lines of the groups and can be read via
user interface registers for checking which interrupts of the group are actually active.
The delay through the INTC from the peripheral interrupt request is set until the interrupt request
to the CPU is set is three cycles of CLK_SYNC.
10.5.1 Non-Maskable Interrupts
A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vec-
tor address defined by the AVR32 architecture, so AUTOVECTOR is undefined when
INTLEVEL indicates that an NMI is pending.
10.5.2 CPU Response
When the CPU receives an interrupt request it checks if any other exceptions are pending. If no
exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt
handling, the corresponding interrupt mask bit is set automatically for this and lower levels in sta-
tus register. E.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits I3M,
I2M, I1M, and I0M are set in status register. If an interrupt of level 1 is approved, the masking
bits I1M and I0M are set in status register. The handler address is calculated by logical OR of
the AUTOVECTOR to the CPU system register Exception Vector Base Address (EVBA). The
CPU will then jump to the calculated address and start executing the interrupt handler.
Setting the interrupt mask bits prevents the interrupts from the same and lower levels to be
passed through the interrupt controller. Setting of the same level mask bit prevents also multiple
requests of the same interrupt to happen.
It is the responsibility of the handler software to clear the interrupt request that caused the inter-
rupt before returning from the interrupt handler. If the conditions that caused the interrupt are not
cleared, the interrupt request remains active.
10.5.3 Clearing an Interrupt Request
Clearing of the interrupt request is done by writing to registers in the corresponding peripheral
module, which then clears the corresponding NMIREQ/IREQ signal.
The recommended way of clearing an interrupt request is a store operation to the controlling
peripheral register, followed by a dummy load operation from the same register. This causes a
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pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is
exited and the interrupt mask is cleared before the interrupt request is cleared.
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10.6 User Interface
Table 10-1. INTC Register Memory Map
Offset Register Register Name Access Reset
0x000 Interrupt Priority Register 0 IPR0 Read/Write 0x00000000
0x004 Interrupt Priority Register 1 IPR1 Read/Write 0x00000000
... ... ... ... ...
0x0FC Interrupt Priority Register 63 IPR63 Read/Write 0x00000000
0x100 Interrupt Request Register 0 IRR0 Read-only N/A
0x104 Interrupt Request Register 1 IRR1 Read-only N/A
... ... ... ... ...
0x1FC Interrupt Request Register 63 IRR63 Read-only N/A
0x200 Interrupt Cause Register 3 ICR3 Read-only N/A
0x204 Interrupt Cause Register 2 ICR2 Read-only N/A
0x208 Interrupt Cause Register 1 ICR1 Read-only N/A
0x20C Interrupt Cause Register 0 ICR0 Read-only N/A
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10.6.1 Interrupt Priority Registers
Name: IPR0...IPR63
Access Type: Read/Write
Offset: 0x000 - 0x0FC
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
INTLEVEL - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - AUTOVECTOR[13:8]
7 6 5 4 3 2 1 0
AUTOVECTOR[7:0]
• INTLEVEL: Interrupt Level
Indicates the EVBA-relative offset of the interrupt handler of the corresponding group:
00: INT0: Lowest priority
01: INT1
10: INT2
11: INT3: Highest priority
• AUTOVECTOR: Autovector Address
Handler offset is used to give the address of the interrupt handler. The least significant bit should be written to zero to give
halfword alignment.
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10.6.2 Interrupt Request Registers
Name: IRR0...IRR63
Access Type: Read-only
Offset: 0x0FF - 0x1FC
Reset Value: N/A
31 30 29 28 27 26 25 24
IRR[32*x+31] IRR[32*x+30] IRR[32*x+29] IRR[32*x+28] IRR[32*x+27] IRR[32*x+26] IRR[32*x+25] IRR[32*x+24]
23 22 21 20 19 18 17 16
IRR[32*x+23] IRR[32*x+22] IRR[32*x+21] IRR[32*x+20] IRR[32*x+19] IRR[32*x+18] IRR[32*x+17] IRR[32*x+16]
15 14 13 12 11 10 9 8
IRR[32*x+15] IRR[32*x+14] IRR[32*x+13] IRR[32*x+12] IRR[32*x+11] IRR[32*x+10] IRR[32*x+9] IRR[32*x+8]
7 6 5 4 3 2 1 0
IRR[32*x+7] IRR[32*x+6] IRR[32*x+5] IRR[32*x+4] IRR[32*x+3] IRR[32*x+2] IRR[32*x+1] IRR[32*x+0]
• IRR: Interrupt Request line
This bit is cleared when no interrupt request is pending on this input request line.
This bit is set when an interrupt request is pending on this input request line.
The are 64 IRRs, one for each group. Each IRR has 32 bits, one for each possible interrupt request, for a total of 2048 possible
input lines. The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The
IRRs are sampled continuously, and are read-only.
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10.6.3 Interrupt Cause Registers
Name: ICR0...ICR3
Access Type: Read-only
Offset: 0x200 - 0x20C
Reset Value: N/A
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - CAUSE
• CAUSE: Interrupt Group Causing Interrupt of Priority n
ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least
one interrupt of level n is pending.
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10.7 Interrupt Request Signal Map
The various modules may output Interrupt request signals. These signals are routed to the Inter-
rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64
groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt
signals in the same group share the same autovector address and priority level. Refer to the
documentation for the individual submodules for a description of the semantics of the different
interrupt requests.
The interrupt request signals are connected to the INTC as follows.
Table 10-2. Interrupt Request Signal Map
Group Line Module Signal
SYSREG
0 0 CPU with optional MPU and optional OCD
COMPARE
0 External Interrupt Controller EIC 0
1 External Interrupt Controller EIC 1
2 External Interrupt Controller EIC 2
3 External Interrupt Controller EIC 3
4 External Interrupt Controller EIC 4
1
5 External Interrupt Controller EIC 5
6 External Interrupt Controller EIC 6
7 External Interrupt Controller EIC 7
8 Real Time Counter RTC
9 Power Manager PM
0 General Purpose Input/Output Controller GPIO 0
1 General Purpose Input/Output Controller GPIO 1
2 General Purpose Input/Output Controller GPIO 2
3 General Purpose Input/Output Controller GPIO 3
4 General Purpose Input/Output Controller GPIO 4
5 General Purpose Input/Output Controller GPIO 5
6 General Purpose Input/Output Controller GPIO 6
2
7 General Purpose Input/Output Controller GPIO 7
8 General Purpose Input/Output Controller GPIO 8
9 General Purpose Input/Output Controller GPIO 9
10 General Purpose Input/Output Controller GPIO 10
11 General Purpose Input/Output Controller GPIO 11
12 General Purpose Input/Output Controller GPIO 12
13 General Purpose Input/Output Controller GPIO 13
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Table 10-2. Interrupt Request Signal Map
0 Peripheral DMA Controller PDCA 0
1 Peripheral DMA Controller PDCA 1
2 Peripheral DMA Controller PDCA 2
3 Peripheral DMA Controller PDCA 3
3
4 Peripheral DMA Controller PDCA 4
5 Peripheral DMA Controller PDCA 5
6 Peripheral DMA Controller PDCA 6
7 Peripheral DMA Controller PDCA 7
4 0 Flash Controller FLASHC
Universal Synchronous/Asynchronous
5 0 USART0
Receiver/Transmitter
Universal Synchronous/Asynchronous
6 0 USART1
Receiver/Transmitter
Universal Synchronous/Asynchronous
7 0 USART2
Receiver/Transmitter
Universal Synchronous/Asynchronous
8 0 USART3
Receiver/Transmitter
9 0 Serial Peripheral Interface SPI0
10 0 Serial Peripheral Interface SPI1
11 0 Two-wire Master Interface TWIM0
12 0 Two-wire Master Interface TWIM1
13 0 Synchronous Serial Controller SSC
0 Timer/Counter TC00
14 1 Timer/Counter TC01
2 Timer/Counter TC02
15 0 Analog to Digital Converter ADC
0 Timer/Counter TC10
16 1 Timer/Counter TC11
2 Timer/Counter TC12
17 0 USB 2.0 OTG Interface USBB
18 0 SDRAM Controller SDRAMC
19 0 Audio Bitstream DAC ABDAC
20 0 Mulitmedia Card Interface MCI
21 0 Advanced Encryption Standard AES
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Table 10-2. Interrupt Request Signal Map
0 DMA Controller DMACA BLOCK
1 DMA Controller DMACA DSTT
22 2 DMA Controller DMACA ERR
3 DMA Controller DMACA SRCT
4 DMA Controller DMACA TFR
26 0 Memory Stick Interface MSI
27 0 Two-wire Slave Interface TWIS0
28 0 Two-wire Slave Interface TWIS1
Error code corrector Hamming and Reed
29 0 ECCHRS
Solomon
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11. External Interrupt Controller (EIC)
Rev: 2.4.0.0
11.1 Features
• Dedicated interrupt request for each interrupt
• Individually maskable interrupts
• Interrupt on rising or falling edge
• Interrupt on high or low level
• Asynchronous interrupts for sleep modes without clock
• Filtering of interrupt lines
• Maskable NMI interrupt
• Keypad scan support
11.2 Overview
The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked. Each external
interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt
input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can
also be configured to be asynchronous in order to wake up the part from sleep modes where the
CLK_SYNC clock has been disabled.
A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other
external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any
other interrupt mode.
The EIC can wake up the part from sleep modes without triggering an interrupt. In this mode,
code execution starts from the instruction following the sleep instruction.
The External Interrupt Controller has support for keypad scanning for keypads laid out in rows
and columns. Columns are driven by a separate set of scanning outputs, while rows are sensed
by the external interrupt lines. The pressed key will trigger an interrupt, which can be identified
through the user registers of the module.
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11.3 Block Diagram
Figure 11-1. EIC Block Diagram
LEVEL
MODE ASYNC
EDGE
EN P o la r it y A s y n c h ro n u s IC R IE R
D IS c o n tro l d e te c to r CTRL ID R
E n a b le LEVEL IN T n M ask IR Q n
F IL T E R MODE
EDGE
E X T IN T n
NMI IS R IM R
CTRL E d g e /L e v e l
F ilt e r
D e te c to r
W ake
E IC _ W A K E
CLK_SYN C d e te c t
CLK_RC SYS
P r e s c a le r S h if t e r SCANm
PRESC EN P IN
SCAN
11.4 I/O Lines Description
Table 11-1. I/O Lines Description
Pin Name Pin Description Type
NMI Non-Maskable Interrupt Input
EXTINTn External Interrupt Input
SCANm Keypad scan pin m Output
11.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
11.5.1 I/O Lines
The external interrupt pins (EXTINTn and NMI) are multiplexed with I/O lines. To generate an
external interrupt from an external source the source pin must be configured as an input pins by
the I/O Controller. It is also possible to trigger the interrupt by driving these pins from registers in
the I/O Controller, or another peripheral output connected to the same pin.
11.5.2 Power Management
All interrupts are available in all sleep modes as long as the EIC module is powered. However, in
sleep modes where CLK_SYNC is stopped, the interrupt must be configured to asynchronous
mode.
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11.5.3 Clocks
The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager.
The filter and synchronous edge/level detector runs on a clock which is stopped in any of the
sleep modes where the system RC oscillator is not running. This clock is referred to as
CLK_SYNC. Refer to the Module Configuration section at the end of this chapter for details.
The Keypad scan function operates on the system RC oscillator clock CLK_RCSYS.
11.5.4 Interrupts
The external interrupt request lines are connected to the interrupt controller. Using the external
interrupts requires the interrupt controller to be programmed first.
Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed.
11.5.5 Debug Operation
The EIC is frozen during debug operation, unless the OCD system keeps peripherals running
during debug operation.
11.6 Functional Description
11.6.1 External Interrupts
The external interrupts are not enabled by default, allowing the proper interrupt vectors to be set
up by the CPU before the interrupts are enabled.
Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge,
or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL regis-
ters. Each interrupt n has a bit INTn in each of these registers. Writing a zero to the INTn bit in
the MODE register enables edge triggered interrupts, while writing a one to the bit enables level
triggered interrupts.
If INTn is configured as an edge triggered interrupt, writing a zero to the INTn bit in the EDGE
register will cause the interrupt to be triggered on a falling edge on EXTINTn, while writing a one
to the bit will cause the interrupt to be triggered on a rising edge on EXTINTn.
If INTn is configured as a level triggered interrupt, writing a zero to the INTn bit in the LEVEL
register will cause the interrupt to be triggered on a low level on EXTINTn, while writing a one to
the bit will cause the interrupt to be triggered on a high level on EXTINTn.
Each interrupt has a corresponding bit in each of the interrupt control and status registers. Writ-
ing a one to the INTn bit in the Interrupt Enable Register (IER) enables the external interrupt
from pin EXTINTn to propagate from the EIC to the interrupt controller, while writing a one to
INTn bit in the Interrupt Disable Register (IDR) disables this propagation. The Interrupt Mask
Register (IMR) can be read to check which interrupts are enabled. When an interrupt triggers,
the corresponding bit in the Interrupt Status Register (ISR) will be set. This bit remains set until a
one is written to the corresponding bit in the Interrupt Clear Register (ICR) or the interrupt is
disabled.
Writing a one to the INTn bit in the Enable Register (EN) enables the external interrupt on pin
EXTINTn, while writing a one to INTn bit in the Disable Register (DIS) disables the external inter-
rupt. The Control Register (CTRL) can be read to check which interrupts are enabled. If a bit in
the CTRL register is set, but the corresponding bit in IMR is not set, an interrupt will not propa-
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gate to the interrupt controller. However, the corresponding bit in ISR will be set, and
EIC_WAKE will be set.
If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an
external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR.
11.6.2 Synchronization and Filtering of External Interrupts
In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so
spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The syn-
chronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the
interrupt controller by two cycles of CLK_SYNC, see Figure 11-2 on page 110 and Figure 11-3
on page 110 for examples (FILTER off).
It is also possible to apply a filter on EXTINTn by writing a one to INTn bit in the FILTER register.
This filter is a majority voter, if the condition for an interrupt is true for more than one of the latest
three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propagation of
the interrupt to the interrupt controller by one or two cycles of CLK_SYNC, see Figure 11-2 on
page 110 and Figure 11-3 on page 110 for examples (FILTER on).
Figure 11-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge
CLK_SYNC
EXTINTn/NMI
ISR.INTn:
FILTER off
ISR.INTn:
FILTER on
Figure 11-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge
CLK_SYNC
EXTINTn/NMI
ISR.INTn:
FILTER off
ISR.INTn:
FILTER on
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11.6.3 Non-Maskable Interrupt
The NMI supports the same features as the external interrupts, and is accessed through the
same registers. The description in Section 11.6.1 should be followed, accessing the NMI bit
instead of the INTn bits.
The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution
mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled
by accessing the registers in the EIC.
11.6.4 Asynchronous Interrupts
Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC reg-
ister. This will route the interrupt signal through the asynchronous path of the module. All edge
interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is config-
ured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted
as low level, and a one in EDGE.INTn will be interpreted as high level.
EIC_WAKE will be set immediately after the source triggers the interrupt, while the correspond-
ing bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of
CLK_SYNC. Please refere to Figure 11-4 on page 111 for details.
When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike
on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be
updated on the first rising edge of CLK_SYNC.
Figure 11-4. Timing Diagram, Asynchronous Interrupts
CLK_SYNC CLK_SYNC
EXTINTn/NMI EXTINTn/NMI
ISR.INTn: ISR.INTn:
rising EDGE or high rising EDGE or high
LEVEL LEVEL
EIC_WAKE: EIC_WAKE:
rising EDGE or high rising EDGE or high
LEVEL LEVEL
11.6.5 Wakeup
The external interrupts can be used to wake up the part from sleep modes. The wakeup can be
interpreted in two ways. If the corresponding bit in IMR is one, then the execution starts at the
interrupt handler for this interrupt. If the bit in IMR is zero, then the execution starts from the next
instruction after the sleep instruction.
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11.6.6 Keypad scan support
The External Interrupt Controller also includes support for keypad scanning. The keypad scan
feature is compatible with keypads organized as rows and columns, where a row is shorted
against a column when a key is pressed.
The rows should be connected to the external interrupt pins with pull-ups enabled in the I/O Con-
troller. These external interrupts should be enabled as low level or falling edge interrupts. The
columns should be connected to the available scan pins. The I/O Controller must be configured
to let the required scan pins be controlled by the EIC. Unused external interrupt or scan pins can
be left controlled by the I/O Controller or other peripherals.
The Keypad Scan function is enabled by writing SCAN.EN to 1, which starts the keypad scan
counter. The SCAN outputs are tri-stated, except SCAN[0], which is driven to zero. After
2(SCAN.PRESC+1) RC clock cycles this pattern is left shifted, so that SCAN[1] is driven to zero while
the other outputs are tri-stated. This sequence repeats infinitely, wrapping from the most signifi-
cant SCAN pin to SCAN[0].
When a key is pressed, the pulled-up row is driven to zero by the column, and an external inter-
rupt triggers. The scanning stops, and the software can then identify the key pressed by the
interrupt status register and the SCAN.PINS value.
The scanning stops whenever there is an active interrupt request from the EIC to the CPU.
When the CPU clears the interrupt flags, scanning resumes.
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11.7 User Interface
Table 11-2. EIC Register Memory Map
Offset Register Register Name Access Reset
0x000 Interrupt Enable Register IER Write-only 0x00000000
0x004 Interrupt Disable Register IDR Write-only 0x00000000
0x008 Interrupt Mask Register IMR Read-only 0x00000000
0x00C Interrupt Status Register ISR Read-only 0x00000000
0x010 Interrupt Clear Register ICR Write-only 0x00000000
0x014 Mode Register MODE Read/Write 0x00000000
0x018 Edge Register EDGE Read/Write 0x00000000
0x01C Level Register LEVEL Read/Write 0x00000000
0x020 Filter Register FILTER Read/Write 0x00000000
0x024 Test Register TEST Read/Write 0x00000000
0x028 Asynchronous Register ASYNC Read/Write 0x00000000
0x2C Scan Register SCAN Read/Write 0x00000000
0x030 Enable Register EN Write-only 0x00000000
0x034 Disable Register DIS Write-only 0x00000000
0x038 Control Register CTRL Read-only 0x00000000
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11.7.1 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x000
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will set the corresponding bit in IMR.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will set the corresponding bit in IMR.
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11.7.2 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x004
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in IMR.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in IMR.
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11.7.3 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x008
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is written to one.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is disabled.
1: The Non-Maskable Interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is written to one.
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11.7.4 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x00C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
0: An interrupt event has not occurred
1: An interrupt event has occurred
This bit is cleared by writing a one to the corresponding bit in ICR.
• NMI: Non-Maskable Interrupt
0: An interrupt event has not occurred
1: An interrupt event has occurred
This bit is cleared by writing a one to the corresponding bit in ICR.
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11.7.5 Interrupt Clear Register
Name: ICR
Access Type: Write-only
Offset: 0x010
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in ISR.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in ISR.
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11.7.6 Mode Register
Name: MODE
Access Type: Read/Write
Offset: 0x014
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
0: The external interrupt is edge triggered.
1: The external interrupt is level triggered.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is edge triggered.
1: The Non-Maskable Interrupt is level triggered.
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11.7.7 Edge Register
Name: EDGE
Access Type: Read/Write
Offset: 0x018
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
0: The external interrupt triggers on falling edge.
1: The external interrupt triggers on rising edge.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt triggers on falling edge.
1: The Non-Maskable Interrupt triggers on rising edge.
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11.7.8 Level Register
Name: LEVEL
Access Type: Read/Write
Offset: 0x01C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
0: The external interrupt triggers on low level.
1: The external interrupt triggers on high level.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt triggers on low level.
1: The Non-Maskable Interrupt triggers on high level.
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11.7.9 Filter Register
Name: FILTER
Access Type: Read/Write
Offset: 0x020
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
0: The external interrupt is not filtered.
1: The external interrupt is filtered.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is not filtered.
1: The Non-Maskable Interrupt is filtered.
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11.7.10 Test Register
Name: TEST
Access Type: Read/Write
Offset: 0x024
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• TESTEN: Test Enable
0: This bit disables external interrupt test mode.
1: This bit enables external interrupt test mode.
• INTn: External Interrupt n
If TESTEN is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored.
• NMI: Non-Maskable Interrupt
If TESTEN is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored.
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11.7.11 Asynchronous Register
Name: ASYNC
Access Type: Read/Write
Offset: 0x028
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
0: The external interrupt is synchronized to CLK_SYNC.
1: The external interrupt is asynchronous.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is synchronized to CLK_SYNC
1: The Non-Maskable Interrupt is asynchronous.
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11.7.12 Scan Register
Name: SCAN
Access Type: Read/Write
Offset: 0x2C
Reset Value: 0x0000000
31 30 29 28 27 26 25 24
- - - - - PIN[2:0]
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - PRESC[4:0]
7 6 5 4 3 2 1 0
- - - - - - - EN
• EN
0: Keypad scanning is disabled
1: Keypad scanning is enabled
• PRESC
Prescale select for the keypad scan rate:
Scan rate = 2(SCAN.PRESC+1) TRC
The RC clock period can be found in the Electrical Characteristics section.
• PIN
The index of the currently active scan pin. Writing to this bitfield has no effect.
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11.7.13 Enable Register
Name: EN
Access Type: Write-only
Offset: 0x030
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the corresponding external interrupt.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Non-Maskable Interrupt.
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11.7.14 Disable Register
Name: DIS
Access Type: Write-only
Offset: 0x034
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will disable the corresponding external interrupt.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will disable the Non-Maskable Interrupt.
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11.7.15 Control Register
Name: CTRL
Access Type: Read-only
Offset: 0x038
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - NMI
7 6 5 4 3 2 1 0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
• INTn: External Interrupt n
0: The corresponding external interrupt is disabled.
1: The corresponding external interrupt is enabled.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is disabled.
1: The Non-Maskable Interrupt is enabled.
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11.8 Module Configuration
The specific configuration for each EIC instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
chapter for details.
Table 11-3. Module Configuration
Feature EIC
Number of external interrupts, including NMI 9
Table 11-4. Module Clock Name
Module Name Clock Name
EIC CLK_EIC
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12. Flash Controller (FLASHC)
Rev: 2.2.1.3
12.1 Features
• Controls flash block with dual read ports allowing staggered reads.
• Supports 0 and 1 wait state bus access.
• Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle.
• 32-bit HSB interface for reads from flash array and writes to page buffer.
• 32-bit PB interface for issuing commands to and configuration of the controller.
• 16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16)
pages.
• Regions can be individually protected or unprotected.
• Additional protection of the Boot Loader pages.
• Supports reads and writes of general-purpose NVM bits.
• Supports reads and writes of additional NVM pages.
• Supports device protection through a security bit.
• Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
• Interface to Power Manager for power-down of flash-blocks in sleep mode.
•
12.2 Overview
The flash controller (None) interfaces a flash block with the 32-bit internal HSB bus. Perfor-
mance for uncached systems with high clock-frequency and one wait state is increased by
placing words with sequential addresses in alternating flash subblocks. Having one read inter-
face per subblock allows them to be read in parallel. While data from one flash subblock is being
output on the bus, the sequential address is being read from the other flash subblock and will be
ready in the next clock cycle.
The controller also manages the programming, erasing, locking and unlocking sequences with
dedicated commands.
12.3 Product dependencies
12.3.1 Power Manager
The FLASHC has two bus clocks connected: One High speed bus clock (CLK_FLASHC_HSB)
and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are generated by the Power
manager. Bot h clocks are turned on by default, but the user has t o ensure that
CLK_FLASHC_HSB is not turned off before reading the flash or writing the pagebuffer and that
CLK_FLASHC_PB is not turned of before accessing the FLASHC configuration and control
registers.
12.3.2 Interrupt Controller
The FLASHC interrupt lines are connected to internal sources of the interrupt controller. Using
FLASHC interrutps requires the interrupt controller to be programmed first.
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12.4 Functional description
12.4.1 Bus interfaces
The None has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the flash
array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands
and control to and reading status from the controller.
12.4.2 Memory organization
To maximize performance for high clock-frequency systems, None interfaces to a flash block
with two read ports. The flash block has several parameters, given by the design of the flash
block. Refer to the “Memories” chapter for the device-specific values of the parameters.
• p pages (FLASH_P)
• w words in each page and in the page buffer (FLASH_W)
• pw words in total (FLASH_PW)
• f general-purpose fuse bits (FLASH_F)
• 1 security fuse bit
• 1 User Page
12.4.3 User page
The User page is an additional page, outside the regular flash array, that can be used to store
various data, like calibration data and serial numbers. This page is not erased by regular chip
erase. The User page can only be written and erased by proprietary commands. Read accesses
to the User page is performed just as any other read access to the flash. The address map of the
User page is given in Figure 12-1.
12.4.4 Read operations
The None provides two different read modes:
• 0 wait state (0ws) for clock frequencies < (access time of the flash plus the bus delay)
• 1 wait state (1ws) for clock frequencies < (access time of the flash plus the bus delay)/2
Higher clock frequencies that would require more wait states are not supported by the flash
controller.
The programmer can select the wait states required by writing to the FWS field in the Flash Con-
trol Register (FCR). It is the responsibility of the programmer to select a number of wait states
compatible with the clock frequency and timing characteristics of the flash block.
In 0ws mode, only one of the two flash read ports is accessed. The other flash read port is idle.
In 1ws mode, both flash read ports are active. One read port reading the addressed word, and
the other reading the next sequential word.
If the clock frequency allows, the user should use 0ws mode, because this gives the lowest
power consumption for low-frequency systems as only one flash read port is read. Using 1ws
mode has a power/performance ratio approaching 0ws mode as the clock frequency
approaches twice the max frequency of 0ws mode. Using two flash read ports use twice the
power, but also give twice the performance.
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The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in Figure
12-1. Reading the memory space between address pw and 2^21-1 returns an undefined result.
The User page is permanently mapped to word address 2^21.
Table 12-1. User page addresses
Memory type Start address, byte sized Size
Main array 0 pw words = 4pw bytes
User 2^23 = 8388608 128 words = 512 bytes
Figure 12-1. Memory map for the Flash memories
A ll a d d r e s s e s a r e w o r d a d d r e s s e s
2^21+128 U nused
2^21 U ser page
Unused
pw
p w -1
Flash data array
0
F la s h w it h
e x tra p a g e
Figure 12-2.
12.4.5 High Speed Read Mode
The flash provides a High Speed Read Mode, offering slightly higher flash read speed at the
cost of higher power consumption. Two dedicated commands, High Speed Read Mode Enable
(HSEN) and High Speed Read Mode Disable (HSDIS) control the speed mode. When a High
Speed Read Mode command is detected, the FLASHC automatically inserts additional wait
states until it is ready for the next read in flash. After reset, the High Speed Mode is disabled,
and must be manually enabled if the user wants to.
Refer to the Electrical Characteristics chapter at the end of this datasheet for details on the max-
imum clock frequencies in Normal and High Speed Read Mode.
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Figure 12-3. High Speed Mode
Frequency
1 wait state
0 wait state
Frequency limit
for 0 wait state
operation
N Speed mode
H
or
ig
m
h
al
12.4.6 Quick Page Read
A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed
page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result is
placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR). The QPR
command is useful to check that a page is in an erased state. The QPR instruction is much
faster than performing the erased-page check using a regular software subroutine.
12.4.7 Write page buffer operations
The internal memory area reserved for the embedded flash can also be written through a write-
only page buffer. The page buffer is addressed only by the address bits required to address w
words (since the page buffer is word addressable) and thus wrap around within the internal
memory area address space and appear to be repeated within it.
When writing to the page buffer, the PAGEN field in the FCMD register is updated with the page
number corresponding to page address of the latest word written into the page buffer.
The page buffer is also used for writes to the User page.
Write operations can be prevented by programming the Memory Protection Unit of the CPU.
Writing 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data
corruption.
Page buffer write operations are performed with 2.2.0 wait states.
Writing to the page buffer can only change page buffer bits from one to zero, ie writing
0xaaaaaaaa to a page buffer location that has the value 0x00000000, will not change the page
buffer value. The only way to change a bit from zero to one, is to reset the entire page buffer with
the Clear Page Buffer command.
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The page buffer is not automatically reset after a page write. The programmer should do this
manually by issuing the Clear Page Buffer flash command. This can be done after a page write,
or before the page buffer is loaded with data to be stored to the flash page.
Example: Writing a word into word address 130 of a flash with 128 words in the page buffer.
PAGEN will be updated with the value 1, and the word will be written into word 2 in the page
buffer.
12.4.8 Writing words to a page that is not completely erased
This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an
entire page. Only words that are in an completely erased state (0xFFFFFFFF) can be changed.
The procedure is as follows:
1. Clear page buffer
2. Write to the page buffer the result of the logical bitwise AND operation between the
contents of the flash page and the new data to write. Only words that were in an erased
state can be changed from the original page.
3. Write Page.
12.5 Flash commands
The None offers a command set to manage programming of the flash memory, locking and
unlocking of regions, and full flash erasing. See chapter 12.8.3 for a complete list of commands.
To run a command, the field CMD of the Flash Command Register (FCMD) has to be written
with the command number. As soon as the FCMD register is written, the FRDY flag is automati-
cally cleared. Once the current command is complete, the FRDY flag is automatically set. If an
interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash control-
ler is activated. All flash commands except for Quick Page Read (QPR) will generate an interrupt
request upon completion if FRDY is set.
After a command has been written to FCMD, the programming algorithm should wait until the
command has been executed before attempting to read instructions or data from the flash or
writing to the page buffer, as the flash will be busy. The waiting can be performed either by poll-
ing the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The command
written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHC is
IDLE. The user must make sure that the access pattern to the FLASHC HSB interface contains
an IDLE cycle so that the command is allowed to start. Make sure that no bus masters such as
DMA controllers are performing endless burst transfers from the flash. Also, make sure that the
CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter
sleep mode after writing to FCMD, or by polling FSR for command completion. This polling will
result in an access pattern with IDLE HSB cycles.
All the commands are protected by the same keyword, which has to be written in the eight high-
est bits of the FCMD register. Writing FCMD with data that does not contain the correct key
and/or with an invalid command has no effect on the flash memory; however, the PROGE flag is
set in the Flash Status Register (FSR). This flag is automatically cleared by a read access to the
FSR register.
Writing a command to FCMD while another command is being executed has no effect on the
flash memory; however, the PROGE flag is set in the Flash Status Register (FSR). This flag is
automatically cleared by a read access to the FSR register.
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If the current command writes or erases a page in a locked region, or a page protected by the
BOOTPROT fuses, the command has no effect on the flash memory; however, the LOCKE flag
is set in the FSR register. This flag is automatically cleared by a read access to the FSR register.
12.5.1 Write/erase page operation
Flash technology requires that an erase must be done before programming. The entire flash can
be erased by an Erase All command. Alternatively, pages can be individually erased by the
Erase Page command.
The User page can be written and erased using the mechanisms described in this chapter.
After programming, the page can be locked to prevent miscellaneous write or erase sequences.
Locking is performed on a per-region basis, so locking a region locks all pages inside the region.
Additional protection is provided for the lowermost address space of the flash. This address
space is allocated for the Boot Loader, and is protected both by the lock bit(s) corresponding to
this address space, and the BOOTPROT[2:0] fuses.
Data to be written are stored in an internal buffer called page buffer. The page buffer contains w
words. The page buffer wraps around within the internal memory area address space and
appears to be repeated by the number of pages in it. Writing of 8-bit and 16-bit data to the page
buffer is not allowed and may lead to unpredictable data corruption.
Data must be written to the page buffer before the programming command is written to the Flash
Command Register FCMD. The sequence is as follows:
• Reset the page buffer with the Clear Page Buffer command.
• Fill the page buffer with the desired contents, using only 32-bit access.
• Programming starts as soon as the programming key and the programming command are
written to the Flash Command Register. The PAGEN field in the Flash Command Register
(FCMD) must contain the address of the page to write. PAGEN is automatically updated
when writing to the page buffer, but can also be written to directly. The FRDY bit in the Flash
Status Register (FSR) is automatically cleared when the page write operation starts.
• When programming is completed, the bit FRDY in the Flash Status Register (FSR) is set. If
an interrupt was enabled by setting the bit FRDY in FCR, the interrupt line of the flash
controller is set.
Two errors can be detected in the FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
• Lock Error: The page to be programmed belongs to a locked region. A command must be
executed to unlock the corresponding region before programming can start.
12.5.2 Erase All operation
The entire memory is erased if the Erase All command (EA) is written to the Flash Command
Register (FCMD). Erase All erases all bits in the flash array. The User page is not erased. All
flash memory locations, the general-purpose fuse bits, and the security bit are erased (reset to
0xFF) after an Erase All.
The EA command also ensures that all volatile memories, such as register file and RAMs, are
erased before the security bit is erased.
Erase All operation is allowed only if no regions are locked, and the BOOTPROT fuses are pro-
grammed with a region size of 0. Thus, if at least one region is locked, the bit LOCKE in FSR is
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set and the command is cancelled. If the bit LOCKE has been written to 1 in FCR, the interrupt
line rises.
When the command is complete, the bit FRDY bit in the Flash Status Register (FSR) is set. If an
interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash control-
ler is set. Two errors can be detected in the FSR register after issuing the command:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
• Lock Error: At least one lock region to be erased is protected, or BOOTPROT is different from
0. The erase command has been refused and no page has been erased. A Clear Lock Bit
command must be executed previously to unlock the corresponding lock regions.
12.5.3 Region lock bits
The flash block has p pages, and these pages are grouped into 16 lock regions, each region
containing p/16 pages. Each region has a dedicated lock bit preventing writing and erasing
pages in the region. After production, the device may have some regions locked. These locked
regions are reserved for a boot or default application. Locked regions can be unlocked to be
erased and then programmed with another application or other data.
To lock or unlock a region, the commands Lock Region Containing Page (LP) and Unlock
Region Containing Page (UP) are provided. Writing one of these commands, together with the
number of the page whose region should be locked/unlocked, performs the desired operation.
One error can be detected in the FSR register after issuing the command:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that
lock bits can also be set/cleared using the commands for writing/erasing general-purpose fuse
bits, see chapter 12.6. The general-purpose bit being in an erased (1) state means that the
region is unlocked.
The lowermost pages in the Flash can additionally be protected by the BOOTPROT fuses, see
Section 12.6.
12.6 General-purpose fuse bits
Each flash block has a number of general-purpose fuse bits that the application programmer can
use freely. The fuse bits can be written and erased using dedicated commands, and read
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through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are
reserved for special purposes, and should not be used for other functions.:
Table 12-2. General-purpose fuses with special functions
General-
Purpose fuse
number Name Usage
15:0 LOCK Region lock bits.
External Privileged Fetch Lock. Used to prevent the CPU from
fetching instructions from external memories when in privileged
mode. This bit can only be changed when the security bit is
cleared. The address range corresponding to external
memories is device-specific, and not known to the flash
controller. This fuse bit is simply routed out of the CPU or bus
system, the flash controller does not treat this fuse in any
special way, except that it can not be altered when the security
16 EPFL bit is set.
If the security bit is set, only an external JTAG Chip Erase can
clear EPFL. No internal commands can alter EPFL if the
security bit is set.
When the fuse is erased (i.e. "1"), the CPU can execute
instructions fetched from external memories. When the fuse is
programmed (i.e. "0"), instructions can not be executed from
external memories.
Used to select one of eight different bootloader sizes. Pages
included in the bootloader area can not be erased or
programmed except by a JTAG chip erase. BOOTPROT can
only be changed when the security bit is cleared.
19:17 BOOTPROT If the security bit is set, only an external JTAG Chip Erase can
clear BOOTPROT, and thereby allow the pages protected by
BOOTPROT to be programmed. No internal commands can
alter BOOTPROT or the pages protected by BOOTPROT if the
security bit is set.
The BOOTPROT fuses protects the following address space for the Boot Loader:
Table 12-3. Boot Loader area specified by BOOTPROT
Pages protected by Size of protected
BOOTPROT BOOTPROT memory
7 None 0
6 0-1 1kByte
5 0-3 2kByte
4 0-7 4kByte
3 0-15 8kByte
2 0-31 16kByte
1 0-63 32kByte
0 0-127 64kByte
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To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit
(WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these com-
mands, together with the number of the fuse to write/erase, performs the desired operation.
An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse
Byte (PGPFB) instruction. A PGPFB to GP fuse byte 2 is not allowed if the flash is locked by the
security bit. The PFB command is issued with a parameter in the PAGEN field:
• PAGEN[2:0] - byte to write
• PAGEN[10:3] - Fuse value to write
All General-Purpose fuses can be erased by the Erase All General-Purpose fuses (EAGP) com-
mand. An EAGP command is not allowed if the flash is locked by the security bit.
Two errors can be detected in the FSR register after issuing these commands:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
• Lock Error: A write or erase of any of the special-function fuse bits in Table 12-3 was
attempted while the flash is locked by the security bit.
The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that
the 16 lowest general-purpose fuse bits can also be written/erased using the commands for
locking/unlocking regions, see Section 12.5.3.
12.7 Security bit
The security bit allows the entire chip to be locked from external JTAG or other debug access for
code security. The security bit can be written by a dedicated command, Set Security Bit (SSB).
Once set, the only way to clear the security bit is through the JTAG Chip Erase command.
Once the Security bit is set, the following Flash controller commands will be unavailable and
return a lock error if attempted:
• Write General-Purpose Fuse Bit (WGPB) to BOOTPROT or EPFL fuses
• Erase General-Purpose Fuse Bit (EGPB) to BOOTPROT or EPFL fuses
• Program General-Purpose Fuse Byte (PGPFB) of fuse byte 2
• Erase All General-Purpose Fuses (EAGPF)
One error can be detected in the FSR register after issuing the command:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
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12.8 User interface
12.8.1 Address map
The following addresses are used by the None. All offsets are relative to the base address allo-
cated to the flash controller.
Table 12-4. Flash controller register mapping
Reset
Offset Register Name Access state
0x0 Flash Control Register FCR R/W 0
0x4 Flash Command Register FCMD R/W 0
0x8 Flash Status Register FSR R/W 0 (*)
0xc Flash General Purpose Fuse Register Hi FGPFRHI R NA (*)
0x10 Flash General Purpose Fuse Register Lo FGPFRLO R NA (*)
(*) The value of the Lock bits is dependent of their programmed state. All other bits in FSR are 0.
All bits in FGPFR and FCFR are dependent on the programmed state of the fuses they map to.
Any bits in these registers not mapped to a fuse read 0.
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12.8.2 Flash Control Register
Name: FCR
Access Type: Read/Write
Offset: 0x00
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- FWS - - PROGE LOCKE - FRDY
• FRDY: Flash Ready Interrupt Enable
0: Flash Ready does not generate an interrupt.
1: Flash Ready generates an interrupt.
• LOCKE: Lock Error Interrupt Enable
0: Lock Error does not generate an interrupt.
1: Lock Error generates an interrupt.
• PROGE: Programming Error Interrupt Enable
0: Programming Error does not generate an interrupt.
1: Programming Error generates an interrupt.
• FWS: Flash Wait State
0: The flash is read with 0 wait states.
1: The flash is read with 1 wait state.
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12.8.3 Flash Command Register
Name: FCMD
Access Type: Read/Write
Offset: 0x04
Reset value: 0x00000000
The FCMD can not be written if the flash is in the process of performing a flash command. Doing
so will cause the FCR write to be ignored, and the PROGE bit to be set.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
PAGEN [15:8]
15 14 13 12 11 10 9 8
PAGEN [7:0]
7 6 5 4 3 2 1 0
- - CMD
• CMD: Command
This field defines the flash command. Issuing any unused command will cause the Programming Error flag to be set, and the
corresponding interrupt to be requested if the PROGE bit in FCR is set.
Table 12-5. Set of commands
Command Value Mnemonic
No operation 0 NOP
Write Page 1 WP
Erase Page 2 EP
Clear Page Buffer 3 CPB
Lock region containing given Page 4 LP
Unlock region containing given Page 5 UP
Erase All 6 EA
Write General-Purpose Fuse Bit 7 WGPB
Erase General-Purpose Fuse Bit 8 EGPB
Set Security Bit 9 SSB
Program GP Fuse Byte 10 PGPFB
Erase All GPFuses 11 EAGPF
Quick Page Read 12 QPR
Write User Page 13 WUP
Erase User Page 14 EUP
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Table 12-5. Set of commands
Command Value Mnemonic
Quick Page Read User Page 15 QPRUP
Read High Speed Enable 16 HSEN
Read High Speed Disable 17 HSDIS
• PAGEN: Page number
The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify programming, the PAGEN field
is automatically updated every time the page buffer is written to. For every page buffer write, the PAGEN field is updated with the
page number of the address being written to. Hardware automatically masks writes to the PAGEN field so that only bits
representing valid page numbers can be written, all other bits in PAGEN are always 0. As an example, in a flash with 1024
pages (page 0 - page 1023), bits 15:10 will always be 0.
Table 12-6. Semantic of PAGEN field in different commands
Command PAGEN description
No operation Not used
Write Page The number of the page to write
Clear Page Buffer Not used
Lock region containing given Page Page number whose region should be locked
Unlock region containing given Page Page number whose region should be unlocked
Erase All Not used
Write General-Purpose Fuse Bit GPFUSE #
Erase General-Purpose Fuse Bit GPFUSE #
Set Security Bit Not used
Program GP Fuse Byte WriteData[7:0], ByteAddress[2:0]
Erase All GP Fuses Not used
Quick Page Read Page number
Write User Page Not used
Erase User Page Not used
Quick Page Read User Page Not used
• KEY: Write protection key
This field should be written with the value 0xA5 to enable the command defined by the bits of the register. If the field is written
with a different value, the write is not performed and no action is started.
This field always reads as 0.
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12.8.4 Flash Status Register
Name: FSR
Access Type: Read/Write
Offset: 0x08
Reset value: 0x00000000
31 30 29 28 27 26 25 24
LOCK15 LOCK14 LOCK13 LOCK12 LOCK11 LOCK10 LOCK9 LOCK8
23 22 21 20 19 18 17 16
LOCK7 LOCK6 LOCK5 LOCK4 LOCK3 LOCK2 LOCK1 LOCK0
15 14 13 12 11 10 9 8
FSZ - - - -
7 6 5 4 3 2 1 0
- QPRR SECURITY PROGE LOCKE - FRDY
• FRDY: Flash Ready Status
0: The flash controller is busy and the application must wait before running a new command.
1: The flash controller is ready to run a new command.
• LOCKE: Lock Error Status
Automatically cleared when FSR is read.
0: No programming of at least one locked lock region has happened since the last read of FSR.
1: Programming of at least one locked lock region has happened since the last read of FSR.
• PROGE: Programming Error Status
Automatically cleared when FSR is read.
0: No invalid commands and no bad keywords were written in the Flash Command Register FCMD.
1: An invalid command and/or a bad keyword was/were written in the Flash Command Register FCMD.
• SECURITY: Security Bit Status
0: The security bit is inactive.
1: The security bit is active.
• QPRR: Quick Page Read Result
0: The result is zero, i.e. the page is not erased.
1: The result is one, i.e. the page is erased.
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• FSZ: Flash Size
The size of the flash. Not all device families will provide all flash sizes indicated in the table.
Table 12-7. Flash size
FSZ Flash Size
0 32 KByte
1 64 kByte
2 128 kByte
3 256 kByte
4 384 kByte
5 512 kByte
6 768 kByte
7 1024 kByte
• LOCKx: Lock Region x Lock Status
0: The corresponding lock region is not locked.
1: The corresponding lock region is locked.
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12.8.5 Flash General Purpose Fuse Register High
Name: FGPFRHI
Access Type: Read
Offset: 0x0C
Reset value: N/A
31 30 29 28 27 26 25 24
GPF63 GPF62 GPF61 GPF60 GPF59 GPF58 GPF57 GPF56
23 22 21 20 19 18 17 16
GPF55 GPF54 GPF53 GPF52 GPF51 GPF50 GPF49 GPF48
15 14 13 12 11 10 9 8
GPF47 GPF46 GPF45 GPF44 GPF43 GPF42 GPF41 GPF40
7 6 5 4 3 2 1 0
GPF39 GPF38 GPF37 GPF36 GPF35 GPF34 GPF33 GPF32
This register is only used in systems with more than 32 GP fuses.
• GPFxx: General Purpose Fuse xx
0: The fuse has a written/programmed state.
1: The fuse has an erased state.
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12.8.6 Flash General Purpose Fuse Register Low
Name: FGPFRLO
Access Type: Read
Offset: 0x10
Reset value: N/A
31 30 29 28 27 26 25 24
GPF31 GPF30 GPF29 GPF28 GPF27 GPF26 GPF25 GPF24
23 22 21 20 19 18 17 16
GPF23 GPF22 GPF21 GPF20 GPF19 GPF18 GPF17 GPF16
15 14 13 12 11 10 9 8
GPF15 GPF14 GPF13 GPF12 GPF11 GPF10 GPF09 GPF08
7 6 5 4 3 2 1 0
GPF07 GPF06 GPF05 GPF04 GPF03 GPF02 GPF01 GPF00
• GPFxx: General Purpose Fuse xx
0: The fuse has a written/programmed state.
1: The fuse has an erased state.
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12.9 Fuses Settings
The flash block contains 32 general purpose fuses. These 32 fuses can be found in the Flash
General Purpose Fuse Register Low (FGPFRLO) of the Flash Controller (FLASHC).
Some of the FGPFRLO fuses have defined meanings outside the FLASHC and are described in
this section.
The general purpose fuses are set by a JTAG chip erase.
12.9.1 Flash General Purpose Fuse Register Low (FGPFRLO)
Table 12-8. FGPFRLO Register Description
31 30 29 28 27 26 25 24
GPF31 GPF30 GPF29 BODEN BODHYST BODLEVEL[5:4]
23 22 21 20 19 18 17 16
BODLEVEL[3:0] BOOTPROT EPFL
15 14 13 12 11 10 9 8
LOCK[15:8]
7 6 5 4 3 2 1 0
LOCK[7:0]
• BODEN: Brown Out Detector Enable
Table 12-9. BODEN Field Description
BODEN Description
0x0 Brown Out Detector (BOD) disabled
0x1 BOD enabled, BOD reset enabled
0x2 BOD enabled, BOD reset disabled
0x3 BOD disabled
• BODHYST: Brown Out Detector Hystersis
0: The BOD hysteresis is disabled
1: The BOD hysteresis is enabled
• BODLEVEL: Brown Out Detector Trigger Level
This controls the voltage trigger level for the Brown out detector. For value description refer to Electrical Characteristics chapter.
If the BODLEVEL is set higher than VDDCORE and enabled by fuses, the part will be in constant reset. To recover from this
situation, apply an external voltage on VDDCORE that is higher than the BOD Trigger level and disable the BOD.
• LOCK, EPFL, BOOTPROT
These are Flash controller fuses and are described in the FLASHC chapter.
12.9.2 Default Fuse Value
The devices are shipped with the FGPFRLO register value: 0xFFF7FFFF:
• GPF31 reserved for future use
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• GPF30 reserved for future use
• GPF29 reserved for future use
• BODEN fuses set to 0b11. BOD is disabled.
• BODHYST fuse set to 0b1. The BOD hystersis is enabled.
• BODLEVEL fuses set to 0b111111. This is the minimum voltage trigger level. BOD will never
trigger as this level is below the POR level.
• BOOTPROT fuses set to 0b011. The bootloader protected size is 8KBytes.
• EPFL fuse set to 0b1. External privileged fetch is not locked.
• LOCK fuses set to 0b1111111111111111. No region locked.
The devices are shipped with 2 bootloader configuration words in the flash user pages:
at adress 808001F8h and 808001FCh. See also the USB DFU bootloader user guide document.
After the JTAG chip erase command, the FGPFRLO register value is 0xFFFFFFFF.
12.10 Serial number in the factory page
Each device has a unique 120 bits serial number located in the factory page and readable from
address 0x80800204 to 0x80800212.
12.11 Module configuration
The specific configuration for the FLASHC instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 12-10. Module Configuration
Feature FLASH
Devices ATUC3A3256S ATUC3A3128S ATUC3A364S
ATUC3A3256 ATUC3A3128 ATUC3A364
ATUC3A4256S ATUC3A4128S ATUC3A464
ATUC3A4256 ATUC3A4128 ATUC3A464
Flash size 256Kbytes 128Kbytes 64Kbytes
Number of
512 256 128
pages
Page size 512 bytes 512 bytes 512 bytes
Table 12-11. Module Clock Name
Module name Clock name Clock name
FLASHC CLK_FLASHC_HSB CLK_FLASHC_PB
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13. HSB Bus Matrix (HMATRIX)
Rev: 2.3.0.2
13.1 Features
• User Interface on peripheral bus
• Configurable Number of Masters (Up to sixteen)
• Configurable Number of Slaves (Up to sixteen)
• One Decoder for Each Master
•
• Programmable Arbitration for Each Slave
– Round-Robin
– Fixed Priority
• Programmable Default Master for Each Slave
– No Default Master
– Last Accessed Default Master
– Fixed Default Master
• One Cycle Latency for the First Access of a Burst
• Zero Cycle Latency for Default Master
• One Special Function Register for Each Slave (Not dedicated)
13.2 Overview
The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
13.3 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
13.3.1 Clocks
The clock for the HMATRIX bus interface (CLK_HMATRIX) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the HMATRIX before disabling the clock, to avoid freezing the HMATRIX in an undefined
state.
13.4 Functional Description
13.4.1 Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
transfer. This bus granting mechanism sets a different default master for every slave.
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At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master and fixed default master.
13.4.1.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from
all masters. No Default Master suits low-power mode.
13.4.1.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to
the last master that performed an access request.
13.4.1.3 Fixed Default Master
At the end of the current access, if no other request is pending, the slave connects to its fixed
default master. Unlike last access master, the fixed master does not change unless the user
modifies it by a software action (field FIXED_DEFMSTR of the related SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the
Slave Configuration Registers, one for each slave, that set a default master for each slave. The
Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The
2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed
default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master pro-
vided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user
interface description.
13.4.2 Arbitration
The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases
occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter
per HSB slave is provided, thus arbitrating each slave differently.
The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types for
each slave:
1. Round-Robin Arbitration (default)
2. Fixed Priority Arbitration
This choice is made via the field ARBT of the Slave Configuration Registers (SCFG).
Each algorithm may be complemented by selecting a default master configuration for each
slave.
When a re-arbitration must be done, specific conditions apply. See Section 13.4.2.1 ”Arbitration
Rules” on page 150.
13.4.2.1 Arbitration Rules
Each arbiter has the ability to arbitrate between two or more different master requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra-
tion may only take place during the following cycles:
1. Idle Cycles: When a slave is not connected to any master or is connected to a master
which is not currently accessing it.
2. Single Cycles: When a slave is currently doing a single access.
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3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst.
4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that
the current master access is too long and must be broken.
• Undefined Length Burst Arbitration
In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix pro-
vides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end
of burst is used as a defined length burst transfer and can be selected from among the following
five possibilities:
1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will
never be broken.
2. One beat bursts: Predicted end of burst is generated at each single transfer inside the
INCP transfer.
3. Four beat bursts: Predicted end of burst is generated at the end of each four beat
boundary inside INCR transfer.
4. Eight beat bursts: Predicted end of burst is generated at the end of each eight beat
boundary inside INCR transfer.
5. Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat
boundary inside INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers
(MCFG).
• Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a
very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches
zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word
transfer.
13.4.2.2 Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave in a round-robin manner. If two or more master requests arise at the same time,
the master with the lowest number is first serviced, then the others are serviced in a round-robin
manner.
There are three round-robin algorithms implemented:
1. Round-Robin arbitration without default master
2. Round-Robin arbitration with last default master
3. Round-Robin arbitration with fixed default master
• Round-Robin Arbitration without Default Master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch
requests from different masters to the same slave in a pure round-robin manner. At the end of
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the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency cycle for the first access of a burst. Arbitration without
default master can be used for masters that perform significant bursts.
• Round-Robin Arbitration with Last Default Master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to
remove the one latency cycle for the last master that accessed the slave. In fact, at the end of
the current transfer, if no other master request is pending, the slave remains connected to the
last master that performed the access. Other non privileged masters still get one latency cycle if
they want to access the same slave. This technique can be used for masters that mainly perform
single accesses.
• Round-Robin Arbitration with Fixed Default Master
This is another biased round-robin algorithm. It allows the Bus Matrix arbiters to remove the one
latency cycle for the fixed default master per slave. At the end of the current access, the slave
remains connected to its fixed default master. Every request attempted by this fixed default mas-
ter will not cause any latency whereas other non privileged masters will still get one latency
cycle. This technique can be used for masters that mainly perform single accesses.
13.4.2.3 Fixed Priority Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixed priority defined by the user. If two or more master requests are
active at the same time, the master with the highest priority number is serviced first. If two or
more master requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (PRAS and PRBS).
13.4.3 Slave and Master assignation
The index number assigned to Bus Matrix slaves and masters are described in Memories
chapter.
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13.5 User Interface
Table 13-1. HMATRIX Register Memory Map
Offset Register Name Access Reset Value
0x0000 Master Configuration Register 0 MCFG0 Read/Write 0x00000002
0x0004 Master Configuration Register 1 MCFG1 Read/Write 0x00000002
0x0008 Master Configuration Register 2 MCFG2 Read/Write 0x00000002
0x000C Master Configuration Register 3 MCFG3 Read/Write 0x00000002
0x0010 Master Configuration Register 4 MCFG4 Read/Write 0x00000002
0x0014 Master Configuration Register 5 MCFG5 Read/Write 0x00000002
0x0018 Master Configuration Register 6 MCFG6 Read/Write 0x00000002
0x001C Master Configuration Register 7 MCFG7 Read/Write 0x00000002
0x0020 Master Configuration Register 8 MCFG8 Read/Write 0x00000002
0x0024 Master Configuration Register 9 MCFG9 Read/Write 0x00000002
0x0028 Master Configuration Register 10 MCFG10 Read/Write 0x00000002
0x002C Master Configuration Register 11 MCFG11 Read/Write 0x00000002
0x0030 Master Configuration Register 12 MCFG12 Read/Write 0x00000002
0x0034 Master Configuration Register 13 MCFG13 Read/Write 0x00000002
0x0038 Master Configuration Register 14 MCFG14 Read/Write 0x00000002
0x003C Master Configuration Register 15 MCFG15 Read/Write 0x00000002
0x0040 Slave Configuration Register 0 SCFG0 Read/Write 0x00000010
0x0044 Slave Configuration Register 1 SCFG1 Read/Write 0x00000010
0x0048 Slave Configuration Register 2 SCFG2 Read/Write 0x00000010
0x004C Slave Configuration Register 3 SCFG3 Read/Write 0x00000010
0x0050 Slave Configuration Register 4 SCFG4 Read/Write 0x00000010
0x0054 Slave Configuration Register 5 SCFG5 Read/Write 0x00000010
0x0058 Slave Configuration Register 6 SCFG6 Read/Write 0x00000010
0x005C Slave Configuration Register 7 SCFG7 Read/Write 0x00000010
0x0060 Slave Configuration Register 8 SCFG8 Read/Write 0x00000010
0x0064 Slave Configuration Register 9 SCFG9 Read/Write 0x00000010
0x0068 Slave Configuration Register 10 SCFG10 Read/Write 0x00000010
0x006C Slave Configuration Register 11 SCFG11 Read/Write 0x00000010
0x0070 Slave Configuration Register 12 SCFG12 Read/Write 0x00000010
0x0074 Slave Configuration Register 13 SCFG13 Read/Write 0x00000010
0x0078 Slave Configuration Register 14 SCFG14 Read/Write 0x00000010
0x007C Slave Configuration Register 15 SCFG15 Read/Write 0x00000010
0x0080 Priority Register A for Slave 0 PRAS0 Read/Write 0x00000000
0x0084 Priority Register B for Slave 0 PRBS0 Read/Write 0x00000000
0x0088 Priority Register A for Slave 1 PRAS1 Read/Write 0x00000000
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Table 13-1. HMATRIX Register Memory Map (Continued)
Offset Register Name Access Reset Value
0x008C Priority Register B for Slave 1 PRBS1 Read/Write 0x00000000
0x0090 Priority Register A for Slave 2 PRAS2 Read/Write 0x00000000
0x0094 Priority Register B for Slave 2 PRBS2 Read/Write 0x00000000
0x0098 Priority Register A for Slave 3 PRAS3 Read/Write 0x00000000
0x009C Priority Register B for Slave 3 PRBS3 Read/Write 0x00000000
0x00A0 Priority Register A for Slave 4 PRAS4 Read/Write 0x00000000
0x00A4 Priority Register B for Slave 4 PRBS4 Read/Write 0x00000000
0x00A8 Priority Register A for Slave 5 PRAS5 Read/Write 0x00000000
0x00AC Priority Register B for Slave 5 PRBS5 Read/Write 0x00000000
0x00B0 Priority Register A for Slave 6 PRAS6 Read/Write 0x00000000
0x00B4 Priority Register B for Slave 6 PRBS6 Read/Write 0x00000000
0x00B8 Priority Register A for Slave 7 PRAS7 Read/Write 0x00000000
0x00BC Priority Register B for Slave 7 PRBS7 Read/Write 0x00000000
0x00C0 Priority Register A for Slave 8 PRAS8 Read/Write 0x00000000
0x00C4 Priority Register B for Slave 8 PRBS8 Read/Write 0x00000000
0x00C8 Priority Register A for Slave 9 PRAS9 Read/Write 0x00000000
0x00CC Priority Register B for Slave 9 PRBS9 Read/Write 0x00000000
0x00D0 Priority Register A for Slave 10 PRAS10 Read/Write 0x00000000
0x00D4 Priority Register B for Slave 10 PRBS10 Read/Write 0x00000000
0x00D8 Priority Register A for Slave 11 PRAS11 Read/Write 0x00000000
0x00DC Priority Register B for Slave 11 PRBS11 Read/Write 0x00000000
0x00E0 Priority Register A for Slave 12 PRAS12 Read/Write 0x00000000
0x00E4 Priority Register B for Slave 12 PRBS12 Read/Write 0x00000000
0x00E8 Priority Register A for Slave 13 PRAS13 Read/Write 0x00000000
0x00EC Priority Register B for Slave 13 PRBS13 Read/Write 0x00000000
0x00F0 Priority Register A for Slave 14 PRAS14 Read/Write 0x00000000
0x00F4 Priority Register B for Slave 14 PRBS14 Read/Write 0x00000000
0x00F8 Priority Register A for Slave 15 PRAS15 Read/Write 0x00000000
0x00FC Priority Register B for Slave 15 PRBS15 Read/Write 0x00000000
0x0110 Special Function Register 0 SFR0 Read/Write –
0x0114 Special Function Register 1 SFR1 Read/Write –
0x0118 Special Function Register 2 SFR2 Read/Write –
0x011C Special Function Register 3 SFR3 Read/Write –
0x0120 Special Function Register 4 SFR4 Read/Write –
0x0124 Special Function Register 5 SFR5 Read/Write –
0x0128 Special Function Register 6 SFR6 Read/Write –
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Table 13-1. HMATRIX Register Memory Map (Continued)
Offset Register Name Access Reset Value
0x012C Special Function Register 7 SFR7 Read/Write –
0x0130 Special Function Register 8 SFR8 Read/Write –
0x0134 Special Function Register 9 SFR9 Read/Write –
0x0138 Special Function Register 10 SFR10 Read/Write –
0x013C Special Function Register 11 SFR11 Read/Write –
0x0140 Special Function Register 12 SFR12 Read/Write –
0x0144 Special Function Register 13 SFR13 Read/Write –
0x0148 Special Function Register 14 SFR14 Read/Write –
0x014C Special Function Register 15 SFR15 Read/Write –
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13.5.1 Master Configuration Registers
Name: MCFG0...MCFG15
Access Type: Read/Write
Offset: 0x00 - 0x3C
Reset Value: 0x00000002
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – ULBT
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst.
2: Four Beat Burst
The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end.
3: Eight Beat Burst
The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end.
4: Sixteen Beat Burst
The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end.
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13.5.2 Slave Configuration Registers
Name: SCFG0...SCFG15
Access Type: Read/Write
Offset: 0x40 - 0x7C
Reset Value: 0x00000010
31 30 29 28 27 26 25 24
– – – – – – – ARBT
23 22 21 20 19 18 17 16
– – FIXED_DEFMSTR DEFMSTR_TYPE
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
SLOT_CYCLE
• ARBT: Arbitration Type
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
• FIXED_DEFMSTR: Fixed Default Master
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master
which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
The size of this field depends on the number of masters. This size is log2(number of masters).
• DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having
accessed it.
This results in not having one cycle latency when the last master tries to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number
that has been written in the FIXED_DEFMSTR field.
This results in not having one cycle latency when the fixed master tries to access the slave again.
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking a very slow slave when very long bursts are used.
This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing
any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
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13.5.3 Priority Registers A For Slaves
Name: PRAS0...PRAS15
Access Type: Read/Write
Offset: -
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – M7PR – – M6PR
23 22 21 20 19 18 17 16
– – M5PR – – M4PR
15 14 13 12 11 10 9 8
– – M3PR – – M2PR
7 6 5 4 3 2 1 0
– – M1PR – – M0PR
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
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13.5.4 Priority Registers B For Slaves
Name: PRBS0...PRBS15
Access Type: Read/Write
Offset: -
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – M15PR – – M14PR
23 22 21 20 19 18 17 16
– – M13PR – – M12PR
15 14 13 12 11 10 9 8
– – M11PR – – M10PR
7 6 5 4 3 2 1 0
– – M9PR – – M8PR
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
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13.5.5 Special Function Registers
Name: SFR0...SFR15
Access Type: Read/Write
Offset: 0x110 - 0x115
Reset Value: -
31 30 29 28 27 26 25 24
SFR
23 22 21 20 19 18 17 16
SFR
15 14 13 12 11 10 9 8
SFR
7 6 5 4 3 2 1 0
SFR
• SFR: Special Function Register Fields
Those registers are not a HMATRIX specific register. The field of those will be defined where they are used.
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13.6 Bus Matrix Connections
Accesses to unused areas returns an error result to the master requesting such an access.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU Data master interface.
Table 13-2. High Speed Bus masters
Master 0 CPU Data
Master 1 CPU Instruction
Master 2 CPU SAB
Master 3 PDCA
Master 4 DMACA HSB Master 1
Master 5 DMACA HSB Master 2
Master 6 USBB DMA
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, HMATRIX
SCFG4 register is associated with the Embedded CPU SRAM Slave Interface.
Table 13-3. High Speed Bus slaves
Slave 0 Internal Flash
Slave 1 HSB-PB Bridge A
Slave 2 HSB-PB Bridge B
Slave 3 AES
Slave 4 Embedded CPU SRAM
Slave 5 USBB DPRAM
Slave 6 EBI
Slave 7 DMACA Slave
Slave 8 HRAMC0
Slave 9 HRAMC1
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Figure 13-1. HMATRIX Master / Slave Connections
HMATRIX SLAVES
Internal Flash
USB DPRAM
CPU SRAM
Embedded
HRAMC0
HRAMC1
Bridge A
Bridge B
HSB-PB
HSB-PB
DMACA
Slave
AES
EBI
0 1 2 3 4 5 6 7 8 9
CPU Data 0
CPU
1
Instruction
CPU SAB 2
HMATRIX MASTERS
PDCA 3
DMACA
4
Master 0
DMACA
5
Master 1
USBB
6
DMA
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14. External Bus Interface (EBI)
Rev.: 1.7.0.1
14.1 Features
• Optimized for application memory space support
• Integrates three external memory controllers:
– Static Memory Controller (SMC)
– SDRAM Controller (SDRAMC)
– Error Corrected Code (ECCHRS) controller
• Additional logic for NAND Flash/SmartMediaTM and CompactFlashTM support
– NAND Flash support: 8-bit as well as 16-bit devices are supported
– CompactFlash support: Attribute Memory, Common Memory, I/O modes are supported but
the signal _IOIS16 (I/O mode) is not handled.
• Optimized external bus:16-bit data bus
– Up to 24-bit Address Bus, Up to 8-Mbytes Addressable
– Optimized pin multiplexing to reduce latencies on external memories
• Up to 6 Chip Selects, Configurable Assignment:
– Static Memory Controller on Chip Select 0
– SDRAM Controller or Static Memory Controller on Chip Select 1
– Static Memory Controller on Chip Select 2, Optional NAND Flash support
– Static Memory Controller on Chip Select 3, Optional NAND Flash support
– Static Memory Controller on Chip Select 4, Optional CompactFlashTM support
– Static Memory Controller on Chip Select 5, Optional CompactFlashTM support
14.2 Overview
The External Bus Interface (EBI) is designed to ensure the successful data transfer between
several external devices and the embedded memory controller of an 32-bit AVR device. The
Static Memory, SDRAM and ECCHRS Controllers are all featured external memory controllers
on the EBI. These external memory controllers are capable of handling several types of external
memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and
SDRAM.
The EBI also supports the CompactFlash and the NAND Flash/SmartMedia protocols via inte-
grated circuitry that greatly reduces the requirements for external components. Furthermore, the
EBI handles data transfers with up to six external devices, each assigned to six address spaces
defined by the embedded memory controller. Data transfers are performed through a 16-bit, an
address bus of up to 23 bits, up to six chip select lines (NCS[5:0]), and several control pins that
are generally multiplexed between the different external memory controllers.
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14.3 Block Diagram
Figure 14-1. EBI Block Diagram
INTC
SDRAMC_irq ECCHRS_irq
HMATRIX EBI
DATA[15:0]
HSB SDRAM
Controller
NWE1
NWE0
Static NRD
Memory
Controller NCS[5:0]
ADDR[23:0]
CAS
ECCHRS
Controller I/O
RAS
MUX
Logic Controller
SDA10
NAND Flash SDWE
SmartMedia
Logic SDCK
SFR
registers
SDCKE
Compact
FLash
Logic NANDOE
NANDWE
Address Chip Select
Decoders Assignor CFRNW
CFCE1
CFCE2
HSB-PB
Bridge NWAIT
Peripheral Bus
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14.4 I/O Lines Description
Table 14-1. EBI I/O Lines Description
Alternate Active
Pin Name Name Pin Description Type Level
EBI common lines
DATA[15:0] Data Bus I/O
SMC dedicated lines
ADDR[1] SMC Address Bus Line 1 Output
ADDR[12] SMC Address Bus Line 12 Output
ADDR[15] SMC Address Bus Line 15 Output
ADDR[23:18] SMC Address Bus Line [23:18] Output
NCS[0] SMC Chip Select Line 0 Output Low
NWAIT SMC External Wait Signal Input Low
SDRAMC dedicated lines
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDWE SDRAM Write Enable Output Low
SDA10 SDRAM Address Bus Line 10 Output Low
RAS - CAS Row and Column Signal Output Low
CompactFlash dedicated lines
CFCE1 -
CompactFlash Chip Enable Output Low
CFCE2
CFRNW CompactFlash Read Not Write Signal Output
NAND Flash/SmartMedia dedicated lines
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
SMC/SDRAMC shared lines
NCS[1] SMC Chip Select Line 1
NCS[1] Output Low
SDCS0 SDRAMC Chip Select Line 0
DQM0 SDRAMC DQM1
ADDR[0] Output
ADDR[0]-NBS0 SMC Address Bus Line 0 or Byte Select 1
ADDR[9:0] SDRAMC Address Bus Lines [9:0]
ADDR[11:2] Output
ADDR[11:2] SMC Address Bus Lines [11:2]
ADDR[9:0] SDRAMC Address Bus Lines [12:11]
ADDR[14:13] Output
ADDR[14:13] SMC Address Bus Lines [14:13]
BA0 SDRAMC Bank 0
ADDR[16] Output
ADDR[16] SMC Address Bus Line 16
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Alternate Active
Pin Name Name Pin Description Type Level
BA1 SDRAMC Bank 1
ADDR[17] Output
ADDR[17] SMCAddress Bus Line 17
SMC/CompactFlash shared lines
NRD SMC Read Signal
NRD Output Low
CFNOE CompactFlash CFNOE
NWE0-NWE SMC Write Enable10 or Write enable
NWE0 Output Low
CFNWE CompactFlash CFNWE
NCS[4] SMC Chip Select Line 4
NCS[4] Output Low
CFCS[0] CompactFlash Chip Select Line 0
NCS[5] SMC Chip Select Line 5
NCS[5] Output Low
CFCS[1] CompactFlash Chip Select Line 1
SMC/NAND Flash/SmartMedia shared lines
SMC Chip Select Line 2
NCS[2]
NCS[2] NANDFlash/SmartMedia Chip Select Line Output Low
NANDCS[0]
0
SMC Chip Select Line 3
NCS[3]
NCS[3] NANDFlash/SmartMedia Chip Select Line Output Low
NANDCS[1]
1
SDRAMC/SMC/CompactFlash shared lines
DQM1/ SDRAMC DQM1
NWE1 NWE1-NBS1/ SMC Write Enable1 or Byte Select 1 Output
CFNIORD CompactFlash CFNIORD
14.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
14.5.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with I/O Con-
troller lines. The user must first configure the I/O Controller to assign the EBI pins to their
peripheral functions.
14.5.2 Power Management
To prevent bus errors EBI operation must be terminated before entering sleep mode.
14.5.3 Clocks
A number of clocks can be selected as source for the EBI. The selected clock must be enabled
by the Power Manager.
The following clock sources are available:
• CLK_EBI
• CLK_SDRAMC
• CLK_SMC
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• CLK_ECCHRS
Refer to Table 14-2 on page 167 to configure those clocks.
Table 14-2. EBI Clocks Configuration
Type of the Interfaced Device
Clocks SRAM, PROM,
Clocks name NandFlash
type SDRAM EPROM, CompactFlash
SmartMedia
EEPROM, Flash
CLK_EBI HSB X X X X
CLK_SDRAMC PB X
CLK_SMC PB X X X
CLK_ECCHRS PB X
14.5.4 Interrupts
The EBI interface has two interrupt lines connected to the Interrupt Controller:
• SDRAMC_IRQ: Interrupt signal coming from the SDRAMC
• ECCHRS_IRQ: Interrupt signal coming from the ECCHRS
Handling the EBI interrupt requires configuring the interrupt controller before configuring the EBI.
14.5.5 HMATRIX
The EBI interface is connected to the HMATRIX Special Function Register 6 (SFR6). The user
must first write to this HMATRIX.SFR6 to configure the EBI correctly.
Table 14-3. EBI Special Function Register Fields Description
SFR6 Bit
Number Bit name Description
[31:6] Reserved
0 = Chip Select 5 (NCS[5]) is connected to a Static Memory device. For each
access to the NCS[5] memory space, all related pins act as SMC pins
5 CS5A 1 = Chip Select 5 (NCS[5]) is connected to a CompactFlash device. For each
access to the NCS[5] memory space, all related pins act as CompactFlash
pins
0 = Chip Select 4 (NCS[4]) is connected to a Static Memory device. For each
access to the NCS[4] memory space, all related pins act as SMC pins
4 CS4A 1 = Chip Select 4 (NCS[4]) is connected to a CompactFlash device. For each
access to the NCS[4] memory space, all related pins act as CompactFlash
pins
0 = Chip Select 3 (NCS[3]) is connected to a Static Memory device. For each
access to the NCS[3] memory space, all related pins act as SMC pins
3 CS3A 1 = Chip Select 3 (NCS[3]) is connected to a NandFlash or a SmartMedia
device. For each access to the NCS[3] memory space, all related pins act as
NandFlash or SmartMedia pins
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Table 14-3. EBI Special Function Register Fields Description
SFR6 Bit
Number Bit name Description
0 = Chip Select 2 (NCS[2]) is connected to a Static Memory device. For each
access to the NCS[2] memory space, all related pins act as SMC pins
2 CS2A 1 = Chip Select 2 (NCS[2]) is connected to a NandFlash or a SmartMedia
device. For each access to the NCS[2] memory space, all related pins act as
NandFlash or SmartMedia pins
0 = Chip Select 1 (NCS[1]) is connected to a Static Memory device. For each
access to the NCS[1] memory space, all related pins act as SMC pins
1 CS1A
1 = Chip Select 1 (NCS[1]) is connected to a SDRAM device. For each access
to the NCS[1] memory space, all related pins act as SDRAM pins
0 Reserved
14.6 Functional Description
The EBI transfers data between the internal HSB bus (handled by the HMATRIX) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control busses and is composed of the following elements:
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• The ECCHRS Controller (ECCHRS)
• A chip select assignment feature that assigns an HSB address space to the external devices
• A multiplex controller circuit that shares the pins between the different memory controllers
• Programmable CompactFlash support logic
• Programmable SmartMedia and NAND Flash support logic
14.6.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 16-bit data lines, the address
lines of up to 24 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAMC without delaying the
other external memory controller accesses.
14.6.2 Static Memory Controller
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
14.6.3 SDRAM Controller
Writing a one to the HMATRIX.SFR6.CS1A bit enables the SDRAM logic.
For information on the SDRAM Controller, refer to the SDRAM Section.
14.6.4 ECCHRS Controller
For information on the ECCHRS Controller, refer to the ECCHRS Section.
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14.6.5 CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the SMC on the NCS[4] and/or NCS[5] address space.
Writing to the HMATRIX.SFR6.CS4A and/or HMATRIX.SFR6.CS5A bits the appropriate value
enables this logic. Access to an external CompactFlash device is then made by accessing the
address space reserved to NCS[4] and/or NCS[5].
Attribute Memory, Common Memory, I/O modes are supported but the signals _IOWR, _IOIS16
(I/O mode) are not handled.
14.6.5.1 I/O Mode, Common Memory Mode, Attribute Memory Mode
Within the NCS[4] and/or NCS[5] address space, the current transfer address is used to distin-
guish I/O mode, common memory mode andattribute memory mode.
The different modes are accessed through a specific memory mapping as illustrated on Figure
14-2 on page 169. ADDR[23:21] bits of the transfer address are used to select the desired mode
as described in Table 14-4 on page 169.
Figure 14-2. CompactFlash Memory Mapping
I/O Mode Space
(Read operations)
Offset 0x0080 0000
CF Address Space
Common Memory Mode Space
Offset 0x0040 0000
I/O Mode Space
(Write operations)
Offset 0x0020 0000
Attribute Memory Mode Space
Offset 0x0000 0000
Note: The ADDR[22] I/O line is used to drive the REG signal of the CompactFlash Device.
Table 14-4. CompactFlash Mode Selection
ADDR[23:21] Mode Base Address
000 Attribute Memory
001 I/O Mode (Write operations)
010 Common Memory
100 I/O Mode (Read operations)
14.6.5.2 CFCE1 and CFCE2 signals
To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit
data bus. The odd byte access on the DATA[7:0] bus is only possible when the SMC is config-
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ured to drive 8-bit memory devices on the corresponding NCS pin (NCS[4] or NCS[5]). The Data
Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address
space must be written as shown in Table 14-5 on page 170 to enable the required access type.
NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set
in Byte Select mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the SMC Section.
Table 14-5. CFCE1 and CFCE2 Truth Table
SMC Access
Mode CFCE2 CFCE1 DBW Comment Mode
Access to Even Byte on
Attribute Memory NBS1 NBS0 16 bits Byte Select
DATA[7:0]
Access to Even Byte on
DATA[7:0]
NBS1 NBS0 16bits Byte Select
Access to Odd Byte on
Common Memory DATA[15:8]
Access to Odd Byte on
1 0 8 bits
DATA[7:0]
Access to Even Byte on
DATA[7:0]
NBS1 NBS0 16 bits Byte Select
Access to Odd Byte on
I/O Mode DATA[15:8]
Access to Odd Byte on
1 0 8 bits
DATA[7:0]
14.6.5.3 Read/Write signals
During read operations, in I/O mode, the CompactFlash logic drives the read command signals
of the SMC on CFNIORD signal, while the CFNOE is deactivated. Likewise, in common memory
mode and attribute memory mode, the SMC signals are driven on the CFNOE signal, while the
CFNIORD is deactivated. Figure 14-3 on page 171 demonstrates a schematic representation of
this logic.
During write operations, in all modes, the CompactFlash logic drives the write command signal
of the SMC on CFNWE signal. Addtionnal external logic is required to drive _WE and _IOWR
compact flash signals based on CFNWE. Figure 14-3 on page 171 demonstrates a schematic
representation of this logic. No external logic is required if I/O mode is not used (in this case,
CNFWE signal can drive directly _WE compact flash signal).
Attribute memory mode, common memory mode and I/O mode are supported by writing the
address setup and hold time on the NCS[4] (and/or NCS[5]) chip select to the appropriate val-
ues. For details on these signal waveforms, please refer to the section: Setup and Hold Cycles
of the SMC Section.
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Figure 14-3. CompactFlash Read/Write Control Signals
EBI
SMC Compact Flash Logic
A23
1
1
0 CFNOE
0
CFNWE
1 1
A22
NRD
0 CFNIORD
NWR0/NWE
1 1
Table 14-6. CompactFlash Mode Selection
Mode Base Address CFNOE CFNWE CFNIORD
Attribute Memory
I/O Mode (Write operations) NRD_NOE NWR0_NWE 1
Common Memory
I/O Mode (Read operations) 1 1 NRD_NOE
14.6.5.4 Multiplexing of CompactFlash signals on EBI pins
Table 14-7 on page 171 and Table on page 171 illustrate the multiplexing of the CompactFlash
logic signals with other EBI signals on the EBI pins. The EBI pins in Table 14-7 on page 171 are
strictly dedicated to the CompactFlash interface as soon as the HMATRIX.SFR6.CS4A and/or
HMATRIX.SFR6.CS5A bits is/are written. These pins must not be used to drive any other mem-
ory devices.
The EBI pins in Table 14-8 on page 172 remain shared between all memory areas when the cor-
responding CompactFlash interface is enabled (CS4A = 1 and/or CS5A = 1).
Table 14-7. Dedicated CompactFlash Interface Multiplexing
CompactFlash Signals EBI Signals
Pins
CS4A = 1 CS5A = 1 CS4A = 0 CS5A = 0
NCS[4] CFCS0 NCS[4]
NCS[5] CFCS1 NCS[5]
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Table 14-8. Shared CompactFlash Interface Multiplexing
Access to
CompactFlash Device
Pins CompactFlash Signals
NRD CFNOE
NWE0 CFNWE
NWE1 CFNIORD
CFRNW CFRNW
14.6.5.5 Application example
Figure 14-4 on page 172 illustrates an example of a CompactFlash application. CFCS0 and
CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc-
tion and the output enable of the buffers between the EBI and the CompactFlash Device. The
timing of the CFCS0 signal is identical to the NCS[4] signal. The CFRNW signal remains valid
throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is con-
nected to the NWAIT input of the Static Memory Controller. For details on these waveforms and
timings, refer to the SMC Section.
Figure 14-4. CompactFlash Application Example with I/O mode
CompactFlash
EBI Connector
DATA[15:0] D[15:0]
DIR /OE
CFRNW
NCS[4]
_CD1
Pxx
_CD2
/OE
ADDR[10:0] A[10:0]
ADDR[22] _REG
NRD _OE
NWE0 _WE
NWE1 _IORD
_IOWR
ADDR[21]
CFCE1 _CE1
CFCE2 _CE2
NWAIT _WAIT
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Figure 14-5. CompactFlash Application Example without I/O mode
CompactFlash
EBI Connector
DATA[15:0] D[15:0]
DIR /OE
CFRNW
NCS[4]
_CD1
Pxx
_CD2
/OE
ADDR[10:0] A[10:0]
ADDR[22] _REG
NRD _OE
NWE0 _WE
NWE1 _IORD
_IOWR
ADDR[21]
CFCE1 _CE1
CFCE2 _CE2
NWAIT _WAIT
14.6.6 SmartMedia and NAND Flash Support
The EBI integrates circuitry that interfaces to SmartMedia and NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller on the NCS[2] (and/or NCS[3])
address space. Writing to the HMATRIX.SFR6.CS2A (and/or HMATRIX.SFR6.CS3A) bit the
appropriate value enables the NAND Flash logic. Access to an external NAND Flash device is
then made by accessing the address space reserved to NCS[2] (and/or NCS[3]).
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS[2] (and/or NCS[3]) signal is active. NANDOE and
NANDWE are invalidated as soon as the transfer address fails to lie in the NCS[2] (and/or
NCS[3]) address space. See Figure 14-6 on page 174 for more informations. For details on
these waveforms, refer to the SMC Section.
The SmartMedia device is connected the same way as the NAND Flash device.
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Figure 14-6. NAND Flash Signal Multiplexing on EBI Pins
EBI
SMC NandFlash
Logic
NANDOE
NCS[2]/[3]
NRD
NANDWE
NWR0_NWE
14.6.6.1 NAND Flash signals
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits ADDR[22] and ADDR[21] of the EBI address bus. The user should note
that any bit on the EBI address bus can also be used for this purpose. The command, address or
data words on the data bus of the NAND Flash device are distinguished by using their address
within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy
(R/B) signals are connected to I/O Controller lines. The CE signal then remains asserted even
when NCSx is not selected, preventing the device from returning to standby mode.
Figure 14-7. NAND Flash Application Example
DATA[7:0] AD[7:0]
ADDR[22] ALE
ADDR[21] CLE
NandFlash
EBI
NANDOE NOE
NANDWE NWE
NCS[2/3]
Or I/O line CE
I/O line R/B
Note: The External Bus Interfaces is also able to support 16-bits devices.
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14.7 Application Example
14.7.1 Hardware Interface
Table 14-9. EBI Pins and External Static Devices Connections
Pins of the Interfaced Device
2 x 8-bit
8-bit Static 16-bit Static
Static
Device Device
Pins name Devices
Controller SMC
DATA[7:0] D[7:0] D[7:0] D[7:0]
DATA[15:0 – D[15:8] D[15:8]
ADDR[0] A[0] – NBS0(2)
ADDR[1] A[1] A[0] A[0]
ADDR[23:2] A[23:2] A[22:1] A[22:1]
NCS[0] - NCS[5] CS CS CS
NRD OE OE OE
(1)
NWE0 WE WE WE
(1)
NWE1 – WE NBS1(2)
Note: 1. NWE1 enables upper byte writes. NWE0 enables lower byte writes.
2. NBS1 enables upper byte writes. NBS0 enables lower byte writes.
Table 14-10. EBI Pins and External Devices Connections
Pins of the Interfaced Device
Smart Media
Compact
SDRAM or
Flash
Pins name NAND Flash
Controller SDRAMC SMC
DATA[7:0] D[7:0] D[7:0] AD[7:0]
DATA[15:8] D[15:8] D[15:8] AD[15:8]
ADDR[0] DQM0 A[0] –
ADDR[1] – A[1] –
ADDR[10:2] A[8:0] A[10:2] –
ADDR[11] A[9] – –
SDA10 A[10] – –
ADDR[12] – – –
ADDR[14:13] A[12:11] – –
ADDR[15] – – –
ADDR[16] BA0 – –
ADDR[17] BA1 – –
ADDR[20:18] – – –
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Table 14-10. EBI Pins and External Devices Connections (Continued)
Pins of the Interfaced Device
Smart Media
Compact
SDRAM or
Flash
Pins name NAND Flash
Controller SDRAMC SMC
ADDR[21] – – CLE(3)
ADDR[22] – REG ALE(3)
NCS[0] – – –
NCS[1] SDCS[0] – –
NCS[2] – – CE0
NCS[3] – – CE1
(1)
NCS[4] – CFCS0 –
(1)
NCS[5] – CFCS1 –
NANDOE – – OE
NANDWE – – WE
NRD – OE –
NWE0 – WE –
NWE1 DQM1 IOR –
(1)
CFRNW – CFRNW –
CFCE1 – CE1 –
CFCE2 – CE2 –
SDCK CLK – –
SDCKE CKE – –
RAS RAS – –
CAS CAS – –
SDWE WE – –
NWAIT – WAIT –
(2)
Pxx – CD1 or CD2 –
(2)
Pxx – – RDY
Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer
between the EBI data bus and the CompactFlash slot.
2. Any I/O Controller line.
3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For
details, see Section 14.6.6.
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14.7.2 Connection Examples
Figure 14-8 on page 177shows an example of connections between the EBI and external
devices.
Figure 14-8. EBI Connections to Memory Devices
EBI
DATA[15:0]
RAS
CAS SDRAM SDRAM
SDCK
SDCKE
DATA[7:0]
D[7:0]
2Mx8 DATA[15:8] 2Mx8
D[7:0]
SDWE
ADDR[0] CS ADDR[11:2] CS ADDR[11:2]
SDCK A[9:0] SDCK A[9:0]
NWE1 CLK SDA10 CLK SDA10
SDCKE A[10] SDCKE A[10]
NRD CKE ADDR[13] CKE ADDR[13]
SDWE A[11] SDWE A[11]
NWE0 WE ADDR[16] WE ADDR[16]
RAS BA0 ADDR[17]
RAS BA0 ADDR[17]
CAS RAS BA1 CAS RAS BA1
ADDR[0] CAS NWE1 CAS
DQM DQM
SDA10
ADDR[17:1]
NCS[1]
NCS[0]
DATA[15:8]
DATA[7:0]
SRAM SRAM
128Kx8 128Kx8
D[7:0] A[16:0] ADDR[17:1] D[7:0] A[16:0] ADDR[17:1]
NCS[0] NCS[0]
CS CS
NRD NRD
OE OE
NWE0 NWE1
WE WE
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15. Static Memory Controller (SMC)
Rev. 1.0.6.5
15.1 Features
• 6 chip selects available
• 16-Mbytes address space per chip select
• 8- or 16-bit data bus
• Word, halfword, byte transfers
• Byte write or byte select lines
• Programmable setup, pulse and hold time for read signals per chip select
• Programmable setup, pulse and hold time for write signals per chip select
• Programmable data float time per chip select
• Compliant with LCD module
• External wait request
• Automatic switch to slow clock mode
• Asynchronous read in page mode supported: page size ranges from 4 to 32 bytes
15.2 Overview
The Static Memory Controller (SMC) generates the signals that control the access to the exter-
nal memory devices or peripheral devices. It has 6 chip selects and a 24-bit address bus. The
16-bit data bus can be configured to interface with 8-16-bit external devices. Separate read and
write control signals allow for direct memory and peripheral interfacing. Read and write signal
waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-
programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.
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15.3 Block Diagram
Figure 15-1. SMC Block Diagram (AD_MSB=23)
NCS[5:0]
NCS[5:0]
SMC NRD
NRD
HMatrix Chip Select
NWR0/NWE
NWE0
A0/NBS0
ADDR[0]
NWR1/NBS1
NWE1
SMC A1/NWR2/NBS2 EBI I/O
ADDR[1]
Mux Logic Controller
Power CLK_SMC
Manager A[AD_MSB:2]
ADDR[AD_MSB:2]
D[15:0]
DATA[15:0]
NWAIT
NWAIT
User Interface
Peripheral Bus
15.4 I/O Lines Description
Table 15-1. I/O Lines Description
Pin Name Pin Description Type Active Level
NCS[5:0] Chip Select Lines Output Low
NRD Read Signal Output Low
NWR0/NWE Write 0/Write Enable Signal Output Low
A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low
NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low
A[23:2] Address Bus Output
D[15:0] Data Bus Input/Output
NWAIT External Wait Signal Input Low
15.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
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15.5.1 I/O Lines
The SMC signals pass through the External Bus Interface (EBI) module where they are multi-
plexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to
SMC signals to their peripheral function. If the I/O lines of the EBI corresponding to SMC signals
are not used by the application, they can be used for other purposes by the I/O Controller.
15.5.2 Clocks
The clock for the SMC bus interface (CLK_SMC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SMC before disabling the clock, to avoid freezing the SMC in an undefined state.
15.6 Functional Description
15.6.1 Application Example
Figure 15-2. SMC Connections to Static Memory Devices
D0-D15
A0/NBS0 128K x 8 128K x 8
NWR0/NWE
NWR1/NBS1 SRAM SRAM
D0-D7 D8-D15
D0-D7 D0-D7
CS CS
A0-A16 A2-A18 A0-A16 A2-A18
NRD NRD
NCS0 OE OE
NCS1 NWR0/NWE NWR1/NBS1
WE WE
NCS2
NCS3
NCS4
NCS5
Static Memory
Controller
A2-A18
15.6.2 External Memory Mapping
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address
up to 16Mbytes of memory.
If the physical memory device connected on one chip select is smaller than 16Mbytes, it wraps
around and appears to be repeated within this space. The SMC correctly handles any valid
access to the memory device within the page (see Figure 15-3 on page 181).
A[23:0] is only significant for 8-bit memory, A[23:1] is used for 16-bit memory23.
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Figure 15-3. Memory Connections for Six External Devices
NCS[0] - NCS[5]
NRD
SMC NWE NCS5
Memory Enable
A[AD_MSB:0] NCS4
Memory Enable
D[15:0] NCS3
Memory Enable
NCS2
Memory Enable
NCS1
Memory Enable
NCS0
Memory Enable
Output Enable
Write Enable
A[AD_MSB:0]
8 or 16
D[15:0] or D[7:0]
15.6.3 Connection to External Devices
15.6.3.1 Data bus width
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by
the Data Bus Width field in the Mode Register (MODE.DBW) for the corresponding chip select.
Figure 15-4 on page 181 shows how to connect a 512K x 8-bit memory on NCS2. Figure 15-5 on
page 182 shows how to connect a 512K x 16-bit memory on NCS2.
15.6.3.2 Byte write or byte select access
Each chip select with a 16-bit data bus can operate with one of two different types of write
access: byte write or byte select access. This is controlled by the Byte Access Type bit in the
MODE register (MODE.BAT) for the corresponding chip select.
Figure 15-4. Memory Connection for an 8-bit Data Bus
D[7:0] D[7:0]
A[18:2] A[18:2]
A0 A0
SMC A1 A1
NWE Write Enable
NRD Output Enable
NCS[2] Memory Enable
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Figure 15-5. Memory Connection for a 16-bit Data Bus
D[15:0] D[15:0]
A[19:2] A[18:1]
A1 A[0]
SMC NBS0 Low Byte Enable
NBS1 High Byte Enable
NWE Write Enable
NRD Output Enable
NCS[2] Memory Enable
•Byte write access
The byte write access mode supports one byte write signal per byte of the data bus and a single
read signal.
Note that the SMC does not allow boot in byte write access mode.
• For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0
(lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
The byte write access mode is used to connect two 8-bit devices as a 16-bit memory.
The byte write option is illustrated on Figure 15-6 on page 183.
•Byte select access
In this mode, read/write operations can be enabled/disabled at a byte level. One byte select line
per byte of the data bus is provided. One NRD and one NWE signal control read and write.
• For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively
byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. The byte select access is used to
connect one 16-bit device.
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Figure 15-6. Connection of two 8-bit Devices on a 16-bit Bus: Byte Write Option
D[7:0] D[7:0]
D[15:8]
A[24:2] A[23:1]
SMC A1 A[0]
NWR0 Write Enable
NWR1
NRD Read Enable
NCS[3] Memory Enable
D[15:8]
A[23:1]
A[0]
Write Enable
Read Enable
Memory Enable
•Signal multiplexing
Depending on the MODE.BAT bit, only the write signals or the byte select signals are used. To
save I/Os at the external bus interface, control signals at the SMC interface are multiplexed.
For 16-bit devices, bit A0 of address is unused. When byte select option is selected, NWR1 is
unused. When byte write option is selected, NBS0 to NBS1 are unused.
Table 15-3. SMC Multiplexed Signal Translation
Signal Name 16-bit Bus 8-bit Bus
Device Type 1 x 16-bit 2 x 8-bit 1 x 8-bit
Byte Access Type (BAT) Byte Select Byte Write
NBS0_A0 NBS0 A0
NWE_NWR0 NWE NWR0 NWE
NBS1_NWR1 NBS1 NWR1
NBS2_NWR2_A1 A1 A1 A1
15.6.4 Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to
NBS1) always have the same timing as the address bus (A). NWE represents either the NWE
signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write
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access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..5] chip select lines.
15.6.4.1 Read waveforms
The read cycle is shown on Figure 15-7 on page 184.
The read cycle starts with the address setting on the memory address bus, i.e.:
{A[23:2], A1, A0} for 8-bit devices
{A[23:2], A1} for 16-bit devices
Figure 15-7. Standard Read Cycle
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
NRDSETUP NRDPULSE NRDHOLD
NCSRDSETUP NCSRDPULSE NCSRDHOLD
NRDCYCLE
•NRD waveform
The NRD signal is characterized by a setup timing, a pulse width, and a hold timing.
1. NRDSETUP: the NRD setup time is defined as the setup of address before the NRD
falling edge.
2. NRDPULSE: the NRD pulse length is the time between NRD falling edge and NRD ris-
ing edge.
3. NRDHOLD: the NRD hold time is defined as the hold time of address after the NRD ris-
ing edge.
•NCS waveform
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time.
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1. NCSRDSETUP: the NCS setup time is defined as the setup time of address before the
NCS falling edge.
2. NCSRDPULSE: the NCS pulse length is the time between NCS falling edge and NCS
rising edge.
3. NCSRDHOLD: the NCS hold time is defined as the hold time of address after the NCS
rising edge.
•Read cycle
The NRDCYCLE time is defined as the total duration of the read cycle, i.e., from the time where
address is set on the address bus to the point where address may change. The total read cycle
time is equal to:
NRDCYCLE = NRDSETUP + NRDPULSE + NRDHOLD
Similarly,
NRDCYCLE = NCSRDSETUP + NCSRDPULSE + NCSRDHOLD
All NRD and NCS timings are defined separately for each chip select as an integer number of
CLK_SMC cycles. To ensure that the NRD and NCS timings are coherent, the user must define
the total read cycle instead of the hold timing. NRDCYCLE implicitly defines the NRD hold time
and NCS hold time as:
NRDHOLD = NRDCYCLE – NRDSETUP – NRDPULSE
And,
NCSRDHOLD = NRDCYCLE – NCSRDSETUP – NCSRDPULSE
•Null delay setup and hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain
active continuously in case of consecutive read cycles in the same memory (see Figure 15-8 on
page 186).
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Figure 15-8. No Setup, No Hold on NRD, and NCS Read Signals
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
NRDSETUP NRDPULSE NRDPULSE
NCSRDPULSE NCSRDPULSE NCSRDPULSE
NRDCYCLE NRDCYCLE NRDCYCLE
• Null Pulse
Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads
to unpredictable behavior.
15.6.4.2 Read mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
i n g s t o k n o w w h i c h s ig n a l r i s e s f i r s t . T h e R e a d M o d e b it i n t h e M O D E r e g i s t e r
(MODE.READMODE) of the corresponding chip select indicates which signal of NRD and NCS
controls the read operation.
•Read is controlled by NRD (MODE.READMODE = 1)
Figure 15-9 on page 187 shows the waveforms of a read operation of a typical asynchronous
RAM. The read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the ris-
ing edge of NRD. In this case, the MODE.READMODE bit must be written to one (read is
controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC sam-
ples the read data internally on the rising edge of CLK_SMC that generates the rising edge of
NRD, whatever the programmed waveform of NCS may be.
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Figure 15-9. READMODE = 1: Data Is Sampled by SMC Before the Rising Edge of NRD
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
tPACC
D[15:0]
Data Sampling
•Read is controlled by NCS (MODE.READMODE = 0)
Figure 15-10 on page 188 shows the typical read cycle of an LCD module. The read data is valid
tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data
must be sampled when NCS is raised. In that case, the MODE.READMODE bit must be written
to zero (read is controlled by NCS): the SMC internally samples the data on the rising edge of
CML_SMC that generates the rising edge of NCS, whatever the programmed waveform of NRD
may be.
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Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
tPACC
D[15:0]
Data Sampling
15.6.4.3 Write waveforms
The write protocol is similar to the read protocol. It is depicted in Figure 15-11 on page 189. The
write cycle starts with the address setting on the memory address bus.
•NWE waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
1. NWESETUP: the NWE setup time is defined as the setup of address and data before
the NWE falling edge.
2. NWEPULSE: the NWE pulse length is the time between NWE falling edge and NWE
rising edge.
3. NWEHOLD: the NWE hold time is defined as the hold time of address and data after
the NWE rising edge.
The NWE waveforms apply to all byte-write lines in byte write access mode: NWR0 to NWR3.
15.6.4.4 NCS waveforms
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined.
1. NCSWRSETUP: the NCS setup time is defined as the setup time of address before the
NCS falling edge.
2. NCSWRPULSE: the NCS pulse length is the time between NCS falling edge and NCS
rising edge;
3. NCSWRHOLD: the NCS hold time is defined as the hold time of address after the NCS
rising edge.
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Figure 15-11. Write Cycle
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NCS
NWESETUP NWEPULSE NWEHOLD
NCSWRSETUP NCSWRPULSE NCSWRHOLD
NWECYCLE
•Write cycle
The write cycle time is defined as the total duration of the write cycle, that is, from the time where
address is set on the address bus to the point where address may change. The total write cycle
time is equal to:
NWECYCLE = NWESETUP + NWEPULSE + NWEHOLD
Similarly,
NWECYCLE = NCSWRSETUP + NCSWRPULSE + NCSWRHOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of CLK_SMC cycles. To ensure that the NWE and NCS timings are coherent, the user must
define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time
and NCS (write) hold times as:
NWEHOLD = NWECYCLE – NWESETUP – NWEPULSE
And,
NCSWRHOLD = NWECYCLE – NCSWRSETUP – NCSWRPULSE
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•Null delay setup and hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see Figure 15-12 on page
190). However, for devices that perform write operations on the rising edge of NWE or NCS,
such as SRAM, either a setup or a hold must be programmed.
Figure 15-12. Null Setup and Hold Values of NCS and NWE in Write Cycle
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWE0, NWE1
NCS
D[15:0]
NWESETUP NWEPULSE NWEPULSE
NCSWRSETUP NCSWRPULSE NCSWRPULSE
NWECYCLE NWECYCLE NWECYCLE
•Null pulse
Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads
to unpredictable behavior.
15.6.4.5 Write mode
The Write Mode bit in the MODE register (MODE.WRITEMODE) of the corresponding chip
select indicates which signal controls the write operation.
•Write is controlled by NWE (MODE.WRITEMODE = 1)
Figure 15-13 on page 191 shows the waveforms of a write operation with MODE.WRITEMODE
equal to one. The data is put on the bus during the pulse and hold steps of the NWE signal. The
internal data buffers are turned out after the NWESETUP time, and until the end of the write
cycle, regardless of the programmed waveform on NCS.
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Figure 15-13. WRITEMODE = 1. The Write Operation Is Controlled by NWE
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWR0, NWR1
NCS
D[15:0]
•Write is controlled by NCS (MODE.WRITEMODE = 0)
Figure 15-14 on page 191 shows the waveforms of a write operation with MODE.WRITEMODE
written to zero. The data is put on the bus during the pulse and hold steps of the NCS signal.
The internal data buffers are turned out after the NCSWRSETUP time, and until the end of the
write cycle, regardless of the programmed waveform on NWE.
Figure 15-14. WRITEMODE = 0. The Write Operation Is Controlled by NCS
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWR0, NWR1
NCS
D[15:0]
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15.6.4.6 Coding timing parameters
All timing parameters are defined for one chip select and are grouped together in one register
according to their type.
The Setup register (SETUP) groups the definition of all setup parameters:
• NRDSETUP, NCSRDSETUP, NWESETUP, and NCSWRSETUP.
The Pulse register (PULSE) groups the definition of all pulse parameters:
• NRDPULSE, NCSRDPULSE, NWEPULSE, and NCSWRPULSE.
The Cycle register (CYCLE) groups the definition of all cycle parameters:
• NRDCYCLE, NWECYCLE.
Table 15-4 on page 192 shows how the timing parameters are coded and their permitted range.
Table 15-4. Coding and Range of Timing Parameters
Permitted Range
Coded Value Number of Bits Effective Value Coded Value Effective Value
0 ≤ value ≤ 31 0 ≤ value ≤ 31
setup [5:0] 6 128 x setup[5] + setup[4:0]
32 ≤ value ≤ 63 128 ≤ value ≤ 128+31
0 ≤ value ≤ 63 0 ≤ value ≤ 63
pulse [6:0] 7 256 x pulse[6] + pulse[5:0]
64≤ value ≤ 127 256 ≤ value ≤ 256+63
0 ≤ value ≤ 127 0 ≤ value ≤ 127
128 ≤ value ≤ 255 256 ≤ value ≤ 256+127
cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0]
256 ≤ value ≤ 383 512 ≤ value ≤ 512+127
384 ≤ value ≤ 511 768 ≤ value ≤ 768+127
15.6.4.7 Usage restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP
and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpre-
dictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the
memory interface because of the propagation delay of theses signals through external logic and
pads. If positive setup and hold values must be verified, then it is strictly recommended to pro-
gram non-null values so as to cover possible skews between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address,
byte select lines, and NCS signal after the rising edge of NWE. This is true if the MODE.WRITE-
MODE bit is written to one. See Section 15.6.5.2.
For read and write operations: a null value for pulse parameters is forbidden and may lead to
unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the
address bus. For external devices that require setup and hold time between NCS and NRD sig-
nals (read), or between NCS and NWE signals (write), these setup and hold times must be
converted into setup and hold times in reference to the address bus.
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15.6.5 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
15.6.5.1 Chip select wait states
The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the deactivation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to
NWR3, NCS[0..5], NRD lines are all set to high level.
Figure 15-15 on page 193 illustrates a chip select wait state between access on Chip Select 0
(NCS0) and Chip Select 2 (NCS2).
Figure 15-15. Chip Select Wait State Between a Read Access on NCS0 and a Write Access on
NCS2
CLK_SMC
_MSB:2]
, NBS1,
, A1
NRD
NWE
NCS0
NCS2
NRDCYCLE NWECYCLE
D[15:0]
Read to Write Chip Select
Wait State Wait State
15.6.5.2 Early read wait state
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
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An early read wait state is automatically inserted if at least one of the following conditions is
valid:
• if the write controlling signal has no hold time and the read controlling signal has no setup
time (Figure 15-16 on page 194).
• in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the
NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode
(Figure 15-17 on page 195). The write operation must end with a NCS rising edge. Without
an early read wait state, the write operation could not complete properly.
• in NWE controlled mode (MODE.WRITEMODE = 1) and if there is no hold timing
(NWEHOLD = 0), the feedback of the write control signal is used to control address, data,
chip select, and byte select lines. If the external write control signal is not inactivated as
expected due to load capacitances, an early read wait state is inserted and address, data
and control signals are maintained one more cycle. See Figure 15-18 on page 196.
Figure 15-16. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NRD
No hold
No setup
D[15:0]
Write cycle Read cycle
Early Read
Wait state
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Figure 15-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read
with No Setup.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NRD
No hold No setup
D[15:0]
Write cycle Early Read Read cycle
(WRITEMODE=0) Wait State (READMODE=0 or READMODE=1)
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Figure 15-18. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read
with one Set-up Cycle.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Internal write controlling signal
external write controlling
signal(NWE)
No hold Read setup=1
NRD
D[15:0]
Write cycle Early Read Read cycle
(WRITEMODE = 1) Wait State (READMODE=0 or READMODE=1)
15.6.5.3 Reload user configuration wait state
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC
inserts a wait state before starting the next access. The so called “reload user configuration wait
state” is used by the SMC to load the new set of parameters to apply to next accesses.
The reload configuration wait state is not applied in addition to the chip select wait state. If
accesses before and after reprogramming the user interface are made to different devices (dif-
ferent chip selects), then one single chip select wait state is applied.
On the other hand, if accesses before and after writing the user interface are made to the same
device, a reload configuration wait state is inserted, even if the change does not concern the cur-
rent chip select.
•User procedure
To insert a reload configuration wait state, the SMC detects a write access to any MODE register
of the user interface. If the user only modifies timing registers (SETUP, PULSE, CYCLE regis-
ters) in the user interface, he must validate the modification by writing the MODE register, even
if no change was made on the mode parameters.
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•Slow clock mode transition
A reload configuration wait state is also inserted when the slow clock mode is entered or exited,
after the end of the current transfer (see Section 15.6.8).
15.6.5.4 Read to write wait state
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and
write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states
when they are to be inserted. See Figure 15-15 on page 193.
15.6.6 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to
add wait states (data float wait states) after a read access:
• before starting a read access to a different external memory.
• before starting a write access to the same device or to a different external one.
The Data Float Output Time (tDF) for each external memory device is programmed in the Data
Float Time field of the MODE register (MODE.TDFCYCLES) for the corresponding chip select.
The value of MODE.TDFCYCLES indicates the number of data float wait cycles (between 0 and
15) before the external device releases the bus, and represents the time allowed for the data
output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long t DF will not slow down the execution of a program from internal
memory.
The data float wait states management depends on the MODE.READMODE bit and the TDF
Optimization bit of the MODE register (MODE.TDFMODE) for the corresponding chip select.
15.6.6.1 Read mode
Writing a one to the MODE.READMODE bit indicates to the SMC that the NRD signal is respon-
sible for turning off the tri-state buffers of the external memory device. The data float period then
begins after the rising edge of the NRD signal and lasts MODE.TDFCYCLES cycles of the
CLK_SMC clock.
When the read operation is controlled by the NCS signal (MODE.READMODE = 0), the
MODE.TDFCYCLES field gives the number of CLK_SMC cycles during which the data bus
remains busy after the rising edge of NCS.
Figure 15-19 on page 198 illustrates the data float period in NRD-controlled mode
(MODE.READMODE =1), assuming a data float period of two cycles (MODE.TDFCYCLES = 2).
Figure 15-20 on page 198 shows the read operation when controlled by NCS (MODE.READ-
MODE = 0) and the MODE.TDFCYCLES field equals to three.
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Figure 15-19. TDF Period in NRD Controlled Read Access (TDFCYCLES = 2)
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
tPACC
D[15:0]
TDF = 2 clock cycles
NRD controlled read operation
Figure 15-20. TDF Period in NCS Controlled Read Operation (TDFCYCLES = 3)
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
tPACC
D[15:0]
TDF = 3 clock cycles
NCS controlled read operation
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15.6.6.2 TDF optimization enabled (MODE.TDFMODE = 1)
When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to
insert.
Figure 15-21 on page 199 shows a read access controlled by NRD, followed by a write access
controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRDHOLD = 4; READMODE = 1 (NRD controlled)
NWESETUP = 3; WRITEMODE = 1 (NWE controlled)
TDFCYCLES = 6; TDFMODE = 1 (optimization enabled).
Figure 15-21. TDF Optimization: No TDF Wait States Are Inserted if the TDF Period Is over when the Next Access Begins
CLK_SMC
A[AD_MSB:2]
NRD
NRDHOLD = 4
NWE
NWESETUP = 3
NCS0
TDFCYCLES = 6
D[15:0]
Read access on NCS0 (NRD controlled) Write access on NCS0 (NWE controlled)
Read to Write
Wait State
15.6.6.3 TDF optimization disabled (MODE.TDFMODE = 0)
When optimization is disabled, data float wait states are inserted at the end of the read transfer,
so that the data float period is ended when the second access begins. If the hold period of the
read1 controlling signal overlaps the data float period, no additional data float wait states will be
inserted.
Figure 15-22 on page 200, Figure 15-23 on page 200 and Figure 15-24 on page 201 illustrate
the cases:
• read access followed by a read access on another chip select.
• read access followed by a write access on another chip select.
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• read access followed by a write access on the same chip select.
with no TDF optimization.
Figure 15-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Dif-
ferent Chip Selects.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD) Read1 hold = 1 Read2 setup = 1
Read2 controlling
signal(NRD) TDFCYCLES = 6
D[15:0]
5 TDF WAIT STATES
Read1 cycle Read 2 cycle
TDFCYCLES = 6 TDFMODE=0
(optimization disabled)
Chip Select Wait State
Figure 15-23. TDF Optimization Disabled (MODE.TDFMODE= 0). TDF Wait States between a Read and a Write Access
on Different Chip Selects.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Read1 hold = 1 Write2 setup = 1
Write2 controlling
signal(NWE) TDFCYCLES = 4
D[15:0]
2 TDF WAIT STATES Write 2 cycle
Read1 cycle
TDFCYCLES = 4 TDFMODE=0
Read to Write Chip Select (optimization disabled)
Wait State Wait State
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Figure 15-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on
the Same Chip Select.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Read1 hold = 1 Write2 setup = 1
Write2 controlling
signal(NWE) TDFCYCLES = 5
D[15:0]
4 TDF WAIT STATES
Read1 cycle
TDFCYCLES = 5 Write 2 cycle
Read to Write TDFMODE=0
Wait State (optimization disabled)
15.6.7 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The External Wait Mode field of the MODE register (MODE.EXNWMODE) on the corresponding
chip select must be written to either two (frozen mode) or three (ready mode). When the
MODE.EXNWMODE field is written to zero (disabled), the NWAIT signal is simply ignored on
the corresponding chip select. The NWAIT signal delays the read or write operation in regards to
the read or write controlling signal, depending on the read and write modes of the corresponding
chip select.
15.6.7.1 Restriction
When one of the MODE.EXNWMODE is enabled, it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in
Page Mode (Section 15.6.9), or in Slow Clock Mode (Section 15.6.8).
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
15.6.7.2 Frozen mode
When the external device asserts the NWAIT signal (active low), and after internal synchroniza-
tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control
signals remain unchanged. When the synchronized NWAIT signal is deasserted, the SMC com-
pletes the access, resuming the access from the point where it was stopped. See Figure 15-25
on page 202. This mode must be selected when the external device uses the NWAIT signal to
delay the access and to freeze the SMC.
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The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure
15-26 on page 203.
Figure 15-25. Write Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
FROZEN STATE
4 3 2 1 1 1 1 0
NWE
6 5 4 3 2 2 2 2 0
NCS
D[15:0]
NWAIT
Internally synchronized
NWAIT signal
Write cycle
EXNWMODE = 2 (Frozen)
WRITEMODE = 1 (NWE controlled)
NWEPULSE = 5
NCSWRPULSE = 7
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Figure 15-26. Read Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
FROZEN STATE
4 3 2 2 2 1 0
NCS 2 1 0
1 0
NRD 5 5 5 4 3 2 1 0
NWAIT
Internally synchronized
NWAIT signal
Read cycle
EXNWMODE = 2 (Frozen)
READMODE = 0 (NCS controlled)
Assertion is ignored
NRDPULSE = 2, NRDHOLD = 6
NCSRDPULSE = 5, NCSRDHOLD = 3
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15.6.7.3 Ready mode
In Ready mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC
begins the access by down counting the setup and pulse counters of the read/write controlling
signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 15-27 on page 204 and Figure
15-28 on page 205. After deassertion, the access is completed: the hold step of the access is
performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in Fig-
ure 15-28 on page 205.
Figure 15-27. NWAIT Assertion in Write Access: Ready Mode (MODE.EXNWMODE = 3).
CLK_SM C
A [A D _ M S B :2 ]
N B S 0, N B S 1,
A0, A1
FRO ZEN STATE
4 3 2 1 0 0 0
NW E
6 5 4 3 2 1 1 1 0
NCS
D [1 5 :0 ]
N W A IT
In te rn a lly s y n c h ro n iz e d
N W A IT s ig n a l
W rite c y c le
E X N W M O D E = 3 (R e a d y m o d e)
W R IT E M O D E = 1 (N W E _ c o n tro lle d )
NW EPULSE = 5
NCSW RPULSE = 7
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Figure 15-28. NWAIT Assertion in Read Access: Ready Mode (EXNWMODE = 3).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Wait STATE
6 5 4 3 2 1 0 0
NCS
6 5 4 3 2 1 1 0
NRD
NWAIT
Internally synchronized
NWAIT signal
Read cycle
EXNWMODE = 3 (Ready mode)
READMODE = 0 (NCS_controlled)
Assertion is ignored
Assertion is ignored
NRDPULSE = 7
NCSRDPULSE = 7
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15.6.7.4 NWAIT latency and read/write timings
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the two cycles of resynchronization
plus one cycle. Otherwise, the SMC may enter the hold state of the access without detecting the
NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated
on Figure 15-29 on page 206.
When the MODE.EXNWMODE field is enabled (ready or frozen), the user must program a pulse
length of the read and write controlling signal of at least:
minimal pulse length = NWAIT latency + 2 synchronization cycles + 1 cycle
Figure 15-29. NWAIT Latency
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Wait STATE
4 3 2 1 0 0 0
NRD
Minimal pulse length
NWAIT
nternally synchronized NWAIT latency 2 cycle resynchronization
NWAIT signal
Read cycle
EXNWMODE = 2 or 3
READMODE = 1 (NRD controlled)
NRDPULSE = 5
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15.6.8 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the SMC’s Power Management Controller is asserted because
CLK_SMC has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode,
the user-programmed waveforms are ignored and the slow clock mode waveforms are applied.
This mode is provided so as to avoid reprogramming the User Interface with appropriate wave-
forms at very slow clock rate. When activated, the slow mode is active on all chip selects.
15.6.8.1 Slow clock mode waveforms
Figure 15-30 on page 207 illustrates the read and write operations in slow clock mode. They are
valid on all chip selects. Table 15-5 on page 207 indicates the value of read and write parame-
ters in slow clock mode.
Figure 15-30. Read and Write Cycles in Slow Clock Mode
CLK_SMC CLK_SMC
A[AD_MSB:2] A[AD_MSB:2]
NBS0, NBS1, NBS0, NBS1,
A0, A1 A0, A1
NRD
NWE 1 1 1
1 1
NCS
NCS
NRDCYCLES = 2
NWECYCLES = 3
SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ
Table 15-5. Read and Write Timing Parameters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRDSETUP 1 NWESETUP 1
NRDPULSE 1 NWEPULSE 1
NCSRDSETUP 0 NCSWRSETUP 0
NCSRDPULSE 2 NCSWRPULSE 3
NRDCYCLE 2 NWECYCLE 3
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15.6.8.2 Switching from (to) slow clock mode to (from) normal mode
When switching from slow clock mode to the normal mode, the current slow clock mode transfer
is completed at high clock rate, with the set of slow clock mode parameters. See Figure 15-31
on page 208. The external device may not be fast enough to support such timings.
Figure 15-32 on page 209 illustrates the recommended procedure to properly switch from one
mode to the other.
Figure 15-31. Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Slow Clock Mode
Internal signal from PM
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
1 1 1 1 1 1 2 3 2
NCS
NWECYCLE = 3 NWECYCLE = 7
SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE NORMAL MODE WRITE
This write cycle finishes with the slow clock mode set Slow clock mode transition is detected:
of parameters after the clock rate transition Reload Configuration Wait State
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Figure 15-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow
Clock Mode
Slow Clock Mode
Internal signal from PM
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
1 1 1 2 3 2
NCS
SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE
Reload Configuration
Wait State
15.6.9 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the Page Mode
Enabled bit is written to one in the MODE register (MODE.PMEN). The page size must be con-
figured in the Page Size field in the MODE register (MODE.PS) to 4, 8, 16, or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in Table 15-6 on page 209.
With page mode memory devices, the first access to one page (tpa) takes longer than the subse-
quent accesses to the page (tsa) as shown in Figure 15-33 on page 210. When in page mode,
the SMC enables the user to define different read timings for the first access within one page,
and next accesses within the page.
Table 15-6. Page Address and Data Address within a Page
Page Size Page Address(1) Data Address in the Page(2)
4 bytes A[23:2] A[1:0]
8 bytes A[23:3] A[2:0]
16 bytes A[23:4] A[3:0]
32 bytes A[23:5] A[4:0]
Notes: 1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored.
15.6.9.1 Protocol and timings in page mode
Figure 15-33 on page 210 shows the NRD and NCS timings in page mode access.
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Figure 15-33. Page Mode Read Protocol (Address MSB and LSB Are Defined in Table 15-6 on page 209)
CLK_SMC
A[MSB]
A[LSB]
NRD
tpa tsa tsa
NCS
D[15:0]
NCSRDPULSE NRDPULSE NRDPULSE
The NRD and NCS signals are held low during all read transfers, whatever the programmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
PULSE.NCSRDPULSE field value. The pulse length of subsequent accesses within the page
are defined using the PULSE.NRDPULSE field value.
In page mode, the programming of the read timings is described in Table 15-7 on page 210:
Table 15-7. Programming of Read Timings in Page Mode
Parameter Value Definition
READMODE ‘x’ No impact
NCSRDSETUP ‘x’ No impact
NCSRDPULSE tpa Access time of first access to the page
NRDSETUP ‘x’ No impact
NRDPULSE tsa Access time of subsequent accesses in the page
NRDCYCLE ‘x’ No impact
The SMC does not check the coherency of timings. It will always apply the NCSRDPULSE tim-
ings as page access timing (tpa) and the NRDPULSE for accesses to the page (tsa), even if the
programmed value for tpa is shorter than the programmed value for tsa.
15.6.9.2 Byte access type in page mode
The byte access type configuration remains active in page mode. For 16-bit or 32-bit page mode
devices that require byte selection signals, configure the MODE.BAT bit to zero (byte select
access type).
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15.6.9.3 Page mode restriction
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and
the NWAIT signal may lead to unpredictable behavior.
15.6.9.4 Sequential and non-sequential accesses
If the chip select and the MSB of addresses as defined in Table 15-6 on page 209 are identical,
then the current access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed
with a minimum access time (tsa). Figure 15-34 on page 211 illustrates access to an 8-bit mem-
ory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long
access time (tpa). Accesses to D3 and D7, though they are not sequential accesses, only require
a short access time (tsa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same
way, if the chip select is different from the previous access, a page break occurs. If two sequen-
tial accesses are made to the page mode memory, but separated by an other internal or external
peripheral access, a page break occurs on the second access because the chip select of the
device was deasserted between both accesses.
Figure 15-34. Access to Non-sequential Data within the Same Page
CLK_SMC
A[AD_MSB:3] Page address
A[2], A1, A0 A1 A3 A7
NRD
NCS
D[7:0]
D1 D3 D7
NCSRDPULSE NRDPULSE NRDPULSE
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15.7 User Interface
The SMC is programmed using the registers listed in Table 15-8 on page 212. For each chip select, a set of four registers
is used to program the parameters of the external device connected on it. In Table 15-8 on page 212, “CS_number”
denotes the chip select number. Sixteen bytes (0x10) are required per chip select.
The user must complete writing the configuration by writing anyone of the Mode Registers.
Table 15-8. SMC Register Memory Map
Offset Register Register Name Access Reset
0x00 + CS_number*0x10 Setup Register SETUP Read/Write 0x01010101
0x04 + CS_number*0x10 Pulse Register PULSE Read/Write 0x01010101
0x08 + CS_number*0x10 Cycle Register CYCLE Read/Write 0x00030003
0x0C + CS_number*0x10 Mode Register MODE Read/Write 0x10002103
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15.7.1 Setup Register
Register Name: SETUP
Access Type: Read/Write
Offset: 0x00 + CS_number*0x10
Reset Value: 0x01010101
31 30 29 28 27 26 25 24
– – NCSRDSETUP
23 22 21 20 19 18 17 16
– – NRDSETUP
15 14 13 12 11 10 9 8
– – NCSWRSETUP
7 6 5 4 3 2 1 0
– – NWESETUP
• NCSRDSETUP: NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS Setup Length in read access = ( 128 × NCSRDSETUP [ 5 ] + NCSRDSETUP [ 4:0 ] ) clock cycles
• NRDSETUP: NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD Setup Length = ( 128 × NRDSETUP [ 5 ] + NRDSETUP [ 4:0 ] ) clock cycles
• NCSWRSETUP: NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS Setup Length in write access = ( 128 × NCSWRSETUP [ 5 ] + NCSWRSETUP [ 4:0 ] ) clock cycles
• NWESETUP: NWE Setup Length
The NWE signal setup length is defined as:
NWE Setup Length = ( 128 × NWESETUP [ 5 ] + NWESETUP [ 4:0 ] ) clock cycles
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15.7.2 Pulse Register
Register Name: PULSE
Access Type: Read/Write
Offset: 0x04 + CS_number*0x10
Reset Value: 0x01010101
31 30 29 28 27 26 25 24
– NCSRDPULSE
23 22 21 20 19 18 17 16
– NRDPULSE
15 14 13 12 11 10 9 8
– NCSWRPULSE
7 6 5 4 3 2 1 0
– NWEPULSE
• NCSRDPULSE: NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS Pulse Length in read access = ( 256 × NCSRDPULSE [ 6 ] + NCSRDPULSE [ 5:0 ] ) clock cycles
The NCS pulse length must be at least one clock cycle.
In page mode read access, the NCSRDPULSE field defines the duration of the first access to one page.
• NRDPULSE: NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
NRD Pulse Length = ( 256 × NRDPULSE [ 6 ] + NRDPULSE [ 5:0 ] ) clock cycles
The NRD pulse length must be at least one clock cycle.
In page mode read access, the NRDPULSE field defines the duration of the subsequent accesses in the page.
• NCSWRPULSE: NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
NCS Pulse Length in write access = ( 256 × NCSWRPULSE [ 6 ] + NCSWRPULSE [ 5:0 ] ) clock cycles
The NCS pulse length must be at least one clock cycle.
• NWEPULSE: NWE Pulse Length
The NWE signal pulse length is defined as:
NWE Pulse Length = ( 256 × NWEPULSE [ 6 ] + NWEPULSE [ 5:0 ] ) clock cycles
The NWE pulse length must be at least one clock cycle.
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15.7.3 Cycle Register
Register Name: CYCLE
Access Type: Read/Write
Offset: 0x08 + CS_number*0x10
Reset Value: 0x00030003
31 30 29 28 27 26 25 24
– – – – – – – NRDCYCLE[8]
23 22 21 20 19 18 17 16
NRDCYCLE[7:0]
15 14 13 12 11 10 9 8
– – – – – – – NWECYCLE[8]
7 6 5 4 3 2 1 0
NWECYCLE[7:0]
• NRDCYCLE[8:0]: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and
hold steps of the NRD and NCS signals. It is defined as:
Read Cycle Length = ( 256 × NRDCYCLE [ 8:7 ] + NRDCYCLE [ 6:0 ] ) clock cycles
• NWECYCLE[8:0]: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and
hold steps of the NWE and NCS signals. It is defined as:
Write Cycle Length = ( 256 × NWECYCLE [ 8:7 ] + NWECYCLE [ 6:0 ] ) clock cycles
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15.7.4 Mode Register
Register Name: MODE
Access Type: Read/Write
Offset: 0x0C + CS_number*0x10
Reset Value: 0x10002103
31 30 29 28 27 26 25 24
– – PS – – – PMEN
23 22 21 20 19 18 17 16
– – – TDFMODE TDFCYCLES
15 14 13 12 11 10 9 8
– – DBW – – – BAT
7 6 5 4 3 2 1 0
– – EXNWMODE – – WRITEMODE READMODE
• PS: Page Size
If page mode is enabled, this field indicates the size of the page in bytes.
PS Page Size
0 4-byte page
1 8-byte page
2 16-byte page
3 32-byte page
• PMEN: Page Mode Enabled
1: Asynchronous burst read in page mode is applied on the corresponding chip select.
0: Standard read is applied.
• TDFMODE: TDF Optimization
1: TDF optimization is enabled. The number of TDF wait states is optimized using the setup period of the next read/write
access.
0: TDF optimization is disabled.The number of TDF wait states is inserted before the next access begins.
• TDFCYCLES: Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the
read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDFCYCLES period. The external
bus cannot be used by another chip select during TDFCYCLES plus one cycles. From 0 up to 15 TDFCYCLES can be set.
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• DBW: Data Bus Width
DBW Data Bus Width
0 8-bit bus
1 16-bit bus
2 Reserved
3 Reserved
• BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
BAT Byte Access Type
Byte select access type:
0 Write operation is controlled using NCS, NWE, NBS0, NBS1
Read operation is controlled using NCS, NRD, NBS0, NBS1
Byte write access type:
1 Write operation is controlled using NCS, NWR0, NWR1
Read operation is controlled using NCS and NRD
• EXNWMODE: External WAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the
read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for
the read and write controlling signal.
EXNWMODE External NWAIT Mode
Disabled:
0
the NWAIT input signal is ignored on the corresponding chip select.
1 Reserved
Frozen Mode:
2 if asserted, the NWAIT signal freezes the current read or write cycle. after deassertion, the read or write cycle
is resumed from the point where it was stopped.
Ready Mode:
the NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read
3
or write signal, to complete the access. If high, the access normally completes. If low, the access is extended
until NWAIT returns high.
• WRITEMODE: Write Mode
1: The write operation is controlled by the NWE signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be
inserted after the setup of NWE.
0: The write operation is controlled by the NCS signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be
inserted after the setup of NCS.
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• READMODE: Read Mode
READMODE Read Access Mode
The read operation is controlled by the NCS signal.
0 If TDF are programmed, the external bus is marked busy after the rising edge of NCS.
If TDF optimization is enabled (TDFMODE = 1), TDF wait states are inserted after the setup of NCS.
The read operation is controlled by the NRD signal.
1 If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
If TDF optimization is enabled (TDFMODE =1), TDF wait states are inserted after the setup of NRD.
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16. SDRAM Controller (SDRAMC)
Rev: 2.2.0.4
16.1 Features
• 128-Mbytes address space
• Numerous configurations supported
– 2K, 4K, 8K row address memory parts
– SDRAM with two or four internal banks
– SDRAM with 16-bit data path
• Programming facilities
– Word, halfword, byte access
– Automatic page break when memory boundary has been reached
– Multibank ping-pong access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
• Energy-saving capabilities
– Self-refresh, power-down, and deep power-down modes supported
– Supports mobile SDRAM devices
• Error detection
– Refresh error interrupt
• SDRAM power-up initialization by software
• CAS latency of one, two, and three supported
• Auto Precharge command not used
16.2 Overview
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an external 16-bit SDRAM device. The page size supports ranges from 2048 to 8192
and the number of columns from 256 to 2048. It supports byte (8-bit) and halfword (16-bit)
accesses.
The SDRAMC supports a read or write burst length of one location. It keeps track of the active
row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in
one bank and data in the other banks. So as to optimize performance, it is advisable to avoid
accessing different rows in the same bank.
The SDRAMC supports a CAS latency of one, two, or three and optimizes the read access
depending on the frequency.
The different modes available (self refresh, power-down, and deep power-down modes) mini-
mize power consumption on the SDRAM device.
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16.3 Block Diagram
Figure 16-1. SDRAM Controller Block Diagram
SDCK SDCK
SDCKE
SDRAMC SDCKE
C h ip S elect
SDCS
M e m o ry N C S [1]
C o ntro lle r B A [1:0]
A D D R [17:1 6]
SDRAMC
In te rrup t RAS
RAS
CAS
CAS
SDW E
SDW E
P ow e r C L K _S D R A M C SDRAMC
EBI I/O
M a n ag e r D Q M [0 ]
M U X Lo g ic C on trolle r A D D R [0]
D Q M [1 ]
NW E1
S D R A M C _A [9:0]
A D D R [11:2 ]
S D R A M C _ A [10]
SDA10
S D R A M C _ A [1 2:11]
A D D R [13:1 4]
U se r Interfa ce
D [1 5:0 ]
D A T A [15:0]
P e rip h eral B us
16.4 I/O Lines Description
Table 16-1. I/O Lines Description
Name Description Type Active Level
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDCS SDRAM Chip Select Output Low
BA[1:0] Bank Select Signals Output
RAS Row Signal Output Low
CAS Column Signal Output Low
SDWE SDRAM Write Enable Output Low
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Table 16-1. I/O Lines Description
Name Description Type Active Level
DQM[1:0] Data Mask Enable Signals Output High
SDRAMC_A[12:0] Address Bus Output
D[15:0] Data Bus Input/Output
16.5 Application Example
16.5.1 Hardware Interface
Figure 16-2 on page 221 shows an example of SDRAM device connection using a 16-bit data
bus width. It is important to note that this example is given for a direct connection of the devices
to the SDRAMC, without External Bus Interface or I/O Controller multiplexing.
Figure 16-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
D0-D31
RAS 2Mx8 2Mx8
CAS
SDCK D0-D7
SDRAM D8-D15
SDRAM
SDCKE D0-D7 D0-D7
SDWE CS CS
DQM[0-1] CLK CLK
CKE A0-A9 A11 CKE A0-A9 A11
WE SDRAMC_A10 WE
RAS
A10 BA0 A10 SDRAMC_A10
BA0 RAS BA0 BA0
CAS BA1 BA1
BA1 CAS
SDRAM DQM0
DQM
DQM1
DQM
BA1
Controller
SDRAMC_A[0-12]
BA0
BA1
SDCS
16.5.2 Software Interface
The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows
mapping different memory types according to the values set in the SDRAMC Configuration Reg-
ister (CR).
The SDRAMC’s function is to make the SDRAM device access protocol transparent to the user.
Table 16-2 on page 222 to Table 16-4 on page 222 illustrate the SDRAM device memory map-
ping seen by the user in correlation with the device structure. Various configurations are
illustrated.
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16.5.2.1 16-bit memory data bus width
Table 16-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BA[1:0] Row[10:0] Column[7:0] M0
BA[1:0] Row[10:0] Column[8:0] M0
BA[1:0] Row[10:0] Column[9:0] M0
BA[1:0] Row[10:0] Column[10:0] M0
Table 16-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BA[1:0] Row[11:0] Column[7:0] M0
BA[1:0] Row[11:0] Column[8:0] M0
BA[1:0] Row[11:0] Column[9:0] M0
BA[1:0] Row[11:0] Column[10:0] M0
Table 16-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BA[1:0] Row[12:0] Column[7:0] M0
BA[1:0] Row[12:0] Column[8:0] M0
BA[1:0] Row[12:0] Column[9:0] M0
BA[1:0] Row[12:0] Column[10:0] M0
Notes: 1. M0 is the byte address inside a 16-bit halfword.
16.6 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
16.6.1 I/O Lines
The SDRAMC module signals pass through the External Bus Interface (EBI) module where they
are multiplexed. The user must first configure the I/O controller to assign the EBI pins corre-
sponding to SDRAMC signals to their peripheral function. If I/O lines of the EBI corresponding to
SDRAMC signals are not used by the application, they can be used for other purposes by the
I/O Controller.
16.6.2 Power Management
The SDRAMC must be properly stopped before entering in reset mode, i.e., the user must issue
a Deep power mode command in the Mode (MD) register and wait for the command to be
completed.
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16.6.3 Clocks
The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined
state.
16.6.4 Interrupts
The SDRAMC interrupt request line is connected to the interrupt controller. Using the SDRAMC
interrupt requires the interrupt controller to be programmed first.
16.7 Functional Description
16.7.1 SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
1. SDRAM features must be defined in the CR register by writing the following fields with
the desired value: asynchronous timings (TXSR, TRAS, TRCD, TRP, TRC, and TWR),
Number of Columns (NC), Number of Rows (NR), Number of Banks (NB), CAS Latency
(CAS), and the Data Bus Width (DBW).
2. For mobile SDRAM devices, Temperature Compensated Self Refresh (TCSR), Drive
Strength (DS) and Partial Array Self Refresh (PASR) fields must be defined in the Low
Power Register (LPR).
3. The Memory Device Type field must be defined in the Memory Device Register
(MDR.MD).
4. A No Operation (NOP) command must be issued to the SDRAM devices to start the
SDRAM clock. The user must write the value one to the Command Mode field in the
SDRAMC Mode Register (MR.MODE) and perform a write access to any SDRAM
address.
5. A minimum pause of 200µs is provided to precede any signal toggle.
6. An All Banks Precharge command must be issued to the SDRAM devices. The user
must write the value two to the MR.MODE field and perform a write access to any
SDRAM address.
7. Eight Auto Refresh commands are provided. The user must write the value four to the
MR.MODE field and performs a write access to any SDRAM location eight times.
8. A Load Mode Register command must be issued to program the parameters of the
SDRAM devices in its Mode Register, in particular CAS latency, burst type, and burst
length. The user must write the value three to the MR.MODE field and perform a write
access to the SDRAM. The write address must be chosen so that BA[1:0] are set to
zero. See Section 16.8.1 for details about Load Mode Register command.
9. For mobile SDRAM initialization, an Extended Load Mode Register command must be
issued to program the SDRAM devices parameters (TCSR, PASR, DS). The user must
write the value five to the MR.MODE field and perform a write access to the SDRAM.
The write address must be chosen so that BA[1] or BA[0] are equal to one. See Section
16.8.1 for details about Extended Load Mode Register command.
10. The user must go into Normal Mode, writing the value 0 to the MR.MODE field and per-
forming a write access at any location in the SDRAM.
11. Write the refresh rate into the Refresh Timer Count field in the Refresh Timer Register
(TR.COUNT). The refresh rate is the delay between two successive refresh cycles. The
SDRAM device requires a refresh every 15.625µs or 7.81µs. With a 100MHz fre-
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quency, the TR register must be written with the value 1562 (15.625 µs x 100 MHz) or
781 (7.81 µs x 100 MHz).
After initialization, the SDRAM devices are fully functional.
Figure 16-3. SDRAM Device Initialization Sequence
SDCKE
tRP tRC tMRD
SDCK
SDRAMC_A[9:0]
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
DQM
Inputs Stable for Precharge All Banks 1st Auto Refresh 8th Auto Refresh LMR Command Valid Command
200 usec
16.7.2 SDRAM Controller Write Cycle
The SDRAMC allows burst access or single access. In both cases, the SDRAMC keeps track of
the active row in each bank, thus maximizing performance. To initiate a burst access, the
SDRAMC uses the transfer type signal provided by the master requesting the access. If the next
access is a sequential write access, writing to the SDRAM device is carried out. If the next
access is a write-sequential access, but the current access is to a boundary page, or if the next
access is in another row, then the SDRAMC generates a precharge command, activates the
new row and initiates a write command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge and active (tRP) commands and between active
and write (tRCD ) commands. For definition of these timing parameters, refer to the Section
16.8.3. This is described in Figure 16-4 on page 225.
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Figure 16-4. Write Burst, 16-bit SDRAM Access
tRCD = 3
SDCS
SDCK
SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f Col g Col h Col i Col j Col k Col l
RAS
CAS
SDWE
D[15:0] Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl
16.7.3 SDRAM Controller Read Cycle
The SDRAMC allows burst access, incremental burst of unspecified length or single access. In
all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing perfor-
mance of the SDRAM. If row and bank addresses do not match the previous row/bank address,
then the SDRAMC automatically generates a precharge command, activates the new row and
starts the read command. To comply with the SDRAM timing parameters, additional clock cycles
on SDCK are inserted between precharge and active (tRP) commands and between active and
read (tRCD) commands. These two parameters are set in the CR register of the SDRAMC. After a
read command, additional wait states are generated to comply with the CAS latency (one, two,
or three clock delays specified in the CR register).
For a single access or an incremented burst of unspecified length, the SDRAMC anticipates the
next access. While the last value of the column is returned by the SDRAMC on the bus, the
SDRAMC anticipates the read to the next column and thus anticipates the CAS latency. This
reduces the effect of the CAS latency on the internal bus.
For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads
to the best performance. If the burst is broken (border, busy mode, etc.), the next access is han-
dled as an incrementing burst of unspecified length.
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Figure 16-5. Read Burst, 16-bit SDRAM Access
tRCD = 3 CAS = 2
SDCS
SDCK
SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f
RAS
CAS
SDWE
D[15:0] Dnc Dne
Dna Dnb Dnd Dnf
(Input)
16.7.4 Border Management
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAMC generates a precharge command, activates the new row and initiates a read
or write command. To comply with SDRAM timing parameters, an additional clock cycle is
inserted between the precharge and active (tRP) commands and between the active and read
(tRCD) commands. This is described in Figure 16-6 on page 227.
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Figure 16-6. Read Burst with Boundary Row Access
TRP = 3 TRCD = 3 CAS = 2
SDCS
SDCK
Row n
SDRAMC_A[12:0] Col a Col b Col c Col d Row m Col a Col b Col c Col d Col e
RAS
CAS
SDWE
D[15:0] Dna Dnb Dnc Dnd Dma Dmb Dmc Dmd Dme
16.7.5 SDRAM Controller Refresh Cycles
An auto refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto refresh automatically.
The SDRAMC generates these auto refresh commands periodically. An internal timer is loaded
with the value in the Refresh Timer Register (TR) that indicates the number of clock cycles
between successive refresh cycles.
A refresh error interrupt is generated when the previous auto refresh command did not perform.
In this case a Refresh Error Status bit is set in the Interrupt Status Register (ISR.RES). It is
cleared by reading the ISR register.
When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not
delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is
busy and the master is held by a wait signal. See Figure 16-7 on page 228.
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Figure 16-7. Refresh Cycle Followed by a Read Access
tRP = 3 tRC = 8 tRCD = 3 CAS = 2
SDCS
SDCK
Row n
SDRAMC_A[12:0] Col c Col d Row m Col a
RAS
CAS
SDWE
D[15:0] Dma
Dnb Dnc Dnd
(input)
16.7.6 Power Management
Three low power modes are available:
• Self refresh mode: the SDRAM executes its own auto refresh cycles without control of the
SDRAMC. Current drained by the SDRAM is very low.
• Power-down mode: auto refresh cycles are controlled by the SDRAMC. Between auto refresh
cycles, the SDRAM is in power-down. Current drained in power-down mode is higher than in
self refresh mode.
• Deep power-down mode (only available with mobile SDRAM): the SDRAM contents are lost,
but the SDRAM does not drain any current.
The SDRAMC activates one low power mode as soon as the SDRAM device is not selected. It is
possible to delay the entry in self refresh and power-down mode after the last access by config-
uring the Timeout field in the Low Power Register (LPR.TIMEOUT).
16.7.6.1 Self refresh mode
This mode is selected by writing the value one to the Low Power Configuration Bits field in the
SDRAMC Low Power Register (LPR.LPCB). In self refresh mode, the SDRAM device retains
data without external clocking and provides its own internal clocking, thus performing its own
auto refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE,
which remains low. As soon as the SDRAM device is selected, the SDRAMC provides a
sequence of commands and exits self refresh mode.
Some low power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter
or all banks of the SDRAM array. This feature reduces the self refresh current. To configure this
feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR)
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and Drive Strength (DS) parameters must be set by writing the corresponding fields in the LPR
register, and transmitted to the low power SDRAM device during initialization.
After initialization, as soon as the LPR.PASR, LPR.DS, or LPR.TCSR fields are modified and
self refresh mode is activated, the SDRAMC issues an Extended Load Mode Register command
to the SDRAM and the Extended Mode Register of the SDRAM device is accessed automati-
cally. The PASR/DS/TCSR parameters values are therefore updated before entry into self
refresh mode.
The SDRAM device must remain in self refresh mode for a minimum period of tRAS and may
remain in self refresh mode for an indefinite period. This is described in Figure 16-8 on page
229.
Figure 16-8. Self Refresh Mode Behavior
Self Refresh Mode TXSR = 3
SDRAMC_A[12:0] Row
SDCK
SDCKE
SDCS
RAS
CAS
SDWE
Access Request
To the SDRAM Controller
16.7.6.2 Low power mode
This mode is selected by writing the value two to the LPR.LPCB field. Power consumption is
greater than in self refresh mode. All the input and output buffers of the SDRAM device are
deactivated except SDCKE, which remains low. In contrast to self refresh mode, the SDRAM
device cannot remain in low power mode longer than the refresh period (64 ms for a whole
device refresh operation). As no auto refresh operations are performed by the SDRAM itself, the
SDRAMC carries out the refresh operation. The exit procedure is faster than in self refresh
mode.
This is described in Figure 16-9 on page 230.
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Figure 16-9. Low Power Mode Behavior
TRCD = 3 CAS = 2 Low Power Mode
SDCS
SDCK
SDRAMC_A[12:0] Row n Col a Col b Col c Col d Col e Col f
RAS
CAS
SDCKE
D[15:0]
Dna Dnb Dnc Dnd Dne Dnf
(input)
16.7.6.3 Deep power-down mode
This mode is selected by writing the value three to the LPR.LPCB field. When this mode is acti-
vated, all internal voltage generators inside the SDRAM are stopped and all data is lost.
When this mode is enabled, the user must not access to the SDRAM until a new initialization
sequence is done (See Section 16.7.1).
This is described in Figure 16-10 on page 231.
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Figure 16-10. Deep Power-down Mode Behavior
tRP = 3
SDCS
SDCK
Row n
SDRAMC_A[12:0] Col c Col d
RAS
CAS
SDWE
SCKE
D[15:0]
Dnb Dnc Dnd
(Input)
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16.8 User Interface
Table 16-5. SDRAMC Register Memory Map
Offset Register Register Name Access Reset
0x00 Mode Register MR Read/Write 0x00000000
0x04 Refresh Timer Register TR Read/Write 0x00000000
0x08 Configuration Register CR Read/Write 0x852372C0
0x0C High Speed Register HSR Read/Write 0x00000000
0x10 Low Power Register LPR Read/Write 0x00000000
0x14 Interrupt Enable Register IER Write-only 0x00000000
0x18 Interrupt Disable Register IDR Write-only 0x00000000
0x1C Interrupt Mask Register IMR Read-only 0x00000000
0x20 Interrupt Status Register ISR Read-only 0x00000000
0x24 Memory Device Register MDR Read/Write 0x00000000
0xFC Version Register VERSION Read-only - (1)
1. The reset values for these fields are device specific. Please refer to the Module Configuration section at the end of this chap-
ter.
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16.8.1 Mode Register
Register Name: MR
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - MODE
• MODE: Command Mode
This field defines the command issued by the SDRAMC when the SDRAM device is accessed.
MODE Description
0 Normal mode. Any access to the SDRAM is decoded normally.
1 The SDRAMC issues a “NOP” command when the SDRAM device is accessed regardless of the cycle.
The SDRAMC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of
2
the cycle.
The SDRAMC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the
cycle. This command will load the CR.CAS field into the SDRAM device Mode Register. All the other parameters
3
of the SDRAM device Mode Register will be set to zero (burst length, burst type, operating mode, write burst
mode...).
The SDRAMC issues an “Auto Refresh” command when the SDRAM device is accessed regardless of the cycle.
4
Previously, an “All Banks Precharge” command must be issued.
The SDRAMC issues an “Extended Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. This command will load the LPR.PASR, LPR.DS, and LPR.TCR fields into the SDRAM
5
device Extended Mode Register. All the other bits of the SDRAM device Extended Mode Register will be set to
zero.
6 Deep power-down mode. Enters deep power-down mode.
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16.8.2 Refresh Timer Register
Register Name: TR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - COUNT[11:8]
7 6 5 4 3 2 1 0
COUNT[7:0]
• COUNT[11:0]: Refresh Timer Count
This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst
is initiated.
The value to be loaded depends on the SDRAMC clock frequency (CLK_SDRAMC), the refresh rate of the SDRAM device and
the refresh burst length where 15.6µs per row is a typical value for a burst of length one.
To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued
and no refresh of the SDRAM device is carried out.
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16.8.3 Configuration Register
Register Name: CR
Access Type: Read/Write
Offset: 0x08
Reset Value: 0x852372C0
31 30 29 28 27 26 25 24
TXSR TRAS
23 22 21 20 19 18 17 16
TRCD TRP
15 14 13 12 11 10 9 8
TRC TWR
7 6 5 4 3 2 1 0
DBW CAS NB NR NC
• TXSR: Exit Self Refresh to Active Delay
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is between
0 and 15.
• TRAS: Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate command and a Precharge command in number of cycles. Number of cycles is
between 0 and 15.
• TRCD: Row to Column Delay
Reset value is two cycles.
This field defines the delay between an Activate command and a Read/Write command in number of cycles. Number of cycles
is between 0 and 15.
• TRP: Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge command and another command in number of cycles. Number of cycles is
between 0 and 15.
• TRC: Row Cycle Delay
Reset value is seven cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0
and 15.
• TWR: Write Recovery Delay
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
• DBW: Data Bus Width
Reset value is 16 bits.
0: Reserved.
1: Data bus width is 16 bits.
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• CAS: CAS Latency
Reset value is two cycles.
In the SDRAMC, only a CAS latency of one, two and three cycles is managed.
CAS CAS Latency (Cycles)
0 Reserved
1 1
2 2
3 3
• NB: Number of Banks
Reset value is two banks.
NB Number of Banks
0 2
1 4
• NR: Number of Row Bits
Reset value is 11 row bits.
NR Row Bits
0 11
1 12
2 13
3 Reserved
• NC: Number of Column Bits
Reset value is 8 column bits.
NC Column Bits
0 8
1 9
2 10
3 11
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16.8.4 High Speed Register
Register Name: HSR
Access Type: Read/Write
Offset: 0x0C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - DA
• DA: Decode Cycle Enable
A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus.
The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.
1: Decode cycle is enabled.
0: Decode cycle is disabled.
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16.8.5 Low Power Register
Register Name: LPR
Access Type: Read/Write
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - TIMEOUT DS TCSR
7 6 5 4 3 2 1 0
- PASR - - LPCB
• TIMEOUT: Time to Define when Low Power Mode Is Enabled
TIMEOUT Time to Define when Low Power Mode Is Enabled
0 The SDRAMC activates the SDRAM low power mode immediately after the end of the last transfer.
1 The SDRAMC activates the SDRAM low power mode 64 clock cycles after the end of the last transfer.
2 The SDRAMC activates the SDRAM low power mode 128 clock cycles after the end of the last transfer.
3 Reserved.
• DS: Drive Strength (only for low power SDRAM)
This field is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be
set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its DS parameter value is updated before entry in self refresh mode.
• TCSR: Temperature Compensated Self Refresh (only for low power SDRAM)
This field is transmitted to the SDRAM during initialization to set the refresh interval during self refresh mode depending on the
temperature of the low power SDRAM. This parameter must be set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its TCSR parameter value is updated before entry in self refresh mode.
• PASR: Partial Array Self Refresh (only for low power SDRAM)
This field is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the
SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode. This parameter must be set according to the
SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its PASR parameter value is updated before entry in self refresh mode.
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• LPCB: Low Power Configuration Bits
LPCB Low Power Configuration
Low power feature is inhibited: no power-down, self refresh or deep power-down command is issued to
0
the SDRAM device.
The SDRAMC issues a self refresh command to the SDRAM device, the SDCLK clock is deactivated and
1 the SDCKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and
enters it after the access.
The SDRAMC issues a power-down command to the SDRAM device after each access, the SDCKE
2 signal is set to low. The SDRAM device leaves the power-down mode when accessed and enters it after
the access.
The SDRAMC issues a deep power-down command to the SDRAM device. This mode is unique to low-
3
power SDRAM.
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16.8.6 Interrupt Enable Register
Register Name: IER
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - RES
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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16.8.7 Interrupt Disable Register
Register Name: IDR
Access Type: Write-only
Offset: 0x18
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - RES
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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16.8.8 Interrupt Mask Register
Register Name: IMR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - RES
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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16.8.9 Interrupt Status Register
Register Name: ISR
Access Type: Read-only
Offset: 0x20
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - RES
• RES: Refresh Error Status
This bit is set when a refresh error is detected.
This bit is cleared when the register is read.
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16.8.10 Memory Device Register
Register Name: MDR
Access Type: Read/Write
Offset: 0x24
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - MD
• MD: Memory Device Type
MD Device Type
0 SDRAM
1 Low power SDRAM
Other Reserved
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16.8.11 Version Register
Register Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION
7 6 5 4 3 2 1 0
VERSION
• Variant: Variant Number
Reserved. No functionality associated.
• Version: Version Number
Version number of the module.No functionality associated.
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17. Error Corrected Code Controller (ECCHRS)
Rev. 1.0.0.0
17.1 Features
• Hardware Error Corrected Code Generation with two methods :
– Hamming code detection and correction by software (ECC-H)
– Reed-Solomon code detection by hardware, correction by hardware or software (ECC-RS)
• Supports NAND Flash and SmartMedia™ devices with 8- or 16-bit data path for ECC-H, and with
8-bit data path for ECC-RS
• Supports NAND Flash and SmartMedia™ with page sizes of 528, 1056, 2112, and 4224 bytes
(specified by software)
• ECC_H supports :
– One bit correction per page of 512,1024,2048, or 4096 bytes
– One bit correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, or 4096
bytes
– One bit correction per sector of 256 bytes of data for a page size of 512, 1024, 2048, or 4096
bytes
• ECC_RS supports :
– 4 errors correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, and
4096 bytes with 8-bit data path
17.2 Overview
NAND Flash and SmartMedia™ devices contain by default invalid blocks which have one or
more invalid bits. Over the NAND Flash and SmartMedia™ lifetime, additional invalid blocks may
occur which can be detected and corrected by an Error Corrected Code (ECC).
The ECC Controller is a mechanism that encodes data in a manner that makes possible the
identification and correction of certain errors in data. The ECC controller is capable of single-bit
error correction and two-bit random detection when using the Hamming code (ECC-H) and up to
four symbols (a symbol is a 8-bit data) correction whatever the number of errors in symbol (1 to
8 bits of error) when using the Reed-Solomon code (ECC-RS).
When NAND Flash/SmartMedia™ have more than two erroneous bits when using the Hamming
code (ECC-H) or more than four bits in error when using the Reed-Solomon code (ECC-RS), the
data cannot be corrected.
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17.3 Block Diagram
Figure 17-1. ECCHRS Block Diagram
NAND Flash
Rom 1024x10
Encoder RS4 10
Error Evaluator
SmartMedia GF(2 )
Logic
Polynomial
Partial Syndrome Chien Search
process
Static ECC Controller
Memory
Controller Ctrl/ECC 1bit Algorithm
User Interface
HECC
Peripheral Bus
17.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
17.4.1 I/O Lines
The ECCHRS signals pass through the External Bus Interface module (EBI) where they are
multiplexed.
The programmer must first configure the I/O Controller to assign the EBI pins corresponding to
the Static Memory Controller (SMC) signals to their peripheral function. If I/O lines of the EBI corre-
sponding to SMC signals are not used by the application, they can be used for other purposes by
the I/O Controller.
17.4.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the ECCHRS, the ECCHRS will
stop functioning and resume operation after the system wakes up from sleep mode.
17.4.3 Clocks
The clock for the ECCHRS bus interface (CLK_ECCHRS) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the ECCHRS before disabling the clock, to avoid freezing the ECCHRS in an undefined
state.
17.4.4 Interrupts
The ECCHRS interrupt request line is connected to the interrupt controller. Using the ECCHRS
interrupt requires the interrupt controller to be programmed first.
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17.5 Functional Description
A page in NAND Flash and SmartMedia™ memories contains an area for main data and an addi-
tional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page
size corresponds to the number of words in the main area plus the number of words in the extra
area used for redundancy.
Over time, some memory locations may fail to program or erase properly. In order to ensure that
data is stored properly over the life of the NAND Flash device, NAND Flash providers recom-
mend to utilize either one ECC per 256 bytes of data, one ECC per 512 bytes of data, or one
ECC for all of the page. For the next generation of deep micron SLC NAND Flash and with the
new MLC NAND Flash, it is also recommended to ensure at least a four-error ECC per 512
bytes whatever is the page size.
The only configurations required for ECC are the NAND Flash or the SmartMedia™ page size
(528/1056/2112/4224) and the type of correction wanted (one ECC-H for all the page, one ECC-
H per 256 bytes of data, one ECC-H per 512 bytes of data, or four-error ECC-RS per 512 bytes
of data). The page size is configured by writing in the Page Size field in the Mode Register
(MD.PAGESIZE). Type of correction is configured by writing the Type of Correction field in the
Mode Register (MD.TYPECORREC).
The ECC is automatically computed as soon as a read (0x00) or a write (0x80) command to the
NAND Flash or the SmartMedia ™ is detected. Read and write access must start at a page
boundary.
The ECC results are available as soon as the counter reaches the end of the main area. The val-
ues in the Parity Registers (PR0 to PR15) for ECC-H and in the Codeword Parity registers
(CWPS00 to CWPS79) for ECC-RS are then valid and locked until a new start condition occurs
(read/write command followed by address cycles).
17.5.1 Write Access
Once the Flash memory page is written, the computed ECC codes are available in PR0 to PR15
registers for ECC-H and in CWPS00 to CWPS79 registers for ECC-RS. The ECC code values
must be written by the software application in the extra area used for redundancy. The number
of write access in the extra area depends on the value of the MD.TYPECORREC field.
For example, for one ECC per 256 bytes of data for a page of 512 bytes, only the values of PR0
and PR1 must be written by the software application in the extra area. For ECC-RS, a NAND
Flash with page of 512 bytes, the software application will have to write the ten registers
CWPS00 to CWPS09 in the extra area, and would have to write 40 registers (CWPS00 to
CWPS39) for a NAND Flash with page of 2048 bytes.
Other registers are meaningless.
17.5.2 Read Access
After reading the whole data in the main area, the application must perform read accesses to the
extra area where ECC code has been previously stored. Error detection is automatically per-
formed by the ECC-H controller or the ECC-RS controller. In ECC-RS, writing a one to the Halt
of Computation bit in the ECC Mode Register (MD.FREEZE) allows to stop error detection when
software is jumping to the correct parity area.
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Figure 17-2. FREEZE signal waveform
Nand Flash page 2048B Spare Zone
512B 512B 512B 512B
FREEZE
The application can check the ECC Status Registers (SR1/SR2) for any detected errors. It is up
to the application to correct any detected error for ECC-H. The application can correct any
detected error or let the hardware do the correction by writing a one to the Correction Enable bit
in the MD register (MD.CORRS4) for ECC-RS.
ECC computation can detect four different circumstances:
• No error: XOR between the ECC computation and the ECC code stored at the end of the
NAND Flash or SmartMedia™ page is equal to zero. All bits in the SR1 and SR2 registers will
be cleared.
• Recoverable error: Only the Recoverable Error bits in the ECC Status registers
(SR1.RECERRn and/or SR2.RECERRn) are set. The corrupted word offset in the read page
is defined by the Word Address field (WORDADDR) in the PR0 to PR15 registers. The
corrupted bit position in the concerned word is defined in the Bit Address field (BITADDR) in
the PR0 to PR15 registers.
• ECC error: The ECC Error bits in the ECC Status Registers (SR1.ECCERRn /
SR2.ECCERRn) are set. An error has been detected in the ECC code stored in the Flash
memory. The position of the corrupted bit can be found by the application performing an XOR
between the Parity and the NParity contained in the ECC code stored in the Flash memory.
For ECC-RS it is the responsibility of the software to determine where the error is located on
ECC code stored in the spare zone flash area and not on user data area.
• Non correctable error: The Multiple Error bits (MULERRn) in the SR1 and SR2 registers are
set. Several unrecoverable errors have been detected in the Flash memory page.
ECC Status Registers, ECC Parity Registers are cleared when a read/write command is
detected or a software reset is performed.
For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) Hsiao code is used.
24-bit ECC is generated in order to perform one bit correction per 256 or 512 bytes for pages of
512/2048/4096 8-bit words. 32-bit ECC is generated in order to perform one bit correction per
512/1024/2048/4096 8- or 16-bit words.They are generated according to the schemes shown in
Figure 17-3 on page 250 and Figure 17-4 on page 251.
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Figure 17-3. Parity Generation for 512/1024/2048/4096 8-bit Words
1st byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8
P16
2nd byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8'
P32
3rd byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8 PX
P16'
th
4 byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8'
(page size-3)th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8
P16
(page size-2)th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8' PX’
P32'
(page size-1)th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8
P16'
page size th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8'
P1 P1' P1 P1' P1 P1' P1 P1'
P2 P2' P2 P2'
P4 P4'
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1
Page size = 512 Px = 2048 P2=bit7(+)bit6(+)bit3(+)bit2(+)P2
Page size = 1024 Px = 4096 P4=bit7(+)bit6(+)bit5(+)bit4(+)P4
Page size = 2048 Px = 8192 P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'
Page size = 4096 Px = 16384 P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'
P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
Page size = 2n
for i =0 to n
begin
for (j = 0 to page_size_byte)
begin
if(j[i] ==1)
P[2i+3]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]
else
P[2i+3]’=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]'
end
end
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Figure 17-4. Parity Generation for 512/1024/2048/4096 16-bit Words
1st byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8
P16
nd
2 byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8'
P32
3rd byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8 PX
P16'
4th byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8'
(page size-3)th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8
P16
(page size-2)th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8' PX’
P32'
(page size-1)th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8
P16'
page size th byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P8'
P1 P1' P1 P1' P1 P1' P1 P1' P1 P1' P1 P1' P1 P1' P1 P1'
P2 P2' P2 P2' P2 P2' P2 P2'
P4 P4' P4 P4'
P5 P5'
Page size = 512 Px = 2048 P1=bit15(+)bit13(+)bit11(+)bit9(+)bit7(+)bit5(+)bit3(+)bit1(+)P1
Page size = 1024 Px = 4096 P2=bit15(+)bit14(+)bit11(+)bit10(+)bit7(+)bit6(+)bit3(+)bit2(+)P2
Page size = 2048 Px = 8192 P4=bit15(+)bit14(+)bit13(+)bit12(+)bit7(+)bit6(+)bit5(+)bit4(+)P4
Page size = 4096 Px = 16384 P5=bit15(+)bit14(+)bit13(+)bit12(+)bit11(+)bit10(+)bit9(+)bit8(+)P5
To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
Page size = 2n
for i =0 to n
begin
for (j = 0 to page_size_word)
begin
if(j[i] ==1)
P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+)
bit11(+)bit10(+)bit9(+)bit8(+)
bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2n+3]
else
P[2i+3]’=bit15(+)bit14(+)bit13(+)bit12(+)
bit11(+)bit10(+)bit9(+)bit8(+)
bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]'
end
end
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For ECC-RS, in order to perform 4-error correction per 512 bytes of 8-bit words, the codeword
have to be generated by the RS4 Encoder module and stored into the NAND Flash extra area,
according to the scheme shown in Figure 17-5 on page 252
Figure 17-5. RS Codeword Generation
Feedback
α28 α 500 α 397 α 402 α 603 α 395 α 383 α 539
+ DataIn
CW7 + CW6 + CW5 + CW4 + CW3 + CW2 + CW1 + CW0
In read mode, firstly, the detection for any error is done with the partial syndrome module. It is
the responsibility of the ECC-RS Controller to determine after receiving the old codeword stored
in the extra area if there is any error on data and /or on the old codeword. If all syndromes (Si)
are equal to zero, there is no error, otherwise a polynomial representation is written into
CWPS00 to CWPS79 registers. The Partial Syndrome module performs an algorithm according
to the scheme in Figure 17-6 on page 252
Figure 17-6. Partial Syndrome Block Diagram
S7
Mult α i
x S2
x S1
x RegOct S0
DataIn(x)
If the Correction Enable bit is set in the ECC Mode Register (MD.CORRS4) then the polynomial
representation of error are sent to the polynomial processor. The aim of this module is to per-
form the polynomial division in order to calculate two polynomials, Omega (Z) and Lambda (Z),
which are necessary for the two following modules (Chien Search and Error Evaluator). In order
to perform addition, multiplication, and division a Read Only Memory (ROM) has been added
containing the 1024 elements of the Galois field. Both Chien Search and Error Evaluator work in
parallel. The Error Evaluator has the responsibility to determine the Nth error value in the data
and in the old codeword according to the scheme in Figure 17-7 on page 253
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Figure 17-7. Error Evaluator Block Diagram
α -1 α -3 α -4 α-5 α -7
ω0 ω1 ω3 ω4 ω5 ω7
+
ω (α )
-j
Λ odd( α )
-j Rom 1024x10
10 Array - Mult Error value
GF(2 ) inverted
@ position j
ErrorLoc
The Chien Search takes charge of determining if an error has occurred at symbol N according to
the scheme in Figure 17-8 on page 253
Figure 17-8. Chien Search Block Diagram
α-2 α-8 α-1 α-3 α-7
λ 00 λ2 λ8 λ1 λ3 λ7
+ +
Degree of Lambda
+
Λ (α )
-j
Error Located
Not
counter
Flag error Error located Λ odd(α ) -j
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17.6 User Interface
Table 17-1. ECCHRS Register Memory Map
Offset Register Name Access Reset
0x000 Control Register CTRL Write-only 0x00000000
0x004 Mode Register MD Read/write 0x00000000
0x008 Status Register 1 SR1 Read-only 0x00000000
0x00C Parity Register 0 PR0 Read-only 0x00000000
0x010 Parity Register 1 PR1 Read-only 0x00000000
0x014 Status Register 2 SR2 Read-only 0x00000000
0x018 Parity Register 2 PR2 Read-only 0x00000000
0x01C Parity Register 3 PR3 Read-only 0x00000000
0x020 Parity Register 4 PR4 Read-only 0x00000000
0x024 Parity Register 5 PR5 Read-only 0x00000000
0x028 Parity Register 6 PR6 Read-only 0x00000000
0x02C Parity Register 7 PR7 Read-only 0x00000000
0x030 Parity Register 8 PR8 Read-only 0x00000000
0x034 Parity Register 9 PR9 Read-only 0x00000000
0x038 Parity Register 10 PR10 Read-only 0x00000000
0x03C Parity Register 11 PR11 Read-only 0x00000000
0x040 Parity Register 12 PR12 Read-only 0x00000000
0x044 Parity Register 13 PR13 Read-only 0x00000000
0x048 Parity Register 14 PR14 Read-only 0x00000000
0x04C Parity Register 15 PR15 Read-only 0x00000000
Codeword and Syndrome 00 - CWPS00 -
0x050 - 0x18C Read-only 0x00000000
Codeword and Syndrome 79 CWPS79
0x190 - 0x19C MaskData 0 - Mask Data 3 MDATA0 - MDATA3 Read-only 0x00000000
0x1A0 - 0x1AC Address Offset 0 - Address Offset 3 ADOFF0 - ADOFF3 Read-only 0x00000000
0x1B0 Interrupt Enable Register IER Write-only 0x00000000
0x1B4 Interrupt Disable Register IDR Write-only 0x00000000
0x1B8 Interrupt Mask Register MR Read-only 0x00000000
0x1BC Interrupt Status Register ISR Read-only 0x00000000
0x1C0 Interrupt Status Clear Register ISCR Write-only 0x00000000
0x1FC Version Register VERSION Read-only -(1)
Note: 1. The reset value is device specific. Please refer to the Module Configuration section at the end of this chapter.
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17.6.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x000
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - RST
• RST: RESET Parity
Writing a one to this bit will reset the ECC Parity registers.
Writing a zero to this bit has no effect.
This bit always reads as zero.
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17.6.2 Mode Register
Name: MD
Access Type: Read/Write
Offset: 0x004
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - CORRS4 - FREEZE
7 6 5 4 3 2 1 0
- TYPECORREC - PAGESIZE
• CORRS4: Correction Enable
Writing a one to this bit will enable the correction to be done after the Partial Syndrome process and allow interrupt to be sent to
CPU.
Writing a zero to this bit will stop the correction after the Partial Syndrome process.
1: The correction will continue after the Partial Syndrome process.
0: The correction will stop after the Partial Syndrome process.
• FREEZE: Halt of Computation
Writing a one to this bit will stop the computation.
Writing a zero to this bit will allow the computation as soon as read/write command to the NAND Flash or the SmartMedia™ is
detected.
1: The computation will stop until a zero is written to this bit.
0: The computation is allowed.
• TYPECORREC: Type of Correction
ECC code TYPECORREC Description
0b000 One bit correction per page
ECC-H 0b001 One bit correction per sector of 256 bytes
0b010 One bit correction per sector of 512 bytes
ECC-RS 0b100 Four bits correction per sector of 512 bytes
- Others Reserved
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• PAGESIZE: Page Size
This table defines the page size of the NAND Flash device when using the ECC-H code (TYPECORREC = 0b0xx).
Page Size Description
0 528 words
1 1056 words
2 2112 words
3 4224 words
Others Reserved
A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMedia™ memory organization.
This table defines the page size of the NAND Flash device when using the ECC-RS code (TYPECORREC = 0b1xx)
Page Size Description Comment
0 528 bytes 1 page of 512 bytes
1 1056 bytes 2 pages of 512 bytes
2 1584 bytes 3 pages of 512 bytes
3 2112 bytes 4 pages of 512 bytes
4 2640 bytes 5 pages of 512 bytes
5 3168 bytes 6 pages of 512 bytes
6 3696 bytes 7 pages of 512 bytes
7 4224 bytes 8 pages of 512 bytes
i.e.: for NAND Flash device with page size of 4096 bytes and 128 bytes extra area ECC-RS can manage any sub page of
512 bytes up to 8.
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17.6.3 Status Register 1
Name: SR1
Access Type: Read-only
Offset: 0x008
Reset Value: 0x000000000
MD.TYPECORREC=0b0xx, using ECC-H code
31 30 29 28 27 26 25 24
- MULERR7 ECCERR7 RECERR7 - MULERR6 ECCERR6 RECERR6
23 22 21 20 19 18 17 16
- MULERR5 ECCERR5 RECERR5 - MULERR4 ECCERR4 RECERR4
15 14 13 12 11 10 9 8
- MULERR3 ECCERR3 RECERR3 - MULERR2 ECCERR2 RECERR2
7 6 5 4 3 2 1 0
- MULERR1 ECCERR1 RECERR1 - MULERR0 ECCERR0 RECERR0
• MULERRn: Multiple Error in the sector number n of 256/512 bytes in the page
1: Multiple errors are detected.
0: No multiple error is detected.
TYPECORREC Sector Size Comments
0 page size Only MULERR0 is used
1 256 MULERR0 to MULERR7 are used depending on the page size
2 512 MULERR0 to MULERR7 are used depending on the page size
Others Reserved
• ECCERRn: ECC Error in the packet number n of 256/512 bytes in the page
1: A single bit error has occurred.
0: No error have been detected.
TYPECORREC Sector Size Comments
Only ECCERR0 is used
0 page size The user should read PR0 and PR1 to know where the error occurs
in the page.
1 256 ECCERR0 to ECCERR7 are used depending on the page size
2 512 ECCERR0 to ECCERR7 are used depending on the page size
Others Reserved
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• RECERRn: Recoverable Error in the packet number n of 256/512 Bytes in the page
1: Errors detected. If MULERRn is zero, a single correctable error was detected. Otherwise multiple uncorrected errors were
detected.
0: No errors have been detected.
TYPECORREC sector size Comments
0 page size Only RECERR0 is used
1 256 RECERR0 to RECERR7 are used depending on the page size
2 512 RECERR0 to RECERR7 are used depending on the page size
Others Reserved
MD.TYPECORREC=0b1xx, using ECC-RS code
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
SYNVEC
• SYNVEC: Syndrome Vector
After reading a page made of n sector of 512 bytes, this field returns which sector contains error detected after the syndrome
analysis.
The SYNVEC[n] bit is set when there is at least one error in the corresponding sector.
The SYNVEC[n] bit is cleared when a read/write command is detected or a software reset is performed.
1: At least one error has occurred in the corresponding sector.
0: No error has been detected.
Bit Index (n) Sector Boundaries
0 0-511
1 512-1023
2 1023-1535
3 1536-2047
4 2048-2559
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Bit Index (n) Sector Boundaries
5 2560-3071
6 3072-3583
7 3584-4095
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17.6.4 Parity Register 0
Name: PR0
Access Type: Read-only
Offset: 0x00C
Reset Value: 0x00000000
Using ECC-H code, one bit correction per page (MD.TYPECORREC=0b000)
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
WORDADDR[11:4]
7 6 5 4 3 2 1 0
WORDADDR[3:0] BITADDR
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• WORDADDR: Word Address
During a page read, this field contains the word address (8-bit or 16-bit word, depending on the memory plane organization)
where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless.
• BITADDR: Bit Address
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001)
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- NPARITY0[10:4]
15 14 13 12 11 10 9 8
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NPARITY0[3:0] 0 WORDADD0[7:5]
7 6 5 4 3 2 1 0
WORDADD0[4:0] BITADDR0
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITY0: Parity N
Parity calculated by the ECC-H.
• WORDADDR0: Corrupted Word Address in the page between the first byte and the 255th byte
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDR0: Corrupted Bit Address in the page between the first byte and the 255th byte
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
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Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010)
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
NPARITY0[11:4]
15 14 13 12 11 10 9 8
NPARITY0[3:0] WORDADD0[8:5]
7 6 5 4 3 2 1 0
WORDADD0[4:0] BITADDR0
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITY0: Parity N
Parity calculated by the ECC-H.
• WORDADDR0: Corrupted Word Address in the page between the first byte and the 511th byte
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDR0: Corrupted Bit Address in the page between the first byte and the 511th byte
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
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17.6.5 Parity Register 1
Name: PR1
Access Type: Read-only
Offset: 0x010
Reset Value: 0x00000000
Using ECC-H code, one bit correction per page (MD.TYPECORREC=0b000)
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NPARITY[15:8]
7 6 5 4 3 2 1 0
NPARITY[7:0]
• NPARITY: Parity N
During a write, the field of this register must be written in the extra area used for redundancy (for a 512-byte page size:
address 514-515).
Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001)
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- NPARITY1[10:0]
15 14 13 12 11 10 9 8
NPARITY1[3:0] 0 WORDADD1[7:5]
7 6 5 4 3 2 1 0
WORDADD1[4:0] BITADDR1
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Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITY1: Parity N
Parity alculated by the ECC-H.
• WORDADDR1: corrupted Word Address in the page between the 256th and the 511th byte
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDR1: corrupted Bit Address in the page between the 256th and the 511th byte
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010)
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
NPARITY1[11:4]
15 14 13 12 11 10 9 8
NPARITY1[3:0] WORDADD1[8:5]
7 6 5 4 3 2 1 0
WORDADD1[4:0] BITADDR1
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITY1: Parity N
Parity calculated by the ECC-H.
• WORDADDR1: Corrupted Word Address in the page between the 512th and the 1023th byte
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDR1: Corrupted Bit Address in the page between the 512th and the 1023th byte
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
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17.6.6 Status Register 2
Name: SR2
Access Type: Read-only
Offset: 0x014
Reset Value: 0x00000000
MD.TYPECORREC=0b0xx, using ECC-H code
31 30 29 28 27 26 25 24
- MULERR15 ECCERR15 RECERR15 - MULERR14 ECCERR14 RECERR14
23 22 21 20 19 18 17 16
- MULERR13 ECCERR13 RECERR13 - MULERR12 ECCERR12 RECERR12
15 14 13 12 11 10 9 8
- MULERR11 ECCERR11 RECERR11 - MULERR10 ECCERR10 RECERR10
7 6 5 4 3 2 1 0
- MULERR9 ECCERR9 RECERR9 - MULERR8 ECCERR8 RECERR8
• MULERRn: Multiple Error in the sector number n of 256/512 bytes in the page
1: Multiple errors are detected.
0: No multiple error is detected.
TYPECORREC Sector Size Comments
0 page size Only MULERR0 is used
1 256 MULERR0 to MULERR7 are used depending on the page size
2 512 MULERR0 to MULERR7 are used depending on the page size
Others Reserved
• ECCERRn: ECC Error in the packet number n of 256/512 bytes in the page
1: A single bit error has occurred.
0: No error is detected.
TYPECORREC sector size Comments
Only ECCERR0 is used
0 page size The user should read PR0 and PR1 to know where the error occurs
in the page.
1 256 ECCERR0 to ECCERR7 are used depending on the page size
2 512 ECCERR0 to ECCERR7 are used depending on the page size
Others Reserved
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MD.TYPECORREC=0b1xx, using ECC-RS code
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - MULERR RECERR
Only one sub page of 512 bytes is corrected at a time. If several sub page are on error then it is necessary to do several time the
correction process.
• MULERR: Multiple error
This bit is set to one when a multiple error have been detected by the ECC-RS.
This bit is cleared when a read/write command is detected or a software reset is performed.
1: Multiple errors detected: more than four errors.Registers for one ECC for a page of 512/1024/2048/4096 bytes
0: No multiple error detected
• RECERR: Number of recoverable errors if MULERR is zero
RECERR Comments
000 no error
001 one single error detected
010 two errors detected
011 three errors detected
100 four errors detected
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17.6.7 Parity Register 2 - 15
Name: PR2 - PR15
Access Type: Read-only
Offset: 0x018 - 0x04C
Reset Value: 0x00000000
Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001)
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- NPARITYn[10:4]
15 14 13 12 11 10 9 8
NPARITYn[3:0] 0 WORDADDn[7:5]
7 6 5 4 3 2 1 0
WORDADDn[4:0] BITADDRn
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITYn: Parity N
Parity calculated by the ECC-H.
• WORDADDRn: corrupted Word Address in the packet number n of 256 bytes in the page
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDRn: corrupted Bit Address in the packet number n of 256 bytes in the page
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
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Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010)
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
NPARITYn[11:4]
15 14 13 12 11 10 9 8
NPARITYn[3:0] WORDADDn[8:5]
7 6 5 4 3 2 1 0
WORDADDn[4:0] BITADDRn
Once the entire main area of a page is written with data, this register content must be stored to any free location of the spare
area.
Only PR2 to PR7 registers are available in this case.
• NPARITYn: Parity N
Parity calculated by the ECC-H.
• WORDADDRn: corrupted Word Address in the packet number n of 512 bytes in the page
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDRn: corrupted Bit Address in the packet number n of 512 bytes in the page
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
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17.6.8 Codeword 00 - Codeword79
Name: CWPS00 - CWPS79
Access Type: Read-only
Offset: 0x050 - 0x18C
Reset Value: 0x00000000
Page Write:
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
CODEWORD
• CODEWORD:
Once the 512 bytes of a page is written with data, this register content must be stored to any free location of the spare area.
For a page of 512 bytes the entire redundancy words are made of 8 words of 10 bits. All those redundancies words are
concatenated to a word of 80 bits and then cut to 10 words of 8 bits to facilitate their writing in the extra area.
At the end of a page write, this field contains the redundancy word to be stored to the extra area.
Page Read:
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
PARSYND
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• PARSYND:
At the end of a page read, this field contains the Partial Syndrome S.
PARSYND00-PARSYND09: this conclude all the codeword and partial syndrome word for the sub page 1
PARSYND10-PARSYND19: this conclude all the codeword and partial syndrome word for the sub page 2
PARSYND20-PARSYND29: this conclude all the codeword and partial syndrome word for the sub page 3
PARSYND30-PARSYND39: this conclude all the codeword and partial syndrome word for the sub page 4
PARSYND40-PARSYND49: this conclude all the codeword and partial syndrome word for the sub page 5
PARSYND50-PARSYND59: this conclude all the codeword and partial syndrome word for the sub page 6
PARSYND60-PARSYND69: this conclude all the codeword and partial syndrome word for the sub page 7
PARSYND70-PARSYND79: this conclude all the codeword and partial syndrome word for the sub page 8
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17.6.9 Mask Data 0 - Mask Data 3
Name: MDATA0 -MDATA3
Access Type: Read-only
Offset: 0x190 - 0x19C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - MASKDATA[9:8]
7 6 5 4 3 2 1 0
MASKDATA[7:0]
• MASKDATA:
At the end of the correction process, this field contains the mask to be XORed with the data read to perform the final
correction.This XORed is under the responsibility of the software.
This field is meaningless if MD.CORRS4 is zero.
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17.6.10 Address Offset 0 - Address Offset 3
Name: ADOFF0 - ADOFF3
Access Type: Read-only
Offset: 0x1A0 - 0x1AC
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - OFFSET[9:8]
7 6 5 4 3 2 1 0
OFFSET[7:0]
• OFFSET:
At the end of correction process, this field contains the offset address of the data read to be corrected.
This field is meaningless if MD.CORRS4 is zero.
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17.6.11 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x1B0
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - ENDCOR
• ENDCOR:
Writing a zero to this bit has no effect.
Writing a one to this bit will set the corresponding bit in IMR.
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17.6.12 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x1B4
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - ENDCOR
• ENDCOR:
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in IMR.
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17.6.13 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x1B8
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - ENDCOR
• ENDCOR:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is written to one.
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17.6.14 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x1BC
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - ENDCOR
• ENDCOR:
This bit is cleared when the corresponding bit in ISCR is written to one.
This bit is set when a correction process has ended.
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17.6.15 Interrupt Status Clear Register
Name: ISCR
Access Type: Write-only
Offset: 0x1C0
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - ENDCOR
• ENDCOR:
Writing a zero to this bit has no effect
Writing a one to this bit will clear the corresponding bit in ISR and the corresponding interrupt request.
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17.6.16 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0x1FC
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
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17.7 Module Configuration
The specific configuration for the ECCHRS instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 17-2. Module clock name
Module name Clock name
ECCHRS CLK_ECCHRS
Table 17-3. Register Reset Values
Register Reset Value
VERSION 0x00000100
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18. Peripheral DMA Controller (PDCA)
Rev: 1.1.0.1
18.1 Features
• Multiple channels
• Generates transfers between memories and peripherals such as USART and SPI
• Two address pointers/counters per channel allowing double buffering
• Performance monitors to measure average and maximum transfer latency
18.2 Overview
The Peripheral DMA Controller (PDCA) transfers data between on-chip peripheral modules such
as USART, SPI and memories (those memories may be on- and off-chip memories). Using the
PDCA avoids CPU intervention for data transfers, improving the performance of the microcon-
troller. The PDCA can transfer data from memory to a peripheral or from a peripheral to memory.
The PDCA consists of multiple DMA channels. Each channel has:
• A Peripheral Select Register
• A 32-bit memory pointer
• A 16-bit transfer counter
• A 32-bit memory pointer reload value
• A 16-bit transfer counter reload value
The PDCA communicates with the peripheral modules over a set of handshake interfaces. The
peripheral signals the PDCA when it is ready to receive or transmit data. The PDCA acknowl-
edges the request when the transmission has started.
When a transmit buffer is empty or a receive buffer is full, an optional interrupt request can be
generated.
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18.3 Block Diagram
Figure 18-1. PDCA Block Diagram
Peripheral
Memory
0
HSB to PB
HSB Bridge
HSB Peripheral
1
Peripheral Bus
High Speed
Bus Matrix
HSB Peripheral
2
Peripheral DMA
...
Controller
(PDCA)
Interrupt IRQ Peripheral
Controller (n-1)
Handshake Interfaces
18.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
18.4.1 Power Management
If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning
and resume operation after the system wakes up from sleep mode.
18.4.2 Clocks
The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and
one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled in the Power Manager. It is
recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in
an undefined state.
18.4.3 Interrupts
The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA
interrupts requires the interrupt controller to be programmed first.
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18.5 Functional Description
18.5.1 Basic Operation
The PDCA consists of multiple independent PDCA channels, each capable of handling DMA
requests in parallel. Each PDCA channels contains a set of configuration registers which must
be configured to start a DMA transfer.
In this section the steps necessary to configure one PDCA channel is outlined.
The peripheral to transfer data to or from must be configured correctly in the Peripheral Select
Register (PSR). This is performed by writing the Peripheral Identity (PID) value for the corre-
sponding peripheral to the PID field in the PSR register. The PID also encodes the transfer
direction, i.e. memory to peripheral or peripheral to memory. See Section 18.5.5.
The transfer size must be written to the Transfer Size field in the Mode Register (MR.SIZE). The
size must match the data size produced or consumed by the selected peripheral. See Section
18.5.6.
The memory address to transfer to or from, depending on the PSR, must be written to the Mem-
ory Address Register (MAR). For each transfer the memory address is increased by either a
one, two or four, depending on the size set in MR. See Section 18.5.2.
The number of data items to transfer is written to the TCR register. If the PDCA channel is
enabled, a transfer will start immediately after writing a non-zero value to TCR or the reload ver-
sion of TCR, TCRR. After each transfer the TCR value is decreased by one. Both MAR and TCR
can be read while the PDCA channel is active to monitor the DMA progress. See Section 18.5.3.
The channel must be enabled for a transfer to start. A channel is enable by writing a one to the
EN bit in the Control Register (CR).
18.5.2 Memory Pointer
Each channel has a 32-bit Memory Address Register (MAR). This register holds the memory
address for the next transfer to be performed. The register is automatically updated after each
transfer. The address will be increased by either one, two or four depending on the size of the
DMA transfer (byte, halfword or word). The MAR can be read at any time during transfer.
18.5.3 Transfer Counter
Each channel has a 16-bit Transfer Counter Register (TCR). This register must be written with
the number of transfers to be performed. The TCR register should contain the number of data
items to be transferred independently of the transfer size. The TCR can be read at any time dur-
ing transfer to see the number of remaining transfers.
18.5.4 Reload Registers
Both the MAR and the TCR have a reload register, respectively Memory Address Reload Regis-
ter (MARR) and Transfer Counter Reload Register (TCRR). These registers provide the
possibility for the PDCA to work on two memory buffers for each channel. When one buffer has
completed, MAR and TCR will be reloaded with the values in MARR and TCRR. The reload logic
is always enabled and will trigger if the TCR reaches zero while TCRR holds a non-zero value.
After reload, the MARR and TCRR registers are cleared.
If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the
value written in TCRR and MARR.
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18.5.5 Peripheral Selection
The Peripheral Select Register (PSR) decides which peripheral should be connected to the
PDCA channel. A peripheral is selected by writing the corresponding Peripheral Identity (PID) to
the PID field in the PSR register. Writing the PID will both select the direction of the transfer
(memory to peripheral or peripheral to memory), which handshake interface to use, and the
address of the peripheral holding register. Refer to the Peripheral Identity (PID) table in the Mod-
ule Configuration section for the peripheral PID values.
18.5.6 Transfer Size
The transfer size can be set individually for each channel to be either byte, halfword or word (8-
bit, 16-bit or 32-bit respectively). Transfer size is set by writing the desired value to the Transfer
Size field in the Mode Register (MR.SIZE).
When the PDCA moves data between peripherals and memory, data is automatically sized and
aligned. When memory is accessed, the size specified in MR.SIZE and system alignment is
used. When a peripheral register is accessed the data to be transferred is converted to a word
where bit n in the data corresponds to bit n in the peripheral register. If the transfer size is byte or
halfword, bits greater than 8 and16 respectively are set to zero.
Refer to the Module Configuration section for information regarding what peripheral registers are
used for the different peripherals and then to the peripheral specific chapter for information
about the size option available for the different registers.
18.5.7 Enabling and Disabling
Each DMA channel is enabled by writing a one to the Transfer Enable bit in the Control Register
(CR.TEN) and disabled by writing a one to the Transfer Disable bit (CR.TDIS). The current sta-
tus can be read from the Status Register (SR).
While the PDCA channel is enabled all DMA request will be handled as long the TCR and TCRR
is not zero.
18.5.8 Interrupts
Interrupts can be enabled by writing a one to the corresponding bit in the Interrupt Enable Regis-
ter (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable Register
(IDR). The Interrupt Mask Register (IMR) can be read to see whether an interrupt is enabled or
not. The current status of an interrupt source can be read through the Interrupt Status Register
(ISR).
The PDCA has three interrupt sources:
• Reload Counter Zero - The TCRR register is zero.
• Transfer Finished - Both the TCR and TCRR registers are zero.
• Transfer Error - An error has occurred in accessing memory.
18.5.9 Priority
If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are
prioritized by their channel number. Channels with lower numbers have priority over channels
with higher numbers, giving channel zero the highest priority.
18.5.10 Error Handling
If the Memory Address Register (MAR) is set to point to an invalid location in memory, an error
will occur when the PDCA tries to perform a transfer. When an error occurs, the Transfer Error
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bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the
error will be stopped. In order to restart the channel, the user must program the Memory
Address Register to a valid address and then write a one to the Error Clear bit in the Control
Register (CR.ECLR). If the Transfer Error interrupt is enabled, an interrupt request will be gener-
ated when a transfer error occurs.
18.6 Performance Monitors
Up to two performance monitors allow the user to measure the activity and stall cycles for PDCA
transfers. To monitor a PDCA channel, the corresponding channel number must be written to
one of the MON0/1CH fields in the Performance Control Register (PCONTROL) and a one must
be written to the corresponding CH0/1EN bit in the same register.
Due to performance monitor hardware resource sharing, the two monitor channels should NOT
be programmed to monitor the same PDCA channel. This may result in UNDEFINED perfor-
mance monitor behavior.
18.6.1 Measuring mechanisms
Three different parameters can be measured by each channel:
• The number of data transfer cycles since last channel reset, both for read and write
• The number of stall cycles since last channel reset, both for read and write
• The maximum latency since last channel reset, both for read and write
These measurements can be extracted by software and used to generate indicators for bus
latency, bus load, and maximum bus latency.
Each of the counters has a fixed width, and may therefore overflow. When an overflow is
encountered in either the Performance Channel Data Read/Write Cycle registers (PRDATA0/1
and PWDATA0/1) or the Performance Channel Read/Write Stall Cycles registers (PRSTALL0/1
and PWSTALL0/1) of a channel, all registers in the channel are reset. This behavior is altered if
the Channel Overflow Freeze bit is one in the Performance Control register (PCON-
TROL.CH0/1OVF). If this bit is one, the channel registers are frozen when either DATA or
STALL reaches its maximum value. This simplifies one-shot readout of the counter values.
The registers can also be manually reset by writing a one to the Channel Reset bit in the PCON-
TROL register (PCONTROL.CH0/1RES). The Performance Channel Read/Write Latency
registers (PRLAT0/1 and PWLAT0/1) are saturating when their maximum count value is
reached. The PRLAT0/1 and PWLAT0/1 registers can only be reset by writing a one to the cor-
responding reset bit in PCONTROL (PCONTROL.CH0/1RES).
A counter is enabled by writing a one to the Channel Enable bit in the Performance Control Reg-
ister (PCONTROL.CH0/1EN).
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18.7 User Interface
18.7.1 Memory Map Overview
Table 18-1. PDCA Register Memory Map
Address Range Contents
0x000 - 0x03F DMA channel 0 configuration registers
0x040 - 0x07F DMA channel 1 configuration registers
... ...
(0x000 - 0x03F)+m*0x040 DMA channel m configuration registers
0x800-0x830 Performance Monitor registers
0x834 Version register
The channels are mapped as shown in Table 18-1. Each channel has a set of configuration reg-
isters, shown in Table 18-2, where n is the channel number.
18.7.2 Channel Memory Map
Table 18-2. PDCA Channel Configuration Registers
Offset Register Register Name Access Reset
0x000 + n*0x040 Memory Address Register MAR Read/Write 0x00000000
0x004 + n*0x040 Peripheral Select Register PSR Read/Write - (1)
0x008 + n*0x040 Transfer Counter Register TCR Read/Write 0x00000000
0x00C + n*0x040 Memory Address Reload Register MARR Read/Write 0x00000000
0x010 + n*0x040 Transfer Counter Reload Register TCRR Read/Write 0x00000000
0x014 + n*0x040 Control Register CR Write-only 0x00000000
0x018 + n*0x040 Mode Register MR Read/Write 0x00000000
0x01C + n*0x040 Status Register SR Read-only 0x00000000
0x020 + n*0x040 Interrupt Enable Register IER Write-only 0x00000000
0x024 + n*0x040 Interrupt Disable Register IDR Write-only 0x00000000
0x028 + n*0x040 Interrupt Mask Register IMR Read-only 0x00000000
0x02C + n*0x040 Interrupt Status Register ISR Read-only 0x00000000
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the
end of this chapter.
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18.7.3 Performance Monitor Memory Map
Table 18-3. PDCA Performance Monitor Registers(1)
Offset Register Register Name Access Reset
0x800 Performance Control Register PCONTROL Read/Write 0x00000000
0x804 Channel0 Read Data Cycles PRDATA0 Read-only 0x00000000
0x808 Channel0 Read Stall Cycles PRSTALL0 Read-only 0x00000000
0x80C Channel0 Read Max Latency PRLAT0 Read-only 0x00000000
0x810 Channel0 Write Data Cycles PWDATA0 Read-only 0x00000000
0x814 Channel0 Write Stall Cycles PWSTALL0 Read-only 0x00000000
0x818 Channel0 Write Max Latency PWLAT0 Read-only 0x00000000
0x81C Channel1 Read Data Cycles PRDATA1 Read-only 0x00000000
0x820 Channel1 Read Stall Cycles PRSTALL1 Read-only 0x00000000
0x824 Channel1 Read Max Latency PRLAT1 Read-only 0x00000000
0x828 Channel1 Write Data Cycles PWDATA1 Read-only 0x00000000
0x82C Channel1 Write Stall Cycles PWSTALL1 Read-only 0x00000000
0x830 Channel1 Write Max Latency PWLAT1 Read-only 0x00000000
Note: 1. The number of performance monitors is device specific. If the device has only one perfor-
mance monitor, the Channel1 registers are not available. Please refer to the Module
Configuration section at the end of this chapter for the number of performance monitors on this
device.
18.7.4 Version Register Memory Map
Table 18-4. PDCA Version Register Memory Map
Offset Register Register Name Access Reset
0x834 Version Register VERSION Read-only - (1)
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
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18.7.5 Memory Address Register
Name: MAR
Access Type: Read/Write
Offset: 0x000 + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
MADDR[31:24]
23 22 21 20 19 18 17 16
MADDR[23:16]
15 14 13 12 11 10 9 8
MADDR[15:8]
7 6 5 4 3 2 1 0
MADDR[7:0]
• MADDR: Memory Address
Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the
PDCA. During transfer, MADDR will point to the next memory location to be read/written.
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18.7.6 Peripheral Select Register
Name: PSR
Access Type: Read/Write
Offset: 0x004 + n*0x040
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
PID
• PID: Peripheral Identifier
The Peripheral Identifier selects which peripheral should be connected to the DMA channel. Writing a PID will select both which
handshake interface to use, the direction of the transfer and also the address of the Receive/Transfer Holding Register for the
peripheral. See the Module Configuration section of PDCA for details. The width of the PID field is device specific and
dependent on the number of peripheral modules in the device.
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18.7.7 Transfer Counter Register
Name: TCR
Access Type: Read/Write
Offset: 0x008 + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TCV[15:8]
7 6 5 4 3 2 1 0
TCV[7:0]
• TCV: Transfer Counter Value
Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made.
During transfer, TCV contains the number of remaining transfers to be done.
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18.7.8 Memory Address Reload Register
Name: MARR
Access Type: Read/Write
Offset: 0x00C + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
MARV[31:24]
23 22 21 20 19 18 17 16
MARV[23:16]
15 14 13 12 11 10 9 8
MARV[15:8]
7 6 5 4 3 2 1 0
MARV[7:0]
• MARV: Memory Address Reload Value
Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a non-
zero value.
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18.7.9 Transfer Counter Reload Register
Name: TCRR
Access Type: Read/Write
Offset: 0x010 + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TCRV[15:8]
7 6 5 4 3 2 1 0
TCRV[7:0]
• TCRV: Transfer Counter Reload Value
Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value. If TCRV
is zero, no more transfers will be performed for the channel. When TCR is reloaded, the TCRR register is cleared.
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18.7.10 Control Register
Name: CR
Access Type: Write-only
Offset: 0x014 + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - ECLR
7 6 5 4 3 2 1 0
- - - - - - TDIS TEN
• ECLR: Transfer Error Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.TERR). Clearing the SR.TERR bit will allow the
channel to transmit data. The memory address must first be set to point to a valid location.
• TDIS: Transfer Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will disable transfer for the DMA channel.
• TEN: Transfer Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable transfer for the DMA channel.
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18.7.11 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x018 + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - SIZE
• SIZE: Size of Transfer
Table 18-5. Size of Transfer
SIZE Size of Transfer
0 Byte
1 Halfword
2 Word
3 Reserved
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18.7.12 Status Register
Name: SR
Access Type: Read-only
Offset: 0x01C + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - TEN
• TEN: Transfer Enabled
This bit is cleared when the TDIS bit in CR is written to one.
This bit is set when the TEN bit in CR is written to one.
0: Transfer is disabled for the DMA channel.
1: Transfer is enabled for the DMA channel.
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18.7.13 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x020 + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - TERR TRC RCZ
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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18.7.14 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x024 + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - TERR TRC RCZ
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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18.7.15 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x028 + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - TERR TRC RCZ
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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18.7.16 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x02C + n*0x040
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - TERR TRC RCZ
• TERR: Transfer Error
This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR.
This bit is set when one or more transfer errors has occurred since reset or the last write to CR.ECLR.
• TRC: Transfer Complete
This bit is cleared when the TCR and/or the TCRR holds a non-zero value.
This bit is set when both the TCR and the TCRR are zero.
• RCZ: Reload Counter Zero
This bit is cleared when the TCRR holds a non-zero value.
This bit is set when TCRR is zero.
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18.7.17 Performance Control Register
Name: PCONTROL
Access Type: Read/Write
Offset: 0x800
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - MON1CH
23 22 21 20 19 18 17 16
- - MON0CH
15 14 13 12 11 10 9 8
- - - - - - CH1RES CH0RES
7 6 5 4 3 2 1 0
- - CH1OF CH0OF - - CH1EN CH0EN
• MON1CH: Performance Monitor Channel 1
• MON0CH: Performance Monitor Channel 0
The PDCA channel number to monitor with counter n
Due to performance monitor hardware resource sharing, the two performance monitor channels should NOT be programmed to
monitor the same PDCA channel. This may result in UNDEFINED monitor behavior.
• CH1RES: Performance Channel 1 Counter Reset
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in the channel specified in MON1CH.
This bit always reads as zero.
• CH0RES: Performance Channel 0 Counter Reset
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in the channel specified in MON0CH.
This bit always reads as zero.
• CH1OF: Channel 1 Overflow Freeze
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
• CH1OF: Channel 0 Overflow Freeze
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
• CH1EN: Performance Channel 1 Enable
0: Performance channel 1 is disabled.
1: Performance channel 1 is enabled.
• CH0EN: Performance Channel 0 Enable
0: Performance channel 0 is disabled.
1: Performance channel 0 is enabled.
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18.7.18 Performance Channel 0 Read Data Cycles
Name: PRDATA0
Access Type: Read-only
Offset: 0x804
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA: Data Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
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18.7.19 Performance Channel 0 Read Stall Cycles
Name: PRSTALL0
Access Type: Read-only
Offset: 0x808
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
7 6 5 4 3 2 1 0
STALL[7:0]
• STALL: Stall Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
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18.7.20 Performance Channel 0 Read Max Latency
Name: PRLAT0
Access Type: Read/Write
Offset: 0x80C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
LAT[15:8]
7 6 5 4 3 2 1 0
LAT[7:0]
• LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one.
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18.7.21 Performance Channel 0 Write Data Cycles
Name: PWDATA0
Access Type: Read-only
Offset: 0x810
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA: Data Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
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18.7.22 Performance Channel 0 Write Stall Cycles
Name: PWSTALL0
Access Type: Read-only
Offset: 0x814
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
7 6 5 4 3 2 1 0
STALL[7:0]
• STALL: Stall Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
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18.7.23 Performance Channel 0 Write Max Latency
Name: PWLAT0
Access Type: Read/Write
Offset: 0x818
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
LAT[15:8]
7 6 5 4 3 2 1 0
LAT[7:0]
• LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one.
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18.7.24 Performance Channel 1 Read Data Cycles
Name: PRDATA1
Access Type: Read-only
Offset: 0x81C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA: Data Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
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18.7.25 Performance Channel 1 Read Stall Cycles
Name: PRSTALL1
Access Type: Read-only
Offset: 0x820
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
7 6 5 4 3 2 1 0
STALL[7:0]
• STALL: Stall Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
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18.7.26 Performance Channel 1 Read Max Latency
Name: PRLAT1
Access Type: Read/Write
Offset: 0x824
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
LAT[15:8]
7 6 5 4 3 2 1 0
LAT[7:0]
• LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one.
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18.7.27 Performance Channel 1 Write Data Cycles
Name: PWDATA1
Access Type: Read-only
Offset: 0x828
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA: Data Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
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18.7.28 Performance Channel 1 Write Stall Cycles
Name: PWSTALL1
Access Type: Read-only
Offset: 0x82C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
7 6 5 4 3 2 1 0
STALL[7:0]
• STALL: Stall Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
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18.7.29 Performance Channel 1 Write Max Latency
Name: PWLAT1
Access Type: Read/Write
Offset: 0x830
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
LAT[15:8]
7 6 5 4 3 2 1 0
LAT[7:0]
• LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one.
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18.7.30 PDCA Version Register
Name: VERSION
Access Type: Read-only
Offset: 0x834
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
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18.8 Module Configuration
The specific configuration for the PDCA instance is listed in the following tables.
Table 18-6. PDCA Configuration
Features PDCA
Number of channels 8
Table 18-7. Register Reset Values
Register Reset Value
PSRn n
VERSION 0x00000110
18.8.1 DMA Handshake Signals
The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as
observed from the memory, so RX means transfers from peripheral to memory and TX means
from memory to peripheral.
Table 18-8. PDCA Handshake Signals
PID Value Direction Peripheral Instance Peripheral Register
0 RX ADC CDRx
1 RX SSC RHR
2 RX USART0 RHR
3 RX USART1 RHR
4 RX USART2 RHR
5 RX USART3 RHR
6 RX TWIM0 RHR
7 RX TWIM1 RHR
8 RX TWIS0 RHR
9 RX TWIS1 RHR
10 RX SPI0 RDR
11 RX SPI1 RDR
12 TX SSC THR
13 TX USART0 THR
14 TX USART1 THR
15 TX USART2 THR
16 TX USART3 THR
17 TX TWIM0 THR
18 TX TWIM1 THR
19 TX TWIS0 THR
20 TX TWIS1 THR
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Table 18-8. PDCA Handshake Signals
PID Value Direction Peripheral Instance Peripheral Register
21 TX SPI0 TDR
22 TX SPI1 TDR
23 TX ABDAC SDR
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19. DMA Controller (DMACA)
Rev: 2.0.6.6
19.1 Features
• 2 HSB Master Interfaces
• 4 Channels
• Software and Hardware Handshaking Interfaces
– 8 Hardware Handshaking Interfaces
• Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer
• Single-block DMA Transfer
• Multi-block DMA Transfer
– Linked Lists
– Auto-Reloading
– Contiguous Blocks
• DMA Controller is Always the Flow Controller
• Additional Features
– Scatter and Gather Operations
– Channel Locking
– Bus Locking
– FIFO Mode
– Pseudo Fly-by Operation
19.2 Overview
The DMA Controller (DMACA) is an HSB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more System Bus. One channel is
required for each source/destination pair. In the most basic configuration, the DMACA has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two System Bus transfers are required for each DMA data transfer. This is
also known as a dual-access transfer.
The DMACA is programmed via the HSB slave interface.
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19.3 Block Diagram
Figure 19-1. DMA Controller (DMACA) Block Diagram
DMA Controller
HSB Slave irq_dma
HSB Slave Interrupt
CFG
I/F Generator
Channel 1
Channel 0
FIFO
HSB Master
HSB Master
I/F
SRC DST
FSM FSM
19.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
19.4.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with GPIO lines.
The user must first program the GPIO controller to assign the DMACA pins to their peripheral
functions.
19.4.2 Power Management
To prevent bus errors the DMACA operation must be terminated before entering sleep mode.
19.4.3 Clocks
The CLK_DMACA to the DMACA is generated by the Power Manager (PM). Before using the
DMACA, the user must ensure that the DMACA clock is enabled in the power manager.
19.4.4 Interrupts
The DMACA interface has an interrupt line connected to the Interrupt Controller. Handling the
DMACA interrupt requires programming the interrupt controller before configuring the DMACA.
19.4.5 Peripherals
Both the source peripheral and the destination peripheral must be set up correctly prior to the
DMA transfer.
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19.5 Functional Description
19.5.1 Basic Definitions
Source peripheral: Device on a System Bus layer from where the DMACA reads data, which is
then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to
form a channel.
Destination peripheral: Device to which the DMACA writes the stored data from the FIFO (pre-
viously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMA transfer and does not require a
handshaking interface to interact with the DMACA. A peripheral should be assigned as memory
only if it does not insert more than 16 wait states. If more than 16 wait states are required, then
the peripheral should use a handshaking interface (the default if the peripheral is not pro-
grammed to be memory) in order to signal when it is ready to accept or supply data.
Channel: Read/write datapath between a source peripheral on one configured System Bus
layer and a destination peripheral on the same or different System Bus layer that occurs through
the channel FIFO. If the source peripheral is not memory, then a source handshaking interface
is assigned to the channel. If the destination peripheral is not memory, then a destination hand-
shaking interface is assigned to the channel. Source and destination handshaking interfaces can
be assigned dynamically by programming the channel registers.
Master interface: DMACA is a master on the HSB bus reading data from the source and writing
it to the destination over the HSB bus.
Slave interface: The HSB interface over which the DMACA is programmed. The slave interface
in practice could be on the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake
between the DMACA and source or destination peripheral to control the transfer of a single or
burst transaction between them. This interface is used to request, acknowledge, and control a
DMACA transaction. A channel can receive a request through one of three types of handshaking
interface: hardware, software, or peripheral interrupt.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or
burst transaction between the DMACA and the source or destination peripheral.
Software handshaking interface: Uses software registers to control the transfer of a single or
burst transaction between the DMACA and the source or destination peripheral. No special
DMACA handshaking signals are needed on the I/O of the peripheral. This mode is useful for
interfacing an existing peripheral to the DMACA without modifying it.
Peripheral interrupt handshaking interface: A simple use of the hardware handshaking inter-
face. In this mode, the interrupt line from the peripheral is tied to the dma_req input of the
hardware handshaking interface. Other interface signals are ignored.
Flow controller: The device (either the DMACA or source/destination peripheral) that deter-
mines the length of and terminates a DMA block transfer. If the length of a block is known before
enabling the channel, then the DMACA should be programmed as the flow controller. If the
length of a block is not known prior to enabling the channel, the source or destination peripheral
needs to terminate a block transfer. In this mode, the peripheral is the flow controller.
Flow control mode (CFGx.FCMODE): Special mode that only applies when the destination
peripheral is the flow controller. It controls the pre-fetching of data from the source peripheral.
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Transfer hierarchy: Figure 19-2 on page 319 illustrates the hierarchy between DMACA trans-
fers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for
non-memory peripherals. Figure 19-3 on page 319 shows the transfer hierarchy for memory.
Figure 19-2. DMACA Transfer Hierarchy for Non-Memory Peripheral
DMAC Transfer DMA Transfer
Level
Block Transfer
Block Block Block
Level
Burst Burst Burst Single DMA Transaction
Transaction Transaction Transaction Transaction Level
System Bus System Bus System Bus System Bus System Bus
Burst Single Single System Bus
Burst Burst
Transfer Transfer Transfer Transfer Transfer Transfer Level
Figure 19-3. DMACA Transfer Hierarchy for Memory
DMAC Transfer DMA Transfer
Level
Block Transfer
Block Block Block
Level
System Bus System Bus System Bus System Bus
Burst Single System Bus
Burst Burst
Transfer Transfer Transfer Transfer Transfer Level
Block: A block of DMACA data. The amount of data (block length) is determined by the flow
controller. For transfers between the DMACA and memory, a block is broken directly into a
sequence of System Bus bursts and single transfers. For transfers between the DMACA and a
non-memory peripheral, a block is broken into a sequence of DMACA transactions (single and
bursts). These are in turn broken into a sequence of System Bus transfers.
Transaction: A basic unit of a DMACA transfer as determined by either the hardware or soft-
ware handshaking interface. A transaction is only relevant for transfers between the DMACA
and a source or destination peripheral if the source or destination peripheral is a non-memory
device. There are two types of transactions: single and burst.
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– Single transaction: The length of a single transaction is always 1 and is converted
to a single System Bus transfer.
– Burst transaction: The length of a burst transaction is programmed into the
DMACA. The burst transaction is converted into a sequence of System Bus bursts
and single transfers. DMACA executes each burst transfer by performing
incremental bursts that are no longer than the maximum System Bus burst size set.
The burst transaction length is under program control and normally bears some
relationship to the FIFO sizes in the DMACA and in the source and destination
peripherals.
DMA transfer: Software controls the number of blocks in a DMACA transfer. Once the DMA
transfer has completed, then hardware within the DMACA disables the channel and can gener-
ate an interrupt to signal the completion of the DMA transfer. You can then re-program the
channel for a new DMA transfer.
Single-block DMA transfer: Consists of a single block.
Multi-block DMA transfer: A DMA transfer may consist of multiple DMACA blocks. Multi-block
DMA transfers are supported through block chaining (linked list pointers), auto-reloading of
channel registers, and contiguous blocks. The source and destination can independently select
which method to use.
– Linked lists (block chaining) – A linked list pointer (LLP) points to the location in
system memory where the next linked list item (LLI) exists. The LLI is a set of
registers that describe the next block (block descriptor) and an LLP register. The
DMACA fetches the LLI at the beginning of every block when block chaining is
enabled.
– Auto-reloading – The DMACA automatically reloads the channel registers at the
end of each block to the value when the channel was first enabled.
– Contiguous blocks – Where the address between successive blocks is selected to
be a continuation from the end of the previous block.
Scatter: Relevant to destination transfers within a block. The destination System Bus address is
incremented or decremented by a programmed amount -the scatter increment- when a scatter
boundary is reached. The destination System Bus address is incremented or decremented by
the value stored in the destination scatter increment (DSRx.DSI) field, multiplied by the number
of bytes in a single HSB transfer to the destination (decoded value of CTLx.DST_TR_WIDTH)/8.
The number of destination transfers between successive scatter boundaries is programmed into
the Destination Scatter Count (DSC) field of the DSRx register.
Scatter is enabled by writing a ‘1’ to the CTLx.DST_SCATTER_EN bit. The CTLx.DINC field
determines if the address is incremented, decremented or remains fixed when a scatter bound-
ary is reached. If the CTLx.DINC field indicates a fixed-address control throughout a DMA
transfer, then the CTLx.DST_SCATTER_EN bit is ignored, and the scatter feature is automati-
cally disabled.
Gather: Relevant to source transfers within a block. The source System Bus address is incre-
mented or decremented by a programmed amount when a gather boundary is reached. The
number of System Bus transfers between successive gather boundaries is programmed into the
Source Gather Count (SGRx.SGC) field. The source address is incremented or decremented by
the value stored in the source gather increment (SGRx.SGI) field multiplied by the number of
bytes in a single HSB transfer from the source -(decoded value of CTLx.SRC_TR_WIDTH)/8 -
when a gather boundary is reached.
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Gather is enabled by writing a ‘1’ to the CTLx.SRC_GATHER_EN bit. The CTLx.SINC field
determines if the address is incremented, decremented or remains fixed when a gather bound-
ary is reached. If the CTLx.SINC field indicates a fixed-address control throughout a DMA
transfer, then the CTLx.SRC_GATHER_EN bit is ignored and the gather feature is automatically
disabled.
Note: For multi-block transfers, the counters that keep track of the number of transfer left to
reach a gather/scatter boundary are re-initialized to the source gather count (SGRx.SGC) and
destination scatter count (DSRx.DSC), respectively, at the start of each block transfer.
Figure 19-4. Destination Scatter Transfer
System Memory
Scatter Boundary A0 + 0x220
D11
d11
A0 + 0x218
D10
A0 + 0x210
D9
A0 + 0x208
D8 d8
A0 + 0x200
Data Stream
Scatter Increment d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
0 x 080
Scatter Boundary A0 + 0x120
D7
A0 + 0x118 d7
D6
A0 + 0x110
D5
A0 + 0x108 d4
D4
A0 + 0x100
Scatter Increment
0 x 080
Scatter Boundary A0 + 0x020
D3 d3
A0 + 0x018
D2
A0 + 0x010 CTLx.DST_TR_WIDTH = 3'b011 (64bit/8 = 8 bytes)
D1
d0 DSR.DSI = 16
A0 + 0x008
D0 DSR.DSC = 4
A0 DSR.DSI * 8 = 0x80 (Scatter Increment in bytes)
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Figure 19-5. Source Gather Transfer
System Memory
Gather Boundary A0 + 0x38
D11 Gather Increment = 4
d11
A0 + 0x034
D10
A0 + 0x030
D9
A0 + 0x02C Data Stream
D8 d8
A0 + 0x028 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
A0 + 0x020 Gather Boundary A0 + 0x24
D7 d7 Gather Increment = 4
A0 + 0x01C
D6
A0 + 0x018
D5
A0 + 0x014 d4
D4
Gather Boundary A0 + 0x10
D3 d3 Gather Increment = 4
A0 + 0x00C
D2
A0 + 0x008 CTLx.SRC_TR_WIDTH = 3'b010 (32bit/8 = 4 bytes)
D1 d0
A0 + 0x004 SGR.SGI = 1
D0 SGR.SGC = 4
A0
SGR.SGI * 4 = 0x4 (Gather Increment in bytes)
Channel locking: Software can program a channel to keep the HSB master interface by locking
the arbitration for the master bus interface for the duration of a DMA transfer, block, or transac-
tion (single or burst).
Bus locking: Software can program a channel to maintain control of the System Bus bus by
asserting hlock for the duration of a DMA transfer, block, or transaction (single or burst). Chan-
nel locking is asserted for the duration of bus locking at a minimum.
FIFO mode: Special mode to improve bandwidth. When enabled, the channel waits until the
FIFO is less than half full to fetch the data from the source peripheral and waits until the FIFO is
greater than or equal to half full to send data to the destination peripheral. Thus, the channel can
transfer the data using System Bus bursts, eliminating the need to arbitrate for the HSB master
interface for each single System Bus transfer. When this mode is not enabled, the channel only
waits until the FIFO can transmit/accept a single System Bus transfer before requesting the
master bus interface.
Pseudo fly-by operation: Typically, it takes two System Bus cycles to complete a transfer, one
for reading the source and one for writing to the destination. However, when the source and des-
tination peripherals of a DMA transfer are on different System Bus layers, it is possible for the
DMACA to fetch data from the source and store it in the channel FIFO at the same time as the
DMACA extracts data from the channel FIFO and writes it to the destination peripheral. This
activity is known as pseudo fly-by operation. For this to occur, the master interface for both
source and destination layers must win arbitration of their HSB layer. Similarly, the source and
destination peripherals must win ownership of their respective master interfaces.
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19.6 Arbitration for HSB Master Interface
Each DMACA channel has two request lines that request ownership of a particular master bus
interface: channel source and channel destination request lines.
Source and destination arbitrate separately for the bus. Once a source/destination state
machine gains ownership of the master bus interface and the master bus interface has owner-
ship of the HSB bus, then HSB transfers can proceed between the peripheral and the DMACA.
An arbitration scheme decides which of the request lines (2 * DMAH_NUM_CHANNELS) is
granted the particular master bus interface. Each channel has a programmable priority. A
request for the master bus interface can be made at any time, but is granted only after the cur-
rent HSB transfer (burst or single) has completed. Therefore, if the master interface is
transferring data for a lower priority channel and a higher priority channel requests service, then
the master interface will complete the current burst for the lower priority channel before switch-
ing to transfer data for the higher priority channel.
If only one request line is active at the highest priority level, then the request with the highest pri-
ority wins ownership of the HSB master bus interface; it is not necessary for the priority levels to
be unique.
If more than one request is active at the highest requesting priority, then these competing
requests proceed to a second tier of arbitration:
If equal priority requests occur, then the lower-numbered channel is granted.
In other words, if a peripheral request attached to Channel 7 and a peripheral request attached
to Channel 8 have the same priority, then the peripheral attached to Channel 7 is granted first.
19.7 Memory Peripherals
Figure 19-3 on page 319 shows the DMA transfer hierarchy of the DMACA for a memory periph-
eral. There is no handshaking interface with the DMACA, and therefore the memory peripheral
can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately
without waiting for a transaction request. The alternative to not having a transaction-level hand-
shaking interface is to allow the DMACA to attempt System Bus transfers to the peripheral once
the channel is enabled. If the peripheral slave cannot accept these System Bus transfers, it
inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait
states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to
the DMACA that it is ready to transmit/receive data, and then the DMACA can access the
peripheral without the peripheral inserting wait states onto the bus.
19.8 Handshaking Interface
Handshaking interfaces are used at the transaction level to control the flow of single or burst
transactions. The operation of the handshaking interface is different and depends on whether
the peripheral or the DMACA is the flow controller.
The peripheral uses the handshaking interface to indicate to the DMACA that it is ready to trans-
fer/accept data over the System Bus. A non-memory peripheral can request a DMA transfer
through the DMACA using one of two handshaking interfaces:
• Hardware handshaking
• Software handshaking
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Software selects between the hardware or software handshaking interface on a per-channel
basis. Software handshaking is accomplished through memory-mapped registers, while hard-
ware handshaking is accomplished using a dedicated handshaking interface.
19.8.1 Software Handshaking
When the slave peripheral requires the DMACA to perform a DMA transaction, it communicates
this request by sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMA trans-
action. These software registers are used to implement the software handshaking interface.
The HS_SEL_SRC/HS_SEL_DST bit in the CFGx channel configuration register must be set to
enable software handshaking.
When the peripheral is not the flow controller, then the last transaction registers LstSrcReg and
LstDstReg are not used, and the values in these registers are ignored.
19.8.1.1 Burst Transactions
Writing a 1 to the ReqSrcReg[x]/ReqDstReg[x] register is always interpreted as a burst transac-
tion request, where x is the channel number. However, in order for a burst transaction request to
start, software must write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] register.
You can write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] and ReqSrcReg[x]/ReqDstReg[x]
registers in any order, but both registers must be asserted in order to initiate a burst transaction.
Upon completion of the burst transaction, the hardware clears the SglReqSrcReg[x]/SglReqD-
stReg[x] and ReqSrcReg[x]/ReqDstReg[x] registers.
19.8.1.2 Single Transactions
Writing a 1 to the SglReqSrcReg/SglReqDstReg initiates a single transaction. Upon completion
of the single transaction, both the SglReqSrcReg/SglReqDstReg and ReqSrcReg/ReqDstReg
bits are cleared by hardware. Therefore, writing a 1 to the ReqSrcReg/ReqDstReg is ignored
while a single transaction has been initiated, and the requested burst transaction is not serviced.
Again, writing a 1 to the ReqSrcReg/ReqDstReg register is always a burst transaction request.
However, in order for a burst transaction request to start, the corresponding channel bit in the
SglReqSrcReg/SglReqDstReg must be asserted. Therefore, to ensure that a burst transaction is
serviced, you must write a 1 to the ReqSrcReg/ReqDstReg before writing a 1 to the SglReqSr-
cReg/SglReqDstReg register.
Software can poll the relevant channel bit in the SglReqSrcReg/ SglReqDstReg and ReqSr-
cReg/ReqDstReg registers. When both are 0, then either the requested burst or single
transaction has completed. Alternatively, the IntSrcTran or IntDstTran interrupts can be enabled
and unmasked in order to generate an interrupt when the requested source or destination trans-
action has completed.
Note: The transaction-complete interrupts are triggered when both single and burst transactions are
complete. The same transaction-complete interrupt is used for both single and burst transactions.
19.8.2 Hardware Handshaking
There are 8 hardware handshaking interfaces between the DMACA and peripherals. Refer to
the module configuration chapter for the device-specific mapping of these interfaces.
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19.8.2.1 External DMA Request Definition
When an external slave peripheral requires the DMACA to perform DMA transactions, it commu-
nicates its request by asserting the external nDMAREQx signal. This signal is resynchronized to
ensure a proper functionality (see ”External DMA Request Timing” on page 325).
The external nDMAREQx signal should be asserted when the source threshold level is reached.
After resynchronization, the rising edge of dma_req starts the transfer. An external DMAACKx
acknowledge signal is also provided to indicate when the DMA transfer has completed. The
peripheral should de-assert the DMA request signal when DMAACKx is asserted.
The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted
again before a new transaction starts.
For a source FIFO, an active edge should be triggered on nDMAREQx when the source FIFO
exceeds a watermark level. For a destination FIFO, an active edge should be triggered on
nDMAREQx when the destination FIFO drops below the watermark level.
The source transaction length, CTLx.SRC_MSIZE, and destination transaction length,
CTLx.DEST_MSIZE, must be set according to watermark levels on the source/destination
peripherals.
Figure 19-6. External DMA Request Timing
Hclk
DMA Transaction
nDMAREQx
dma_req
DMA Transfers DMA Transfers DMA Transfers
dma_ack
19.9 DMACA Transfer Types
A DMA transfer may consist of single or multi-block transfers. On successive blocks of a multi-
block transfer, the SARx/DARx register in the DMACA is reprogrammed using either of the fol-
lowing methods:
• Block chaining using linked lists
• Auto-reloading
• Contiguous address between blocks
On successive blocks of a multi-block transfer, the CTLx register in the DMACA is re-pro-
grammed using either of the following methods:
• Block chaining using linked lists
• Auto-reloading
When block chaining, using linked lists is the multi-block method of choice, and on successive
blocks, the LLPx register in the DMACA is re-programmed using the following method:
• Block chaining using linked lists
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A block descriptor (LLI) consists of following registers, SARx, DARx, LLPx, CTL. These regis-
ters, along with the CFGx register, are used by the DMACA to set up and describe the block
transfer.
19.9.1 Multi-block Transfers
19.9.1.1 Block Chaining Using Linked Lists
In this case, the DMACA re-programs the channel registers prior to the start of each block by
fetching the block descriptor for that block from system memory. This is known as an LLI update.
DMACA block chaining is supported by using a Linked List Pointer register (LLPx) that stores the
address in memory of the next linked list item. Each LLI (block descriptor) contains the corre-
sponding block descriptor (SARx, DARx, LLPx, CTLx).
To set up block chaining, a sequence of linked lists must be programmed in memory.
The SARx, DARx, LLPx and CTLx registers are fetched from system memory on an LLI update.
The updated contents of the CTLx register are written back to memory on block completion. Fig-
ure 19-7 on page 326 shows how to use chained linked lists in memory to define multi-block
transfers using block chaining.
The Linked List multi-block transfers is initiated by programming LLPx with LLPx(0) (LLI(0) base
address) and CTLx with CTLx.LLP_S_EN and CTLx.LLP_D_EN.
Figure 19-7. Multi-block Transfer Using Linked Lists
System Memory
LLI(0) LLI(1)
CTLx[63..32] CTLx[63..32]
CTLx[31..0] CTLx[31..0]
LLPx(1) LLPx(2)
DARx DARx
SARx SARx LLPx(2)
LLPx(0) LLPx(1)
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Table 19-1. Programming of Transfer Types and Channel Register Update Method (DMACA State Machine Table)
RELOAD RELOAD_ CTLx,
LLP. LLP_S_EN _SR LLP_D_EN DS LLPx SARx DARx
Transfer Type LOC ( ( ( ( Update Update Update Write
=0 CTLx) CFGx) CTLx) CFGx) Method Method Method Back
1) Single Block or
None, user None
last transfer of Yes 0 0 0 0 None (single) No
reprograms (single)
multi-Block
2) Auto Reload
CTLx,LLPx are
multi-block transfer Auto-
Yes 0 0 0 1 reloaded from Contiguous No
with contiguous Reload
initial values.
SAR
3) Auto Reload
CTLx,LLPx are
multi-block transfer Con-
Yes 0 1 0 0 reloaded from Auto-Reload No
with contiguous tiguous
initial values.
DAR
CTLx,LLPx are
4) Auto Reload Auto-
Yes 0 1 0 1 reloaded from Auto-Reload No
multi-block transfer Reload
initial values.
5) Single Block or
None, user None
last transfer of No 0 0 0 0 None (single) Yes
reprograms (single)
multi-block
6) Linked List CTLx,LLPx
multi-block transfer loaded from Linked
No 0 0 1 0 Contiguous Yes
with contiguous next Linked List List
SAR item
7) Linked List CTLx,LLPx
multi-block transfer loaded from Linked
No 0 1 1 0 Auto-Reload Yes
with auto-reload next Linked List List
SAR item
8) Linked List CTLx,LLPx
multi-block transfer loaded from Con-
No 1 0 0 0 Linked List Yes
with contiguous next Linked List tiguous
DAR item
9) Linked List CTLx,LLPx
multi-block transfer loaded from Auto-
No 1 0 0 1 Linked List Yes
with auto-reload next Linked List Reload
DAR item
CTLx,LLPx
10) Linked List loaded from Linked
No 1 0 1 0 Linked List Yes
multi-block transfer next Linked List List
item
19.9.1.2 Auto-reloading of Channel Registers
During auto-reloading, the channel registers are reloaded with their initial values at the comple-
tion of each block and the new values used for the new block. Depending on the row number in
Table 19-1 on page 327, some or all of the SARx, DARx and CTLx channel registers are
reloaded from their initial value at the start of a block transfer.
19.9.1.3 Contiguous Address Between Blocks
In this case, the address between successive blocks is selected to be a continuation from the
end of the previous block. Enabling the source or destination address to be contiguous between
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blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and
CFGx.RELOAD_DS registers (see Figure 19-1 on page 317).
Note: Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is
required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the max-
imum value, use Row 10 of Table 19-1 on page 327 and setup the LLI.SARx address of the
block descriptor to be equal to the end SARx address of the previous block. Similarly, setup the
LLI.DARx address of the block descriptor to be equal to the end DARx address of the previous
block.
19.9.1.4 Suspension of Transfers Between Blocks
At the end of every block transfer, an end of block interrupt is asserted if:
• interrupts are enabled, CTLx.INT_EN = 1
• the channel block interrupt is unmasked, MaskBlock[n] = 0, where n is the channel number.
Note: The block complete interrupt is generated at the completion of the block transfer to the destination.
For rows 6, 8, and 10 of Table 19-1 on page 327, the DMA transfer does not stall between block
transfers. For example, at the end of block N, the DMACA automatically proceeds to block N + 1.
For rows 2, 3, 4, 7, and 9 of Table 19-1 on page 327 (SARx and/or DARx auto-reloaded between
block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted
if the end of block interrupt is enabled and unmasked.
The DMACA does not proceed to the next block transfer until a write to the block interrupt clear
register, ClearBlock[n], is performed by software. This clears the channel block complete
interrupt.
For rows 2, 3, 4, 7, and 9 of Table 19-1 on page 327 (SARx and/or DARx auto-reloaded between
block transfers), the DMA transfer does not stall if either:
• interrupts are disabled, CTLx.INT_EN = 0, or
• the channel block interrupt is masked, MaskBlock[n] = 1, where n is the channel number.
Channel suspension between blocks is used to ensure that the end of block ISR (interrupt ser-
vice routine) of the next-to-last block is serviced before the start of the final block commences.
This ensures that the ISR has cleared the CFGx.RELOAD_SR and/or CFGx.RELOAD_DS bits
b efo re co mp let ion of t he fina l blo ck. Th e r elo ad bit s CFGx .REL OAD _SR a nd /o r
CFGx.RELOAD_DS should be cleared in the ‘end of block ISR’ for the next-to-last block
transfer.
19.9.2 Ending Multi-block Transfers
All multi-block transfers must end as shown in either Row 1 or Row 5 of Table 19-1 on page 327.
At the end of every block transfer, the DMACA samples the row number, and if the DMACA is in
Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA trans-
fer is terminated.
Note: Row 1 and Row 5 are used for single block transfers or terminating multiblock transfers. Ending in
Row 5 state enables status fetch for the last block. Ending in Row 1 state disables status fetch for
the last block.
For rows 2,3 and 4 of Table 19-1 on page 327, (LLPx = 0 and CFGx.RELOAD_SR and/or
CFGx.RELOAD_DS is set), multi-block DMA transfers continue until both the
CFGx.RELOAD_SR and CFGx.RELOAD_DS registers are cleared by software. They should be
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programmed to zero in the end of block interrupt service routine that services the next-to-last
block transfer. This puts the DMACA into Row 1 state.
For rows 6, 8, and 10 (both CFGx.RELOAD_SR and CFGx.RELOAD_DS cleared) the user must
setup the last block descriptor in memory such that both LLI.CTLx.LLP_S_EN and
LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is
non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block
descriptor in memory is zero, then the DMA transfer is terminated in Row 1.
For rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last block
transfer should clear the CFGx.RELOAD_SR and CFGx.RELOAD_DS reload bits. The last
block descriptor in memory should be set up so that both the LLI.CTLx.LLP_S_EN and
LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is
non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block
descriptor in memory is zero, then the DMA transfer is terminated in Row 1.
Note: The only allowed transitions between the rows of Table 19-1 on page 327are from any row into
row 1 or row 5. As already stated, a transition into row 1 or row 5 is used to terminate the DMA
transfer. All other transitions between rows are not allowed. Software must ensure that illegal tran-
sitions between rows do not occur between blocks of a multi-block transfer. For example, if block N
is in row 10 then the only allowed rows for block N + 1 are rows 10, 5 or 1.
19.10 Programming a Channel
Three registers, the LLPx, the CTLx and CFGx, need to be programmed to set up whether single
or multi-block transfers take place, and which type of multi-block transfer is used. The different
transfer types are shown in Table 19-1 on page 327.
The “Update Method” column indicates where the values of SARx, DARx, CTLx, and LLPx are
obtained for the next block transfer when multi-block DMACA transfers are enabled.
Note: In Table 19-1 on page 327, all other combinations of LLPx.LOC = 0, CTLx.LLP_S_EN,
CFGx.RELOAD_SR, CTLx.LLP_D_EN, and CFGx.RELOAD_DS are illegal, and causes indeter-
minate or erroneous behavior.
19.10.1 Programming Examples
19.10.1.1 Single-block Transfer (Row 1)
Row 5 in Table 19-1 on page 327 is also a single block transfer.
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
3. Program the following channel registers:
a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx according to Row 1 as shown in Table 19-1 on page 327.
Program the LLPx register with ‘0’.
d. Write the control information for the DMA transfer in the CTLx register for channel
x. For example, in the register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the TT_FC of the CTLx register.
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– ii. Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_TR_WIDTH field.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS field where source resides.
– Destination master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
e. Write the channel configuration information into the CFGx register for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination requests.
Writing a ‘1’ activates the software handshaking interface to handle
source/destination requests.
– ii. If the hardware handshaking interface is activated for the source or destination
peripheral, assign a handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
4. After the DMACA selected channel has been programmed, enable the channel by writ-
ing a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is
enabled.
5. Source and destination request single and burst DMA transactions to transfer the block
of data (assuming non-memory peripherals). The DMACA acknowledges at the com-
pletion of every transaction (burst and single) in the block and carry out the block
transfer.
6. Once the transfer completes, hardware sets the interrupts and disables the channel. At
this time you can either respond to the Block Complete or Transfer Complete interrupts,
or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to
detect when the transfer is complete.
19.10.1.2 Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as block descriptors) in memory.
Write the control information in the LLI.CTLx register location of the block descriptor for
each LLI in memory (see Figure 19-7 on page 326) for channel x. For example, in the
register, you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flow control device by programming the TT_FC of the CTLx register.
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
3. Write the channel configuration information into the CFGx register for channel x.
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a. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
b. If the hardware handshaking interface is activated for the source or destination
peripheral, assign the handshaking interface to the source and destination periph-
eral. This requires programming the SRC_PER and DEST_PER bits, respectively.
4. Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the
last) are set as shown in Row 10 of Table 19-1 on page 327. The LLI.CTLx register of
the last Linked List Item must be set as described in Row 1 or Row 5 of Table 19-1 on
page 327. Figure 19-9 on page 333 shows a Linked List example with two list items.
5. Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the
last) are non-zero and point to the base address of the next Linked List Item.
6. Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory
point to the start source/destination block address preceding that LLI fetch.
7. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI
entries in memory are cleared.
8. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
9. Program the CTLx, CFGx registers according to Row 10 as shown in Table 19-1 on
page 327.
10. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
11. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
performed.
12. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note: The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers are fetched. The DMACA automati-
cally reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0).
13. Source and destination request single and burst DMA transactions to transfer the block
of data (assuming non-memory peripheral). The DMACA acknowledges at the comple-
tion of every transaction (burst and single) in the block and carry out the block transfer.
Note: Table 19-1 on page 327
14. The DMACA does not wait for the block interrupt to be cleared, but continues fetching
the next LLI from the memory location pointed to by current LLPx register and automat-
ically reprograms the SARx, DARx, LLPx and CTLx channel registers. The DMA
transfer continues until the DMACA determines that the CTLx and LLPx registers at the
end of a block transfer match that described in Row 1 or Row 5 of Table 19-1 on page
327. The DMACA then knows that the previous block transferred was the last block in
the DMA transfer. The DMA transfer might look like that shown in Figure 19-8 on page
332.
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Figure 19-8. Multi-Block with Linked List Address for Source and Destination
Address of Address of
Source Layer Destination Layer
Block 2 Block 2
SAR(2) DAR(2)
Block 1 Block 1
SAR(1) DAR(1)
Block 0 Block 0
SAR(0) DAR(0)
Source Blocks Destination Blocks
If the user needs to execute a DMA transfer where the source and destination address are con-
tiguous but the amount of data to be transferred is greater than the maximum block size
CTLx.BLOCK_TS, then this can be achieved using the type of multi-block transfer as shown in
Figure 19-9 on page 333.
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Figure 19-9. Multi-Block with Linked Address for Source and Destination Blocks are
Contiguous
Address of Address of
Source Layer Destination Layer
Block 2
DAR(3)
Block 2
Block 2
SAR(3) DAR(2)
Block 2 Block 1
SAR(2) DAR(1)
Block 1
Block 0
SAR(1) DAR(0)
Block 0
SAR(0)
Source Blocks Destination Blocks
The DMA transfer flow is shown in Figure 19-11 on page 336.
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Figure 19-10. DMA Transfer Flow for Source and Destination Linked List Address
Channel enabled by
software
LLI Fetch
Hardware reprograms
SARx, DARx, CTLx, LLPx
DMAC block transfer
Source/destination
status fetch
Block Complete interrupt
generated here
Is DMAC in
Row1 of no
DMAC State Machine Table?
DMAC transfer Complete yes
interrupt generated here
Channel Disabled by
hardware
19.10.1.3 Multi-block Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 4)
1. Read the Channel Enable register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
3. Program the following channel registers:
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a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx according to Row 4 as shown in Table 19-1 on page 327.
Program the LLPx register with ‘0’.
d. Write the control information for the DMA transfer in the CTLx register for channel
x. For example, in the register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the TT_FC of the CTLx register.
– ii. Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_TR_WIDTH field.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS field where source resides.
– Destination master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
e. Write the channel configuration information into the CFGx register for channel x.
Ensure that the reload bits, CFGx. RELOAD_SR and CFGx.RELOAD_DS are
enabled.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination requests
for the specific channel. Writing a ‘1’ activates the software handshaking interface to
handle source/destination requests.
– ii. If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
4. After the DMACA selected channel has been programmed, enable the channel by writ-
ing a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is
enabled.
5. Source and destination request single and burst DMACA transactions to transfer the
block of data (assuming non-memory peripherals). The DMACA acknowledges on com-
pletion of each burst/single transaction and carry out the block transfer.
6. When the block transfer has completed, the DMACA reloads the SARx, DARx and
CTLx registers. Hardware sets the Block Complete interrupt. The DMACA then sam-
ples the row number as shown in Table 19-1 on page 327. If the DMACA is in Row 1,
then the DMA transfer has completed. Hardware sets the transfer complete interrupt
and disables the channel. So you can either respond to the Block Complete or Transfer
Complete interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is dis-
abled, to detect when the transfer is complete. If the DMACA is not in Row 1, the next
step is performed.
7. The DMA transfer proceeds as follows:
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
block complete interrupt when the block transfer has completed. It then stalls until
the block complete interrupt is cleared by software. If the next block is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
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should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS
registers. This put the DMACA into Row 1 as shown in Table 19-1 on page 327. If
the next block is not the last block in the DMA transfer, then the reload bits should
remain enabled to keep the DMACA in Row 4.
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
masked (MaskBlock[x] = 1’b0, where x is the channel number), then hardware does
not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers to put the
DMACA into ROW 1 of Table 19-1 on page 327 before the last block of the DMA
transfer has completed. The transfer is similar to that shown in Figure 19-11 on
page 336. The DMA transfer flow is shown in Figure 19-12 on page 337.
Figure 19-11. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
Address of Address of
Source Layer Destination Layer
Block0
Block1
Block2
SAR DAR
BlockN
Source Blocks Destination Blocks
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Figure 19-12. DMA Transfer Flow for Source and Destination Address Auto-reloaded
Channel Enabled by
software
Block Transfer
Reload SARx, DARx, CTLx
Block Complete interrupt
generated here
DMAC transfer Complete
interrupt generated here yes Is DMAC in Row1 of
DMAC State Machine Table?
Channel Disabled by
hardware no
CTLx.INT_EN=1
no
&&
MASKBLOCK[x]=1?
yes
Stall until block complete
interrupt cleared by software
19.10.1.4 Multi-block Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row7)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of linked list items (otherwise known as block descriptors) in memory.
Write the control information in the LLI.CTLx register location of the block descriptor for
each LLI in memory for channel x. For example, in the register you can program the
following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flow control peripheral by programming the TT_FC of the CTLx register.
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
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3. Write the starting source address in the SARx register for channel x.
Note: The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in
memory, although fetched during a LLI fetch, are not used.
4. Write the channel configuration information into the CFGx register for channel x.
a. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface source/destination requests.
b. If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
5. Make sure that the LLI.CTLx register locations of all LLIs in memory (except the last)
are set as shown in Row 7 of Table 19-1 on page 327 while the LLI.CTLx register of the
last Linked List item must be set as described in Row 1 or Row 5 of Table 19-1 on page
327. Figure 19-7 on page 326 shows a Linked List example with two list items.
6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last)
are non-zero and point to the next Linked List Item.
7. Make sure that the LLI.DARx register location of all LLIs in memory point to the start
destination block address proceeding that LLI fetch.
8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in
memory is cleared.
9. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
10. Program the CTLx, CFGx registers according to Row 7 as shown in Table 19-1 on page
327.
11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
performed. Make sure that bit 0 of the DmaCfgReg register is enabled.
13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note: The LLI.SARx, LLI.DARx, LLI. LLPx and LLI.CTLx registers are fetched. The LLI.SARx register
although fetched is not used.
14. Source and destination request single and burst DMACA transactions to transfer the
block of data (assuming non-memory peripherals). DMACA acknowledges at the com-
pletion of every transaction (burst and single) in the block and carry out the block
transfer.
15. Table 19-1 on page 327The DMACA reloads the SARx register from the initial value.
Hardware sets the block complete interrupt. The DMACA samples the row number as
shown in Table 19-1 on page 327. If the DMACA is in Row 1 or 5, then the DMA trans-
fer has completed. Hardware sets the transfer complete interrupt and disables the
channel. You can either respond to the Block Complete or Transfer Complete interrupts,
or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to
detect when the transfer is complete. If the DMACA is not in Row 1 or 5 as shown in
Table 19-1 on page 327 the following steps are performed.
16. The DMA transfer proceeds as follows:
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
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block complete interrupt when the block transfer has completed. It then stalls until
the block complete interrupt is cleared by software. If the next block is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
should clear the CFGx.RELOAD_SR source reload bit. This puts the DMACA into
Row1 as shown in Table 19-1 on page 327. If the next block is not the last block in
the DMA transfer, then the source reload bit should remain enabled to keep the
DMACA in Row 7 as shown in Table 19-1 on page 327.
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
masked (MaskBlock[x] = 1’b0, where x is the channel number) then hardware does
not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case, software must clear the
source reload bit, CFGx.RELOAD_SR, to put the device into Row 1 of Table 19-1
on page 327 before the last block of the DMA transfer has completed.
17. The DMACA fetches the next LLI from memory location pointed to by the current LLPx
register, and automatically reprograms the DARx, CTLx and LLPx channel registers.
Note that the SARx is not re-programmed as the reloaded value is used for the next
DMA block transfer. If the next block is the last block of the DMA transfer then the CTLx
and LLPx registers just fetched from the LLI should match Row 1 or Row 5 of Table 19-
1 on page 327. The DMA transfer might look like that shown in Figure 19-13 on page
339.
Figure 19-13. Multi-Block DMA Transfer with Source Address Auto-reloaded and Linked List
Address of Address of
Source Layer Destination Layer
Block0
DAR(0)
Block1
DAR(1)
SAR Block2
DAR(2)
BlockN
DAR(N)
Source Blocks Destination Blocks
Destination Address
The DMA Transfer flow is shown in Figure 19-14 on page 340.
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Figure 19-14. DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destina-
tion Address
Channel Enabled by
software
LLI Fetch
Hardware reprograms
DARx, CTLx, LLPx
DMAC block transfer
Source/destination status fetch
Reload SARx
Block Complete interrupt
generated here
Is DMAC in
yes Row1 or Row5 of
DMAC Transfer Complete
DMAC State Machine Table?
interrupt generated here
Channel Disabled by
no
hardware
CTLx.INT_EN=1 no
&&
MASKBLOCK[X]=1 ?
yes
Stall until block interrupt
Cleared by hardware
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19.10.1.5 Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing
a ‘1’ to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
3. Program the following channel registers:
a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx according to Row 3 as shown in Table 19-1 on page 327.
Program the LLPx register with ‘0’.
d. Write the control information for the DMA transfer in the CTLx register for channel
x. For example, in this register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the TT_FC of the CTLx register.
– ii. Set up the transfer characteristics, such as:
– Transfer width for the source in the SRC_TR_WIDTH field.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS field where source resides.
– Destination master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
e. Write the channel configuration information into the CFGx register for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination requests
for the specific channel. Writing a ‘1’ activates the software handshaking interface to
handle source/destination requests.
– ii. If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
4. After the DMACA channel has been programmed, enable the channel by writing a ‘1’ to
the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is enabled.
5. Source and destination request single and burst DMACA transactions to transfer the
block of data (assuming non-memory peripherals). The DMACA acknowledges at the
completion of every transaction (burst and single) in the block and carries out the block
transfer.
6. When the block transfer has completed, the DMACA reloads the SARx register. The
DARx register remains unchanged. Hardware sets the block complete interrupt. The
DMACA then samples the row number as shown in Table 19-1 on page 327. If the
DMACA is in Row 1, then the DMA transfer has completed. Hardware sets the transfer
complete interrupt and disables the channel. So you can either respond to the Block
Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEn-
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Reg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete.
If the DMACA is not in Row 1, the next step is performed.
7. The DMA transfer proceeds as follows:
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
block complete interrupt when the block transfer has completed. It then stalls until
the block complete interrupt is cleared by software. If the next block is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
should clear the source reload bit, CFGx.RELOAD_SR. This puts the DMACA into
Row1 as shown in Table 19-1 on page 327. If the next block is not the last block in
the DMA transfer then the source reload bit should remain enabled to keep the
DMACA in Row3 as shown in Table 19-1 on page 327.
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
masked (MaskBlock[x] = 1’b0, where x is the channel number) then hardware does
not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
source reload bit, CFGx.RELOAD_SR, to put the device into ROW 1 of Table 19-1
on page 327 before the last block of the DMA transfer has completed.
The transfer is similar to that shown in Figure 19-15 on page 342.
The DMA Transfer flow is shown in Figure 19-16 on page 343.
Figure 19-15. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Desti-
nation Address
Address of Address of
Source Layer Destination Layer
Block2
DAR(2)
Block1
DAR(1)
Block0
SAR
DAR(0)
Source Blocks Destination Blocks
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Figure 19-16. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination
Address
Channel Enabled by
software
Block Transfer
Reload SARx, CTLx
Block Complete interrupt
generated here
DMAC Transfer Complete
interrupt generated here yes Is DMAC in Row1 of
DMAC State Machine Table?
Channel Disabled by no
hardware
CTLx.INT_EN=1
no
&&
MASKBLOCK[x]=1?
yes
Stall until Block Complete
interrupt cleared by software
19.10.1.6 Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the linked list in memory. Write the control information in the LLI. CTLx register
location of the block descriptor for each LLI in memory for channel x. For example, in
the register, you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flow control device by programming the TT_FC of the CTLx register.
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
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– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
3. Write the starting destination address in the DARx register for channel x.
Note: The values in the LLI.DARx register location of each Linked List Item (LLI) in memory, although
fetched during an LLI fetch, are not used.
4. Write the channel configuration information into the CFGx register for channel x.
a. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
b. If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripherals.
This requires programming the SRC_PER and DEST_PER bits, respectively.
5. Make sure that all LLI.CTLx register locations of the LLI (except the last) are set as
shown in Row 8 of Table 19-1 on page 327, while the LLI.CTLx register of the last
Linked List item must be set as described in Row 1 or Row 5 of Table 19-1 on page
327. Figure 19-7 on page 326 shows a Linked List example with two list items.
6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last)
are non-zero and point to the next Linked List Item.
7. Make sure that the LLI.SARx register location of all LLIs in memory point to the start
source block address proceeding that LLI fetch.
8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in
memory is cleared.
9. Clear any pending interrupts on the channel from the previous DMA transfer by writing
a ‘1’ to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
10. Program the CTLx, CFGx registers according to Row 8 as shown in Table 19-1 on page
327
11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
performed. Make sure that bit 0 of the DmaCfgReg register is enabled.
13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note: The LLI.SARx, LLI.DARx, LLI.LLPx and LLI.CTLx registers are fetched. The LLI.DARx register
location of the LLI although fetched is not used. The DARx register in the DMACA remains
unchanged.
14. Source and destination requests single and burst DMACA transactions to transfer the
block of data (assuming non-memory peripherals). The DMACA acknowledges at the
completion of every transaction (burst and single) in the block and carry out the block
transfer.
Note:
15. The DMACA does not wait for the block interrupt to be cleared, but continues and
fetches the next LLI from the memory location pointed to by current LLPx register and
automatically reprograms the SARx, CTLx and LLPx channel registers. The DARx reg-
ister is left unchanged. The DMA transfer continues until the DMACA samples the CTLx
and LLPx registers at the end of a block transfer match that described in Row 1 or Row
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5 of Table 19-1 on page 327. The DMACA then knows that the previous block trans-
ferred was the last block in the DMA transfer.
The DMACA transfer might look like that shown in Figure 19-17 on page 345 Note that the des-
tination address is decrementing.
Figure 19-17. DMA Transfer with Linked List Source Address and Contiguous Destination
Address
Address of Address of
Source Layer Destination Layer
Block 2
SAR(2) Block 2
DAR(2)
Block 1 Block 1
SAR(1) DAR(1)
Block 0
Block 0 DAR(0)
SAR(0)
Source Blocks Destination Blocks
The DMA transfer flow is shown in Figure 19-19 on page 346.
Figure 19-18.
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Figure 19-19. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address
Channel Enabled by
software
LLI Fetch
Hardware reprograms
SARx, CTLx, LLPx
DMAC block transfer
Source/destination
status fetch
Block Complete interrupt
generated here
Is DMAC in no
Row 1 of Table 4 ?
DMAC Transfer Complete yes
interrupt generated here
Channel Disabled by
hardware
19.11 Disabling a Channel Prior to Transfer Completion
Under normal operation, software enables a channel by writing a ‘1’ to the Channel Enable Reg-
ister, ChEnReg.CH_EN, and hardware disables a channel on transfer completion by clearing the
ChEnReg.CH_EN register bit.
The recommended way for software to disable a channel without losing data is to use the
CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register
(CFGx) register.
1. If software wishes to disable a channel prior to the DMA transfer completion, then it can
set the CFGx.CH_SUSP bit to tell the DMACA to halt all transfers from the source
peripheral. Therefore, the channel FIFO receives no new data.
2. Software can now poll the CFGx.FIFO_EMPTY bit until it indicates that the channel
FIFO is empty.
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3. The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is
empty.
When CTLx.SRC_TR_WIDTH is less than CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit
is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single
word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel
FIFO but not enough to form a single transfer of CTLx.DST_TR_WIDTH width. In this configura-
tion, once the channel is disabled, the remaining data in the channel FIFO are not transferred to
the destination peripheral. It is permitted to remove the channel from the suspension state by
writing a ‘0’ to the CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.
Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
19.11.1 Abnormal Transfer Termination
A DMACA DMA transfer may be terminated abruptly by software by clearing the channel enable
bit, ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the
ChEnReg.CH_EN bit is cleared over the HSB slave interface. Consider this as a request to dis-
able the channel. The ChEnReg.CH_EN must be polled and then it must be confirmed that the
channel is disabled by reading back 0. A case where the channel is not be disabled after a chan-
nel disable request is where either the source or destination has received a split or retry
response. The DMACA must keep re-attempting the transfer to the system HADDR that origi-
nally received the split or retry response until an OKAY response is returned. To do otherwise is
an System Bus protocol violation.
Software may terminate all channels abruptly by clearing the global enable bit in the DMACA
Configuration Register (DmaCfgReg[0]). Again, this does not mean that all channels are dis-
abled immediately after the DmaCfgReg[0] is cleared over the HSB slave interface. Consider
this as a request to disable all channels. The ChEnReg must be polled and then it must be con-
firmed that all channels are disabled by reading back ‘0’.
Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to
the destination peripheral and is not present when the channel is re-enabled. For read sensitive
source peripherals such as a source FIFO this data is therefore lost. When the source is not a
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to
empty may be acceptable as the data is available from the source peripheral upon request and is
not lost.
Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
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19.12 User Interface
Table 19-2. DMA Controller Memory Map
Offset Register Register Name Access Reset Value
0x000 Channel 0 Source Address Register SAR0 Read/Write 0x00000000
0x008 Channel 0 Destination Address Register DAR0 Read/Write 0x00000000
0x010 Channel 0 Linked List Pointer Register LLP0 Read/Write 0x00000000
0x018 Channel 0 Control Register Low CTL0L Read/Write 0x00304801
0x01C Channel 0 Control Register High CTL0H Read/Write 0x00000002
0x040 Channel 0 Configuration Register Low CFG0L Read/Write 0x00000c00
0x044 Channel 0 Configuration Register High CFG0H Read/Write 0x00000004
0x048 Channel 0 Source Gather Register SGR0 Read/Write 0x00000000
0x050 Channel 0 Destination Scatter Register DSR0 Read/Write 0x00000000
0x058 Channel 1 Source Address Register SAR1 Read/Write 0x00000000
0x060 Channel 1 Destination Address Register DAR1 Read/Write 0x00000000
0x068 Channel 1 Linked List Pointer Register LLP1 Read/Write 0x00000000
0x070 Channel 1 Control Register Low CTL1L Read/Write 0x00304801
0x074 Channel 1 Control Register High CTL1H Read/Write 0x00000002
0x098 Channel 1 Configuration Register Low CFG1L Read/Write 0x00000c20
0x09C Channel 1 Configuration Register High CFG1H Read/Write 0x00000004
0x0A0 Channel 1Source Gather Register SGR1 Read/Write 0x00000000
0x0A8 Channel 1 Destination Scatter Register DSR1 Read/Write 0x00000000
0x0B0 Channel 2 Source Address Register SAR2 Read/Write 0x00000000
0x0B8 Channel 2 Destination Address Register DAR2 Read/Write 0x00000000
0x0C0 Channel 2 Linked List Pointer Register LLP2 Read/Write 0x00000000
0x0C8 Channel 2 Control Register Low CTL2L Read/Write 0x00304801
0x0CC Channel 2 Control Register High CTL2H Read/Write 0x00000002
0x0F0 Channel 2 Configuration Register Low CFG2L Read/Write 0x00000c40
0x0F4 Channel 2 Configuration Register High CFG2H Read/Write 0x00000004
0x0F8 Channel 2 Source Gather Register SGR2 Read/Write 0x00000000
0x100 Channel 2 Destination Scatter Register DSR2 Read/Write 0x00000000
0x108 Channel 3 Source Address Register SAR3 Read/Write 0x00000000
0x110 Channel 3 Destination Address Register DAR3 Read/Write 0x00000000
0x118 Channel 3 Linked List Pointer Register LLP3 Read/Write 0x00000000
0x120 Channel 3 Control Register Low CTL3L Read/Write 0x00304801
0x124 Channel 3 Control Register High CTL3H Read/Write 0x00000002
0x148 Channel 3 Configuration Register Low CFG3L Read/Write 0x00000c60
0x14c Channel 3 Configuration Register High CFG3H Read/Write 0x00000004
0x150 Channel 3 Source Gather Register SGR3 Read/Write 0x00000000
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Table 19-2. DMA Controller Memory Map (Continued)
Offset Register Register Name Access Reset Value
0x158 Channel 3Destination Scatter Register DSR3 Read/Write 0x00000000
0x2C0 Raw Status for IntTfr Interrupt RawTfr Read-only 0x00000000
0x2C8 Raw Status for IntBlock Interrupt RawBlock Read-only 0x00000000
0x2D0 Raw Status for IntSrcTran Interrupt RawSrcTran Read-only 0x00000000
0x2D8 Raw Status for IntDstTran Interrupt RawDstTran Read-only 0x00000000
0x2E0 Raw Status for IntErr Interrupt RawErr Read-only 0x00000000
0x2E8 Status for IntTfr Interrupt StatusTfr Read-only 0x00000000
0x2F0 Status for IntBlock Interrupt StatusBlock Read-only 0x00000000
0x2F8 Status for IntSrcTran Interrupt StatusSrcTran Read-only 0x00000000
0x300 Status for IntDstTran Interrupt StatusDstTran Read-only 0x00000000
0x308 Status for IntErr Interrupt StatusErr Read-only 0x00000000
0x310 Mask for IntTfr Interrupt MaskTfr Read/Write 0x00000000
0x318 Mask for IntBlock Interrupt MaskBlock Read/Write 0x00000000
0x320 Mask for IntSrcTran Interrupt MaskSrcTran Read/Write 0x00000000
0x328 Mask for IntDstTran Interrupt MaskDstTran Read/Write 0x00000000
0x330 Mask for IntErr Interrupt MaskErr Read/Write 0x00000000
0x338 Clear for IntTfr Interrupt ClearTfr Write-only 0x00000000
0x340 Clear for IntBlock Interrupt ClearBlock Write-only 0x00000000
0x348 Clear for IntSrcTran Interrupt ClearSrcTran Write-only 0x00000000
0x350 Clear for IntDstTran Interrupt ClearDstTran Write-only 0x00000000
0x358 Clear for IntErr Interrupt ClearErr Write-only 0x00000000
0x360 Status for each interrupt type StatusInt Read-only 0x00000000
0x368 Source Software Transaction Request Register ReqSrcReg Read/Write 0x00000000
0x370 Destination Software Transaction Request Register ReqDstReg Read/Write 0x00000000
0x378 Single Source Transaction Request Register SglReqSrcReg Read/Write 0x00000000
0x380 Single Destination Transaction Request Register SglReqDstReg Read/Write 0x00000000
0x388 Last Source Transaction Request Register LstSrcReg Read/Write 0x00000000
0x390 Last Destination Transaction Request Register LstDstReg Read/Write 0x00000000
0x398 DMA Configuration Register DmaCfgReg Read/Write 0x00000000
0x3A0 DMA Channel Enable Register ChEnReg Read/Write 0x00000000
0x3F8 DMA Component ID Register Low DmaCompIdRegL Read-only 0x44571110
0x3FC DMA Component ID Register High DmaCompIdRegH Read-only 0x3230362A
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19.12.1 Channel x Source Address Register
Name: SARx
Access Type: Read/Write
Offset: 0x000 + [x * 0x58]
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
SADD[31:24]
23 22 21 20 19 18 17 16
SADD[23:16]
15 14 13 12 11 10 9 8
SADD[15:8]
7 6 5 4 3 2 1 0
SADD[7:0]
• SADD: Source Address of DMA transfer
The starting System Bus source address is programmed by software before the DMA channel is enabled or by a LLI update
before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the source
address of the current System Bus transfer.
Updated after each source System Bus transfer. The SINC field in the CTLx register determines whether the address incre-
ments, decrements, or is left unchanged on every source System Bus transfer throughout the block transfer.
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19.12.2 Channel x Destination Address Register
Name: DARx
Access Type: Read/Write
Offset: 0x008 + [x * 0x58]
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DADD[31:24]
23 22 21 20 19 18 17 16
DADD[23:16]
15 14 13 12 11 10 9 8
DADD[15:8]
7 6 5 4 3 2 1 0
DADD[7:0]
• DADD: Destination Address of DMA transfer
The starting System Bus destination address is programmed by software before the DMA channel is enabled or by a LLI
update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the desti-
nation address of the current System Bus transfer.
Updated after each destination System Bus transfer. The DINC field in the CTLx register determines whether the address
increments, decrements or is left unchanged on every destination System Bus transfer throughout the block transfer.
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19.12.3 Linked List Pointer Register for Channel x
Name: LLPx
Access Type: Read/Write
Offset: 0x010 + [x * 0x58]
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
LOC[29:22]
23 22 21 20 19 18 17 16
LOC[21:14]
15 14 13 12 11 10 9 8
LOC[13:6]
7 6 5 4 3 2 1 0
LOC[5:0] LMS
• LOC: Address of the next LLI
Starting address in memory of next LLI if block chaining is enabled.
The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if
block chaining is enabled.
The LLP register has two functions:
The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA transfer (single or multi-block).
If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to
enabling the channel in order to set up the transfer type.
It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists. In this case,
LOC[29:0] corresponds to A[31:2] of the next Linked Listed Item address
The LLPx register is also used to point to the address where write back of the control and source/destination status infor-
mation occurs after block completion.
• LMS: List Master Select
Identifies the High speed bus interface for the device that stores the next linked list item:
Table 19-3. List Master Select
LMS HSB Master
0 HSB master 1
1 HSB master 2
Other Reserved
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19.12.4 Control Register for Channel x Low
Name: CTLxL
Access Type: Read/Write
Offset: 0x018 + [x * 0x58]
Reset Value: 0x00304801
31 30 29 28 27 26 25 24
LLP_SRC_E LLP_DST_E
SMS DMS[1]
N N
23 22 21 20 19 18 17 16
DST_GATHE SRC_GATHE SRC_MSIZE
DMS[0] TT_FC
R_EN R_EN [2]
15 14 13 12 11 10 9 8
SRC_MSIZE[1:0] DEST_MSIZE SINC DINC[1]
7 6 5 4 3 2 1 0
DINC[0] SRC_TR_WIDTH DST_TR_WIDTH INT_EN
This register contains fields that control the DMA transfer. The CTLxL register is part of the block descriptor (linked list item)
when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is
enabled.
• LLP_SRC_EN
Block chaining is only enabled on the source side if the LLP_SRC_EN field is high and LLPx.LOC is non-zero.
• LLP_DST_EN
Block chaining is only enabled on the destination side if the LLP_DST_EN field is high and LLPx.LOC is non-zero.
• SMS: Source Master Select
Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from
Table 19-4. Source Master Select
SMS HSB Master
0 HSB master 1
1 HSB master 2
Other Reserved
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• DMS: Destination Master Select
Identifies the Master Interface layer where the destination device (peripheral or memory) resides
Table 19-5. Destination Master Select
DMS HSB Master
0 HSB master 1
1 HSB master 2
Other Reserved
• TT_FC: Transfer Type and Flow Control
The four following transfer types are supported:
• Memory to Memory, Memory to Peripheral, Peripheral to Memory and Peripheral to Peripheral.
The DMACA is always the Flow Controller.
TT_FC Transfer Type Flow Controller
000 Memory to Memory DMACA
001 Memory to Peripheral DMACA
010 Peripheral to Memory DMACA
011 Peripheral to Peripheral DMACA
Other Reserved Reserved
• DST_SCATTER_EN: Destination Scatter Enable
0 = Scatter disabled
1 = Scatter enabled
Scatter on the destination side is applicable only when the CTLx.DINC bit indicates an incrementing or decrementing
address control.
• SRC_GATHER_EN: Source Gather Enable
0 = Gather disabled
1 = Gather enabled
Gather on the source side is applicable only when the CTLx.SINC bit indicates an incrementing or decrementing address
control.
• SRC_MSIZE: Source Burst Transaction Length
Number of data items, each of width CTLx.SRC_TR_WIDTH, to be read from the source every time a source burst transac-
tion request is made from either the corresponding hardware or software handshaking interface.
SRC_MSIZE Size (items number)
0 1
1 4
2 8
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SRC_MSIZE Size (items number)
3 16
4 32
Other Reserved
• DST_MSIZE: Destination Burst Transaction Length
Number of data items, each of width CTLx.DST_TR_WIDTH, to be written to the destination every time a destination burst
transaction request is made from either the corresponding hardware or software handshaking interface.
DST_MSIZE Size (items number)
0 1
1 4
2 8
3 16
4 32
Other Reserved
• SINC: Source Address Increment
Indicates whether to increment or decrement the source address on every source System Bus transfer. If your device is
fetching data from a source peripheral FIFO with a fixed address, then set this field to “No change”
Source Address
SINC Increment
0 Increment
1 Decrement
Other No change
• DINC: Destination Address Increment
Indicates whether to increment or decrement the destination address on every destination System Bus transfer. If your
device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change”
Destination Address
DINC Increment
0 Increment
1 Decrement
Other No change
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• SRT_TR_WIDTH: Source Transfer Width
• DSC_TR_WIDTH: Destination Transfer Width
SRC_TR_WIDTH/DST_TR_WIDTH Size (bits)
0 8
1 16
2 32
Other Reserved
• INT_EN: Interrupt Enable Bit
If set, then all five interrupt generating sources are enabled.
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19.12.5 Control Register for Channel x High
Name: CTLxH
Access Type: Read/Write
Offset: 0x01C + [x * 0x58]
Reset Value: 0x00000002
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - DONE BLOCK_TS[11:8]
7 6 5 4 3 2 1 0
BLOCK_TS[7:0]
• DONE: Done Bit
Software can poll this bit to see when a block transfer is complete
• BLOCK_TS: Block Transfer Size
When the DMACA is flow controller, this field is written by the user before the channel is enabled to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block
transfer, unless the transfer is already in progress, in which case the value of BLOCK_TS indicates the number of single
transactions that have been performed so far.
The width of the single transaction is determined by CTLx.SRC_TR_WIDTH.
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19.12.6 Configuration Register for Channel x Low
Name: CFGxL
Access Type: Read/Write
Offset: 0x040 + [x * 0x58]
• Reset Value: 0x00000C00 + [x * 0x20]
31 30 29 28 27 26 25 24
RELOAD_D RELOAD_S - - - - - -
ST RC
23 22 21 20 19 18 17 16
- - - - SRC_HS_P DST_HS_PO - -
OL L
15 14 13 12 11 10 9 8
- - HS_SEL_SR HS_SEL_DS FIFO_EMPT CH_SUSP
C T Y
7 6 5 4 3 2 1 0
CH_PRIOR - - - - -
• RELOAD_DST: Automatic Destination Reload
The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A
new block transfer is then initiated.
• RELOAD_SRC: Automatic Source Reload
The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A
new block transfer is then initiated.
• SRC_HS_POL: Source Handshaking Interface Polarity
0 = Active high
1 = Active low
• DST_HS_POL: Destination Handshaking Interface Polarity
0 = Active high
1 = Active low
• HS_SEL_SRC: Source Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hardware or software, is active for source requests on this
channel.
0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
1 = Software handshaking interface. Hardware-initiated transaction requests are ignored.
If the source peripheral is memory, then this bit is ignored.
• HS_SEL_DST: Destination Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this
channel.
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0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
1 = Software handshaking interface. Hardware Initiated transaction requests are ignored.
If the destination peripheral is memory, then this bit is ignored.
• FIFO_EMPTY
Indicates if there is data left in the channel's FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a
channel.
1 = Channel's FIFO empty
0 = Channel's FIFO not empty
• CH_SUSP: Channel Suspend
Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction
will complete. Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel without losing any
data.
0 = Not Suspended.
1 = Suspend. Suspend DMA transfer from the source.
• CH_PRIOR: Channel priority
A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range [0, x-1].
A programmed value outside this range causes erroneous behavior.
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19.12.7 Configuration Register for Channel x High
Name: CFGxH
Access Type: Read/Write
Offset: 0x044 + [x * 0x58]
Reset Value: 0x00000004
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- DEST_PER SRC_PER[3:1]
7 6 5 4 3 2 1 0
SRC_PER[0] - - PROTCTL FIFO_MODE FCMODE
• DEST_PER: Destination Hardware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the
CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channel can then communicate with the destination
peripheral connected to that interface via the assigned hardware handshaking interface.
For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
• SRC_PER: Source Hardware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of channel x if the
CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then communicate with the source periph-
eral connected to that interface via the assigned hardware handshaking interface.
For correct DMACA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
• PROTCTL: Protection Control
Bits used to drive the System Bus HPROT[3:1] bus. The System Bus Specification recommends that the default value of
HPROT indicates a non-cached, nonbuffered, privileged data access. The reset value is used to indicate such an access.
HPROT[0] is tied high as all transfers are data accesses as there are no opcode fetches. There is a one-to-one mapping of
these register bits to the HPROT[3:1] master interface signals.
• FIFO_MODE: R/W 0x0 FIFO Mode Select
Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced.
0 = Space/data available for single System Bus transfer of the specified transfer width.
1 = Space/data available is greater than or equal to half the FIFO depth for destination transfers and less than half the FIFO
depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
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• FCMODE: Flow Control Mode
Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller.
0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled.
1 = Source transaction requests are not serviced until a destination transaction request occurs. In this mode the amount of data
transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block termination by
the destination. Data pre-fetching is disabled.
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19.12.8 Source Gather Register for Channel x
Name: SGRx
Access Type: Read/Write
Offset: 0x048 + [x * 0x58]
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
SGC[11:4]
23 22 21 20 19 18 17 16
SGC[3:0] SGI[19:16]
15 14 13 12 11 10 9 8
SGI[15:8]
7 6 5 4 3 2 1 0
SGI[7:0]
• SGC: Source Gather Count
Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This
is defined as a gather boundary.
• SGI: Source Gather Interval
Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a gather boundary when
gather mode is enabled for the source transfer.
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19.12.9 Destination Scatter Register for Channel x
Name: DSRx
Access Type: Read/Write
Offset: 0x050 + [x * 0x58]
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DSC[11:4]
23 22 21 20 19 18 17 16
DSC[3:0] DSI[19:16]
15 14 13 12 11 10 9 8
DSI[15:8]
7 6 5 4 3 2 1 0
DSI[7:0]
• DSC: Destination Scatter Count
Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter
boundaries.
• DSI: Destination Scatter Interval
Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH on a scatter boundary when
scatter mode is enabled for the destination transfer.
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19.12.10 Interrupt Registers
The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel,
there are five types of interrupt sources:
• IntTfr: DMA Transfer Complete Interrupt
This interrupt is generated on DMA transfer completion to the destination peripheral.
• IntBlock: Block Transfer Complete Interrupt
This interrupt is generated on DMA block transfer completion to the destination peripheral.
• IntSrcTran: Source Transaction Complete Interrupt
This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from
the handshaking interface on the source side.
If the source for a channel is memory, then that channel never generates a IntSrcTran interrupt and hence the correspond-
ing bit in this field is not set.
• IntDstTran: Destination Transaction Complete Interrupt
This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from
the handshaking interface on the destination side.
If the destination for a channel is memory, then that channel never generates the IntDstTran interrupt and hence the corre-
sponding bit in this field is not set.
• IntErr: Error Interrupt
This interrupt is generated when an ERROR response is received from an HSB slave on the HRESP bus during a DMA
transfer. In addition, the DMA transfer is cancelled and the channel is disabled.
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19.12.11 Interrupt Raw Status Registers
Name: RawTfr, RawBlock, RawSrcTran, RawDstTran, RawErr
Access Type: Read-only
Offset: 0x2C0, 0x2C8, 0x2D0, 0x2D8, 0x2E0
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - RAW3 RAW2 RAW1 RAW0
• RAW[3:0]Raw interrupt for each channel
Interrupt events are stored in these Raw Interrupt Status Registers before masking: RawTfr, RawBlock, RawSrcTran,
RawDstTran, RawErr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr[2] is Chan-
nel 2’s raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in
the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers.
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19.12.12 Interrupt Status Registers
Name: StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr
Access Type: Read-only
Offset: 0x2E8, 0x2F0, 0x2F8, 0x300, 0x308
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - STATUS3 STATUS2 STATUS1 STATUS0
• STATUS[3:0]
All interrupt events from all channels are stored in these Interrupt Status Registers after masking: StatusTfr, StatusBlock,
StatusSrcTran, StatusDstTran, StatusErr. Each Interrupt Status register has a bit allocated per channel, for example, Sta-
tusTfr[2] is Channel 2’s status transfer complete interrupt.The contents of these registers are used to generate the interrupt
signals leaving the DMACA.
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19.12.13 Interrupt Mask Registers
Name: MaskTfr, MaskBlock, MaskSrcTran, MaskDstTran, MaskErr
Access Type: Read/Write
Offset: 0x310, 0x318, 0x320, 0x328, 0x330
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - INT_M_WE3 INT_M_WE2 INT_M_WE1 INT_M_WE0
7 6 5 4 3 2 1 0
- - - - INT_MASK3 INT_MASK2 INT_MASK1 INT_MASK0
The contents of the Raw Status Registers are masked with the contents of the Mask Registers: MaskTfr, MaskBlock, Mask-
SrcTran, MaskDstTran, MaskErr. Each Interrupt Mask register has a bit allocated per channel, for example, MaskTfr[2] is
the mask bit for Channel 2’s transfer complete interrupt.
A channel’s INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted
on the same System Bus write transfer. This allows software to set a mask bit without performing a read-modified write
operation.
For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr[0], while MaskTfr[7:1] remains unchanged.
Writing hex 00xx leaves MaskTfr[7:0] unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMACA to set the appropri-
ate bit in the Status Registers.
• INT_M_WE[11:8]: Interrupt Mask Write Enable
0 = Write disabled
1 = Write enabled
• INT_MASK[3:0]: Interrupt Mask
0= Masked
1 = Unmasked
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19.12.14 Interrupt Clear Registers
Name: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr
Access Type: Write-only
Offset: 0x338, 0x340, 0x348, 0x350, 0x358
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - CLEAR3 CLEAR2 CLEAR1 CLEAR0
• CLEAR[3:0]: Interrupt Clear
0 = No effect
1 = Clear interrupt
Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in
the Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr. Each Interrupt Clear register has a bit allo-
cated per channel, for example, ClearTfr[2] is the clear bit for Channel 2’s transfer complete interrupt. Writing a 0 has no
effect. These registers are not readable.
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19.12.15 Combined Interrupt Status Registers
Name: StatusInt
Access Type: Read-only
Offset: 0x360
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - ERR DSTT SRCT BLOCK TFR
The contents of each of the five Status Registers (StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr) is
OR’ed to produce a single bit per interrupt type in the Combined Status Register (StatusInt).
• ERR
OR of the contents of StatusErr Register.
• DSTT
OR of the contents of StatusDstTran Register.
• SRCT
OR of the contents of StatusSrcTran Register.
• BLOCK
OR of the contents of StatusBlock Register.
• TFR
OR of the contents of StatusTfr Register.
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19.12.16 Source Software Transaction Request Register
Name: ReqSrcReg
Access Type: Read/write
Offset: 0x368
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
7 6 5 4 3 2 1 0
- - - - SRC_REQ3 SRC_REQ2 SRC_REQ1 SRC_REQ0
A bit is assigned for each channel in this register. ReqSrcReg[n] is ignored when software handshaking is not enabled for
the source of channel n.
A channel SRC_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on
the same System Bus write transfer.
For example, writing 0x101 writes a 1 into ReqSrcReg[0], while ReqSrcReg[4:1] remains unchanged. Writing hex 0x0yy
leaves ReqSrcReg[4:0] unchanged. This allows software to set a bit in the ReqSrcReg register without performing a read-
modified write
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• SRC_REQ[3:0]: Source request
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19.12.17 Destination Software Transaction Request Register
Name: ReqDstReg
Access Type: Read/write
Offset: 0x370
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
7 6 5 4 3 2 1 0
- - - - DST_REQ3 DST_REQ2 DST_REQ1 DST_REQ0
A bit is assigned for each channel in this register. ReqDstReg[n] is ignored when software handshaking is not enabled for
the source of channel n.
A channel DST_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the
same System Bus write transfer.
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• DST_REQ[3:0]: Destination request
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19.12.18 Single Source Transaction Request Register
Name: SglReqSrcReg
Access Type: Read/write
Offset: 0x378
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
7 6 5 4 3 2 1 0
- - - - S_SG_REQ3 S_SG_REQ2 S_SG_REQ1 S_SG_REQ0
A bit is assigned for each channel in this register. SglReqSrcReg[n] is ignored when software handshaking is not enabled
for the source of channel n.
A channel S_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on
the same System Bus write transfer.
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• S_SG_REQ[3:0]: Source single request
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19.12.19 Single Destination Transaction Request Register
Name: SglReqDstReg
Access Type: Read/write
Offset: 0x380
Reset Value: 0x0000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
7 6 5 4 3 2 1 0
- - - - D_SG_REQ3 D_SG_REQ2 D_SG_REQ1 D_SG_REQ0
A bit is assigned for each channel in this register. SglReqDstReg[n] is ignored when software handshaking is not enabled
for the source of channel n.
A channel D_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on
the same System Bus write transfer.
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• D_SG_REQ[3:0]: Destination single request
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19.12.20 Last Source Transaction Request Register
Name: LstSrcReg
Access Type: Read/write
Offset: 0x388
Reset Value: 0x0000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - LSTSRC_W LSTSRC_W LSTSRC_W LSTSRC_W
E3 E2 E1 E0
7 6 5 4 3 2 1 0
- - - - LSTSRC3 LSTSRC2 LSTSRC1 LSTSRC0
A bit is assigned for each channel in this register. LstSrcReg[n] is ignored when software handshaking is not enabled for
the source of channel n.
A channel LSTSRC bit is written only if the corresponding channel write enable bit in the LSTSRC_WE field is asserted on
the same System Bus write transfer.
• LSTSRC_WE[11:8]: Source Last Transaction request write enable
0 = Write disabled
1 = Write enabled
• LSTSRC[3:0]: Source Last Transaction request
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19.12.21 Last Destination Transaction Request Register
Name: LstDstReg
Access Type: Read/write
Offset: 0x390
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - LSTDST_WE LSTDST_WE LSTDST_WE LSTDST_WE
3 2 1 0
7 6 5 4 3 2 1 0
- - - - LSTDST3 LSTDST2 LSTDST1 LSTDST0
A bit is assigned for each channel in this register. LstDstReg[n] is ignored when software handshaking is not enabled for
the source of channel n.
A channel LSTDST bit is written only if the corresponding channel write enable bit in the LSTDST_WE field is asserted on
the same System Bus write transfer.
• LSTDST_WE[11:8]: Destination Last Transaction request write enable
0 = Write disabled
1 = Write enabled
• LSTDST[3:0]: Destination Last Transaction request
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19.12.22 DMA Configuration Register
Name: DmaCfgReg
Access Type: Read/Write
Offset: 0x398
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - DMA_EN
• DMA_EN: DMA Controller Enable
0 = DMACA Disabled
1 = DMACA Enabled.
This register is used to enable the DMACA, which must be done before any channel activity can begin.
If the global channel enable bit is cleared while any channel is still active, then DmaCfgReg.DMA_EN still returns ‘1’ to indi-
cate that there are channels still active until hardware has terminated all activity on all channels, at which point the
DmaCfgReg.DMA_EN bit returns ‘0’.
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19.12.23 DMA Channel Enable Register
Name: ChEnReg
Access Type: Read/Write
Offset: 0x3A0
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - CH_EN_WE CH_EN_WE CH_EN_WE CH_EN_WE
3 2 1 0
7 6 5 4 3 2 1 0
- - - - CH_EN3 CH_EN2 CH_EN1 CH_EN0
• CH_EN_WE[11:8]: Channel Enable Write Enable
The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on
the same System Bus write transfer.
For example, writing 0x101 writes a 1 into ChEnReg[0], while ChEnReg[7:1] remains unchanged.
• CH_EN[3:0]
0 = Disable the Channel
1 = Enable the Channel
Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel.
The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last System Bus transfer of
the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer
has completed.
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19.12.24 DMACA Component Id Register Low
Name: DmaCompIdRegL
Access Type: Read-only
Offset: 0x3F8
Reset Value: 0x44571110
31 30 29 28 27 26 25 24
DMA_COMP_TYPE[31:24]
23 22 21 20 19 18 17 16
DMA_COMP_TYPE[23:16]
15 14 13 12 11 10 9 8
DMA_COMP_TYPE[15:8]
7 6 5 4 3 2 1 0
DMA_COMP_TYPE[7:0]
• DMA_COMP_TYPE
DesignWare component type number = 0x44571110.
This assigned unique hex value is constant and is derived from the two ASCII letters “DW” followed by a 32-bit unsigned
number
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19.12.25 DMACA Component Id Register High
Name: DmaCompIdRegH
Access Type: Read-only
Offset: 0x3FC
Reset Value: 0x3230362A
31 30 29 28 27 26 25 24
DMA_COMP_VERSION[31:24]
23 22 21 20 19 18 17 16
DMA_COMP_VERSION[23:16]
15 14 13 12 11 10 9 8
DMA_COMP_VERSION[15:8]
7 6 5 4 3 2 1 0
DMA_COMP_VERSION[7:0]
• DMA_COMP_VERSION: Version of the component
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19.13 Module Configuration
The following table defines the valid settings for the DEST_PER and SRC_PER fields in the
CFGxH register. The direction is specified as observed from the DMACA. So for instance, AES -
RX means this hardware handshaking interface is connected to the input of the AES modulel
Table 19-6. DMACA Handshake Interfaces
PER Value Hardware Handshaking Interface
0 AES - RX
1 AES - TX
2 MCI - RX
3 MCI -TX
4 MSI - RX
5 MSI - TX
6 DMACA - EXT0
7 DMACA - EXT1
Table 19-7. DMACA External Handshake Signals
Handshaking
Interface Function Signal Name
DMACA - EXT0 DMA Acknowledge (DMACK0) DMAACK[0]
DMA Request (nDMAREQ0) DMARQ[0]
DMACA - EXT1 DMA Acknowledge (DMACK1) DMAACK[1]
DMA Request (nDMAREQ1) DMARQ[1]
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20. General-Purpose Input/Output Controller (GPIO)
Rev: 1.1.0.4
20.1 Features
Each I/O line of the GPIO features:
• Configurable pin-change, rising-edge or falling-edge interrupt on any I/O line
• A glitch filter providing rejection of pulses shorter than one clock cycle
• Input visibility and output control
• Multiplexing of up to four peripheral functions per I/O line
• Programmable internal pull-up resistor
20.2 Overview
The General Purpose Input/Output Controller manages the I/O pins of the microcontroller. Each
I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded
peripheral. This assures effective optimization of the pins of a product.
20.3 Block Diagram
Figure 20-1. GPIO Block Diagram
PB Configuration
Interface
GPIO Interrupt Request
Interrupt Controller PIN
PIN
General Purpose
MCU
Input/Output - GPIO PIN
I/O Pins
CLK_GPIO PIN
Power Manager
PIN
Embedded Pin Control
Peripheral Signals
20.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
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20.4.1 Module Configuration
Most of the features of the GPIO are configurable for each product. The user must refer to the
Package and Pinout chapter for these settings.
Product specific settings includes:
• Number of I/O pins.
• Functions implemented on each pin
• Peripheral function(s) multiplexed on each I/O pin
• Reset value of registers
20.4.2 Clocks
The clock for the GPIO bus interface (CLK_GPIO) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager.
The CLK_GPIO must be enabled in order to access the configuration registers of the GPIO or to
use the GPIO interrupts. After configuring the GPIO, the CLK_GPIO can be disabled if interrupts
are not used.
20.4.3 Interrupts
The GPIO interrupt lines are connected to the interrupt controller. Using the GPIO interrupt
requires the interrupt controller to be configured first.
20.5 Functional Description
The GPIO controls the I/O lines of the microcontroller. The control logic associated with each pin
is represented in the figure below:
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Figure 20-2. Overview of the GPIO Pad Connections
ODER
PUER
1
Periph. A output enable
Periph. B output enable
0
Periph. C output enable
Periph. D output enable
PMR1
GPER
PMR0
Periph. A output data
Periph. B output data
Periph. C output data 0
Periph. D output data
PAD
1
OVR
Periph. A input data
Periph. B input data
Periph. C input data
PVR
Periph. D input data
IER
Edge Detector
1
1
Glitch Filter
Interrupt Request
0
IMR1
GFER IMR0
20.5.1 Basic Operation
20.5.1.1 I/O Line or peripheral function selection
When a pin is multiplexed with one or more peripheral functions, the selection is controlled with
the GPIO Enable Register (GPER). If a bit in GPER is written to one, the corresponding pin is
controlled by the GPIO. If a bit is written to zero, the corresponding pin is controlled by a periph-
eral function.
20.5.1.2 Peripheral selection
The GPIO provides multiplexing of up to four peripheral functions on a single pin. The selection
is performed by accessing Peripheral Mux Register 0 (PMR0) and Peripheral Mux Register 1
(PMR1).
20.5.1.3 Output control
When the I/O line is assigned to a peripheral function, i.e. the corresponding bit in GPER is writ-
ten to zero, the drive of the I/O line is controlled by the peripheral. The peripheral, depending on
the value in PMR0 and PMR1, determines whether the pin is driven or not.
When the I/O line is controlled by the GPIO, the value of the Output Driver Enable Register
(ODER) determines if the pin is driven or not. When a bit in this register is written to one, the cor-
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responding I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not
drive the line.
The level driven on an I/O line can be determined by writing to the Output Value Register (OVR).
20.5.1.4 Inputs
The level on each I/O line can be read through the Pin Value Register (PVR). This register indi-
cates the level of the I/O lines regardless of whether the lines are driven by the GPIO or by an
external component. Note that due to power saving measures, the PVR register can only be
read when GPER is written to one for the corresponding pin or if interrupt is enabled for the pin.
20.5.1.5 Output line timings
The figure below shows the timing of the I/O line when writing a one and a zero to OVR. The
same timing applies when performing a ‘set’ or ‘clear’ access, i.e., writing a one to the Output
Value Set Register (OVRS) or the Output Value Clear Register (OVRC). The timing of PVR is
also shown.
Figure 20-3. Output Line Timings
CLK_GPIO
Write OVR to 1 PB Access
Write OVR to 0 PB Access
OVR / I/O Line
PVR
20.5.2 Advanced Operation
20.5.2.1 Pull-up resistor control
Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled
or disabled by writing a one or a zero to the corresponding bit in the Pull-up Enable Register
(PUER). Control of the pull-up resistor is possible whether an I/O line is controlled by a periph-
eral or the GPIO.
20.5.2.2 Input glitch filter
Optional input glitch filters can be enabled on each I/O line. When the glitch filter is enabled, a
glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with dura-
tion of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock
cycles, the pulse may or may not be taken into account, depending on the precise timing of its
occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for
a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces
2 clock cycles of latency.
The glitch filters are controlled by the Glitch Filter Enable Register (GFER). When a bit is written
to one in GFER, the glitch filter on the corresponding pin is enabled. The glitch filter affects only
interrupt inputs. Inputs to peripherals or the value read through PVR are not affected by the
glitch filters.
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20.5.3 Interrupts
The GPIO can be configured to generate an interrupt when it detects an input change on an I/O
line. The module can be configured to signal an interrupt whenever a pin changes value or only
to trigger on rising edges or falling edges. Interrupts are enabled on a pin by writing a one to the
corresponding bit in the Interrupt Enable Register (IER). The interrupt mode is set by writing to
the Interrupt Mode Register 0 (IMR0) and the Interrupt Mode Register 1(IMR1). Interrupts can be
enabled on a pin, regardless of the configuration of the I/O line, i.e. whether it is controlled by the
GPIO or assigned to a peripheral function.
In every port there are four interrupt lines connected to the interrupt controller. Groups of eight
interrupts in the port are ORed together to form an interrupt line.
When an interrupt event is detected on an I/O line, and the corresponding bit in IER is written to
one, the GPIO interrupt request line is asserted. A number of interrupt signals are ORed-wired
together to generate a single interrupt signal to the interrupt controller.
The Interrupt Flag Register (IFR) can by read to determine which pin(s) caused the interrupt.
The interrupt bit must be cleared by writing a one to the Interrupt Flag Clear Register (IFRC). To
take effect, the clear operation must be performed when the interrupt line is enabled in IER. Oth-
erwise, it will be ignored.
GPIO interrupts can only be triggered when the CLK_GPIO is enabled.
20.5.4 Interrupt Timings
The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter
is disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In
this example, this is not the case for the first pulse. The second pulse is however sampled on a
rising edge and will trigger an interrupt request.
Figure 20-4. Interrupt Timing With Glitch Filter Disabled
clock
Pin Level
GPIO_IFR
The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter
is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges.
In the example, the first pulse is rejected while the second pulse is accepted and causes an
interrupt request.
Figure 20-5. Interrupt Timing With Glitch Filter Enabled
clock
Pin Level
GPIO_IFR
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20.6 User Interface
The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32-
bit ports that are configurable through a PB interface. Each port has a set of configuration regis-
ters. The overall memory map of the GPIO is shown below. The number of pins and hence the
number of ports are product specific.
Figure 20-6. Overall Mermory Map
0x0000
Port 0 Configuration Registers
0x0100
Port 1 Configuration Registers
0x0200
Port 2 Configuration Registers
0x0300
Port 3 Configuration Registers
0x0400
Port 4 Configuration Registers
In the GPIO Controller Function Multiplexingtable in the Package and Pinout chapter, each
GPIO line has a unique number. Note that the PA, PB, PC and PX ports do not directly corre-
spond to the GPIO ports. To find the corresponding port and pin the following formula can be
used:
GPIO port = floor((GPIO number) / 32), example: floor((36)/32) = 1
GPIO pin = GPIO number mod 32, example: 36 mod 32 = 4
The table below shows the configuration registers for one port. Addresses shown are relative to
the port address offset. The specific address of a configuration register is found by adding the
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register offset and the port offset to the GPIO start address. One bit in each of the configuration
registers corresponds to an I/O pin.
Table 20-1. GPIO Register Memory Map
Offset Register Function Name Access Reset value
0x00 GPIO Enable Register Read/Write GPER Read/Write (1)
0x04 GPIO Enable Register Set GPERS Write-Only
0x08 GPIO Enable Register Clear GPERC Write-Only
0x0C GPIO Enable Register Toggle GPERT Write-Only
0x10 Peripheral Mux Register 0 Read/Write PMR0 Read/Write (1)
0x14 Peripheral Mux Register 0 Set PMR0S Write-Only
0x18 Peripheral Mux Register 0 Clear PMR0C Write-Only
0x1C Peripheral Mux Register 0 Toggle PMR0T Write-Only
0x20 Peripheral Mux Register 1 Read/Write PMR1 Read/Write (1)
0x24 Peripheral Mux Register 1 Set PMR1S Write-Only
0x28 Peripheral Mux Register 1 Clear PMR1C Write-Only
0x2C Peripheral Mux Register 1 Toggle PMR1T Write-Only
0x40 Output Driver Enable Register Read/Write ODER Read/Write (1)
0x44 Output Driver Enable Register Set ODERS Write-Only
0x48 Output Driver Enable Register Clear ODERC Write-Only
0x4C Output Driver Enable Register Toggle ODERT Write-Only
0x50 Output Value Register Read/Write OVR Read/Write (1)
0x54 Output Value Register Set OVRS Write-Only
0x58 Output Value Register Clear OVRC Write-Only
0x5c Output Value Register Toggle OVRT Write-Only
0x60 Pin Value Register Read PVR Read-Only (2)
0x70 Pull-up Enable Register Read/Write PUER Read/Write (1)
0x74 Pull-up Enable Register Set PUERS Write-Only
0x78 Pull-up Enable Register Clear PUERC Write-Only
0x7C Pull-up Enable Register Toggle PUERT Write-Only
0x90 Interrupt Enable Register Read/Write IER Read/Write (1)
0x94 Interrupt Enable Register Set IERS Write-Only
0x98 Interrupt Enable Register Clear IERC Write-Only
0x9C Interrupt Enable Register Toggle IERT Write-Only
0xA0 Interrupt Mode Register 0 Read/Write IMR0 Read/Write (1)
0xA4 Interrupt Mode Register 0 Set IMR0S Write-Only
0xA8 Interrupt Mode Register 0 Clear IMR0C Write-Only
0xAC Interrupt Mode Register 0 Toggle IMR0T Write-Only
0xB0 Interrupt Mode Register 1 Read/Write IMR1 Read/Write (1)
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Table 20-1. GPIO Register Memory Map
Offset Register Function Name Access Reset value
0xB4 Interrupt Mode Register 1 Set IMR1S Write-Only
0xB8 Interrupt Mode Register 1 Clear IMR1C Write-Only
0xBC Interrupt Mode Register 1 Toggle IMR1T Write-Only
0xC0 Glitch Filter Enable Register Read/Write GFER Read/Write (1)
0xC4 Glitch Filter Enable Register Set GFERS Write-Only
0xC8 Glitch Filter Enable Register Clear GFERC Write-Only
0xCC Glitch Filter Enable Register Toggle GFERT Write-Only
0xD0 Interrupt Flag Register Read IFR Read-Only (1)
0xD4 Interrupt Flag Register - - -
0xD8 Interrupt Flag Register Clear IFRC Write-Only
0xDC Interrupt Flag Register - - -
1) The reset value for these registers are device specific. Please refer to the Module Config-
uration section at the end of this chapter.
2) The reset value is undefined depending on the pin states.
20.6.1 Access Types
Each configuration register can be accessed in four different ways. The first address location
can be used to write the register directly. This address can also be used to read the register
value. The following addresses facilitate three different types of write access to the register. Per-
forming a “set” access, all bits written to one will be set. Bits written to zero will be unchanged by
the operation. Performing a “clear” access, all bits written to one will be cleared. Bits written to
zero will be unchanged by the operation. Finally, a toggle access will toggle the value of all bits
written to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g.
IFR), not all access methods are permitted.
Note that for ports with less than 32 bits, the corresponding control registers will have unused
bits. This is also the case for features that are not implemented for a specific pin. Writing to an
unused bit will have no effect. Reading unused bits will always return 0.
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20.6.2 Enable Register
Name: GPER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x00, 0x04, 0x08, 0x0C
Reset Value: -
25 24
31 30 29 28 27 26
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-P31: Pin Enable
0: A peripheral function controls the corresponding pin.
1: The GPIO controls the corresponding pin.
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20.6.3 Peripheral Mux Register 0
Name: PMR0
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x10, 0x14, 0x18, 0x1C
Reset Value: -
25 24
31 30 29 28 27 26
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Peripheral Multiplexer Select bit 0
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20.6.4 Peripheral Mux Register 1
Name: PMR1
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x20, 0x24, 0x28, 0x2C
Reset Value: -
25 24
31 30 29 28 27 26
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Peripheral Multiplexer Select bit 1
{PMR1, PMR0} Selected Peripheral Function
00 A
01 B
10 C
11 D
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20.6.5 Output Driver Enable Register
Name: ODER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x40, 0x44, 0x48, 0x4C
Reset Value: -
25 24
31 30 29 28 27 26
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Output Driver Enable
0: The output driver is disabled for the corresponding pin.
1: The output driver is enabled for the corresponding pin.
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20.6.6 Output Value Register
Name: OVR
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x50, 0x54, 0x58, 0x5C
Reset Value: -
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Output Value
0: The value to be driven on the I/O line is 0.
1: The value to be driven on the I/O line is 1.
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20.6.7 Pin Value Register
Name: PVR
Access Type: Read
Offset: 0x60, 0x64, 0x68, 0x6C
Reset Value: -
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Pin Value
0: The I/O line is at level ‘0’.
1: The I/O line is at level ‘1’.
Note that the level of a pin can only be read when GPER is set or interrupt is enabled for the pin.
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20.6.8 Pull-up Enable Register
Name: PUER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x70, 0x74, 0x78, 0x7C
Reset Value: -
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Pull-up Enable
0: The internal pull-up resistor is disabled for the corresponding pin.
1: The internal pull-up resistor is enabled for the corresponding pin.
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20.6.9 Interrupt Enable Register
Name: IER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x90, 0x94, 0x98, 0x9C
Reset Value: -
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Interrupt Enable
0: Interrupt is disabled for the corresponding pin.
1: Interrupt is enabled for the corresponding pin.
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20.6.10 Interrupt Mode Register 0
Name: IMR0
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0xA0, 0xA4, 0xA8, 0xAC
Reset Value: -
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Interrupt Mode Bit 0
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20.6.11 Interrupt Mode Register 1
Name: IMR1
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0xB0, 0xB4, 0xB8, 0xBC
Reset Value: -
25 24
31 30 29 28 27 26
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Interrupt Mode Bit 1
{IMR1, IMR0} Interrupt Mode
00 Pin Change
01 Rising Edge
10 Falling Edge
11 Reserved
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20.6.12 Glitch Filter Enable Register
Name: GFER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0xC0, 0xC4, 0xC8, 0xCC
Reset Value: -
25 24
31 30 29 28 27 26
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Glitch Filter Enable
0: Glitch filter is disabled for the corresponding pin.
1: Glitch filter is enabled for the corresponding pin.
NOTE! The value of this register should only be changed when IER is ‘0’. Updating this GFER while interrupt on the
corresponding pin is enabled can cause an unintentional interrupt to be triggered.
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20.6.13 Interrupt Flag Register
Name: IFR
Access Type: Read, Clear
Offset: 0xD0, 0xD8
Reset Value: -
25 24
31 30 29 28 27 26
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
7 6 5 4 3 2 1 0
P7 P6 P5 P4 P3 P2 P1 P0
• P0-31: Interrupt Flag
1: An interrupt condition has been detected on the corresponding pin.
0: No interrupt condition has beedn detected on the corresponding pin since reset or the last time it was cleared.
The number of interrupt request lines is dependant on the number of I/O pins on the MCU. Refer to the product specific data for
details. Note also that a bit in the Interrupt Flag register is only valid if the corresponding bit in IER is set.
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20.7 Programming Examples
20.7.1 8-bit LED-Chaser
// Set R0 to GPIO base address
mov R0, LO(AVR32_GPIO_ADDRESS)
orh R0, HI(AVR32_GPIO_ADDRESS)
// Enable GPIO control of pin 0-8
mov R1, 0xFF
st.w R0[AVR32_GPIO_GPERS], R1
// Set initial value of port
mov R2, 0x01
st.w R0[AVR32_GPIO_OVRS], R2
// Set up toggle value. Two pins are toggled
// in each round. The bit that is currently set,
// and the next bit to be set.
mov R2, 0x0303
orh R2, 0x0303
loop:
// Only change 8 LSB
mov R3, 0x00FF
and R3, R2
st.w R0[AVR32_GPIO_OVRT], R3
rol R2
rcall delay
rjmp loop
It is assumed in this example that a subroutine "delay" exists that returns after a given time.
20.7.2 Configuration of USART pins
The example below shows how to configure a peripheral module to control I/O pins. It assumed
in this example that the USART receive pin (RXD) is connected to PC16 and that the USART
transmit pin (TXD) is connected to PC17. For both pins, the USART is peripheral B. In this
example, the state of the GPIO registers is assumed to be unknown. The two USART pins are
therefore first set to be controlled by the GPIO with output drivers disabled. The pins can then be
assured to be tri-stated while changing the Peripheral Mux Registers.
// Set up pointer to GPIO, PORTC
mov R0, LO(AVR32_GPIO_ADDRESS + PORTC_OFFSET)
orh R0, HI(AVR32_GPIO_ADDRESS + PORTC_OFFSET)
// Disable output drivers
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mov R1, 0x0000
orh R1, 0x0003
st.w R0[AVR32_GPIO_ODERC], R1
// Make the GPIO control the pins
st.w R0[AVR32_GPIO_GPERS], R1
// Select peripheral B on PC16-PC17
st.w R0[AVR32_GPIO_PMR0S], R1
st.w R0[AVR32_GPIO_PMR1C], R1
// Enable peripheral control
st.w R0[AVR32_GPIO_GPERC], R1
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20.8 Module configuration
The specific configuration for each GPIO instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
Table 20-2. Module configuration
Feature GPIO
Number of GPIO ports 4
Number of peripheral functions 4
Table 20-3. Module clock name
Module name Clock name
GPIO CLK_GPIO
The reset values for all GPIO registers are zero with the following exceptions:
Table 20-4. Register Reset Values
Port Register Reset Value
0 GPER 0xFFFFFFFF
0 GFER 0xFFFFFFFF
1 GPER 0xFFFFFFFF
1 GFER 0xFFFFFFFF
2 GPER 0xFFFFFFFF
2 GFER 0xFFFFFFFF
3 GPER 0x00007FFF
3 GFER 0x00007FFF
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21. Serial Peripheral Interface (SPI)
Rev: 2.1.0.3
21.1 Features
• Compatible with an embedded 32-bit microcontroller
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors
– External co-processors
• Master or Slave Serial Peripheral Bus Interface
– 4 - to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock and data
per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Connection to Peripheral DMA Controller channel capabilities optimizes data transfers
– One channel for the receiver, one channel for the transmitter
– Next buffer support
– Four character FIFO in reception
21.2 Overview
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com-
munication with external devices in Master or Slave mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master
Protocol where one CPU is always the master while all of the others are always slaves) and one
master may simultaneously shift data into multiple slaves. However, only one slave may drive its
output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): this data line supplies the output data from the master shifted
into the input(s) of the slave(s).
• Master In Slave Out (MISO): this data line supplies the output data from a slave to the input of
the master. There may be no more than one slave transmitting data during any particular
transfer.
• Serial Clock (SPCK): this control line is driven by the master and regulates the flow of the
data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once
for each bit that is transmitted.
• Slave Select (NSS): this control line allows slaves to be turned on and off by hardware.
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21.3 Block Diagram
Figure 21-1. SPI Block Diagram
Peripheral DMA
Controller
Peripheral Bus
SPCK
MISO
CLK_SPI MOSI
I/O
Spi Interface NPCS0/NSS
Controller
NPCS1
NPCS2
Interrupt Control
NPCS3
SPI Interrupt
21.4 Application Block Diagram
Figure 21-2. Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK SPCK
MISO MISO
Slave 0
MOSI MOSI
Spi Master NPCS0 NSS
NPCS1
NPCS2 NC SPCK
NPCS3 MISO
Slave 1
MOSI
NSS
SPCK
MISO
Slave 2
MOSI
NSS
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21.5 I/O Lines Description
Table 21-1. I/O Lines Description
Type
Pin Name Pin Description Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Slave In Output Input
SPCK Serial Clock Output Input
NPCS1-NPCS3 Peripheral Chip Selects Output Unused
NPCS0/NSS Peripheral Chip Select/Slave Select Output Input
21.6 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
21.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.
The user must first configure the I/O Controller to assign the SPI pins to their peripheral
functions.
21.6.2 Clocks
The clock for the SPI bus interface (CLK_SPI) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SPI before disabling the clock, to avoid freezing the SPI in an undefined state.
21.6.3 Interrupts
The SPI interrupt request line is connected to the interrupt controller. Using the SPI interrupt
requires the interrupt controller to be programmed first.
21.7 Functional Description
21.7.1 Modes of Operation
The SPI operates in master mode or in slave mode.
Operation in master mode is configured by writing a one to the Master/Slave Mode bit in the
Mode Register (MR.MSTR). The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK
pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output
by the transmitter.
If the MR.MSTR bit is written to zero, the SPI operates in slave mode. The MISO line is driven by
the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the
transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a
Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other
purposes.
The data transfers are identically programmable for both modes of operations. The baud rate
generator is activated only in master mode.
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21.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is
configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock
phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two
bits determine the edges of the clock signal on which data is driven and sampled. Each of the
two bits has two possible states, resulting in four possible combinations that are incompatible
with one another. Thus, a master/slave pair must use the same parameter pair values to com-
municate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
Table 21-2 on page 407 shows the four modes and corresponding parameter settings.
Table 21-2. SPI modes
SPI Mode CPOL NCPHA
0 0 1
1 0 0
2 1 1
3 1 0
Figure 21-3 on page 407 and Figure 21-4 on page 408 show examples of data transfers.
Figure 21-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
SPCK cycle (for reference) 1 2 3 4 5 6 7 8
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI MSB 6 5 4 3 2 1 LSB
(from master)
MISO MSB 6 5 4 3 2 1 LSB ***
(from slave)
NSS
(to slave)
*** Not Defined, but normaly MSB of previous character received
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Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
SPCK cycle (for reference) 1 2 3 4 5 6 7 8
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI MSB 6 5 4 3 2 1 LSB
(from master)
MISO *** MSB 6 5 4 3 2 1 LSB
(from slave)
NSS
(to slave)
*** Not Defined, but normaly LSB of previous character transmitted
21.7.3 Master Mode Operations
When configured in master mode, the SPI uses the internal programmable baud rate generator
as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI
bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data Register (TDR) and the Receive Data
Register (RDR), and a single Shift Register. The holding registers maintain the data flow at a
constant rate.
After enabling the SPI, a data transfer begins when the processor writes to the TDR register.
The written data is immediately transferred in the Shift Register and transfer on the SPI bus
starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled
and shifted in the Shift Register. Transmission cannot occur without reception.
Before writing to the TDR, the Peripheral Chip Select field in TDR (TDR.PCS) must be written in
order to select a slave.
If new data is written to TDR during the transfer, it stays in it until the current transfer is com-
pleted. Then, the received data is transferred from the Shift Register to RDR, the data in TDR is
loaded in the Shift Register and a new transfer starts.
The transfer of a data written in TDR in the Shift Register is indicated by the Transmit Data Reg-
ister Empty bit in the Status Register (SR.TDRE). When new data is written in TDR, this bit is
cleared. The SR.TDRE bit is used to trigger the Transmit Peripheral DMA Controller channel.
The end of transfer is indicated by the Transmission Registers Empty bit in the SR register
(SR.TXEMPTY). If a transfer delay (CSRn.DLYBCT) is greater than zero for the last transfer,
SR.TXEMPTY is set after the completion of said delay. The CLK_SPI can be switched off at this
time.
During reception, received data are transferred from the Shift Register to the reception FIFO.
The FIFO can contain up to 4 characters (both Receive Data and Peripheral Chip Select fields).
While a character of the FIFO is unread, the Receive Data Register Full bit in SR remains high
(SR.RDRF). Characters are read through the RDR register. If the four characters stored in the
FIFO are not read and if a new character is stored, this sets the Overrun Error Status bit in the
SR register (SR.OVRES). The procedure to follow in such a case is described in Section
21.7.3.8.
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In master mode, if the received data is not read fast enough compared to the transfer rhythm
imposed by the write accesses in the TDR, some overrun errors may occur, even if the FIFO is
enabled. To insure a perfect data integrity of received data (especially at high data rate), the
mode Wait Data Read Before Transfer can be enabled in the MR register (MR.WDRBT). When
this mode is activated, no transfer starts while received data remains unread in the RDR. When
data is written to the TDR and if unread received data is stored in the RDR, the transfer is
paused until the RDR is read. In this mode no overrun error can occur. Please note that if this
mode is enabled, it is useless to activate the FIFO in reception.
Figure 21-5 on page 409shows a block diagram of the SPI when operating in master mode. Fig-
ure 21-6 on page 410 shows a flow chart describing how transfers are handled.
21.7.3.1 Master mode block diagram
Figure 21-5. Master Mode Block Diagram
CSR0..3
SCBR
CLK_SPI Baud Rate Generator SPCK
SPI
Clock
RXFIFOEN
RDR RDRF
RD OVRES
CSR0..3
BITS
NCPHA 0
CPOL 1 4 – Character FIFO
LSB Shift Register MSB
MISO MOSI
TDR
TD TDRE
RXFIFOEN
RDR
CSR0..3
CSNAAT 0
1 4 – Character FIFO
PS CSAAT
MR NPCS3
PCSDEC
PCS
NPCS2
0 Current
Peripheral NPCS1
TDR
PCS
NPCS0
1
MSTR
MODF
NPCS0
MODFDIS
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21.7.3.2 Master mode flow diagram
Figure 21-6. Master Mode Flow Diagram
SPI Enable - NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- When NPCS is 0xF, CSAAT is 0.
1
TDRE ?
Fixed
1 0 peripheral
CSAAT ? PS ?
Variable
0 1 peripheral
Fixed
0 peripheral yes
PS ? TDR(PCS) MR(PCS)
= NPCS ? = NPCS ?
Variable
1 peripheral no no
NPCS = TDR(PCS) NPCS = MR(PCS) NPCS = 0xF NPCS = 0xF
Delay DLYBCS Delay DLYBCS
NPCS = TDR(PCS) NPCS = MR(PCS),
TDR(PCS)
Delay DLYBS
Serializer = TDR(TD)
TDRE = 1
Data Transfer
RDR(RD) = Serializer
RDRF = 1
Delay DLYBCT
0
TDRE ?
1
CSAAT ?
NPCS = 0xF
Delay DLYBCS
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21.7.3.3 Clock generation
The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255.
This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud
rate of CLK_SPI divided by 255.
Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbid-
den. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results.
At reset, CSRn.SCBR is zero and the user has to configure it at a valid value before performing
the first transfer.
The divisor can be defined independently for each chip select, as it has to be configured in the
CSRn.SCBR field. This allows the SPI to automatically adapt the baud rate for each interfaced
peripheral without reprogramming.
21.7.3.4 Transfer delays
Figure 21-7 on page 411 shows a chip select transfer change and consecutive transfers on the
same chip select. Three delays can be configured to modify the transfer waveforms:
• The delay between chip selects, programmable only once for all the chip selects by writing to
the Delay Between Chip Selects field in the MR register (MR.DLYBCS). Allows insertion of a
delay between release of one chip select and before assertion of a new one.
• The delay before SPCK, independently programmable for each chip select by writing the
Delay Before SPCK field in the CSRn registers (CSRn.DLYBS). Allows the start of SPCK to
be delayed after the chip select has been asserted.
• The delay between consecutive transfers, independently programmable for each chip select
by writing the Delay Between Consecutive Transfers field in the CSRn registers
(CSRn.DLYBCT). Allows insertion of a delay between two transfers occurring on the same
chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
Figure 21-7. Programmable Delays
Chip Select 1
Chip Select 2
SPCK
DLYBCS DLYBS DLYBCT DLYBCT
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21.7.3.5 Peripheral selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals are high before and after each transfer.
The peripheral selection can be performed in two different ways:
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Fixed Peripheral Select is activated by writing a zero to the Peripheral Select bit in MR (MR.PS).
In this case, the current peripheral is defined by the MR.PCS field and the TDR.PCS field has no
effect.
Variable Peripheral Select is activated by writing a one to the MR.PS bit . The TDR.PCS field is
used to select the current peripheral. This means that the peripheral selection can be defined for
each new data.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the Periph-
eral DMA Controller is an optimal means, as the size of the data transfer between the memory
and the SPI is either 4 bits or 16 bits. However, changing the peripheral selection requires the
Mode Register to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro-
gramming the MR register. Data written to TDR is 32-bits wide and defines the real data to be
transmitted and the peripheral it is destined to. Using the Peripheral DMA Controller in this mode
requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the
MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO
and MOSI lines with the CSRn registers. This is not the optimal means in term of memory size
for the buffers, but it provides a very effective means to exchange data with several peripherals
without any intervention of the processor.
21.7.3.6 Peripheral chip select decoding
The user can configure the SPI to operate with up to 15 peripherals by decoding the four Chip
Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing a one to
the Chip Select Decode bit in the MR register (MR.PCSDEC).
When operating without decoding, the SPI makes sure that in any case only one chip select line
is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest
numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field of
either the MR register or the TDR register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at one)
when not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, the CRS0
register defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to
the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals
on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
21.7.3.7 Peripheral deselection
When operating normally, as soon as the transfer of the last data written in TDR is completed,
the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding
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to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals
requiring the chip select line to remain active during a full set of transfers.
To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip
Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines
to remain in their current state (low = active) until transfer to another peripheral is required.
When the CSRn.CSAAT bit is written to qero, the NPCS does not rise in all cases between two
transfers on the same peripheral. During a transfer on a Chip Select, the SR.TDRE bit rises as
soon as the content of the TDR is transferred into the internal shifter. When this bit is detected
the TDR can be reloaded. If this reload occurs before the end of the current transfer and if the
next transfer is performed on the same chip select as the current transfer, the Chip Select is not
de-asserted between the two transfers. This might lead to difficulties for interfacing with some
serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate
interfacing with such devices, the CSRn registers can be configured with the Chip Select Not
Active After Transfer bit (CSRn.CSNAAT) written to one. This allows to de-assert systematically
the chip select lines during a time DLYBCS. (The value of the CSRn.CSNAAT bit is taken into
account only if the CSRn.CSAAT bit is written to zero for the same Chip Select).
Figure 21-8 on page 414 shows different peripheral deselection cases and the effect of the
CSRn.CSAAT and CSRn.CSNAAT bits.
21.7.3.8 FIFO management
A FIFO has been implemented in Reception FIFO (both in master and in slave mode), in order to
be able to store up to 4 characters without causing an overrun error. If an attempt is made to
store a fifth character, an overrun error rises. If such an event occurs, the FIFO must be flushed.
There are two ways to Flush the FIFO:
• By performing four read accesses of the RDR (the data read must be ignored)
• By writing a one to the Flush Fifo Command bit in the CR register (CR.FLUSHFIFO).
After that, the SPI is able to receive new data.
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Figure 21-8. Peripheral Deselection
CSAAT = 0 and CSNAAT = 0 CSAAT = 1 and CSNAAT= 0 / 1
TDRE
DLYBCT DLYBCT
NPCS[0..3] A A A A A
DLYBCS DLYBCS
PCS = A PCS = A
Write TDR
TDRE
DLYBCT DLYBCT
NPCS[0..3] A A A A A
DLYBCS DLYBCS
PCS=A PCS = A
Write TDR
TDRE
DLYBCT DLYBCT
NPCS[0..3] A B A B
DLYBCS DLYBCS
PCS = B PCS = B
Write TDR
CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1
DLYBCT DLYBCT
TDRE
NPCS[0..3] A A A A
DLYBCS
PCS = A PCS = A
Write TDR
Figure 21-8 on page 414 shows different peripheral deselection cases and the effect of the
CSRn.CSAAT and CSRn.CSNAAT bits.
21.7.3.9 Mode fault detection
The SPI is capable of detecting a mode fault when it is configured in master mode and NPCS0,
MOSI, MISO, and SPCK are configured as open drain through the I/O Controller with either
internal or external pullup resistors. If the I/O Controller does not have open-drain capability,
mode fault detection must be disabled by writing a one to the Mode Fault Detection bit in the MR
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register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a
low level is driven by an external master on the NPCS0/NSS signal.
When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR
is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable
bit in the CR register (CR.SPIEN).
By default, the mode fault detection circuitry is enabled. The user can disable mode fault detec-
tion by writing a one to the Mode Fault Detection bit in the MR register (MR.MODFDIS).
21.7.4 SPI Slave Mode
When operating in slave mode, the SPI processes data bits on the clock provided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by the Bits Per Transfer field of the Chip Select Register 0 (CSR0.BITS). These bits are
processed following a phase and a polarity defined respectively by the CSR0.NCPHA and
CSR0.CPOL bits. Note that the BITS, CPOL, and NCPHA bits of the other Chip Select Registers
have no effect when the SPI is configured in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
When all the bits are processed, the received data is transferred in the Receive Data Register
and the SR.RDRF bit rises. If the RDR register has not been read before new data is received,
the SR.OVRES bit is set. Data is loaded in RDR even if this flag is set. The user has to read the
SR register to clear the SR.OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the TDR register, the last data received is transferred. If no data has been
received since the last reset, all bits are transmitted low, as the Shift Register resets to zero.
When a first data is written in TDR, it is transferred immediately in the Shift Register and the
SR.TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls
and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in
TDR is transferred in the Shift Register and the SR.TDRE bit rises. This enables frequent
updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the TDR. In case no character is ready to
be transmitted, i.e. no character has been written in TDR since the last load from TDR to the
Shift Register, the Shift Register is not modified and the last received character is retransmitted.
In this case the Underrun Error Status bit is set in SR (SR.UNDES).
Figure 21-9 on page 416 shows a block diagram of the SPI when operating in slave mode.
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Figure 21-9. Slave Mode Functional Block Diagram
SPCK
SPI
NSS Clock
SPIEN
SPIENS RXFIFOEN
RDR RDRF
SPIDIS RD OVRES
CSR0
BITS
0
NCPHA 4 - Character FIFO
1
CPOL
LSB Shift Register MSB
MOSI MISO
TDR UNDES
TD TDRE
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21.8 User Interface
Table 21-3. SPI Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read/Write 0x00000000
0x08 Receive Data Register RDR Read-only 0x00000000
0x0C Transmit Data Register TDR Write-only 0x00000000
0x10 Status Register SR Read-only 0x00000000
0x14 Interrupt Enable Register IER Write-only 0x00000000
0x18 Interrupt Disable Register IDR Write-only 0x00000000
0x1C Interrupt Mask Register IMR Read-only 0x00000000
0x30 Chip Select Register 0 CSR0 Read/Write 0x00000000
0x34 Chip Select Register 1 CSR1 Read/Write 0x00000000
0x38 Chip Select Register 2 CSR2 Read/Write 0x00000000
0x3C Chip Select Register 3 CSR3 Read/Write 0x00000000
0x E4 Write Protection Control Register WPCR Read/Write 0X00000000
0xE8 Write Protection Status Register WPSR Read-only 0x00000000
0xFC Version Register VERSION Read-only - (1)
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
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21.8.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - LASTXFER
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - FLUSHFIFO
7 6 5 4 3 2 1 0
SWRST - - - - - SPIDIS SPIEN
• LASTXFER: Last Transfer
1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
0: Writing a zero to this bit has no effect.
• FLUSHFIFO: Flush Fifo Command
1: If The FIFO Mode is enabled (MR.FIFOEN written to one) and if an overrun error has been detected, this command allows to
empty the FIFO.
0: Writing a zero to this bit has no effect.
• SWRST: SPI Software Reset
1: Writing a one to this bit will reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in
slave mode after software reset. Peripheral DMA Controller channels are not affected by software reset.
0: Writing a zero to this bit has no effect.
• SPIDIS: SPI Disable
1: Writing a one to this bit will disable the SPI. As soon as SPIDIS is written to one, the SPI finishes its transfer, all pins are set
in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is
disabled. If both SPIEN and SPIDIS are equal to one when the CR register is written, the SPI is disabled.
0: Writing a zero to this bit has no effect.
• SPIEN: SPI Enable
1: Writing a one to this bit will enable the SPI to transfer and receive data.
0: Writing a zero to this bit has no effect.
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21.8.2 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
- - - - PCS
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
LLB RXFIFOEN WDRBT- MODFDIS - PCSDEC PS MSTR
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default.
Otherwise, the following equation determines the delay:
Delay Between Chip Selects = DLYBCS
-----------------------
CLKSPI
• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• LLB: Local Loopback Enable
1: Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in master mode only (MISO is
internally connected on MOSI).
0: Local loopback path disabled.
• RXFIFOEN: FIFO in Reception Enable
1: The FIFO is used in reception (four characters can be stored in the SPI).
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0: The FIFO is not used in reception (only one character can be stored in the SPI).
• WDRBT: Wait Data Read Before Transfer
1: In master mode, a transfer can start only if the RDR register is empty, i.e. does not contain any unread data. This mode
prevents overrun error in reception.
0: No Effect. In master mode, a transfer can be initiated whatever the state of the RDR register is.
• MODFDIS: Mode Fault Detection
1: Mode fault detection is disabled. If the I/O controller does not have open-drain capability, mode fault detection must be
disabled for proper operation of the SPI.
0: Mode fault detection is enabled.
• PCSDEC: Chip Select Decode
0: The chip selects are directly connected to a peripheral device.
1: The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The CSRn registers define the characteristics of the 15 chip selects according to the following rules:
CSR0 defines peripheral chip select signals 0 to 3.
CSR1 defines peripheral chip select signals 4 to 7.
CSR2 defines peripheral chip select signals 8 to 11.
CSR3 defines peripheral chip select signals 12 to 14.
• PS: Peripheral Select
1: Variable Peripheral Select.
0: Fixed Peripheral Select.
• MSTR: Master/Slave Mode
1: SPI is in master mode.
0: SPI is in slave mode.
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21.8.3 Receive Data Register
Name: RDR
Access Type: Read-only
Offset: 0x08
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
RD[15:8]
7 6 5 4 3 2 1 0
RD[7:0]
• RD: Receive Data
Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
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21.8.4 Transmit Data Register
Name: TDR
Access Type: Write-only
Offset: 0x0C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - LASTXFER
23 22 21 20 19 18 17 16
- - - - PCS
15 14 13 12 11 10 9 8
TD[15:8]
7 6 5 4 3 2 1 0
TD[7:0]
• LASTXFER: Last Transfer
1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
0: Writing a zero to this bit has no effect.
This field is only used if Variable Peripheral Select is active (MR.PS = 1).
• PCS: Peripheral Chip Select
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
This field is only used if Variable Peripheral Select is active (MR.PS = 1).
• TD: Transmit Data
Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the TDR
register in a right-justified format.
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21.8.5 Status Register
Name: SR
Access Type: Read-only
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - SPIENS
15 14 13 12 11 10 9 8
- - - - - UNDES TXEMPTY NSSR
7 6 5 4 3 2 1 0
- - - - OVRES MODF TDRE RDRF
• SPIENS: SPI Enable Status
1: This bit is set when the SPI is enabled.
0: This bit is cleared when the SPI is disabled.
• UNDES: Underrun Error Status (Slave Mode Only)
1: This bit is set when a transfer begins whereas no data has been loaded in the TDR register.
0: This bit is cleared when the SR register is read.
• TXEMPTY: Transmission Registers Empty
1: This bit is set when TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the
completion of such delay.
0: This bit is cleared as soon as data is written in TDR.
• NSSR: NSS Rising
1: A rising edge occurred on NSS pin since last read.
0: This bit is cleared when the SR register is read.
• OVRES: Overrun Error Status
1: This bit is set when an overrun has occurred. An overrun occurs when RDR is loaded at least twice from the serializer since
the last read of the RDR.
0: This bit is cleared when the SR register is read.
• MODF: Mode Fault Error
1: This bit is set when a Mode Fault occurred.
0: This bit is cleared when the SR register is read.
• TDRE: Transmit Data Register Empty
1: This bit is set when the last data written in the TDR register has been transferred to the serializer.
0: This bit is cleared when data has been written to TDR and not yet transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• RDRF: Receive Data Register Full
1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR.
0: No data has been received since the last read of RDR
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21.8.6 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - UNDES TXEMPTY NSSR
7 6 5 4 3 2 1 0
- - - - OVRES MODF TDRE RDRF
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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21.8.7 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x18
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - UNDES TXEMPTY NSSR
7 6 5 4 3 2 1 0
- - - - OVRES MODF TDRE RDRF
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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21.8.8 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - UNDES TXEMPTY NSSR
7 6 5 4 3 2 1 0
- - - - OVRES MODF TDRE RDRF
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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21.8.9 Chip Select Register 0
Name: CSR0
Access Type: Read/Write
Offset: 0x30
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS CSAAT CSNAAT NCPHA CPOL
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
32 × DLYBCT
Delay Between Consecutive Transfers = ------------------------------------
CLKSPI
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
DLYBS-
Delay Before SPCK = --------------------
CLKSPI
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
CLKSPI
SPCK Baudrate = ---------------------
SCBR
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
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• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of:
DLYBCS
----------------------- (if DLYBCT field is different from 0)
CLKSPI
DLYBCS + 1- (if DLYBCT field equals 0)
--------------------------------
CLKSPI
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CPOL: Clock Polarity
1: The inactive state value of SPCK is logic level one.
0: The inactive state value of SPCK is logic level zero.
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CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
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21.8.10 Chip Select Register 1
Name: CSR1
Access Type: Read/Write
Offset: 0x34
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS CSAAT CSNAAT NCPHA CPOL
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
32 × DLYBCT
Delay Between Consecutive Transfers = ------------------------------------
CLKSPI
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
DLYBS-
Delay Before SPCK = --------------------
CLKSPI
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
CLKSPI
SPCK Baudrate = ---------------------
SCBR
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
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• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of:
DLYBCS
----------------------- (if DLYBCT field is different from 0)
CLKSPI
DLYBCS + 1- (if DLYBCT field equals 0)
--------------------------------
CLKSPI
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CPOL: Clock Polarity
1: The inactive state value of SPCK is logic level one.
0: The inactive state value of SPCK is logic level zero.
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CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
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21.8.11 Chip Select Register 2
Name: CSR2
Access Type: Read/Write
Offset: 0x38
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS CSAAT CSNAAT NCPHA CPOL
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
32 × DLYBCT
Delay Between Consecutive Transfers = ------------------------------------
CLKSPI
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
DLYBS-
Delay Before SPCK = --------------------
CLKSPI
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
CLKSPI
SPCK Baudrate = ---------------------
SCBR
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
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• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of:
DLYBCS
----------------------- (if DLYBCT field is different from 0)
CLKSPI
DLYBCS + 1- (if DLYBCT field equals 0)
--------------------------------
CLKSPI
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CPOL: Clock Polarity
1: The inactive state value of SPCK is logic level one.
0: The inactive state value of SPCK is logic level zero.
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CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
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21.8.12 Chip Select Register 3
Name: CSR3
Access Type: Read/Write
Offset: 0x3C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS CSAAT CSNAAT NCPHA CPOL
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
32 × DLYBCT
Delay Between Consecutive Transfers = ------------------------------------
CLKSPI
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
DLYBS-
Delay Before SPCK = --------------------
CLKSPI
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
CLKSPI
SPCK Baudrate = ---------------------
SCBR
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
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• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of:
DLYBCS
----------------------- (if DLYBCT field is different from 0)
CLKSPI
DLYBCS + 1- (if DLYBCT field equals 0)
--------------------------------
CLKSPI
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CPOL: Clock Polarity
1: The inactive state value of SPCK is logic level one.
0: The inactive state value of SPCK is logic level zero.
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CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
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21.8.13 Write Protection Control Register
Register Name: WPCR
Access Type: Read-write
Offset: 0xE4
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
SPIWPKEY[23:16]
23 22 21 20 19 18 17 16
SPIWPKEY[15:8]
15 14 13 12 11 10 9 8
SPIWPKEY[7:0]
7 6 5 4 3 2 1 0
- - - - - - - SPIWPEN
• SPIWPKEY: SPI Write Protection Key Password
If a value is written in SPIWPEN, the value is taken into account only if SPIWPKEY is written with “SPI” (SPI written in ASCII
Code, i.e. 0x535049 in hexadecimal).
• SPIWPEN: SPI Write Protection Enable
1: The Write Protection is Enabled
0: The Write Protection is Disabled
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21.8.14 Write Protection Status Register
Register Name: WPSR
Access Type: Read-only
Offset: 0xE8
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
SPIWPVSRC
7 6 5 4 3 2 1 0
- - - - - SPIWPVS
• SPIWPVSRC: SPI Write Protection Violation Source
This Field indicates the Peripheral Bus Offset of the register concerned by the violation (MR or CSRx)
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• SPIWPVS: SPI Write Protection Violation Status
SPIWPVS value Violation Type
1 The Write Protection has blocked a Write access to a protected register (since the last read).
Software Reset has been performed while Write Protection was enabled (since the last read
2
or since the last write access on MR, IER, IDR or CSRx).
Both Write Protection violation and software reset with Write Protection enabled have
3
occurred since the last read.
Write accesses have been detected on MR (while a chip select was active) or on CSRi (while
4
the Chip Select “i” was active) since the last read.
The Write Protection has blocked a Write access to a protected register and write accesses
5 have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select
“i” was active) since the last read.
Software Reset has been performed while Write Protection was enabled (since the last read
or since the last write access on MR, IER, IDR or CSRx) and some write accesses have been
6
detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was
active) since the last read.
- The Write Protection has blocked a Write access to a protected register.
and
- Software Reset has been performed while Write Protection was enabled.
7
and
- Write accesses have been detected on MR (while a chip select was active) or on CSRi
(while the Chip Select “i” was active) since the last read.
•
•
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21.8.15 Version Register
Register Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: –
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - MFN
15 14 13 12 11 10 9 8
VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• MFN
Reserved. No functionality associated.
• VERSION
Version number of the module. No functionality associated.
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21.9 Module Configuration
The specific configuration for each SPI instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
section for details.
Table 21-4. Module Clock Name
Module Name Clock Name
SPI0 CLK_SPI0
SPI1 CLK_SPI1
Table 21-5. Register Reset Values
Register Reset Value
VERSION 0x00000210
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22. Two-wire Slave Interface (TWIS)
Rev.: 1.0.0.1
22.1 Features
• Compatible with I²C standard
– Transfer speeds of 100 and 400 kbit/s
– 7 and 10-bit and General Call addressing
• Compatible with SMBus standard
– Hardware Packet Error Checking (CRC) generation and verification with ACK response
– SMBALERT interface
– 25 ms clock low timeout delay
– 25 ms slave cumulative clock low extend time
• Compatible with PMBus
• DMA interface for reducing CPU load
• Arbitrary transfer lengths, including 0 data bytes
• Optional clock stretching if transmit or receive buffers not ready for data transfer
• 32-bit Peripheral Bus interface for configuration of the interface
22.2 Overview
The Atmel Two-wire Slave Interface (TWIS) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus, I²C, or
SMBus-compatible master. The TWIS is always a bus slave and can transfer sequential or sin-
gle bytes.
Below, Table 22-1 lists the compatibility level of the Atmel Two-wire Slave Interface and a full I²C
compatible device.
Table 22-1. Atmel TWIS Compatibility with I²C Standard
I²C Standard Atmel TWIS
Standard-mode (100 kbit/s) Supported
Fast-mode (400 kbit/s) Supported
7 or 10 bits Slave Addressing Supported
START BYTE(1) Not Supported
Repeated Start (Sr) Condition Supported
ACK and NAK Management Supported
Slope control and input filtering (Fast mode) Supported
Clock stretching Supported
Note: 1. START + b000000001 + Ack + Sr
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Below, Table 22-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full
SMBus compatible device.
Table 22-2. Atmel TWIS Compatibility with SMBus Standard
SMBus Standard Atmel TWIS
Bus Timeouts Supported
Address Resolution Protocol Supported
Alert Supported
Packet Error Checking Supported
22.3 List of Abbreviations
Table 22-3. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
P Stop
S Start
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
R Read
W Write
22.4 Block Diagram
Figure 22-1. Block Diagram
Peripheral
Bus Bridge
TWCK
I/O Controller TWD
Two-wire
TWALM
Interface
Power
Manager
CLK_TWIS Interrupt
Controller
TWI Interrupt
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22.5 Application Block Diagram
Figure 22-2. Application Block Diagram
VDD
Rp Rp
TWD
Host with
TWI
Interface TWCK
Atmel TWI I²C LCD I²C temp.
I²C RTC
serial EEPROM controller sensor
Slave 1 Slave 2 Slave 3 Slave 4
Rp: Pull up value as given by the I²C Standard
22.6 I/O Lines Description
Table 22-4. I/O Lines Description
Pin Name Pin Description Type
TWD Two-wire Serial Data Input/Output
TWCK Two-wire Serial Clock Input/Output
TWALM SMBus SMBALERT Input/Output
22.7 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
22.7.1 I/O Lines
TWDand TWCK are bidirectional lines, connected to a positive supply voltage via a current
source or pull-up resistor (see Figure 22-5 on page 448). When the bus is free, both lines are
high. The output stages of devices connected to the bus must have an open-drain or open-col-
lector to perform the wired-AND function.
TWALM is used to implement the optional SMBus SMBALERT signal.
TWALM, TWD, and TWCK pins may be multiplexed with I/O Controller lines. To enable the
TWIS, the user must perform the following steps:
• Program the I/O Controller to:
– Dedicate TWD, TWCK, and optionally TWALM as peripheral lines.
– Define TWD, TWCK, and optionally TWALM as open-drain.
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22.7.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop func-
tioning and resume operation after the system wakes up from sleep mode.
22.7.3 Clocks
The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state.
22.7.4 DMA
The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the
TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting
up the TWIS.
22.7.5 Interrupts
The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS inter-
rupts requires the interrupt controller to be programmed first.
22.7.6 Debug Operation
When an external debugger forces the CPU into debug mode, the TWIS continues normal oper-
ation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.
22.8 Functional Description
22.8.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
22-4 on page 448).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
22-3).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 22-3. START and STOP Conditions
TWD
TWCK
Start Stop
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Figure 22-4. Transfer Format
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop
22.8.2 Operation
The TWIS has two modes of operation:
• Slave transmitter mode
• Slave receiver mode
A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is
assigned an address and responds to requests from the master. These modes are described in
the following chapters.
Figure 22-5. Typical Application Block Diagram
VDD
Rp Rp
TWD
Host with
TWI
Interface TWCK
Atmel TWI I²C LCD I²C Temp.
I²C RTC
Serial EEPROM Controller Sensor
Slave 1 Slave 2 Slave 3 Slave 4
Rp: Pull up value as given by the I²C Standard
22.8.2.1 Bus Timing
The Timing Register (TR) is used to control the timing of bus signals driven by the TWIS. TR
describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling
can be selected through TR.EXP.
f CLK_TWIS
f PRESCALED = ------------------------
-
( EXP + 1 )
2
TR has the following fields:
TLOWS: Prescaled clock cycles used to time SMBUS timeout TLOW:SEXT.
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TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT.
SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT.
EXP: Specifies the clock prescaler setting used for the SMBUS timeouts.
Figure 22-6. Bus Timing Diagram
t HIGH
t LOW
t LOW
t t t t t
HD:STA SU:DAT HD:DAT SU:DAT SU:STO
S P
t
SU:STA
Sr
22.8.2.2 Setting Up and Performing a Transfer
Operation of the TWIS is mainly controlled by the Control Register (CR). The following list pres-
ents the main steps in a typical communication:
4. Before any transfers can be performed, bus timings must be configured by writing to the
Timing Register (TR).If the Peripheral DMA Controller is to be used for the transfers, it
must be set up.
5. The Control Register (CR) must be configured with information such as the slave
address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer, and
which addresses to match.
The interrupt system can be set up to generate interrupt request on specific events or error con-
ditions, for example when a byte has been received.
The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in
SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written to
zero. NBYTES is updated by hardware, so in order to avoid hazards, software updates of
NBYTES can only be done through writes to the NBYTES register.
22.8.2.3 Address Matching
The TWIS can be set up to match several different addresses. More than one address match
may be enabled simultaneously, allowing the TWIS to be assigned to several addresses. The
address matching phase is initiated after a START or REPEATED START condition. When the
TWIS receives an address that generates an address match, an ACK is automatically returned
to the master.
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In I²C mode:
• The address in CR.ADR is checked for address match if CR.SMATCH is one.
• The General Call address is checked for address match if CR.GCMATCH is one.
In SMBus mode:
• The address in CR.ADR is checked for address match if CR.SMATCH is one.
• The Alert Response Address is checked for address match if CR.SMAL is one.
• The Default Address is checked for address match if CR.SMDA is one.
• The Host Header Address is checked for address match if CR.SMHH is one.
22.8.2.4 Clock Stretching
Any slave or bus master taking part in a transfer may extend the TWCK low period at any time.
The TWIS may extend the TWCK low period after each byte transfer if CR.STREN is one and:
• Module is in slave transmitter mode, data should be transmitted, but THR is empty, or
• Module is in slave receiver mode, a byte has been received and placed into the internal
shifter, but the Receive Holding Register (RHR) is full, or
• Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains
stretched until all address match bits in the Status Register (SR) have been cleared.
If CR.STREN is zero and:
• Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit
the value present in THR (the last transmitted byte or reset value), and set SR.URUN.
• Module is in slave receiver mode, a byte has been received and placed into the internal
shifter, but RHR is full: Discard the received byte and set SR.ORUN.
22.8.2.5 Bus Errors
If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and
the TWIS waits for a new START condition.
22.8.3 Slave Transmitter Mode
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it
will enter slave transmitter mode and set the SR.TRA bit (note that SR.TRA is set one
CLK_TWIS cycle after the relevant address match bit in the same register is set).
After the address phase, the following actions are performed:
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to
transmit. This is necessary in order to know when to transmit the PEC byte. NBYTES
can also be used to count the number of bytes received if using DMA.
2. Byte to transmit depends on I²C/SMBus mode and CR.PEC:
– If in I²C mode or CR.PEC is zero or NBYTES is non-zero: The TWIS waits until THR
contains a valid data byte, possibly stretching the low period of TWCK. After THR
contains a valid data byte, the data byte is transferred to a shifter, and then
SR.TXRDY is changed to one because the THR is empty again.
– SMBus mode and CR.PEC is one: If NBYTES is zero, the generated PEC byte is
automatically transmitted instead of a data byte from THR. TWCK will not be
stretched by the TWIS.
3. The data byte in the shifter is transmitted.
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4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is
decremented.
5. After each data byte has been transmitted, the master transmits an ACK (Acknowledge)
or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is
set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the
TWIS to be HIGH (see Figure 22-9). The NAK indicates that the transfer is finished, and
the TWIS will wait for a STOP or REPEATED START. If an ACK bit is received, the
SR.NAK bit remains LOW. The ACK indicates that more data should be transmitted,
jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer Finished
(SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been
sampled by the TWIS to be LOW (see Figure 22-9). Also note that in the event that
SR.NAK bit is set, it must not be cleared before the SR.BTF bit is set to ensure correct
TWIS behavior.
6. If STOP is received, SR.TCOMP and SR.STO will be set.
7. If REPEATED START is received, SR.REP will be set.
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the mas-
ter to pull it down in order to generate the acknowledge. The slave polls the data line during this
clock pulse and sets the NAK bit in SR if the master does not acknowledge the data byte. A NAK
means that the master does not wish to receive additional data bytes. As with the other status
bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER).
SR.TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one.
See Figure 22-7 and Figure 22-8.
Figure 22-7. Slave Transmitter with One Data Byte
TWD S DADR R A DATA N P
TCOMP
TXRDY
Write THR (DATA) STOP sent by master
NBYTES set to 1
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Figure 22-8. Slave Transmitter with Multiple Data Bytes
TWD S DADR R A DATA n A DATA n+5 A DATA n+m N P
TCOMP
TXRDY
STOP sent by master
Write THR (Data n) Write THR (Data n+1) Write THR (Data n+m)
NBYTES set to m Last data sent
Figure 22-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF
TWD DATA (LSB) N P
TWCK
SR.NAK
SR.BTF
t1 t1
t1: (CLK_TWIS period) x 2
22.8.4 Slave Receiver Mode
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is
cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one
CLK_TWIS cycle after the relevant address match bit in the same register is set).
After the address phase, the following is repeated:
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to
receive. This is necessary in order to know which of the received bytes is the PEC byte.
NBYTES can also be used to count the number of bytes received if using DMA.
2. Receive a byte. Set SR.BTF when done.
3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise
NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is
used.
4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordi-
nary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC
is enabled and the last byte received was a PEC byte (indicated by NBYTES equal to
zero), The TWIS will automatically return an ACK if the PEC value was correct, other-
wise a NAK will be returned.
5. If STOP is received, SR.TCOMP will be set.
6. If REPEATED START is received, SR.REP will be set.
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the
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slave to pull it down in order to generate the acknowledge. The master polls the data line during
this clock pulse.
The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also
used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 22-10. Slave Receiver with One Data Byte
TWD S DADR W A DATA A P
TCOMP
RXRDY
Read RHR
Figure 22-11. Slave Receiver with Multiple Data Bytes
TWD S DADR W A DATA n A DATA (n+1) A DAT A (n+m)-1 A DATA (n+m) A P
TCOMP
RXRDY
Read RHR Read RHR Read RHR Read RHR
DATA n DATA (n+1) DAT A (n+m)-1 DATA (n+m)
22.8.5 Using the Peripheral DMA Controller
The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set
up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space
to place received data. By initializing NBYTES to zero before a transfer, and writing a one to
CR.CUP, NBYTES is incremented by one each time a data has been transmitted or received.
This allows the user to detect how much data was actually transferred by the DMA system.
To assure correct behavior, respect the following programming sequences:
22.8.5.1 Data Transmit with the Peripheral DMA Controller
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIS (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to transmit.
4. Wait for the Peripheral DMA Controller end-of-transmit flag.
5. Disable the Peripheral DMA Controller.
22.8.5.2 Data Receive with the Peripheral DMA Controller
1. Initialize the receive Peripheral DMA Controller (memory pointers, size - 1, etc.).
2. Configure the TWIS (ADR, NBYTES, etc.).
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3. Start the transfer by enabling the Peripheral DMA Controller to receive.
4. Wait for the Peripheral DMA Controller end-of-receive flag.
5. Disable the Peripheral DMA Controller.
22.8.6 SMBus Mode
SMBus mode is enabled by writing a one to the SMBus Mode Enable (SMEN) bit in CR. SMBus
mode operation is similar to I²C operation with the following exceptions:
• Only 7-bit addressing can be used.
• The SMBus standard describes a set of timeout values to ensure progress and throughput on
the bus. These timeout values must be written to TR.
• Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
• A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.
• A set of addresses have been reserved for protocol handling, such as Alert Response
Address (ARA) and Host Header (HH) Address. Address matching on these addresses can
be enabled by configuring CR appropriately.
22.8.6.1 Packet Error Checking (PEC)
Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to
the Packet Error Checking Enable (PECEN) bit in CR enables automatic PEC handling in the
current transfer. The PEC generator is always updated on every bit transmitted or received, so
that PEC handling on following linked transfers will be correct.
In slave receiver mode, the master calculates a PEC value and transmits it to the slave after all
data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to
the PEC value it has computed itself. If the values match, the data was received correctly, and
the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the
slave will return a NAK value. The SR.SMBPECERR bit is set automatically if a PEC error
occurred.
In slave transmitter mode, the slave calculates a PEC value and transmits it to the master after
all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare
it to the PEC value it has computed itself. If the values match, the data was received correctly. If
the PEC values differ, data was corrupted, and the master must take appropriate action.
The PEC byte is automatically inserted in a slave transmitter transmission if PEC enabled when
NBYTES reaches zero. The PEC byte is identified in a slave receiver transmission if PEC
enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of
data bytes in the transmission, including the PEC byte.
22.8.6.2 Timeouts
The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave
will leave the bus. The SR.SMBTOUT bit is also set.
22.8.6.3 SMBALERT
A slave can get the master’s attention by pulling the SMBALERT line low. This is done by writing
a one to the SMBus Alert (SMBALERT) bit in CR. This will also enable address match on the
Alert Response Address (ARA).
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22.8.7 Identifying Bus Events
This chapter lists the different bus events, and how these affects the bits in the TWIS registers.
This is intended to help writing drivers for the TWIS.
Table 22-5. Bus Events
Event Effect
SR.THR is cleared.
Slave transmitter has sent a SR.BTF is set.
data byte The value of the ACK bit sent immediately after the data byte is given
by CR.ACK.
SR.RHR is set.
Slave receiver has received
SR.BTF is set.
a data byte
SR.NAK updated according to value of ACK bit received from master.
Start+Sadr on bus, but
None.
address is to another slave
Start+Sadr on bus, current
slave is addressed, but
None.
address match enable bit in
CR is not set
Correct address match bit in SR is set.
Start+Sadr on bus, current
SR.TRA updated according to transfer direction (updating is done one
slave is addressed,
CLK_TWIS cycle after address match bit is set)
corresponding address
match enable bit in CR set Slave enters appropriate transfer direction mode and data transfer
can commence.
Correct address match bit in SR is set.
Start+Sadr on bus, current SR.TRA updated according to transfer direction (updating is done one
slave is addressed, CLK_TWIS cycle after address match bit is set).
corresponding address Slave stretches TWCK immediately after transmitting the address
match enable bit in CR set, ACK bit. TWCK remains stretched until all address match bits in SR
SR.STREN and SR.SOAM have been cleared.
are set. Slave enters appropriate transfer direction mode and data transfer
can commence.
Repeated Start received SR.REP set.
after being addressed SR.TCOMP unchanged.
Stop received after being SR.STO set.
addressed SR.TCOMP set.
Start, Repeated Start, or SR.BUSERR set.
Stop received in illegal SR.STO and SR.TCOMP may or may not be set depending on the
position on bus exact position of an illegal stop.
Data is to be received in
slave receiver mode,
TWCK is stretched until RHR has been read.
SR.STREN is set, and RHR
is full
Data is to be transmitted in
slave receiver mode,
TWCK is stretched until THR has been written.
SR.STREN is set, and THR
is empty
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Table 22-5. Bus Events
Event Effect
Data is to be received in
slave receiver mode, TWCK is not stretched, read data is discarded.
SR.STREN is cleared, and SR.ORUN is set.
RHR is full
Data is to be transmitted in
slave receiver mode, TWCK is not stretched, previous contents of THR is written to bus.
SR.STREN is cleared, and SR.URUN is set.
THR is empty
SR.SMBTOUT is set.
SMBus timeout received
TWCK and TWD are immediately released.
Slave transmitter in SMBus
PEC mode has transmitted Master receiver will transmit a NAK as usual after the last byte of a
a PEC byte, that was not master receiver transfer.
identical to the PEC Master receiver will retry the transfer at a later time.
calculated by the master
receiver.
Slave receiver discovers SR.SMBPECERR is set.
SMBus PEC Error NAK returned after the data byte.
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22.9 User Interface
Table 22-6. TWIS Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Read/Write 0x00000000
0x04 NBYTES Register NBYTES Read/Write 0x00000000
0x08 Timing Register TR Read/Write 0x00000000
0x0C Receive Holding Register RHR Read-only 0x00000000
0x10 Transmit Holding Register THR Write-only 0x00000000
0x14 Packet Error Check Register PECR Read-only 0x00000000
0x18 Status Register SR Read-only 0x00000002
0x1C Interrupt Enable Register IER Write-only 0x00000000
0x20 Interrupt Disable Register IDR Write-only 0x00000000
0x24 Interrupt Mask Register IMR Read-only 0x00000000
0x28 Status Clear Register SCR Write-only 0x00000000
0x2C Parameter Register PR Read-only -(1)
0x30 Version Register VR Read-only -(1)
Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this
chapter.
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22.9.1 Control Register
Name: CR
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - TENBIT ADR[9:8]
23 22 21 20 19 18 17 16
ADR[7:0]
15 14 13 12 11 10 9 8
SOAM CUP ACK PECEN SMHH SMDA SMBALERT
7 6 5 4 3 2 1 0
SWRST - - STREN GCMATCH SMATCH SMEN SEN
• TENBIT: Ten Bit Address Match
0: Disables Ten Bit Address Match.
1: Enables Ten Bit Address Match.
• ADR: Slave Address
Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise.
• SOAM: Stretch Clock on Address Match
0: Does not stretch bus clock after address match.
1: Stretches bus clock after address match.
• CUP: NBYTES Count Up
0: Causes NBYTES to count down (decrement) per byte transferred.
1: Causes NBYTES to count up (increment) per byte transferred.
• ACK: Slave Receiver Data Phase ACK Value
0: Causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode.
1: Causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode.
• PECEN: Packet Error Checking Enable
0: Disables SMBus PEC (CRC) generation and check.
1: Enables SMBus PEC (CRC) generation and check.
• SMHH: SMBus Host Header
0: Causes the TWIS not to acknowledge the SMBus Host Header.
1: Causes the TWIS to acknowledge the SMBus Host Header.
• SMDA: SMBus Default Address
0: Causes the TWIS not to acknowledge the SMBus Default Address.
1: Causes the TWIS to acknowledge the SMBus Default Address.
• SMBALERT: SMBus Alert
0: Causes the TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response Address (ARA).
1: Causes the TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address (ARA).
• SWRST: Software Reset
This bit will always read as 0.
Writing a zero to this bit has no effect.
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Writing a one to this bit resets the TWIS.
• STREN: Clock Stretch Enable
0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun.
1: Enables clock stretching if RHR/THR buffer full/empty.
• GCMATCH: General Call Address Match
0: Causes the TWIS not to acknowledge the General Call Address.
1: Causes the TWIS to acknowledge the General Call Address.
• SMATCH: Slave Address Match
0: Causes the TWIS not to acknowledge the Slave Address.
1: Causes the TWIS to acknowledge the Slave Address.
• SMEN: SMBus Mode Enable
0: Disables SMBus mode.
1: Enables SMBus mode.
• SEN: Slave Enable
0: Disables the slave interface.
1: Enables the slave interface.
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22.9.2 NBYTES Register
Name: NBYTES
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
NBYTES
• NBYTES: Number of Bytes to Transfer
Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer. NBYTES can
be incremented or decremented automatically by hardware.
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22.9.3 Timing Register
Name: TR
Access Type: Read/Write
Offset: 0x08
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
EXP - - - -
23 22 21 20 19 18 17 16
SUDAT
15 14 13 12 11 10 9 8
TTOUT
7 6 5 4 3 2 1 0
TLOWS
• EXP: Clock Prescaler
Used to specify how to prescale the SMBus TLOWS counter. The counter is prescaled according to the following formula:
f CLK_TWIS
f PRESCALED = ------------------------
-
( EXP + 1 )
2
• SUDAT: Data Setup Cycles
Non-prescaled clock cycles for data setup count. Used to time TSU_DAT. Data is driven SUDAT cycles after TWCK low detected.
This timing is used for timing the ACK/NAK bits, and any data bits driven in slave transmitter mode.
• TTOUT: SMBus TTIMEOUT Cycles
Prescaled clock cycles used to time SMBus TTIMEOUT.
• TLOWS: SMBus TLOW:SEXT Cycles
Prescaled clock cycles used to time SMBus TLOW:SEXT.
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22.9.4 Receive Holding Register
Name: RHR
Access Type: Read-only
Offset: 0x0C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
RXDATA
• RXDATA: Received Data Byte
When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
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22.9.5 Transmit Holding Register
Name: THR
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
TXDATA
• TXDATA: Data Byte to Transmit
Write data to be transferred on the TWI bus here.
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22.9.6 Packet Error Check Register
Name: PECR
Access Type: Read-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
PEC
• PEC: Calculated PEC Value
The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a
STOP condition. Provided if the user manually wishes to control when the PEC byte is transmitted, or wishes to access the PEC
value for other reasons. In ordinary operation, the PEC handling is done automatically by hardware.
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22.9.7 Status Register
Name: SR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x000000002
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
7 6 5 4 3 2 1 0
ORUN URUN TRA - TCOMP SEN TXRDY RXRDY
• BTF: Byte Transfer Finished
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when byte transfer has completed.
• REP: Repeated Start Received
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a REPEATED START condition is received.
• STO: Stop Received
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the STOP condition is received.
• SMBDAM: SMBus Default Address Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Default Address.
• SMBHHM: SMBus Host Header Address Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Host Header Address.
• SMBALERTM: SMBus Alert Response Address Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Alert Response Address.
• GCM: General Call Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the General Call Address.
• SAM: Slave Address Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the Slave Address.
• BUSERR: Bus Error
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a misplaced START or STOP condition has occurred.
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• SMBPECERR: SMBus PEC Error
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a SMBus PEC error has occurred.
• SMBTOUT: SMBus Timeout
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a SMBus timeout has occurred.
• NAK: NAK Received
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a NAK was received from the master during slave transmitter operation.
• ORUN: Overrun
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an overrun has occurred in slave receiver mode. Can only occur if CR.STREN is zero.
• URUN: Underrun
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an underrun has occurred in slave transmitter mode. Can only occur if CR.STREN is zero.
• TRA: Transmitter Mode
0: The slave is in slave receiver mode.
1: The slave is in slave transmitter mode.
• TCOMP: Transmission Complete
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when transmission is complete. Set after receiving a STOP after being addressed.
• SEN: Slave Enabled
0: The slave interface is disabled.
1: The slave interface is enabled.
• TXRDY: TX Buffer Ready
0: The TX buffer is full and should not be written to.
1: The TX buffer is empty, and can accept new data.
• RXRDY: RX Buffer Ready
0: No RX data ready in RHR.
1: RX data is ready to be read from RHR.
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22.9.8 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x1C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
7 6 5 4 3 2 1 0
ORUN URUN - - TCOMP - TXRDY RXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will write a one to the corresponding bit in IMR.
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22.9.9 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x20
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
7 6 5 4 3 2 1 0
ORUN URUN - - TCOMP - TXRDY RXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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22.9.10 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x24
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
7 6 5 4 3 2 1 0
ORUN URUN - - TCOMP - TXRDY RXRDY
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is written to one.
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22.9.11 Status Clear Register
Name: SCR
Access Type: Write-only
Offset: 0x28
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
7 6 5 4 3 2 1 0
ORUN URUN - - TCOMP - - -
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
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22.9.12 Parameter Register
Name: PR
Access Type: Read-only
Offset: 0x2C
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -
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22.9.13 Version Register (VR)
Name: VR
Access Type: Read-only
Offset: 0x30
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION [11:8]
7 6 5 4 3 2 1 0
VERSION [7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
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22.10 Module Configuration
The specific configuration for each TWIS instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 22-7. Module Clock Name
Module name Clock name
TWIS0 CLK_TWIS0
TWIS1 CLK_TWIS1
Table 22-8. Register Reset Values
Register Reset Value
VR 0x00000100
PR 0x00000000
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23. Two-wire Master Interface (TWIM)
Rev.: 1.0.0.1
23.1 Features
• Compatible with I²C standard
– Multi-master support
– Transfer speeds of 100 and 400 kbit/s
– 7- and 10-bit and General Call addressing
• Compatible with SMBus standard
– Hardware Packet Error Checking (CRC) generation and verification with ACK control
– SMBus ALERT interface
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low extend time
• Compatible with PMBus
• Compatible with Atmel Two-wire Interface Serial Memories
• DMA interface for reducing CPU load
• Arbitrary transfer lengths, including 0 data bytes
• Optional clock stretching if transmit or receive buffers not ready for data transfer
23.2 Overview
The Atmel Two-wire Master Interface (TWIM) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial
EEPROM and I²C compatible device such as a real time clock (RTC), dot matrix/graphic LCD
controller, and temperature sensor, to name a few. The TWIM is always a bus master and can
transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus
is performed internally and relinquishes the bus automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of
core clock frequencies.Table 23-1 lists the compatibility level of the Atmel Two-wire Interface in
Master Mode and a full I²C compatible device.
Table 23-1. Atmel TWIM Compatibility with I²C Standard
I²C Standard Atmel TWIM
Standard-mode (100 kbit/s) Supported
Fast-mode (400 kbit/s) Supported
Fast-mode Plus (1 Mbit/s) Supported
7- or 10-bits Slave Addressing Supported
(1)
START BYTE Not Supported
Repeated Start (Sr) Condition Supported
ACK and NACK Management Supported
Slope Control and Input Filtering (Fast mode) Supported
Clock Stretching Supported
Note: 1. START + b000000001 + Ack + Sr
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Table 23-2 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus
compatible master.
Table 23-2. Atmel TWIM Compatibility with SMBus Standard
SMBus Standard Atmel TWIM
Bus Timeouts Supported
Address Resolution Protocol Supported
Alert Supported
Host Functionality Supported
Packet Error Checking Supported
23.3 List of Abbreviations
Table 23-3. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
P Stop
S Start
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
R Read
W Write
23.4 Block Diagram
Figure 23-1. Block Diagram
Peripheral
Bus Bridge
TWCK
I/O Controller TWD
Two-wire
TWALM
Interface
Power
Manager
CLK_TWIM
INTC
TWI Interrupt
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23.5 Application Block Diagram
Figure 23-2. Application Block Diagram
VDD
Rp Rp Rp
TWD
TWI TWCK
Master
TWALM
Atmel TWI I2C LCD I2C temp
I2C RTC
serial EEPROM controller sensor
Slave 1 Slave 2 Slave 3 Slave 4
Rp: pull-up value as given by the I2C Standard
23.6 I/O Lines Description
Table 23-4. I/O Lines Description
Pin Name Pin Description Type
TWD Two-wire Serial Data Input/Output
TWCK Two-wire Serial Clock Input/Output
TWALM SMBus SMBALERT Input/Output
23.7 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
23.7.1 I/O Lines
TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current
source or pull-up resistor (see Figure 23-4 on page 478). When the bus is free, both lines are
high. The output stages of devices connected to the bus must have an open-drain or open-col-
lector to perform the wired-AND function.
TWALM is used to implement the optional SMBus SMBALERT signal.
The TWALM, TWD, and TWCK pins may be multiplexed with I/O Controller lines. To enable the
TWIM, the user must perform the following steps:
• Program the I/O Controller to:
– Dedicate TWD, TWCK, and optionally TWALM as peripheral lines.
– Define TWD, TWCK, and optionally TWALM as open-drain.
23.7.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the TWIM, the TWIM will stop func-
tioning and resume operation after the system wakes up from sleep mode.
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23.7.3 Clocks
The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state.
23.7.4 DMA
The TWIM DMA handshake interface is connected to the Peripheral DMA Controller. Using the
TWIM DMA functionality requires the Peripheral DMA Controller to be programmed after setting
up the TWIM.
23.7.5 Interrupts
The TWIM interrupt request lines are connected to the interrupt controller. Using the TWIM inter-
rupts requires the interrupt controller to be programmed first.
23.7.6 Debug Operation
When an external debugger forces the CPU into debug mode, the TWIM continues normal oper-
ation. If the TWIM is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.
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23.8 Functional Description
23.8.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
23-4).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
23-4).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 23-3. START and STOP Conditions
TWD
TWCK
Start Stop
Figure 23-4. Transfer Format
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop
23.8.2 Operation
The TWIM has two modes of operation:
• Master transmitter mode
• Master receiver mode
The master is the device which starts and stops a transfer and generates the TWCK clock.
These modes are described in the following chapters.
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23.8.2.1 Clock Generation
The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK
clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR
describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be
selected through the Clock Prescaler field in CWGR (CWGR.EXP).
f CLK_TWIM
f PRESCALER = -------------------------
-
( EXP + 1 )
2
CWGR has the following fields:
LOW: Prescaled clock cycles in clock low count. Used to time TLOW and TBUF.
HIGH: Prescaled clock cycles in clock high count. Used to time THIGH.
STASTO: Prescaled clock cycles in clock high count. Used to time THD_STA, TSU_STA, TSU_STO.
DATA: Prescaled clock cycles for data setup and hold count. Used to time THD_DAT, TSU_DAT.
EXP: Specifies the clock prescaler setting.
Note that the total clock low time generated is the sum of THD_DAT + TSU_DAT + TLOW.
Any slave or other bus master taking part in the transfer may extend the TWCK low period at any
time.
The TWIM hardware monitors the state of the TWCK line as required by the I²C specification.
The clock generation counters are started when a high/low level is detected on the TWCK line,
not when the TWIM hardware releases/drives the TWCK line. This means that the CWGR set-
tings alone do not determine the TWCK frequency. The CWGR settings determine the clock low
time and the clock high time, but the TWCK rise and fall times are determined by the external cir-
cuitry (capacitive load, etc.).
Figure 23-5. Bus Timing Diagram
t HIGH
t LOW
t LOW
t t t t t
HD:STA SU:DAT HD:DAT SU:DAT SU:STO
S P
t
SU:STA
Sr
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23.8.2.2 Setting up and Performing a Transfer
Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Reg-
ister (CMDR). TWIM status is provided in the Status Register (SR). The following list presents
the main steps in a typical communication:
1. Before any transfers can be performed, bus timings must be configured by writing to the
Clock Waveform Generator Register (CWGR). If operating in SMBus mode, the SMBus
Timing Register (SMBTR) register must also be configured.
2. If the Peripheral DMA Controller is to be used for the transfers, it must be set up.
3. CMDR or NCMDR must be written with a value describing the transfer to be performed.
The interrupt system can be set up to give interrupt requests on specific events or error condi-
tions in the SR, for example when the transfer is complete or if arbitration is lost. The Interrupt
Enable Register (IER) and Interrupt Disable Register (IDR) can be written to specify which bits in
the SR will generate interrupt requests.
The SR.BUSFREE bit is set when activity is completed on the two-wire bus. The SR.CRDY bit is
set when CMDR and/or NCMDR is ready to receive one or more commands.
The controller will refuse to start a new transfer while ANAK, DNAK, or ARBLST in the Status
Register (SR) is one. This is necessary to avoid a race when the software issues a continuation
of the current transfer at the same time as one of these errors happen. Also, if ANAK or DNAK
occurs, a STOP condition is sent automatically. The user will have to restart the transmission by
clearing the error bits in SR after resolving the cause for the NACK.
After a data or address NACK from the slave, a STOP will be transmitted automatically. Note
that the VALID bit in CMDR is NOT cleared in this case. If this transfer is to be discarded, the
VALID bit can be cleared manually allowing any command in NCMDR to be copied into CMDR.
When a data or address NACK is returned by the slave while the master is transmitting, it is pos-
sible that new data has already been written to the THR register. This data will be transferred out
as the first data byte of the next transfer. If this behavior is to be avoided, the safest approach is
to perform a software reset of the TWIM.
23.8.3 Master Transmitter Mode
A START condition is transmitted and master transmitter mode is initiated when the bus is free
and CMDR has been written with START=1 and READ=0. START and SADR+W will then be
transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The
master polls the data line during this clock pulse and sets the Address Not Acknowledged bit
(ANAK) in the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
1. Wait until THR contains a valid data byte, stretching low period of TWCK. SR.TXRDY
indicates the state of THR. Software or the Peripheral DMA Controller must write the
data byte to THR.
2. Transmit this data byte
3. Decrement NBYTES
4. If (NBYTES==0) and STOP=1, transmit STOP condition
Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data
bytes, ie START, SADR+W, STOP.
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TWI transfers require the slave to acknowledge each received data byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not
acknowledge the data byte. As with the other status bits, an interrupt can be generated if
enabled in the Interrupt Enable Register (IER).
TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of a command is marked when the TWIM sets the SR.CCOMP bit. See Figure 23-6 and
Figure 23-7.
Figure 23-6. Master Write with One Data Byte
TWD S DADR W A DATA A P
SR.IDLE
TXRDY
Write THR (DATA) STOP sent automatically
NBYTES set to 1 (ACK received and NBYTES=0)
Figure 23-7. Master Write with Multiple Data Bytes
TWD S DADR W A DATAn A DATAn+5 A DATAn+m A P
SR.IDLE
TXRDY
Write THR Write THR STOP sent automatically
Write THR (ACK received and NBYTES=0)
(DATAn+1) (DATAn+m)
(DATAn)
Last data sent
NBYTES set to n
23.8.4 Master Receiver Mode
A START condition is transmitted and master receiver mode is initiated when the bus is free and
CMDR has been written with START=1 and READ=1. START and SADR+R will then be trans-
mitted. During the address acknowledge clock pulse (9th pulse), the master releases the data
line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master
polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in
the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
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1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state
of RHR. Software or the Peripheral DMA Controller must read any data byte present in
RHR.
2. Release TWCK generating a clock that the slave uses to transmit a data byte.
3. Place the received data byte in RHR, set RXRDY.
4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK.
5. Decrement NBYTES
6. If (NBYTES==0) and STOP=1, transmit STOP condition.
Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data
bytes, ie START, DADR+R, STOP
The TWI transfers require the master to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the mas-
ter to pull it down in order to generate the acknowledge. All data bytes except the last are
acknowledged by the master. Not acknowledging the last byte informs the slave that the transfer
is finished.
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 23-8. Master Read with One Data Byte
TWD S DADR R A DATA N P
SR.IDLE
RXRDY
Write START & Read RHR
STOP bit
NBYTES set to 1
Figure 23-9. Master Read with Multiple Data Bytes
TWD S DADR R A DATAn A DATAn+1 DATAn+m-1 A DATAn+m N P
SR.IDLE
RXRDY
Write START +
STOP bit
Read RHR Read RHR Read RHR Read RHR
NBYTES set to m DATAn DATAn+m-2 DATAn+m-1 DATAn+m
Send STOP
When NBYTES=0
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23.8.5 Using the Peripheral DMA Controller
The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set
up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space
to place received data.
To assure correct behavior, respect the following programming sequences:
23.8.5.1 Data Transmit with the Peripheral DMA Controller
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to transmit.
4. Wait for the Peripheral DMA Controller end-of-transmit flag.
5. Disable the Peripheral DMA Controller.
23.8.5.2 Data Receive with the Peripheral DMA Controller
1. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to receive.
4. Wait for the Peripheral DMA Controller end-of-receive flag.
5. Disable the Peripheral DMA Controller.
23.8.6 Multi-master Mode
More than one master may access the bus at the same time without data corruption by using
arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time,
and stops (arbitration is lost) for the master that intends to send a logical one while the other
master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to
detect a STOP. The SR.ARBLST flag will be set. When the STOP is detected, the master who
lost arbitration may reinitiate the data transfer.
Arbitration is illustrated in Figure 23-11.
If the user starts a transfer and if the bus is busy, the TWIM automatically waits for a STOP con-
dition on the bus before initiating the transfer (see Figure 23-10).
Note: The state of the bus (busy or free) is not indicated in the user interface.
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Figure 23-10. User Sends Data While the Bus is Busy
TWCK
STOP sent by the master START sent by the TWI
TWD DATA sent by a master DATA sent by the TWI
Bus is busy
Bus is free
TWI DATA transfer Transfer is kept
A transfer is programmed Bus is considered as free
(DADR + W + START + Write THR) Transfer is initiated
Figure 23-11. Arbitration Cases
TWCK
TWD
TWCK
Arbitration is lost
Data from a Master S 1 0 0 1 1 P S 1 0 1
The master stops sending data
Arbitration is lost
Data from TWI S 1 0 1 S 1 0 0 1 1
TWI stops sending data
TWD S 1 0 0 1 1 Data from the master P S 1 0 0 1 1 Data from the TWI
ARBLST
Bus is busy Bus is free
TWI DATA transfer Transfer is kept
A transfer is programmed Transfer is stopped Bus is considered as free
Transfer is programmed again Transfer is initiated
(DADR + W + START + Write THR)
(DADR + W + START + Write THR)
23.8.7 Combined Transfers
CMDR and NCMDR may be used to generate longer sequences of connected transfers, since
generation of START and/or STOP conditions is programmable on a per-command basis.
Writing NCMDR with START=1 when the previous transfer was written with STOP=0 will cause
a REPEATED START on the bus. The ability to generate such connected transfers allows arbi-
trary transfer lengths, since it is legal to write CMDR with both START=0 and STOP=0. If this is
done in master receiver mode, the CMDR.ACKLAST bit must also be controlled.
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As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when
data to transmit can be written to THR, or when received data can be read from RHR. Transfer
of data to THR and from RHR can also be done automatically by DMA, see Section 23.8.5
23.8.7.1 Write Followed by Write
Consider the following transfer:
START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP.
To generate this transfer:
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
5. Wait until SR.TXRDY==1, then write third data byte to transfer to THR.
6. Wait until SR.TXRDY==1, then write fourth data byte to transfer to THR.
23.8.7.2 Read Followed by Read
Consider the following transfer:
START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+R, DATA+A, DATA+NA, STOP.
To generate this transfer:
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1.
3. Wait until SR.RXRDY==1, then read first data byte received from RHR.
4. Wait until SR.RXRDY==1, then read second data byte received from RHR.
5. Wait until SR.RXRDY==1, then read third data byte received from RHR.
6. Wait until SR.RXRDY==1, then read fourth data byte received from RHR.
If combining several transfers, without any STOP or REPEATED START between them, remem-
ber to write a one to the ACKLAST bit in CMDR to keep from ending each of the partial transfers
with a NACK.
23.8.7.3 Write Followed by Read
Consider the following transfer:
START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+R, DATA+A, DATA+NA, STOP.
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Figure 23-12. Combining a Write and Read Transfer
THR DATA0 DATA1
RHR DATA2 DATA3
TWD S DADR W A DATA0 A DATA1 NA Sr DADR R A DATA2 A DATA3 A P
SR.IDLE 1
TXRDY
RXRDY
To generate this transfer:
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1.
3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
5. Wait until SR.RXRDY==1, then read first data byte received from RHR.
6. Wait until SR.RXRDY==1, then read second data byte received from RHR.
23.8.7.4 Read Followed by Write
Consider the following transfer:
START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+W, DATA+A, DATA+A, STOP.
Figure 23-13. Combining a Read and Write Transfer
THR DATA2 DATA3
RHR DATA0 DATA3
1
TWD S SADR R A DATA0 A DATA1 A Sr DADR W A DATA2 A DATA3 NA P
SR.IDLE 2
TXRDY
Read
RXRDY TWI_RHR
To generate this transfer:
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.RXRDY==1, then read first data byte received from RHR.
4. Wait until SR.RXRDY==1, then read second data byte received from RHR.
5. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
6. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
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23.8.8 Ten Bit Addressing
Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers
with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of
CMDR.SADR must be written appropriately.
In Figure 23-14 and Figure 23-15, the grey boxes represent signals driven by the master, the
white boxes are driven by the slave.
23.8.8.1 Master Transmitter
To perform a master transmitter transfer:
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the
desired address and NBYTES value.
Figure 23-14. A Write Transfer with 10-bit Addressing
1 1 1 1 0 X X 0
SLAVE ADDRESS SLAVE ADDRESS
S RW A1 A2 DATA A DATA AA P
1st 7 bits 2nd byte
23.8.8.2 Master Receiver
When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be con-
trolled. CMDR.REPSAME must be written to one when the address phase of the transfer should
consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard
specifies that such addressing is required when addressing a slave for reads using 10-bit
addressing.
To perform a master receiver transfer:
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0,
NBYTES=0 and the desired address.
2. Write NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the
desired address and NBYTES value.
Figure 23-15. A Read Transfer with 10-bit Addressing
1 1 1 1 0 X X 0 1 1 1 1 0 X X 1
SLAVE ADDRESS SLAVE ADDRESS SLAVE ADDRESS
S RW A1 A2 Sr RW A3 DATA A DATA A P
1st 7 bits 2nd byte 1st 7 bits
23.8.9 SMBus Mode
SMBus mode is enabled and disabled by writing to the SMEN and SMDIS bits in CR. SMBus
mode operation is similar to I²C operation with the following exceptions:
• Only 7-bit addressing can be used.
• The SMBus standard describes a set of timeout values to ensure progress and throughput on
the bus. These timeout values must be written into SMBTR.
• Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
• A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.
• A set of addresses have been reserved for protocol handling, such as Alert Response
Address (ARA) and Host Header (HH) Address.
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23.8.9.1 Packet Error Checking
Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to
CMDR.PECEN enables automatic PEC handling in the current transfer. Transfers with and with-
out PEC can freely be intermixed in the same system, since some slaves may not support PEC.
The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on
combined transfers will be correct.
In master transmitter mode, the master calculates a PEC value and transmits it to the slave after
all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it
to the PEC value it has computed itself. If the values match, the data was received correctly, and
the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the
slave will return a NACK value. The DNAK bit in SR reflects the state of the last received
ACK/NACK value. Some slaves may not be able to check the received PEC in time to return a
NACK if an error occurred. In this case, the slave should always return an ACK after the PEC
byte, and some other mechanism must be implemented to verify that the transmission was
received correctly.
In master receiver mode, the slave calculates a PEC value and transmits it to the master after all
data bytes have been transmitted. Upon reception of this PEC byte, the master will compare it to
the PEC value it has computed itself. If the values match, the data was received correctly. If the
PEC values differ, data was corrupted, and SR.PECERR is set. In master receiver mode, the
PEC byte is always followed by a NACK transmitted by the master, since it is the last byte in the
transfer.
The PEC byte is automatically inserted in a master transmitter transmission if PEC is enabled
when NBYTES reaches zero. The PEC byte is identified in a master receiver transmission if
PEC is enabled when NBYTES reaches zero. NBYTES must therefore be written with the total
number of data bytes in the transmission, including the PEC byte.
In combined transfers, the PECEN bit should only be written to one in the last of the combined
transfers. Consider the following transfer:
S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P
This transfer is generated by writing two commands to the command registers. The first com-
mand is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2 and
PECEN=1.
Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current
byte. No PEC byte will be sent in this case.
23.8.9.2 Timeouts
The TLOWS and TLOWM fields in SMBTR configure the SMBus timeout values. If a timeout
occurs, the master will transmit a STOP condition and leave the bus. The SR.TOUT bit is set.
23.8.9.3 SMBus ALERT Signal
A slave can get the master’s attention by pulling the TWALM line low. The TWIM will then set the
SR.SMBALERT bit. This can be set up to trigger an interrupt, and software can then take the
appropriate action, as defined in the SMBus standard.
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23.8.10 Identifying Bus Events
This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is
intended to help writing drivers for the TWIM.
Table 23-5. Bus Events
Event Effect
Master transmitter has sent
SR.THR is cleared.
a data byte
Master receiver has
SR.RHR is set.
received a data byte
SR.ANAK is set.
Start+Sadr sent, no ack SR.CCOMP not set.
received from slave CMDR.VALID remains set.
STOP automatically transmitted on bus.
SR.DNAK is set.
Data byte sent to slave, no SR.CCOMP not set.
ack received from slave CMDR.VALID remains set.
STOP automatically transmitted on bus.
SR.ARBLST is set.
SR.CCOMP not set.
Arbitration lost
CMDR.VALID remains set.
TWCK and TWD immediately released to a pulled-up state.
SMBus Alert received SR.SMBALERT is set.
SR.SMBTOUT is set.
SR.CCOMP not set.
SMBus timeout received
CMDR.VALID remains set.
STOP automatically transmitted on bus.
SR.DNAK is set.
Master transmitter receives SR.CCOMP not set.
SMBus PEC Error CMDR.VALID remains set.
STOP automatically transmitted on bus.
SR.PECERR is set.
Master receiver discovers SR.CCOMP not set.
SMBus PEC Error CMDR.VALID remains set.
STOP automatically transmitted on bus.
SR.STOP is set.
SR.CCOMP set.
CR.STOP is written by user
CMDR.VALID remains set.
STOP transmitted on bus after current byte transfer has finished.
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23.9 User Interface
Table 23-6. TWIM Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Clock Waveform Generator Register CWGR Read/Write 0x00000000
0x08 SMBus Timing Register SMBTR Read/Write 0x00000000
0x0C Command Register CMDR Read/Write 0x00000000
0x10 Next Command Register NCMDR Read/Write 0x00000000
0x14 Receive Holding Register RHR Read-only 0x00000000
0x18 Transmit Holding Register THR Write-only 0x00000000
0x1C Status Register SR Read-only 0x00000002
0x20 Interrupt Enable Register IER Write-only 0x00000000
0x24 Interrupt Disable Register IDR Write-only 0x00000000
0x28 Interrupt Mask Register IMR Read-only 0x00000000
0x2C Status Clear Register SCR Write-only 0x00000000
0x30 Parameter Register PR Read-only -(1)
0x34 Version Register VR Read-only -(1)
Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this
chapter.
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23.9.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - STOP
7 6 5 4 3 2 1 0
SWRST - SMDIS SMEN - - MDIS MEN
• STOP: Stop the Current Transfer
Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are
additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully
sent.
Writing a zero to this bit has no effect.
• SWRST: Software Reset
If the TWIM master interface is enabled, writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly
violating the bus semantics.
If the TWIM master interface is not enabled, it must first be enabled before writing a one to this bit.
Writing a zero to this bit has no effect.
• SMDIS: SMBus Disable
Writing a one to this bit disables SMBus mode.
Writing a zero to this bit has no effect.
• SMEN: SMBus Enable
Writing a one to this bit enables SMBus mode.
Writing a zero to this bit has no effect.
• MDIS: Master Disable
Writing a one to this bit disables the master interface.
Writing a zero to this bit has no effect.
• MEN: Master Enable
Writing a one to this bit enables the master interface.
Writing a zero to this bit has no effect.
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23.9.2 Clock Waveform Generator Register
Name: CWGR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- EXP DATA
23 22 21 20 19 18 17 16
STASTO
15 14 13 12 11 10 9 8
HIGH
7 6 5 4 3 2 1 0
LOW
• EXP: Clock Prescaler
Used to specify how to prescale the TWCK clock. Counters are prescaled according to the following formula
f CLK_TWIM
f PRESCALER = -------------------------
-
( EXP + 1 )
2
• DATA: Data Setup and Hold Cycles
Clock cycles for data setup and hold count. Prescaled by CWGR.EXP. Used to time THD_DAT, TSU_DAT.
• STASTO: START and STOP Cycles
Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THD_STA, TSU_STA, TSU_STO
• HIGH: Clock High Cycles
Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THIGH.
• LOW: Clock Low Cycles
Clock cycles in clock low count. Prescaled by CWGR.EXP. Used to time TLOW, TBUF.
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23.9.3 SMBus Timing Register
Name: SMBTR
Access Type: Read/Write
Offset: 0x08
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
EXP - - - -
23 22 21 20 19 18 17 16
THMAX
15 14 13 12 11 10 9 8
TLOWM
7 6 5 4 3 2 1 0
TLOWS
• EXP: SMBus Timeout Clock Prescaler
Used to specify how to prescale the TIM and TLOWM counters in SMBTR. Counters are prescaled according to the following
formula
f CLKTWIM
f prescaled, SMBus = ------------------------
( EXP + 1 )
2
• THMAX: Clock High Maximum Cycles
Clock cycles in clock high maximum count. Prescaled by SMBTR.EXP. Used for bus free detection. Used to time THIGH:MAX.
NOTE: Uses the prescaler specified by CWGR, NOT the prescaler specified by SMBTR.
• TLOWM: Master Clock Stretch Maximum Cycles
Clock cycles in master maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:MEXT
• TLOWS: Slave Clock Stretch Maximum Cycles
Clock cycles in slave maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:SEXT.
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23.9.4 Command Register
Name: CMDR
Access Type: Read/Write
Offset: 0x0C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - ACKLAST PECEN
23 22 21 20 19 18 17 16
NBYTES
15 14 13 12 11 10 9 8
VALID STOP START REPSAME TENBIT SADR[9:7]
7 6 5 4 3 2 1 0
SADR[6:0] READ
• ACKLAST: ACK Last Master RX Byte
0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the standard way of
ending a master receiver transfer.
1: Causes the last byte in master receive mode (when NBYTES has reached 0) to be ACKed. Used for performing linked
transfers in master receiver mode with no STOP or REPEATED START between the subtransfers. This is needed when more
than 255 bytes are to be received in one single transmission.
• PECEN: Packet Error Checking Enable
0: Causes the transfer not to use PEC byte verification. The PEC LFSR is still updated for every bit transmitted or received. Must
be used if SMBus mode is disabled.
1: Causes the transfer to use PEC. PEC byte generation (if master transmitter) or PEC byte verification (if master receiver) will
be performed.
• NBYTES: Number of Data Bytes in Transfer
The number of data bytes in the transfer. After the specified number of bytes have been transferred, a STOP condition is
transmitted if CMDR.STOP is one. In SMBus mode, if PEC is used, NBYTES includes the PEC byte, i.e. there are NBYTES-1
data bytes and a PEC byte.
• VALID: CMDR Valid
0: Indicates that CMDR does not contain a valid command.
1: Indicates that CMDR contains a valid command. This bit is cleared when the command is finished.
• STOP: Send STOP Condition
0: Do not transmit a STOP condition after the data bytes have been transmitted.
1: Transmit a STOP condition after the data bytes have been transmitted.
• START: Send START Condition
0: The transfer in CMDR should not commence with a START or REPEATED START condition.
1: The transfer in CMDR should commence with a START or REPEATED START condition. If the bus is free when the command
is executed, a START condition is used. If the bus is busy, a REPEATED START is used.
• REPSAME: Transfer is to Same Address as Previous Address
Only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode.
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Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous
transfer in order to enter master receiver mode.
Write this bit to zero otherwise.
• TENBIT: Ten Bit Addressing Mode
0: Use 7-bit addressing mode.
1: Use 10-bit addressing mode. Must not be used when the TWIM is in SMBus mode.
• SADR: Slave Address
Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used.
• READ: Transfer Direction
0: Allow the master to transmit data.
1: Allow the master to receive data.
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23.9.5 Next Command Register
Name: NCMDR
Access Type: Read/Write
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - ACKLAST PECEN
23 22 21 20 19 18 17 16
NBYTES
15 14 13 12 11 10 9 8
VALID STOP START REPSAME TENBIT SADR[9:7]
7 6 5 4 3 2 1 0
SADR[6:0] READ
This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR,
clearing the VALID bit in NCMDR. If the VALID bit in CMDR is cleared when NCMDR is written, the content is copied
immediately.
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23.9.6 Receive Holding Register
Name: RHR
Access Type: Read-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
RXDATA
• RXDATA: Received Data
When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
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23.9.7 Transmit Holding Register
Name: THR
Access Type: Write-only
Offset: 0x18
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
TXDATA
• TXDATA: Data to Transmit
Write data to be transferred on the TWI bus here.
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23.9.8 Status Register
Name: SR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000002
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - MENB
15 14 13 12 11 10 9 8
- STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK
7 6 5 4 3 2 1 0
- - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY
• MENB: Master Interface Enable
0: Master interface is disabled.
1: Master interface is enabled.
• STOP: Stop Request Accepted
This bit is one when a STOP request caused by writing a one to CR.STOP has been accepted, and transfer has stopped.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• PECERR: PEC Error
This bit is one when a SMBus PEC error occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• TOUT: Timeout
This bit is one when a SMBus timeout occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• SMBALERT: SMBus Alert
This bit is one when an SMBus Alert was received.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• ARBLST: Arbitration Lost
This bit is one when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority
transmission in progress by a different master.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• DNAK: NAK in Data Phase Received
This bit is one when no ACK was received form slave during data transmission.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• ANAK: NAK in Address Phase Received
This bit is one when no ACK was received from slave during address phase
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• BUSFREE: Two-wire Bus is Free
This bit is one when activity has completed on the two-wire bus.
Otherwise, this bit is cleared.
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• IDLE: Master Interface is Idle
This bit is one when no command is in progress, and no command waiting to be issued.
Otherwise, this bit is cleared.
• CCOMP: Command Complete
This bit is one when the current command has completed successfully.
This bit is zero if the command failed due to conditions such as a NAK receved from slave.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• CRDY: Ready for More Commands
This bit is one when CMDR and/or NCMDR is ready to receive one or more commands.
This bit is cleared when this is no longer true.
• TXRDY: THR Data Ready
This bit is one when THR is ready for one or more data bytes.
This bit is cleared when this is no longer true (i.e. THR is full or transmission has stopped).
• RXRDY: RHR Data Ready
This bit is one when RX data are ready to be read from RHR.
This bit is cleared when this is no longer true.
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23.9.9 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x20
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - PECERR TOUT SMBALERT ARBLST DNAK ANAK
7 6 5 4 3 2 1 0
- - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR
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23.9.10 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x24
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - PECERR TOUT SMBALERT ARBLST DNAK ANAK
7 6 5 4 3 2 1 0
- - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR
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23.9.11 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x28
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - PECERR TOUT SMBALERT ARBLST DNAK ANAK
7 6 5 4 3 2 1 0
- - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is written to one.
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23.9.12 Status Clear Register
Name: SCR
Access Type : Write-only
Offset: 0x2C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK
7 6 5 4 3 2 1 0
- - - - CCOMP - - -
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
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23.9.13 Parameter Register (PR)
Name: PR
Access Type: Read-only
Offset: 0x30
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -
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23.9.14 Version Register (VR)
Name: VR
Access Type: Read-only
Offset: 0x34
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION [11:8]
7 6 5 4 3 2 1 0
VERSION [7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
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23.10 Module Configuration
The specific configuration for each TWIM instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 23-7. Module Clock Name
Module name Clock name
TWIM0 CLK_TWIM0
TWIM1 CLK_TWIM1
Table 23-8. Register Reset Values
Register Reset Value
VR 0x00000100
PR 0x00000000
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24. Synchronous Serial Controller (SSC)
Rev: 3.2.0.2
24.1 Features
• Provides serial synchronous communication links used in audio and telecom applications
• Independent receiver and transmitter, common clock divider
• Interfaced with two Peripheral DMA Controller channels to reduce processor overhead
• Configurable frame sync and data length
• Receiver and transmitter can be configured to start automatically or on detection of different
events on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
24.2 Overview
The Synchronous Serial Controller (SSC) provides a synchronous communication link with
external devices. It supports many serial synchronous communication protocols generally used
in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC consists of a receiver, a transmitter, and a common clock divider. Both the receiver
and the transmitter interface with three signals:
• the TX_DATA/RX_DATA signal for data
• the TX_CLOCK/RX_CLOCK signal for the clock
• the TX_FRAME_SYNC/RX_FRAME_SYNC signal for the frame synchronization
The transfers can be programmed to start automatically or on different events detected on the
Frame Sync signal.
The SSC’s high-level of programmability and its two dedicated Peripheral DMA Controller chan-
nels of up to 32 bits permit a continuous high bit rate data transfer without processor
intervention.
Featuring connection to two Peripheral DMA Controller channels, the SSC permits interfacing
with low processor overhead to the following:
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader
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24.3 Block Diagram
Figure 24-1. SSC Block Diagram
High
Speed
Bus
Peripheral Bus
Bridge
Peripheral DMA
Controller
Peripheral
Bus
TX_FRAME_SYNC
TX_CLOCK
TX_DATA
Power CLK_SSC
Manager I/O
SSC Interface Controller
RX_FRAME_SYNC
RX_CLOCK
Interrupt Control
RX_DATA
SSC Interrupt
24.4 Application Block Diagram
Figure 24-2. SSC Application Block Diagram
Power Interrupt Test
OS or RTOS Driver
Management Management Management
SSC
Time Slot Frame
Serial AUDIO Codec Line Interface
Management Management
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24.5 I/O Lines Description
Table 24-1. I/O Lines Description
Pin Name Pin Description Type
RX_FRAME_SYNC Receiver Frame Synchro Input/Output
RX_CLOCK Receiver Clock Input/Output
RX_DATA Receiver Data Input
TX_FRAME_SYNC Transmitter Frame Synchro Input/Output
TX_CLOCK Transmitter Clock Input/Output
TX_DATA Transmitter Data Output
24.6 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
24.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.
Before using the SSC receiver, the I/O Controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the I/O Controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
24.6.2 Clocks
The clock for the SSC bus interface (CLK_SSC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SSC before disabling the clock, to avoid freezing the SSC in an undefined state.
24.6.3 Interrupts
The SSC interrupt request line is connected to the interrupt controller. Using the SSC interrupt
requires the interrupt controller to be programmed first.
24.7 Functional Description
This chapter contains the functional description of the following: SSC functional block, clock
management, data framing format, start, transmitter, receiver, and frame sync.
The receiver and the transmitter operate separately. However, they can work synchronously by
programming the receiver to use the transmit clock and/or to start a data transfer when transmis-
sion starts. Alternatively, this can be done by programming the transmitter to use the receive
clock and/or to start a data transfer when reception starts. The transmitter and the receiver can
be programmed to operate with the clock signals provided on either the TX_CLOCK or
RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. The maxi-
mum clock speed allowed on the TX_CLOCK and RX_CLOCK pins is CLK_SSC divided by two.
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Figure 24-3. SSC Functional Block Diagram
Transmitter
Clock Output TX_CLOCK
Controller
TX_CLOCK Input
CLK_SSC Clock Transmit Clock TX clock Frame Sync TX_FRAME_SYNC
Divider Controller Controller
RX clock
TX_FRAME_SYNC
Start TX_DATA
RX_FRAME_SYNC Transmit Shift Register
Selector
Peripheral TX_DMA Transmit Holding Transmit Sync
Bus Register Holding Register
Load Shift
User
Interface
Receiver
Clock Output
RX_CLOCK
Controller
RX_CLOCK
Input Receive Clock RX clock Frame Sync
Controller Controller RX_FRAME_SYNC
TX clock
TX_FRAME_SYNC
Start
Receive Shift Register RX_DATA
RX_FRAME_SYNC Selector
RX_DMA Receive Holding Receive Sync
Register Holding Register
DMA Interrupt Control
Load Shift
Interrupt Controller
24.7.1 Clock Management
The transmitter clock can be generated by:
• an external clock received on the TX_CLOCK pin
• the receiver clock
• the internal clock divider
The receiver clock can be generated by:
• an external clock received on the RX_CLOCK pin
• the transmitter clock
• the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TX_CLOCK pin, and
the receiver block can generate an external clock on the RX_CLOCK pin.
This allows the SSC to support many Master and Slave Mode data transfers.
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24.7.1.1 Clock divider
Figure 24-4. Divided Clock Block Diagram
Clock Divider
CMR
CLK_SSC Divided Clock
/2 12-bit Counter
The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is
4095) in the Clock Mode Register (CMR.DIV), allowing a peripheral clock division by up to 8190.
The divided clock is provided to both the receiver and transmitter. When this field is written to
zero, the clock divider is not used and remains inactive.
When CMR.DIV is written to a value equal to or greater than one, the divided clock has a fre-
quency of CLK_SSC divided by two times CMR.DIV. Each level of the divided clock has a
duration of the peripheral clock multiplied by CMR.DIV. This ensures a 50% duty cycle for the
divided clock regardless of whether the CMR.DIV value is even or odd.
Figure 24-5. Divided Clock Generation
CLK_SSC
Divided Clock
DIV = 1
Divided Clock Frequency = CLK_SSC/2
CLK_SSC
Divided Clock
DIV = 3
Divided Clock Frequency = CLK_SSC/6
Table 24-2. Range of Clock Divider
Maximum Minimum
CLK_SSC / 2 CLK_SSC / 8190
24.7.1.2 Transmitter clock management
The transmitter clock is generated from the receiver clock, the divider clock, or an external clock
scanned on the TX_CLOCK pin. The transmitter clock is selected by writing to the Transmit
Clock Selection field in the Transmit Clock Mode Register (TCMR.CKS). The transmit clock can
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be inverted independently by writing a one to the Transmit Clock Inversion bit in TCMR
(TCMR.CKI).
The transmitter can also drive the TX_CLOCK pin continuously or be limited to the actual data
transfer, depending on the Transmit Clock Output Mode Selection field in the TCMR register
(TCMR.CKO). The TCMR.CKI bit has no effect on the clock outputs.
Writing 0b10 to the TCMR.CKS field to select TX_CLOCK pin and 0b001 to the TCMR.CKO field
to select Continuous Transmit Clock can lead to unpredictable results.
Figure 24-6. Transmitter Clock Management
TX_CLOCK
MUX Tri-state Clock
Controller Output
Receiver
Clock
Divider
Clock
CKO Data Transfer
CKS INV Tri-state Transmitter
MUX Controller Clock
CKI CKG
24.7.1.3 Receiver clock management
The receiver clock is generated from the transmitter clock, the divider clock, or an external clock
scanned on the RX_CLOCK pin. The receive clock is selected by writing to the Receive Clock
Selection field in the Receive Clock Mode Register (RCMR.CKS). The receive clock can be
inverted independently by writing a one to the Receive Clock Inversion bit in RCMR
(RCMR.CKI).
The receiver can also drive the RX_CLOCK pin continuously or be limited to the actual data
transfer, depending on the Receive Clock Output Mode Selection field in the RCMR register
(RCMR.CKO). The RCMR.CKI bit has no effect on the clock outputs.
Writing 0b10 to the RCMR.CKS field to select RX_CLOCK pin and 0b001 to the RCMR.CKO
field to select Continuous Receive Clock can lead to unpredictable results.
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Figure 24-7. Receiver Clock Management
RX_CLOCK
MUX Tri-state Clock
Controller Output
Transmitter
Clock
Divider
Clock
CKO Data Transfer
CKS INV Tri-state
MUX Controller Receiver
Clock
CKI CKG
24.7.1.4 Serial clock ratio considerations
The transmitter and the receiver can be programmed to operate with the clock signals provided
on either the TX_CLOCK or RX_CLOCK pins. This allows the SSC to support many slave-mode
data transfers. In this case, the maximum clock speed allowed on the RX_CLOCK pin is:
– CLK_SSC divided by two if RX_FRAME_SYNC is input.
– CLK_SSC divided by three if RX_FRAME_SYNC is output.
In addition, the maximum clock speed allowed on the TX_CLOCK pin is:
– CLK_SSC divided by six if TX_FRAME_SYNC is input.
– CLK_SSC divided by two if TX_FRAME_SYNC is output.
24.7.2 Transmitter Operations
A transmitted frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by writing to the TCMR register. See Section 24.7.4.
The frame synchronization is configured by writing to the Transmit Frame Mode Register
(TFMR). See Section 24.7.5.
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and
the start mode selected in the TCMR register. Data is written by the user to the Transmit Holding
Register (THR) then transferred to the shift register according to the data format selected.
When both the THR and the transmit shift registers are empty, the Transmit Empty bit is set in
the Status Register (SR.TXEMPTY). When the THR register is transferred in the transmit shift
register, the Transmit Ready bit is set in the SR register (SR.TXREADY) and additional data can
be loaded in the THR register.
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Figure 24-8. Transmitter Block Diagram
CR.TXEN
SR.TXEN
CR.TXDIS
TFMR.DATDEF TCMR.STTDLY
TFMR.FSDEN
TFMR.DATNB
1
TX_FRAME_SYNC TX_DATA
TFMR.MSBF 0
RX_FRAME_SYNC
Transmitter Clock
Start
Transmit Shift Register
Selector
TFMR.FSDEN 0 1
TCMR.STTDLY
TFMR.DATLEN THR TSHR TFMR.FSLEN
24.7.3 Receiver Operations
A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by writing to the RCMR register. See Section 24.7.4.
The frame synchronization is configured by writing to the Receive Frame Mode Register
(RFMR). See Section 24.7.5.
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the RCMR register. The data is transferred from the shift register depending on the
data format selected.
When the receiver shift register is full, the SSC transfers this data in the Receive Holding Regis-
ter (RHR), the Receive Ready bit is set in the SR register (SR.RXREADY) and the data can be
read in the RHR register. If another transfer occurs before a read of the RHR register , the
Receive Overrun bit is set in the SR register (SR.OVRUN) and the receiver shift register is trans-
ferred to the RHR register.
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Figure 24-9. Receiver Block Diagram
RX_CLO C K
MUX T ri-sta te C lo ck
C o n tro lle r O u tp u t
T ra n sm itte r
C lo ck
D ivid e r
C lo ck
CKO D a ta T ra n sfe r
CKS IN V T ri-sta te
MUX C o n tro lle r R e ce ive r
C lo ck
CKI CKG
24.7.4 Start
The transmitter and receiver can both be programmed to start their operations when an event
occurs, respectively in the Transmit Start Selection field of the TCMR register (TCMR.START)
and in the Receive Start Selection field of the RCMR register (RCMR.START).
Under the following conditions the start event is independently programmable:
• Continuous: in this case, the transmission starts as soon as a word is written to the THR
register and the reception starts as soon as the receiver is enabled
• Synchronously with the transmitter/receiver
• On detection of a falling/rising edge on TX_FRAME_SYNC/RX_FRAME_SYNC
• On detection of a low/high level on TX_FRAME_SYNC/RX_FRAME_SYNC
• On detection of a level change or an edge on TX_FRAME_SYNC/RX_FRAME_SYNC
A start can be programmed in the same manner on either side of the Transmit/Receive Clock
Mode Register (TCMR/RCMR). Thus, the start could be on TX_FRAME_SYNC (transmit) or
RX_FRAME_SYNC (receive).
Moreover, the receiver can start when data is detected in the bit stream with the compare func-
tions. See Section 24.7.6 for more details on receive compare modes.
Detection on TX_FRAME_SYNC input/output is done by the Transmit Frame Sync Output
Selection field in the TFMR register (TFMR.FSOS). Similarly, detection on RX_FRAME_SYNC
input/output is done by the Receive Frame Output Sync Selection field in the RFMR register
(RFMR.FSOS).
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Figure 24-10. Transmit Start Mode
TX_CLOCK (Input)
TX_FRAME_SYNC (Input)
TX_DATA (Output)
Start= Low Level on TX_FRAME_SYNC X B0 B1
STTDLY
TX_DATA (Output) B0 B1
X
Start= Falling Edge on TX_FRAME_SYNC STTDLY
TX_DATA (Output) X B0 B1
Start= High Level on TX_FRAME_SYNC STTDLY
TX_DATA (Output) B0 B1
X
Start= Rising Edge on TX_FRAME_SYNC STTDLY
TX_DATA (Output)
Start= Level Change on TX_FRAME_SYNC X B0 B1 B0 B1
STTDLY
TX_DATA (Output)
X B0 B1 B0 B1
Start= Any Edge on TX_FRAME_SYNC STTDLY
Figure 24-11. Receive Pulse/Edge Start Modes
RX_CLOCK
RX_FRAME_SYNC (Input)
RX_DATA (Input)
Start = Low Level on RX_FRAME_SYNC X
STTDLY
RX_DATA (Input)
X B0 B1
Start = Falling Edge on RX_FRAME_SYNC STTDLY
RX_DATA (Input)
X B0 B1
Start = High Level on RX_FRAME_SYNC STTDLY
RX_DATA (Input)
X B0 B1
Start = Rising Edge on RX_FRAME_SYNC STTDLY
RX_DATA (Input)
X B0 B1 B0 B1
Start = Level Change on RX_FRAME_SYNC STTDLY
RX_DATA (Input)
Start = Any Edge on RX_FRAME_SYNC X B0 B1 B0 B1
STTDLY
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24.7.5 Frame Sync
The transmitter and receiver frame synchro pins, TX_FRAME_SYNC and RX_FRAME_SYNC,
can be programmed to generate different kinds of frame synchronization signals. The
RFMR.FSOS and TFMR.FSOS fields are used to select the required waveform.
• Programmable low or high levels during data transfer are supported.
• Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, in reception, the Receive Frame Sync Length High Part and the
Receive Frame Sync Length fields in the RFMR register (RFMR.FSLENHI and RFMR.FSLEN)
define the length of the pulse, from 1 bit time up to 256 bit time.
Reception Pulse Length = ((16 × FSLENHI ) + FSLEN + 1) receive clock periods
Similarly, in transmission, the Transmit Frame Sync Length High Part and the Transmit Frame
Sync Length fields in the TFMR register (TFMR.FSLENHI and TFMR.FSLEN) define the length
of the pulse, from 1 bit up to 256 bit time.
Transmission Pulse Length = ((16 × FSLENHI ) + FSLEN + 1) transmit clock periods
The periodicity of the RX_FRAME_SYNC and TX_FRAME_SYNC pulse outputs can be config-
ured respectively through the Receive Period Divider Selection field in the RCMR register
(RCMR.PERIOD) and the Transmit Period Divider Selection field in the TCMR register
(TCMR.PERIOD).
24.7.5.1 Frame sync data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the receiver can sample the RX_DATA line and store the data in
the Receive Sync Holding Register (RSHR) and the transmitter can transfer the Transmit Sync
Holding Register (TSHR) in the shifter register.
The data length to be sampled in reception during the Frame Sync signal shall be written to the
RFMR.FSLENHI and RFMR.FSLEN fields.
The data length to be shifted out in transmission during the Frame Sync signal shall be written to
the TFMR.FSLENHI and TFMR.FSLEN fields.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or
lower than the delay between the start event and the actual data reception, the data sampling
operation is performed in the RSHR through the receive shift register.
The Transmit Frame Sync operation is performed by the transmitter only if the Frame Sync Data
Enable bit in TFMR register (TFMR.FSDEN) is written to one. If the Frame Sync length is equal
to or lower than the delay between the start event and the actual data transmission, the normal
transmission has priority and the data contained in the TSHR is transferred in the transmit regis-
ter, then shifted out.
24.7.5.2 Frame sync edge detection
The Frame Sync Edge detection is configured by writing to the Frame Sync Edge Detection bit in
the RFMR/TFMR registers (RFMR.FSEDGE and TFMR.FSEDGE). This sets the Receive Sync
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and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge
detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC).
24.7.6 Receive Compare Modes
Figure 24-12. Receive Compare Modes
RX_CLOCK
RX_DATA CMP0 CMP1 CMP2 CMP3 Ignored B0 B1 B2
(Input)
Start
{FSLENHI,FSLEN} STTDLY DATLEN
Up to 256 Bits
(4 in This Example)
24.7.6.1 Compare functions
Compare 0 can be one start event of the receiver. In this case, the receiver compares at each
new sample the last {RFMR.FSLENHI, RFMR.FSLEN} bits received to the {RFMR.FSLENHI,
RFMR.FSLEN} lower bits of the data contained in the Receive Compare 0 Register (RC0R).
When this start event is selected, the user can program the receiver to start a new data transfer
either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This
selection is done with the Receive Stop Selection bit in the RCMR register (RCMR.STOP).
24.7.7 Data Framing Format
The data framing format of both the transmitter and the receiver are programmable through the
TFMR, TCMR, RFMR, and RCMR registers. In either case, the user can independently select:
• the event that starts the data transfer (RCMR.START and TCMR.START)
• the delay in number of bit periods between the start event and the first data bit
(RCMR.STTDLY and TCMR.STTDLY)
• the length of the data (RFMR.DATLEN and TFMR.DATLEN)
• the number of data to be transferred for each start event (RFMR.DATNB and TFMR.DATLEN)
• the length of synchronization transferred for each start event (RFMR.FSLENHI,
RFMR.FSLEN, TFMR.FSLENHI, and TFMR.FSLEN)
• the bit sense: most or lowest significant bit first (RFMR.MSBF and TFMR.MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TX_DATA pin while not in data transfer operation. This is done respectively by writing to
the Frame Sync Data Enable and the Data Default Value bits in the TFMR register
(TFMR.FSDEN and TFMR.DATDEF).
Table 24-3. Data Framing Format Registers
Transmitter Receiver Bit/Field Length Comment
TCMR RCMR PERIOD Up to 512 Frame size
TCMR RCMR START Start selection
TCMR RCMR STTDLY Up to 255 Size of transmit start delay
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Table 24-3. Data Framing Format Registers
Transmitter Receiver Bit/Field Length Comment
Number of words transmitted in
TFMR RFMR DATNB Up to 16
frame
TFMR RFMR DATLEN Up to 32 Size of word
TFMR RFMR {FSLENHI,FSLEN} Up to 256 Size of Synchro data register
TFMR RFMR MSBF Most significant bit first
TFMR FSDEN Enable send TSHR
TFMR DATDEF Data default value ended
Figure 24-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes
Start Start
PERIOD
TX_FRAME_SYNC
/ (1)
RX_FRAME_SYNC
FSLEN
TX_DATA
Sync Data Default Data Data Default Sync Data
(If FSDEN = 1)
From TSHR From DATDEF From THR From THR From DATDEF
TX_DATA
(If FSDEN = 0) Default Data Data Default
From DATDEF From THR From THR From DATDEF
RX_DATA Sync Data Ignored Data Data Ignored Sync Data
To RSHR To RHR To RHR
STTDLY DATLEN DATLEN
DATNB
Note: Example of input on falling edge of TX_FRAME_SYNC/RX_FRAME_SYNC.
Figure 24-14. Transmit Frame Format in Continuous Mode
Start
TX_DATA Data Data Default
From THR From THR
DATLEN DATLEN
Start: 1. TXEMPTY set to one
2. Write into the THR
Note: STTDLY is written to zero. In this example, THR is loaded twice. FSDEN value has no effect on the
transmission. SyncData cannot be output in continuous mode.
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Figure 24-15. Receive Frame Format in Continuous Mode
Start = Enable Receiver
RX_DATA Data Data
To RHR To RHR
DATLEN DATLEN
Note: STTDLY is written to zero.
24.7.8 Loop Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by
writing a one to the Loop Mode bit in RFMR register (RFMR.LOOP). In this case, RX_DATA is
connected to TX_DATA, RX_FRAME_SYNC is connected to TX_FRAME_SYNC and
RX_CLOCK is connected to TX_CLOCK.
24.7.9 Interrupt
Most bits in the SR register have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing to the Interrupt Enable Register (IER) and Interrupt Disable Register (IDR).
These registers enable and disable, respectively, the corresponding interrupt by setting and
clearing the corresponding bit in the Interrupt Mask Register (IMR), which controls the genera-
tion of interrupts by asserting the SSC interrupt line connected to the interrupt controller.
Figure 24-16. Interrupt Block Diagram
IM R
IE R ID R
Set C le a r
T ra n s m itte r
TXRDY
TXEM PTY
TXSYNC
S S C In te rru p t
In te rru p t
C o n tro l
R e c e iv e r
RXRDY
OVRUN
RXSYNC
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24.8 SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial
links. Some standard applications are shown in the following figures. All serial link applications
supported by the SSC are not listed here.
Figure 24-17. Audio Application Block Diagram
Clock SCK
TX_CLOCK
Word Select WS
TX_FRAME_SYNC I2S
RECEIVER
Data SD
TX_DATA
SSC
RX_DATA Clock SCK
RX_FRAME_SYNC Word Select WS
RX_CLOCK
Data SD MSB LSB MSB
Left Channel Right Channel
Figure 24-18. Codec Application Block Diagram
Serial Data Clock (SCLK)
TX_CLOCK
Frame sync (FSYNC)
TX_FRAME_SYNC
CODEC
Serial Data Out
TX_DATA
SSC
Serial Data In
RX_DATA
RX_FRAME_SYNC
Serial Data Clock (SCLK)
RX_CLOCK Frame sync (FSYNC) First Time Slot
Dstart Dend
Serial Data Out
Serial Data In
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Figure 24-19. Time Slot Application Block Diagram
SCLK
TX_CLOCK
FSYNC
TX_FRAME_SYNC CODEC
First
Data Out
TX_DATA Time Slot
SSC
Data in
RX_DATA
RX_FRAME_SYNC
RX_CLOCK CODEC
Second
Time Slot
Serial Data Clock (SCLK)
Frame sync (FSYNC) First Time Slot Second Time Slot
Dstart Dend
Serial Data Out
Serial Data In
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24.9 User Interface
Table 24-4. SSC Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Clock Mode Register CMR Read/Write 0x00000000
0x10 Receive Clock Mode Register RCMR Read/Write 0x00000000
0x14 Receive Frame Mode Register RFMR Read/Write 0x00000000
0x18 Transmit Clock Mode Register TCMR Read/Write 0x00000000
0x1C Transmit Frame Mode Register TFMR Read/Write 0x00000000
0x20 Receive Holding Register RHR Read-only 0x00000000
0x24 Transmit Holding Register THR Write-only 0x00000000
0x30 Receive Synchronization Holding Register RSHR Read-only 0x00000000
0x34 Transmit Synchronization Holding Register TSHR Read/Write 0x00000000
0x38 Receive Compare 0 Register RC0R Read/Write 0x00000000
0x3C Receive Compare 1 Register RC1R Read/Write 0x00000000
0x40 Status Register SR Read-only 0x000000CC
0x44 Interrupt Enable Register IER Write-only 0x00000000
0x48 Interrupt Disable Register IDR Write-only 0x00000000
0x4C Interrupt Mask Register IMR Read-only 0x00000000
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24.9.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
SWRST - - - - - TXDIS TXEN
7 6 5 4 3 2 1 0
- - - - - - RXDIS RXEN
• SWRST: Software Reset
1: Writing a one to this bit will perform a software reset. This software reset has priority on any other bit in CR.
0: Writing a zero to this bit has no effect.
• TXDIS: Transmit Disable
1: Writing a one to this bit will disable the transmission. If a character is currently being transmitted, the disable occurs at the end
of the current character transmission.
0: Writing a zero to this bit has no effect.
• TXEN: Transmit Enable
1: Writing a one to this bit will enable the transmission if the TXDIS bit is not written to one.
0: Writing a zero to this bit has no effect.
• RXDIS: Receive Disable
1: Writing a one to this bit will disable the reception. If a character is currently being received, the disable occurs at the end of
current character reception.
0: Writing a zero to this bit has no effect.
• RXEN: Receive Enable
1: Writing a one to this bit will enables the reception if the RXDIS bit is not written to one.
0: Writing a zero to this bit has no effect.
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24.9.2 Clock Mode Register
Name: CMR
Access Type: Read/Write
Offset: 0x04
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - DIV[11:8]
7 6 5 4 3 2 1 0
DIV[7:0]
• DIV[11:0]: Clock Divider
The divided clock equals the CLK_SSC divided by two times DIV. The maximum bit rate is CLK_SSC/2. The minimum bit rate is
CLK_SSC/(2 x 4095) = CLK_SSC/8190.
The clock divider is not active when DIV equals zero.
Divided Clock = CLK_SSC ⁄ ( DIV × 2)
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24.9.3 Receive Clock Mode Register
Name: RCMR
Access Type: Read/Write
Offset: 0x10
Reset value: 0x00000000
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
- - - STOP START
7 6 5 4 3 2 1 0
CKG CKI CKO CKS
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) receive clock periods.
• STTDLY: Receive Start Delay
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the receiver is programmed to start synchronously with the transmitter, the delay is also applied.
Note: It is very important that STTDLY be written carefully. If STTDLY must be written, it should be done in relation to Receive
Sync Data reception.
• STOP: Receive Stop Selection
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new
Compare 0.
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• START: Receive Start Selection
START Receive Start
Continuous, as soon as the receiver is enabled, and immediately after the end of
0
transfer of the previous data.
1 Transmit start
2 Detection of a low level on RX_FRAME_SYNC signal
3 Detection of a high level on RX_FRAME_SYNC signal
4 Detection of a falling edge on RX_FRAME_SYNC signal
5 Detection of a rising edge on RX_FRAME_SYNC signal
6 Detection of any level change on RX_FRAME_SYNC signal
7 Detection of any edge on RX_FRAME_SYNC signal
8 Compare 0
Others Reserved
• CKG: Receive Clock Gating Selection
CKG Receive Clock Gating
0 None, continuous clock
1 Receive Clock enabled only if RX_FRAME_SYNC is low
2 Receive Clock enabled only if RX_FRAME_SYNC is high
3 Reserved
• CKI: Receive Clock Inversion
CKI affects only the receive clock and not the output clock signal.
1: The data inputs (Data and Frame Sync signals) are sampled on receive clock rising edge. The Frame Sync signal output is
shifted out on receive clock falling edge.
0: The data inputs (Data and Frame Sync signals) are sampled on receive clock falling edge. The Frame Sync signal output is
shifted out on receive clock rising edge.
• CKO: Receive Clock Output Mode Selection
CKO Receive Clock Output Mode RX_CLOCK pin
0 None Input-only
1 Continuous receive clock Output
2 Receive clock only during data transfers Output
Others Reserved
• CKS: Receive Clock Selection
CKS Selected Receive Clock
0 Divided clock
1 TX_CLOCK clock signal
2 RX_CLOCK pin
3 Reserved
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24.9.4 Receive Frame Mode Register
Name: RFMR
Access Type: Read/Write
Offset: 0x14
Reset value: 0x00000000
31 30 29 28 27 26 25 24
FSLENHI - - - FSEDGE
23 22 21 20 19 18 17 16
- FSOS FSLEN
15 14 13 12 11 10 9 8
- - - - DATNB
7 6 5 4 3 2 1 0
MSBF - LOOP DATLEN
• FSLENHI: Receive Frame Sync Length High Part
The four MSB of the FSLEN field.
• FSEDGE: Receive Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the SR.RXSYN interrupt.
FSEDGE Frame Sync Edge Detection
0 Positive edge detection
1 Negative edge detection
• FSOS: Receive Frame Sync Output Selection
FSOS Selected Receive Frame Sync Signal RX_FRAME_SYNC Pin
0 None Input-only
1 Negative Pulse Output
2 Positive Pulse Output
3 Driven Low during data transfer Output
4 Driven High during data transfer Output
5 Toggling at each start of data transfer Output
Others Reserved Undefined
• FSLEN: Receive Frame Sync Length
This field defines the length of the Receive Frame Sync signal and the number of bits sampled and stored in the RSHR register.
When this mode is selected by the RCMR.START field, it also determines the length of the sampled data to be compared to the
Compare 0 or Compare 1 register.
Note: The four most significant bits for this field are located in the FSLENHI field.
The pulse length is equal to ({FSLENHI,FSLEN} + 1) receive clock periods. Thus, if {FSLENHI,FSLEN} is zero, the Receive
Frame Sync signal is generated during one receive clock period.
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• DATNB: Data Number per Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
• MSBF: Most Significant Bit First
1: The most significant bit of the data register is sampled first in the bit stream.
0: The lowest significant bit of the data register is sampled first in the bit stream.
• LOOP: Loop Mode
1: RX_DATA is driven by TX_DATA, RX_FRAME_SYNC is driven by TX_FRAME_SYNC and TX_CLOCK drives RX_CLOCK.
0: Normal operating mode.
• DATLEN: Data Length
The bit stream contains (DATLEN + 1) data bits.
This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the receiver.
DATLEN Transfer Size
0 Forbidden value
1-7 Data transfer are in bytes
8-15 Data transfer are in halfwords
Others Data transfer are in words
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24.9.5 Transmit Clock Mode Register
Name: TCMR
Access Type: Read/Write
Offset: 0x18
Reset value: 0x00000000
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
- - - - START
7 6 5 4 3 2 1 0
CKG CKI CKO CKS
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) transmit clock periods.
• STTDLY: Transmit Start Delay
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission.
When the transmitter is programmed to start synchronously with the receiver, the delay is also applied.
Note: STTDLY must be written carefully, in relation to Transmit Sync Data transmission.
• START: Transmit Start Selection
START Transmit Start
Continuous, as soon as a word is written to the THR Register (if Transmit is enabled), and
0
immediately after the end of transfer of the previous data.
1 Receive start
2 Detection of a low level on TX_FRAME_SYNC signal
3 Detection of a high level on TX_FRAME_SYNC signal
4 Detection of a falling edge on TX_FRAME_SYNC signal
5 Detection of a rising edge on TX_FRAME_SYNC signal
6 Detection of any level change on TX_FRAME_SYNC signal
7 Detection of any edge on TX_FRAME_SYNC signal
Others Reserved
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• CKG: Transmit Clock Gating Selection
CKG Transmit Clock Gating
0 None, continuous clock
1 Transmit Clock enabled only if TX_FRAME_SYNC is low
2 Transmit Clock enabled only if TX_FRAME_SYNC is high
3 Reserved
• CKI: Transmit Clock Inversion
CKI affects only the Transmit Clock and not the output clock signal.
1: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock rising edge. The Frame sync signal input is
sampled on transmit clock falling edge.
0: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock falling edge. The Frame sync signal input is
sampled on transmit clock rising edge.
• CKO: Transmit Clock Output Mode Selection
CKO Transmit Clock Output Mode TX_CLOCK pin
0 None Input-only
1 Continuous transmit clock Output
2 Transmit clock only during data transfers Output
Others Reserved
• CKS: Transmit Clock Selection
CKS Selected Transmit Clock
0 Divided Clock
1 RX_CLOCK clock signal
2 TX_CLOCK Pin
3 Reserved
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24.9.6 Transmit Frame Mode Register
Name: TFMR
Access Type: Read/Write
Offset: 0x1C
Reset value: 0x00000000
31 30 29 28 27 26 25 24
FSLENHI - - - FSEDGE
23 22 21 20 19 18 17 16
FSDEN FSOS FSLEN
15 14 13 12 11 10 9 8
- - - - DATNB
7 6 5 4 3 2 1 0
MSBF - DATDEF DATLEN
• FSLENHI: Transmit Frame Sync Length High Part
The four MSB of the FSLEN field.
• FSEDGE: Transmit Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the SR.TXSYN interrupt.
FSEDGE Frame Sync Edge Detection
0 Positive Edge Detection
1 Negative Edge Detection
• FSDEN: Transmit Frame Sync Data Enable
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
• FSOS: Transmit Frame Sync Output Selection
FSOS Selected Transmit Frame Sync Signal TX_FRAME_SYNC Pin
0 None Input-only
1 Negative Pulse Output
2 Positive Pulse Output
3 Driven Low during data transfer Output
4 Driven High during data transfer Output
5 Toggling at each start of data transfer Output
Others Reserved Undefined
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if
TFMR.FSDEN is equal to one.
Note: The four most significant bits for this field are located in the FSLENHI field.
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The pulse length is equal to ({FSLENHI,FSLEN} + 1) transmit clock periods, i.e., the pulse length can range from 1 to 256
transmit clock periods. If {FSLENHI,FSLEN} is zero, the Transmit Frame Sync signal is generated during one transmit clock
period.
• DATNB: Data Number per Frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).
• MSBF: Most Significant Bit First
1: The most significant bit of the data register is shifted out first in the bit stream.
0: The lowest significant bit of the data register is shifted out first in the bit stream.
• DATDEF: Data Default Value
This bit defines the level driven on the TX_DATA pin while out of transmission.
Note that if the pin is defined as multi-drive by the I/O Controller, the pin is enabled only if the TX_DATA output is one.
1: The level driven on the TX_DATA pin while out of transmission is one.
0: The level driven on the TX_DATA pin while out of transmission is zero.
• DATLEN: Data Length
The bit stream contains (DATLEN + 1) data bits.
This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the transmitter.
DATLEN Transfer Size
0 Forbidden value (1-bit data length is not supported)
1-7 Data transfer are in bytes
8-15 Data transfer are in halfwords
Others Data transfer are in words
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24.9.7 Receive Holding Register
Name: RHR
Access Type: Read-only
Offset: 0x20
Reset value: 0x00000000
31 30 29 28 27 26 25 24
RDAT[31:24]
23 22 21 20 19 18 17 16
RDAT[23:16]
15 14 13 12 11 10 9 8
RDAT[15:8]
7 6 5 4 3 2 1 0
RDAT[7:0]
• RDAT: Receive Data
Right aligned regardless of the number of data bits defined by the RFMR.DATLEN field.
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24.9.8 Transmit Holding Register
Name: THR
Access Type: Write-only
Offset: 0x24
Reset value: 0x00000000
31 30 29 28 27 26 25 24
TDAT[31:24]
23 22 21 20 19 18 17 16
TDAT[23:16]
15 14 13 12 11 10 9 8
TDAT[15:8]
7 6 5 4 3 2 1 0
TDAT[7:0]
• TDAT: Transmit Data
Right aligned regardless of the number of data bits defined by the TFMR.DATLEN field.
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24.9.9 Receive Synchronization Holding Register
Name: RSHR
Access Type: Read-only
Offset: 0x30
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
RSDAT[15:8]
7 6 5 4 3 2 1 0
RSDAT[7:0]
• RSDAT: Receive Synchronization Data
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24.9.10 Transmit Synchronization Holding Register
Name: TSHR
Access Type: Read/Write
Offset: 0x34
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TSDAT[15:8]
7 6 5 4 3 2 1 0
TSDAT[7:0]
• TSDAT: Transmit Synchronization Data
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24.9.11 Receive Compare 0 Register
Name: RC0R
Access Type: Read/Write
Offset: 0x38
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
CP0[15:8]
7 6 5 4 3 2 1 0
CP0[7:0]
• CP0: Receive Compare Data 0
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24.9.12 Receive Compare 1 Register
Name: RC1R
Access Type: Read/Write
Offset: 0x3C
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
CP1[[15:8]
7 6 5 4 3 2 1 0
CP1[7:0]
• CP1: Receive Compare Data 1
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24.9.13 Status Register
Name: SR
Access Type: Read-only
Offset: 0x40
Reset value: 0x000000CC
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - RXEN TXEN
15 14 13 12 11 10 9 8
- - - - RXSYN TXSYN CP1 CP0
7 6 5 4 3 2 1 0
- - OVRUN RXRDY - - TXEMPTY TXRDY
• RXEN: Receive Enable
This bit is set when the CR.RXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one.
• TXEN: Transmit Enable
This bit is set when the CR.TXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one.
• RXSYN: Receive Sync
This bit is set when a Receive Sync has occurred.
This bit is cleared when the SR register is read.
• TXSYN: Transmit Sync
This bit is set when a Transmit Sync has occurred.
This bit is cleared when the SR register is read.
• CP1: Compare 1
This bit is set when compare 1 has occurred.
This bit is cleared when the SR register is read.
• CP0: Compare 0
This bit is set when compare 0 has occurred.
This bit is cleared when the SR register is read.
• OVRUN: Receive Overrun
This bit is set when data has been loaded in the RHR register while previous data has not yet been read.
This bit is cleared when the SR register is read.
• RXRDY: Receive Ready
This bit is set when data has been received and loaded in the RHR register.
This bit is cleared when the RHR register is empty.
• TXEMPTY: Transmit Empty
This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR
register has been transmitted.
This bit is cleared when data remains in the THR register or is currently transmitted from the TSR register.
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• TXRDY: Transmit Ready
This bit is set when the THR register is empty.
This bit is cleared when data has been loaded in the THR register and is waiting to be loaded in the TSR register.
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24.9.14 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x44
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - RXSYN TXSYN CP1 CP0
7 6 5 4 3 2 1 0
– – OVRUN RXRDY – – TXEMPTY TXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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24.9.15 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x48
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - RXSYN TXSYN CP1 CP0
7 6 5 4 3 2 1 0
– – OVRUN RXRDY – – TXEMPTY TXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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24.9.16 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x4C
Reset value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - RXSYN TXSYN CP1 CP0
7 6 5 4 3 2 1 0
– – OVRUN RXRDY – – TXEMPTY TXRDY
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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25. Universal Synchronous Asynchronous Receiver Transmitter (USART)
Rev: 4.2.0.6
25.1 Features
• Configurable baud rate generator
• 5- to 9-bit full-duplex, synchronous and asynchronous, serial communication
– 1, 1.5, or 2 stop bits in asynchronous mode, and 1 or 2 in synchronous mode
– Parity generation and error detection
– Framing- and overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– Receiver frequency oversampling by 8 or 16 times
– Optional RTS-CTS hardware handshaking
– Optional DTR-DSR-DCD-RI modem signal management
– Receiver Time-out and transmitter Timeguard
– Optional Multidrop mode with address generation and detection
• RS485 with line driver control
• ISO7816, T=0 and T=1 protocols for Interfacing with smart cards
– , NACK handling, and customizable error counter
• IrDA modulation and demodulation
– Communication at up to 115.2Kbit/s
• SPI Mode
– Master or slave
– Configurable serial clock phase and polarity
– CLK SPI serial clock frequency up to a quarter of the CLK_USART internal clock frequency
• LIN Mode
– Compliant with LIN 1.3 and LIN 2.0 specifications
– Master or slave
– Processing of Frames with up to 256 data bytes
– Configurable response data length, optionally defined automatically by the Identifier
– Self synchronization in slave node configuration
– Automatic processing and verification of the “Break Field” and “Sync Field”
– The “Break Field” is detected even if it is partially superimposed with a data byte
– Optional, automatic identifier parity management
– Optional, automatic checksum management
– Supports both “Classic” and “Enhanced” checksum types
– Full LIN error checking and reporting
– Frame Slot Mode: the master allocates slots to scheduled frames automatically.
– Wakeup signal generation
• Test Modes
– Automatic echo, remote- and local loopback
• Supports two Peripheral DMA Controller channels
– Buffer transfers without processor intervention
25.2 Overview
The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides a full
duplex, universal, synchronous/asynchronous serial link. Data frame format is widely configu-
rable, including basic length, parity, and stop bit settings, maximizing standards support. The
receiver implements parity-, framing-, and overrun error detection, and can handle un-fixed
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frame lengths with the time-out feature. The USART supports several operating modes, provid-
ing an interface to RS485, LIN, and SPI buses, with ISO7816 T=0 and T=1 smart card slots,
infrared transceivers, and modem port connections. Communication with slow and remote
devices is eased by the timeguard. Duplex multidrop communication is supported by address
and data differentiation through the parity bit. The hardware handshaking feature enables an
out-of-band flow control, automatically managing RTS and CTS pins. The Peripheral DMA Con-
troller connection enables memory transactions, and the USART supports chained buffer
management without processor intervention. Automatic echo, remote-, and local loopback test
modes are also supported.
25.3 Block Diagram
Figure 25-1. USART Block Diagram
Peripheral DMA
Controller
Channel Channel
USART I/O
Controller
RXD
Receiver
RTS
Interrupt USART TXD
Controller Interrupt Transmitter
CTS
DTR
CLK_USART Modem DSR
Signals
Control DCD
CLK_USART/DIV
Power
DIV
Manager RI
CLK
BaudRate
Generator
User
Interface
Peripheral bus
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Table 25-1. SPI Operating Mode
PIN USART SPI Slave SPI Master
RXD RXD MOSI MISO
TXD TXD MISO MOSI
RTS RTS – CS
CTS CTS CS –
25.4 I/O Lines Description
Table 25-2. I/O Lines Description
Name Description Type Active Level
CLK Serial Clock I/O
Transmit Serial Data
TXD or Master Out Slave In (MOSI) in SPI master mode Output
or Master In Slave Out (MISO) in SPI slave mode
Receive Serial Data
RXD or Master In Slave Out (MISO) in SPI master mode Input
or Master Out Slave In (MOSI) in SPI slave mode
RI Ring Indicator Input Low
DSR Data Set Ready Input Low
DCD Data Carrier Detect Input Low
DTR Data Terminal Ready Output Low
Clear to Send
CTS Input Low
or Slave Select (NSS) in SPI slave mode
Request to Send
RTS Output Low
or Slave Select (NSS) in SPI master mode
25.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
25.5.1 I/O Lines
The USART pins may be multiplexed with the I/O Controller lines. The user must first configure
the I/O Controller to assign these pins to their peripheral functions. Unused I/O lines may be
used for other purposes.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull-up
is required. If the hardware handshaking feature or modem mode is used, the internal pull-up on
RTS must also be enabled.
All the pins of the modems may or may not be implemented on the USART. On USARTs not
equipped with the corresponding pins, the associated control bits and statuses have no effect on
the behavior of the USART.
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25.5.2 Clocks
The clock for the USART bus interface (CLK_USART) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the USART before disabling the clock, to avoid freezing the USART in an undefined state.
25.5.3 Interrupts
The USART interrupt request line is connected to the interrupt controller. Using the USART
interrupt requires the interrupt controller to be programmed first.
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25.6 Functional Description
25.6.1 USART Operating Modes
The USART can operate in several modes:
• Normal
• RS485, described in Section 25.6.5 ”RS485 Mode” on page 560
• Hardware handshaking, described in Section 25.6.6 ”Hardware Handshaking” on page 561
• Modem, described in Section 25.6.7 ”Modem Mode” on page 562
• ISO7816, described in Section 25.6.8 ”ISO7816 Mode” on page 563
• IrDA, described in Section 25.6.9 ”IrDA Mode” on page 566
• LIN Master, described in Section 25.6.10 ”LIN Mode” on page 568
• LIN Slave, described in Section 25.6.10 ”LIN Mode” on page 568
• SPI Master, described in Section 25.6.15 ”SPI Mode” on page 580
• SPI Slave, described in Section 25.6.15 ”SPI Mode” on page 580
The operating mode is selected by writing to the Mode field in the “Mode Register” (MR.MODE).
Table 25-3. MR.MODE
MR.MODE Mode of the USART
0x0 Normal
0x1 RS485
0x2 Hardware Handshaking
0x3 Modem
0x4 IS07816 Protocol: T = 0
0x6 IS07816 Protocol: T = 1
0x8 IrDA
0xA LIN Master
0xB LIN Slave
0xE SPI Master
0xF SPI Slave
Others Reserved
In addition, Synchronous or Asynchronous mode is selected by writing to the Synchronous
Mode Select bit in MR (MR.SYNC). By default, MR.MODE and MR.SYNC are both zero, and the
USART operates in Normal Asynchronous mode.
25.6.2 Basic Operation
To start using the USART, the user must perform the following steps:
1. Configure the baud rate by writing to the Baud Rate Generator Register (BRGR) as
described in ”Baud Rate Generator” on page 558
2. Select the operating mode by writing to the relevant fields in the Mode Regiser (MR)
3. Enable the transmitter and/or receiver, by writing a one to CR.TXEN and/or CR.RXEN
respectively
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4. Check that CSR.TXRDY and/or CSR.RXRDY is one before writing to THR and/or read-
ing from RHR respectively
25.6.2.1 Receiver and Transmitter Control
After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to
the Receiver Enable/Transmitter Enable bit in the Control Register (CR.RXEN/CR.TXEN)
respectively. They may be enabled together and can be configured both before and after they
have been enabled. The user can reset the USART receiver/transmitter at any time by writing a
one to the Reset Receiver/Reset Transmitter bit (CR.RSTRX/CR.RSTTX) respectively. This
software reset clears status bits and resets internal state machines, immediately halting any
communication. The user interface configuration registers will retain their values.
The user can disable the receiver/transmitter by writing a one to either the Receiver Disable, or
Transmitter Disable bit (CR.RXDIS, or CR.TXDIS). If the receiver is disabled during a character
reception, the USART will wait for the current character to be received before disabling. If the
transmitter is disabled during transmission, the USART will wait until both the current character
and the character stored in the Transmitter Holding Register (THR) are transmitted before dis-
abling. If a timeguard has been implemented it will remain functional during the transmission.
25.6.2.2 Transmitter Operations
The transmitter operates equally in both Synchronous and Asynchronous operating modes
(MR.SYNC). One start bit, up to 9 data bits, an optional parity bit, and up to two stop bits are
successively shifted out on the TXD pin at each falling edge of the serial clock. The number of
data bits is selected by the Character Length field (MR.CHRL) and the 9-bit Character Length bit
in the Mode Register (MR.MODE9). Nine bits are selected by writing a one to MR.MODE9, over-
riding any value in MR.CHRL. The parity bit configuration is selected in the MR.PAR field. The
Most Significant Bit First bit (MR.MSBF) selects which data bit to send first. The number of stop
bits is selected by the MR.NBSTOP field. The 1.5 stop bit configuration is only supported in
asynchronous mode.
Figure 25-2. Character Transmit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
TXD
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
Bit Bit Bit
The characters are sent by writing to the Character to be Transmitted field (THR.TXCHR). The
transmitter status can be read from the Transmitter Ready and Transmitter Empty bits in the
Channel Status Register (CSR.TXRDY/CSR.TXEMPTY). CSR.TXRDY is set when THR is
empty. CSR.TXEMPTY is set when both THR and the transmit shift register are empty (trans-
mission complete). An interrupt request is generated if the corresponding bit in the Interrupt
Mask Register (IMR) is set (IMR.TXRDY/IMR.TXEMPTY). Both CSR.TXRDY and
CSR.TXEMPTY are cleared when the transmitter is disabled. CSR.TXRDY and CSR.TXEMPY
can also be cleared by writing a one to the Start Break bit in CR (CR.STTBRK). Writing a char-
acter to THR while CSR.TXRDY is zero has no effect and the written character will be lost.
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Figure 25-3. Transmitter Status
Baud Rate
Clock
TXD
Start Parity Stop Start Parity Stop
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Bit Bit Bit Bit Bit Bit
Write
THR
TXRDY
TXEMPTY
25.6.2.3 Asynchronous Receiver
If the USART is configured in an asynchronous operating mode (MR.SYNC is zero), the receiver
will oversample the RXD input line by either 8 or 16 times the Baud Rate Clock, as selected by
the Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight con-
secutive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample
will determine the logical value on the line, resulting in bit values being determined at the middle
of the bit period.
The number of data bits, endianess, parity mode, and stop bits are selected by the same bits
and fields as for the transmitter (MR.CHRL, MR.MODE9, MR.MSBF, MR.PAR, and
MR.NBSTOP). The synchronization mechanism will only consider one stop bit, regardless of the
used protocol, and when the first stop bit has been sampled, the receiver will automatically begin
looking for a new start bit, enabling resynchronization even if there is a protocol mismatch. Fig-
ure 25-4 and Figure 25-5 illustrate start bit detection and character reception in asynchronous
mode.
Figure 25-4. Asynchronous Start Bit Detection
Baud Rate
Clock
Sampling
Clock (x16)
RXD
Sampling
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D0
Start Sampling
Detection
RXD
Sampling
1 2 3 4 5 6 7 0 1 2 3 4
Start
Rejection
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Figure 25-5. Asynchronous Mode Character Reception
Example: 8-bit, Parity Enabled
Baud Rate
Clock
RXD
Start 16 16 16 16 16 16 16 16 16 16
Detection samples samples samples samples samples samples samples samples samples samples
D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
Bit Bit
25.6.2.4 Synchronous Receiver
In synchronous mode (MR.SYNC is one), the receiver samples the RXD signal on each rising
edge of the Baud Rate Clock, as illustrated in Figure 25-6. If a low level is detected, it is consid-
ered as a start bit. Configuration bits and fields are the same as in asynchronous mode.
Figure 25-6. Synchronous Mode Character Reception
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
RXD
Sampling
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
Parity Bit
Figure 25-7. Receiver Status
Baud Rate
Clock
RXD
Start Parity Stop Start Parity Stop
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Bit Bit Bit Bit Bit Bit
RSTSTA = 1
Write
CR
Read
RHR
RXRDY
OVRE
25.6.2.5 Receiver Operations
When a character reception is completed, it is transferred to the Received Character field in the
Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status
Register (CSR.RXRDY) is set. An interrupt request is generated if the Receiver Ready bit in the
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Interrupt Mask Register (IMR.RXRDY) is set. If CSR.RXRDY is already set, RHR will be over-
written and the Overrun Error bit (CSR.OVRE) is set. An interrupt request is generated if the
Overrun Error bit in IMR is set. Reading RHR will clear CSR.RXRDY, and writing a one to the
Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE. Refer to Figure 25-
7.
25.6.3 Other Considerations
25.6.3.1 Parity
The USART supports five parity modes, selected by MR.PAR:
• Even parity
• Odd parity
• Parity forced to zero (space)
• Parity forced to one (mark)
• No parity
The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 555. If even par-
ity is selected (MR.PAR is 0x0), the parity bit will be zero if there is an even number of ones in
the data character, and one if there is an odd number. For odd parity the reverse applies. If
space or mark parity is chosen (MR.PAR is 0x2 or 0x3, respectively), the parity bit will always be
a zero or one, respectively. See Table 25-4.
Table 25-4. Parity Bit Examples
Parity Mode
Alphanum
Character Hex Bin Odd Even Mark Space None
A 0x41 0100 0001 1 0 1 0 -
V 0x56 0101 0110 1 0 1 0 -
R 0x52 0101 0010 0 1 1 0 -
The receiver will report parity errors in CSR.PARE, unless parity is disabled. An interrupt request
is generated if the PARE bit in the Interrupt Mask Register is set (IMR.PARE). Writing a one to
CR.RSTSTA will clear CSR.PARE. See Figure 25-8.
Figure 25-8. Parity Error
Baud Rate
Clock
RXD
Start Bad Stop
D0 D1 D2 D3 D4 D5 D6 D7
Bit Parity Bit
Bit RSTSTA = 1
Write
CR
PARE
RXRDY
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25.6.3.2 Multidrop Mode
If MR.PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates
data and address characters. Data has the parity bit zero and addresses have a one. By writing
a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR
to be transmitted as an address. Receiving a character with a one as parity bit will report parity
error by setting CSR.PARE. An interrupt request is generated if the PARE bit in the Interrupt
Mask Register is set (IMR.PARE).
25.6.3.3 Transmitter Timeguard
The timeguard feature enables the USART to interface slow devices by inserting an idle state on
the TXD line in between two characters. This idle state corresponds to a long stop bit, whose
duration is selected by the Timeguard Value field in the Transmitter Timeguard Register
(TTGR.TG). The transmitter will hold the TXD line high for TTGR.TG bit periods, in addition to
the number of stop bits. As illustrated in Figure 25-9, the behavior of TXRDY and TXEMPTY is
modified when TG has a non-zero value. If a pending character has been written to THR, the
CSR.TXRDY bit will not be set until this characters start bit has been sent. CSR.TXEMPTY will
remain low until the timeguard transmission has completed.
Figure 25-9. Timeguard Operation
TG = 4 TG = 4
Baud Rate
Clock
TXD
Start Parity Stop Start Parity Stop
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Bit Bit Bit Bit Bit Bit
Write
THR
TXRDY
TXEMPTY
Table 25-5. Maximum Baud Rate Dependent Timeguard Durations
Baud Rate (bit/sec) Bit time (µs) Timeguard (ms)
1 200 833 212.50
9 600 104 26.56
14400 69.4 17.71
19200 52.1 13.28
28800 34.7 8.85
33400 29.9 7.63
56000 17.9 4.55
57600 17.4 4.43
115200 8.7 2.21
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25.6.3.4 Receiver Time-out
The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enables handling of vari-
able-length frames by detection of selectable idle durations on the RXD line. The value written to
TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the
amount of inactive bit periods matches the initial counter value. If a time-out has not occurred,
the counter will reload and restart every time a new character arrives. A time-out sets the
Receiver Time-out bit in CSR (CSR.TIMEOUT). An interrupt request is generated if the Receiver
Time-out bit in the Interrupt Mask Register (IMR.TIMEOUT) is set. Clearing TIMEOUT can be
done in two ways:
• Writing a one to the Start Time-out bit (CR.STTTO). This also aborts count down until the
next character has been received.
• Writing a one to the Reload and Start Time-out bit (CR.RETTO). This also reloads the
counter and restarts count down immediately.
Figure 25-10. Receiver Time-out Block Diagram
Baud Rate TO
Clock
16-bit
Value
1 D Q Clock 16-bit Time-out
Counter
STTTO = TIMEOUT
Load 0
Clear
Character
Received
RETTO
Table 25-6. Maximum Time-out Period
Baud Rate (bit/sec) Bit Time (µs) Time-out (ms)
600 1 667 109 225
1 200 833 54 613
2 400 417 27 306
4 800 208 13 653
9 600 104 6 827
14400 69 4 551
19200 52 3 413
28800 35 2 276
33400 30 1 962
56000 18 1 170
57600 17 1 138
200000 5 328
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25.6.3.5 Framing Error
The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit
reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing
error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit.
An interrupt request is generated if the Framing Error bit in the Interrupt Mask Register
(IMR.FRAME) is set. CSR.FRAME is cleared by writing a one to CR.RSTSTA.
Figure 25-11. Framing Error Status
Baud Rate
Clock
RXD
Start Parity Stop
D0 D1 D2 D3 D4 D5 D6 D7
Bit Bit Bit
RSTSTA = 1
Write
CR
FRAME
RXRDY
25.6.3.6 Transmit Break
When CSR.TXRDY is set, the user can request the transmitter to generate a break condition on
the TXD line by writing a one to the Start Break bit (CR.STTBRK). The break is treated as a nor-
mal 0x00 character transmission, clearing CSR.TXRDY and CSR.TXEMPTY, but with zeroes for
preambles, start, parity, stop, and time guard bits. Writing a one to the Stop Break bit (CR.STT-
BRK) will stop the generation of new break characters, and send ones for TG duration or at least
12 bit periods, ensuring that the receiver detects end of break, before resuming normal opera-
tion. Figure 25-12 illustrates CR.STTBRK and CR.STPBRK effect on the TXD line.
Writing to CR.STTBRK and CR.STPBRK simultaneously can lead to unpredictable results.
Writes to THR before a pending break has started will be ignored.
Figure 25-12. Break Transmission
Baud Rate
Clock
TXD
Start Parity Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Bit Bit
Break Transmission End of Break
STTBRK = 1 STPBRK = 1
Write
CR
TXRDY
TXEMPTY
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25.6.3.7 Receive Break
A break condition is assumed when incoming data, parity, and stop bits are zero. This corre-
sponds to a framing error, but CSR.FRAME will remain zero while the Break Received/End of
Break bit (CSR.RXBRK) is set. An interrupt request is generated if the Breadk Received/End of
Break bit in the Interrupt Mask Register is set (IMR.RXBRK). Writing a one to CR.RSTSTA will
clear CSR.RXBRK. An end of break will also set CSR.RXBRK, and is assumed when TX is high
for at least 2/16 of a bit period in asynchronous mode, or when a high level is sampled in syn-
chronous mode.
25.6.4 Baud Rate Generator
The baud rate generator provides the bit period clock named the Baud Rate Clock to both
receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider
field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator,
and if BRGR.CD is one, the divider is bypassed and inactive. The Clock Selection field in the
Mode Register (MR.USCLKS) selects clock source between:
• CLK_USART (internal clock, refer to Power Manager chapter for details)
• CLK_USART/DIV (a divided CLK_USART, refer to Module Configuration section)
• CLK (external clock, available on the CLK pin)
If the external clock CLK is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be at least 4.5 times longer than those provided by CLK_USART.
Figure 25-13. Baud Rate Generator
USCLKS CD
CLK_USART CD
0 CLK
CLK_USART/DIV
1
Reserved 16-bit Counter
CLK 2 >1 FIDI
SYNC
3 OVER
1
0
0 0 Sampling
0
Divider
BaudRate
1 Clock
1
SYNC
Sampling
USCLKS= 3 Clock
25.6.4.1 Baud Rate in Asynchronous Mode
If the USART is configured to operate in asynchronous mode (MR.SYNC is zero), the selected
clock is divided by the BRGR.CD value before it is provided to the receiver as a sampling clock.
Depending on the Oversampling Mode bit (MR.OVER) value, the clock is then divided by either
8 (MR.OVER=1), or 16 (MR.OVER=0). The baud rate is calculated with the following formula:
SelectedClock -
BaudRate = -----------------------------------------------
( 8 ( 2 – OVER )CD )
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This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is
the fastest clock available, and that MR.OVER is one.
25.6.4.2 Baud Rate Calculation Example
Table 25-7 shows calculations based on the CD field to obtain 38400 baud from different source
clock frequencies. This table also shows the actual resulting baud rate and error.
Table 25-7. Baud Rate Example (OVER=0)
Expected Baud
Source Clock (Hz) Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error
3 686 400 38 400 6.00 6 38 400.00 0.00%
4 915 200 38 400 8.00 8 38 400.00 0.00%
5 000 000 38 400 8.14 8 39 062.50 1.70%
7 372 800 38 400 12.00 12 38 400.00 0.00%
8 000 000 38 400 13.02 13 38 461.54 0.16%
12 000 000 38 400 19.53 20 37 500.00 2.40%
12 288 000 38 400 20.00 20 38 400.00 0.00%
14 318 180 38 400 23.30 23 38 908.10 1.31%
14 745 600 38 400 24.00 24 38 400.00 0.00%
18 432 000 38 400 30.00 30 38 400.00 0.00%
24 000 000 38 400 39.06 39 38 461.54 0.16%
24 576 000 38 400 40.00 40 38 400.00 0.00%
25 000 000 38 400 40.69 40 38 109.76 0.76%
32 000 000 38 400 52.08 52 38 461.54 0.16%
32 768 000 38 400 53.33 53 38 641.51 0.63%
33 000 000 38 400 53.71 54 38 194.44 0.54%
40 000 000 38 400 65.10 65 38 461.54 0.16%
50 000 000 38 400 81.38 81 38 580.25 0.47%
60 000 000 38 400 97.66 98 38 265.31 0.35%
The baud rate is calculated with the following formula (MR.OVER=0):
CLK_USART
BaudRate = -----------------------------------
CD ⋅ 16
The baud rate error is calculated with the following formula. It is not recommended to work with
an error higher than 5%.
ExpectedBaudRate
Error = 1 – ⎛ ---------------------------------------------------⎞
⎝ ActualBaudRate ⎠
25.6.4.3 Fractional Baud Rate in Asynchronous Mode
The baud rate generator has a limitation: the source frequency is always a multiple of the baud
rate. An approach to this problem is to integrate a high resolution fractional N clock generator,
outputting fractional multiples of the reference source clock. This fractional part is selected with
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the Fractional Part field in BRGR (BRGR.FP), and is activated by giving it a non-zero value. The
resolution is one eighth of CD. The resulting baud rate is calculated using the following formula:
SelectedClock
BaudRate = -------------------------------------------------------------------
-
⎛ 8 ( 2 – OVER ) ⎛ CD + FP -------⎞ ⎞
⎝ ⎝ 8 ⎠⎠
The modified architecture is shown in Figure 25-14.
Figure 25-14. Fractional Baud Rate Generator
FP
USCLKS Modulus
CD
Control
FP
CLK_USART CD
0 CLK
CLK_USART/DIV
1
Reserved 16-bit Counter glitch-free
CLK 2
logic >1 SYNC
3 OVER
1 0
0 0 Sampling
Divider 0
BaudRate
1 Clock
1
SYNC Sampling
USCLKS = 3 Clock
25.6.4.4 Baud Rate in Synchronous and SPI Mode
If the USART is configured to operate in synchronous mode (MR.SYNC is one), the selected
clock is divided by BRGR.CD. This does not apply when the external clock CLK is selected.
BaudRate = SelectedClock
--------------------------------------
CD
When CLK is selected, the frequency of the external clock must be at least 4.5 times lower than
the system clock, and when either CLK or CLK_USART/DIV are selected, BRGR.CD must be
even to ensure a 50/50 duty cycle. If CLK_USART is selected, the generator ensures this
regardless of value.
25.6.5 RS485 Mode
The USART features an RS485 mode, supporting line driver control. This supplements normal
synchronous and asynchronous mode by driving the RTS pin high when the transmitter is oper-
ating. The RTS pin level is the inverse of the CSR.TXEMPTY value. The RS485 mode is
enabled by writing 0x1 to MR.MODE. A typical connection to a RS485 bus is shown in Figure
25-15.
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Figure 25-15. Typical Connection to a RS485 Bus
USART
RXD
Differential
TXD Bus
RTS
If a timeguard has been configured the RTS pin will remain high for the duration specified in TG,
as shown in Figure 25-16.
Figure 25-16. Example of RTS Drive with Timeguard Enabled
TG = 4
Baud Rate
Clock
TXD
Start Parity Stop
D0 D1 D2 D3 D4 D5 D6 D7
Bit Bit Bit
Write
THR
TXRDY
TXEMPTY
RTS
25.6.6 Hardware Handshaking
The USART features an out-of-band hardware handshaking flow control mechanism, imple-
mentable by connecting the RTS and CTS pins with the remote device, as shown in Figure 25-
17.
Figure 25-17. Connection with a Remote Device for Hardware Handshaking
USART Remote
Device
TXD RXD
RXD TXD
CTS RTS
RTS CTS
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Writing 0x2 to the MR.MODE field configures the USART to operate in hardware handshaking
mode. The receiver will drive its RTS pin high when disabled or when the Reception Buffer Full
bit (CSR.RXBUFF) is set by the Buffer Full signal from the Peripheral DMA controller. If the
receiver RTS pin is high, the transmitter CTS pin will also be high and only the active character
transmissions will be completed. Allocating a new buffer to the DMA controller by clearing
RXBUFF, will drive the RTS pin low, allowing the transmitter to resume transmission. Detected
level changes on the CTS pin are reported by the CTS Input Change bit in the Channel Status
Register (CSR.CTSIC). An interrupt request is generated if the Input Change bit in the Interrupt
Mask Register is set. CSR.CTSIC is cleared when reading CSR.
Figure 25-18 illustrates receiver functionality, and Figure 25-19 illustrates transmitter
functionality.
Figure 25-18. Receiver Behavior when Operating with Hardware Handshaking
RXD
RXEN = 1 RXDIS = 1
Write
CR
RTS
RXBUFF
Figure 25-19. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
25.6.7 Modem Mode
The USART features a modem mode, supporting asynchronous communication with the follow-
ing signal pins: Data Terminal Ready (DTR), Data Set Ready (DSR), Request to Send (RTS),
Clear to Send (CTS), Data Carrier Detect (DCD), and Ring Indicator (RI). Modem mode is
enabled by writing 0x3 to MR.MODE. The USART will behave as a Data Terminal Equipment
(DTE), controlling DTR and RTS, while detecting level changes on DSR, DCD, CTS, and RI.
Table 25-8 shows USART signal pins with the corresponding standardized modem connections.
Table 25-8. Circuit References
USART Pin V.24 CCITT Direction
TXD 2 103 From terminal to modem
RTS 4 105 From terminal to modem
DTR 20 108.2 From terminal to modem
RXD 3 104 From modem to terminal
CTS 5 106 From terminal to modem
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Table 25-8. Circuit References
USART Pin V.24 CCITT Direction
DSR 6 107 From terminal to modem
DCD 8 109 From terminal to modem
RI 22 125 From terminal to modem
The DTR pin is controlled by the DTR enable and disable bits in CR (CR.DTREN and
CR.DTRDIS). Writing a one to CR.DTRDIS drives DTR high, and writing a one to CR.DTREN
drives DTR low. The RTS pin is controlled automatically.
Detected level changes are reported by the respective Input Change bits in CSR (CSR.RIIC,
CSR.DSRIC, CSR.DCDIC, and CSR.CTSIC). An interrupt request is generated if the corre-
sponding bit in the Interrupt Mask Register is set. The Input Change bits in CSR are
automatically cleared when CSR is read. When the CTS pin goes high, the USART will wait for
the transmitter to complete any ongoing character transmission before automatically disabling it.
25.6.8 ISO7816 Mode
The USART features an ISO7816 compatible mode, enabling interfacing with smart cards and
Security Access Modules (SAM) through an ISO7816 compliant link. T=0 and T=1 protocols, as
defined in the ISO7816 standard, are supported. The ISO7816 mode is selected by writing the
value 0x4 (T=0 protocol) or 0x6 (T=1 protocol) to MR.MODE.
25.6.8.1 ISO7816 Mode Overview
ISO7816 specifies half duplex communication on one bidirectional line. The baud rate is a frac-
tion of the clock provided by the master on the CLK pin (see ”Baud Rate Generator” on page
558). The USART connects to a smart card as shown in Figure 25-20. The TXD pin is bidirec-
tional and is routed to the receiver when the transmitter is disabled. Having both receiver and
transmitter enabled simultaneously may lead to unpredictable results.
Figure 25-20. USART (Master) Connected to a Smart Card
USART
CLK
CLK
Smart
I/O Card
TXD
In both T=0 and T=1 modes, the character format is fixed to eight data bits, and one or two stop
bits, regardless of CHRL, MODE9, and CHMODE values. Parity according to specification is
even. If the inverse transmission format is used, where payload data bits are transmitted
inverted on the I/O line, the user can use odd parity and perform an XOR on data headed to
THR and coming from RHR.
25.6.8.2 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
Di
B = ------ × f
Fi
where:
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• B is the bit rate
• Di is the bit-rate adjustment factor
• Fi is the clock frequency division factor
• f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 25-9.
Table 25-9. Binary and Decimal Values for Di
DI field 0001 0010 0011 0100 0101 0110 1000 1001
Di (decimal) 1 2 4 8 16 32 12 20
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 25-10.
Table 25-10. Binary and Decimal Values for Fi
FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101
Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048
Table 25-11 shows the resulting Fi/Di ratio, which is the ratio between the ISO7816 clock and
the Baud Rate Clock.
Table 25-11. Possible Values for the Fi/Di Ratio
Fi 372 558 744 1116 1488 1860 512 768 1024 1536 2048
Di=2 186 279 372 558 744 930 256 384 512 768 1024
Di=4 93 139.5 186 279 372 465 128 192 256 384 512
Di=8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256
Di=16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128
Di=32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64
Di=12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6
Di=20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
The clock selected by MR.USCLKS can be output on the CLK pin to feed the smart card clock
inputs. To output the clock, the user must write a one to the Clock Output Select bit in MR
(MR.CLKO). The clock is divided by BRGR.CD before it is output on the CLK pin. If CLK is
selected as clock source in MR.USCLKS, the clock can not be output on the CLK pin.
The selected clock is divided by the FI Over DI Ratio Value field in the FI DI Ratio Register
(FIDI.FI_DI_RATIO), which can be up to 2047 in ISO7816 mode. This will be rounded off to an
integral so the user has to select a FI_DI_RATIO value that comes as close as possible to the
expected Fi/Di ratio. The FI_DI_RATIO reset value is 0x174 (372 in decimal) and is the most
common divider between the ISO7816 clock and bit rate (Fi=372, Di=1). Figure 25-21 shows the
relationship between the Elementary Time Unit (ETU), corresponding to a bit period, and the
ISO 7816 clock.
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Figure 25-21. Elementary Time Unit (ETU)
FI_DI_RATIO
ISO7816 Clock Cycles
ISO7816 Clock
on CLK
ISO7816 I/O Line
on TXD
1 ETU
25.6.8.3 Protocol T=0
In T=0 protocol, a character is made up of one start bit, eight data bits, one parity bit, and a two
bit period guard time. During the guard time, the line will be high if the receiver does not signal a
parity error, as shown in Figure 25-22. The receiver signals a parity error, aka non-acknowledge
(NACK), by pulling the line low for a bit period within the guard time, resulting in the total charac-
ter length being incremented by one, see Figure 25-23. The USART will not load data to RHR if
it detects a parity error, and will set PARE if it receives a NACK.
Figure 25-22. T=0 Protocol without Parity Error
Baud Rate
Clock
RXD
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next
Bit Bit Time 1 Time 2 Start
Bit
Figure 25-23. T=0 Protocol with Parity Error
Baud Rate
Clock
I/O Error
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Start D0 D1
Bit Bit Time 1 Time 2 Bit
Repetition
25.6.8.4 Protocol T=1
In T=1 protocol, the character resembles an asynchronous format with only one stop bit. The
parity is generated when transmitting and checked when receiving. Parity errors set PARE.
25.6.8.5 Receive Error Counter
The USART receiver keeps count of up to 255 errors in the Number Of Errors field in the Num-
ber of Error Register (NER.NB_ERRORS). Reading NER automatically clears NB_ERRORS.
25.6.8.6 Receive NACK Inhibit
The USART can be configured to ignore parity errors by writing a one to the Inhibit Non
Acknowledge bit (MR.INACK). Erroneous characters will be treated as if they were ok, not gen-
erating a NACK, loaded to RHR, and raising RXRDY.
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25.6.8.7 Transmit Character Repetition
The USART can be configured to automatically re-send a character if it receives a NACK. Writ-
ing a non-zero value to MR.MAX_ITERATION will enable and determine the number of
consecutive re-transmissions. If the number of unsuccessful re-transmissions equals
MAX_ITERATION, the iteration bit (CSR.ITER) is set. An interrupt request is generated if the
ITER bit in the Interrupt Mask Register (IMR.ITER) is set. Writing a one to the Reset Iteration bit
(CR.RSTIT) will clear CSR.ITER.
25.6.8.8 Disable Successive Receive NACK
The receiver can limit the number of consecutive NACKs to the value in MR.MAX_ITERATION.
This is enabled by writing a one to the Disable Successive NACK bit (MR.DSNACK). If the num-
ber of NACKs is about to exceed MR.MAX_ITERATION, the character will instead be accepted
as valid and CSR.ITER is set.
25.6.9 IrDA Mode
The USART features an IrDA mode, supporting asynchronous, half-duplex, point-to-point wire-
less communication. It embeds the modulator and demodulator, allowing for a glueless
connection to the infrared transceivers, as shown in Figure 25-24. The IrDA mode is enabled by
writing 0x8 to MR.MODE. This activates the IrDA specification v1.1 compliant modem. Data
transfer speeds ranging from 2.4Kbit/s to 115.2Kbit/s are supported and the character format is
fixed to one start bit, eight data bits, and one stop bit.
Figure 25-24. Connection to IrDA Transceivers
USART IrDA
Transceivers
Receiver Demodulator RXD RX
TX
Transmitter Modulator TXD
The receiver and the transmitter must be exclusively enabled or disabled, according to the direc-
tion of the transmission. To receive IrDA signals, the following needs to be done:
• Disable TX and enable RX.
• Configure the TXD pin as an I/O, outputting zero to avoid LED activation. Disable the internal
pull-up for improved power consumption.
• Receive data.
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25.6.9.1 IrDA Modulation
The RZI modulation scheme is used, where a zero is represented by a light pulse 3/16 of a bit
period, and no pulse to represent a one. Some examples of signal pulse duration are shown in
Table 25-12.
Table 25-12. IrDA Pulse Duration
Baud Rate Pulse Duration (3/16)
2.4 Kbit/s 78.13 µs
9.6 Kbit/s 19.53 µs
19.2 Kbit/s 9.77 µs
38.4 Kbit/s 4.88 µs
57.6 Kbit/s 3.26 µs
115.2 Kbit/s 1.63 µs
Figure 25-25 shows an example of character transmission.
Figure 25-25. IrDA Modulation
Start Data Bits Stop
Bit Bit
Transmitter
0 1 0 1 0 0 1 1 0 1
Output
TXD
Bit Period 3
16 Bit Period
25.6.9.2 IrDA Baud Rate
As the IrDA mode shares some logic with the ISO7816 mode, the FIDI.FI_DI_RATIO field must
be configured correctly. See Section “25.6.16” on page 583. Table 25-13 shows some examples
of BRGR.CD values, baud rate error, and pulse duration. Note that the maximal acceptable error
rate of ±1.87% must be met.
Table 25-13. IrDA Baud Rate Error
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
3 686 400 115 200 2 0.00% 1.63
20 000 000 115 200 11 1.38% 1.63
32 768 000 115 200 18 1.25% 1.63
40 000 000 115 200 22 1.38% 1.63
3 686 400 57 600 4 0.00% 3.26
20 000 000 57 600 22 1.38% 3.26
32 768 000 57 600 36 1.25% 3.26
40 000 000 57 600 43 0.93% 3.26
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Table 25-13. IrDA Baud Rate Error (Continued)
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
3 686 400 38 400 6 0.00% 4.88
20 000 000 38 400 33 1.38% 4.88
32 768 000 38 400 53 0.63% 4.88
40 000 000 38 400 65 0.16% 4.88
3 686 400 19 200 12 0.00% 9.77
20 000 000 19 200 65 0.16% 9.77
32 768 000 19 200 107 0.31% 9.77
40 000 000 19 200 130 0.16% 9.77
3 686 400 9 600 24 0.00% 19.53
20 000 000 9 600 130 0.16% 19.53
32 768 000 9 600 213 0.16% 19.53
40 000 000 9 600 260 0.16% 19.53
3 686 400 2 400 96 0.00% 78.13
20 000 000 2 400 521 0.03% 78.13
32 768 000 2 400 853 0.04% 78.13
25.6.9.3 IrDA Demodulator
The demodulator depends on an 8-bit down counter loaded with the value in the IRDA_Filter
field in the IrDA Filter Register (IFR.IRDA_FILTER). When a falling edge on RXD is detected,
the counter starts decrementing at CLK_USART speed. If a rising edge on RXD is detected , the
counter stops and is reloaded with the IrD Filter value. If no rising edge has been detected when
the counter reaches zero, the receiver input is pulled low during one bit period, see Figure 25-
26. Writing a one to the Infrared Receive Line Filter bit (MR.FILTER), enables a noise filter that,
instead of using just one sample, will choose the majority value from three consecutive samples.
Figure 25-26. IrDA Demodulator Operations
CLK_USART
RXD
Counter Pulse
Value 6 5 4 3 2 6 6 5 4 3 2 1 0 Accepted
Pulse
Rejected
Receiver
Input Driven Low During 16 Baud Rate Clock Cycles
25.6.10 LIN Mode
The USART features a Local Interconnect Network (LIN) 1.3 and 2.0 compliant mode, embed-
ding full error checking and reporting, automatic frame processing with up to 256 data bytes,
customizable response data lengths, and requiring minimal CPU resources. The LIN mode is
enabled by writing 0xA (master) or 0xB (slave) to MR.MODE.
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25.6.10.1 Modes of Operation
Changing LIN mode after initial configuration must be followed by a transceiver software reset in
order to avoid unpredictable behavior.
25.6.10.2 Receiver and Transmitter Control
See Section “25.6.2.1” on page 551.
25.6.10.3 Baud Rate Configuration
The LIN nodes baud rate is configured in the Baud Rate Generator Register (BRGR), See Sec-
tion “25.6.4.1” on page 558.
25.6.10.4 Character Transmission and Reception
See ”Transmitter Operations” on page 551, and ”Receiver Operations” on page 553.
25.6.10.5 Header Transmission (Master Node Configuration)
All LIN frames start with a header sent by the master. As soon as the identifier has been written
to the Identifier Character field in the LIN Identifier Register (LINIR.IDCHR), CSR.TXRDY is
cleared and the header is sent. The header consists of a Break field, a Sync field, and an Identi-
fier field. CSR.TXRDY is set when the identifier has been transferred into the transmitters shift
register. An interrupt request is generated if IMR.TXRDY is set.
The Break field consists of 13 dominant bits (the break) and one recessive bit (the break delim-
iter). The Sync field consists of a start bit, the Sync byte (the character 0x55), and a stop bit,
refer to Figure 25-29. The Identifier field contains the Identifier as written to LINIR.IDCHR. The
identifier parity bits can be generated automatically (see Section 25.6.10.8).
Figure 25-27. Header Transmission
Baud Rate
Clock
TXD
Break Start Stop Start Stop
Break Field 1 0 1 0 1 0 1 0 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Delimiter Bit Bit Bit Bit
13 dominant bits (at 0) Synch Byte = 0x55
1 recessive bit
Write (at 1)
LINIR
LINIR ID
TXRDY
See also ”Master Node Configuration” on page 574.
25.6.10.6 Header Reception (Slave Node Configuration)
The USART stays idle until it detects a break field, consisting of at least 11 consecutive domi-
nant bits (zeroes) on the bus. The Sync field is used to synchronize the baud rate (see Section
25.6.10.7). IDCHR is updated and the LIN Identifier bit (CSR.LINIR) is set when the Identifier
has been received. An interrupt request is generated if the Lin Identifier bit in the Interrupt Mask
Register (IMR.LINIR) is set. The Identifier parity bits can be automatically checked (see Section
25.6.10.8). Writing a one to CR.RSTSTA will clear CSR.LINIR.
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Figure 25-28. Header Reception
Baud Rate
Clock
RXD
Break Field Break Start Stop Start Stop
1 0 1 0 1 0 1 0 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
13 dominant bits (at 0) Delimiter Bit Bit Bit Bit
1 recessive bit Synch Byte = 0x55
(at 1)
LINID
US_LINIR
Write US_CR
With RSTSTA=1
See also ”Slave Node Configuration” on page 576.
25.6.10.7 Slave Node Synchronization
Synchronization is only done by the slave. If the Sync byte is not 0x55, an Inconsistent Sync
Field error is generated, and the LIN Inconsistend Sync Field Error bit in CSR (CSR.LINISFE) is
set. An interrupt request is generated if the LINISFE bit in IMR is set. CSR.LINISFE is cleared by
writing a one to CR.RSTSTA. The time between falling edges is measured by a 19-bit counter,
driven by the sampling clock (see Section 25.6.4).
Figure 25-29. Sync Field
Synch Field
8 Tbit
2 Tbit 2 Tbit 2 Tbit 2 Tbit
Start Stop
bit bit
The counter starts when the Sync field start bit is detected, and continues for eight bit periods.
The 16 most significant bits (counter value divided by 8) becomes the new clock divider
(BRGR.CD), and the three least significant bits (the remainder) becomes the new fractional part
(BRGR.FP).
Figure 25-30. Slave Node Synchronization
Baud Rate
Clock
RXD
Break Start Stop Start Stop
Break Field 1 0 1 0 1 0 1 0 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Delimiter Bit Bit Bit Bit
13 dominant bits (at 0) Synch Byte = 0x55
1 recessive bit
(at 1)
LINIDRX
Reset
Synchro Counter 000_0011_0001_0110_1101
BRGR Initial CD 0000_0110_0010_1101
Clcok Divider (CD)
BRGR Initial FP 101
Fractional Part (FP)
The synchronization accuracy depends on:
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• The theoretical slave node clock frequency; nominal clock frequency (FNom)
• The baud rate
• The oversampling mode (OVER=0 => 16x, or OVER=1 => 8x)
The following formula is used to calculate synchronization deviation, where FSLAVE is the real
slave node clock frequency, and FTOL_UNSYNC is the difference between FNom and FSLAVE. Accord-
ing to the LIN specification, FTOL_UNSYNCH may not exceed ±15%, and the bit rates between two
nodes must be within ±2% of each other, resulting in a maximal BaudRate_deviation of ±1%.
[ α × 8 × ( 2 – OVER ) + β ] × BaudRate
BaudRate_deviation = ⎛ 100 × ---------------------------------------------------------------------------------------------------⎞ %
⎝ 8 × F SLAVE ⎠
⎛ ⎞
⎜ α × 8 × ( 2 – OVER ) + β ] × BaudRate-⎟
[--------------------------------------------------------------------------------------------------
BaudRate_deviation = ⎜ 100 × ⎟%
⎜ ⎛
F TOL_UNSYNC
⎞ ⎟
⎝ 8 × ------------------------------------ xF Nom ⎠
⎝ 100 ⎠
– 0,5 ≤ α ≤ +0,5 -1 < β < +1
Minimum nominal clock frequency with a fractional part:
⎛ ⎞
⎜ 0,5 × 8 × ( 2 – OVER ) + 1 ] × BaudRate-⎟
[------------------------------------------------------------------------------------------------------
F Nom ( min ) = ⎜ 100 × ⎟ Hz
⎜ ⎛ – 15
8 × ---------- + 1 × 1% ⎞ ⎟
⎝ ⎝ 100 ⎠ ⎠
Examples:
• Baud rate = 20 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 2.64 MHz
• Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 1.47 MHz
• Baud rate = 1 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 132 kHz
• Baud rate = 1 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 74 kHz
If the fractional part is not used, the synchronization accuracy is much lower. The 16 most signif-
icant bits, added with the first least significant bit, becomes the new clock divider (CD). The
equation of the baud rate deviation is the same as above, but the constants are:
– 4 ≤ α ≤ +4 -1 < β < +1
Minimum nominal clock frequency without a fractional part:
⎛ ⎞
⎜ 4 × 8 × ( 2 – OVER ) + 1 ] × Baudrate-⎟
[----------------------------------------------------------------------------------------------
F Nom ( min ) = ⎜ 100 × ⎟ Hz
⎜ 8 × ⎛ ---------
– 15- + 1⎞ × 1% ⎟
⎝ ⎝ 100 ⎠ ⎠
Examples:
• Baud rate = 20 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 19.12 MHz
• Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 9.71 MHz
• Baud rate = 1 kbit/s, OVER=0 (Oversampling 16x) => FNom(min) = 956 kHz
• Baud rate = 1 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 485 kHz
25.6.10.8 Identifier Parity
An identifier field consists of two sub-fields; the identifier and its parity. Bits 0 to 5 are assigned
to the identifier, while bits 6 and 7 are assigned to parity. Automatic parity management is
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enabled by default, and can be disabled by writing a one to the Parity Disable bit in the LIN
Mode register (LINMR.PARDIS).
• LINMR.PARDIS=0: During header transmission, the parity bits are computed and in the shift
register they replace bits 6 and 7 from LINIR.IDCHR. During header reception, the parity bits
are checked and can generate a LIN Identifier Parity Error (see Section 25.6.10.13). Bits 6
and 7 in LINIR.IDCHR read as zero when receiving.
• LINMR.PARDIS=1: During header transmission, all the bits in LINIR.IDCHR are sent on the
bus. During header reception, all the bits in LINIR.IDCHR are updated with the received
Identifier.
25.6.10.9 Node Action
After an identifier transaction, a LIN response mode must be selected. This is done in the Node
Action field (LINMR.NACT). Below are some response modes exemplified in a small LIN cluster:
• Response, from master to slave1:
Master: NACT=PUBLISH
Slave1: NACT=SUBSCRIBE
Slave2: NACT=IGNORE
• Response, from slave1 to master:
Master: NACT=SUBSCRIBE
Slave1: NACT=PUBLISH
Slave2: NACT=IGNORE
• Response, from slave1 to slave2:
Master: NACT=IGNORE
Slave1: NACT=PUBLISH
Slave2: NACT=SUBSCRIBE
25.6.10.10 LIN Response Data Length
The response data length is the number of data fields (bytes), excluding the checksum.
Figure 25-31. Response Data Length
User configuration: 1 - 256 data fields (DLC+1)
Identifier configuration: 2/4/8 data fields
Sync Sync Identifier Data Data Data Data Checksum
Break Field Field Field Field Field Field Field
The response data length can be configured, either by the user, or automatically by bits 4 and 5
in the Identifier (LINIR.IDCHR), in accordance to LIN 1.1. The user selects one of these modes
by writing to the Data Length Mode bit (LINMR.DLM):
• LINMR.DLM=0: the response data length is configured by the user by writing to the 8-bit Data
Length Control field (LINMR.DLC). The response data length equals DLC + 1 bytes.
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• LINMR.DLM=1: the response data length is defined by the Identifier (LINIR.IDCHR) bits
according to the table below.
Table 25-14. Response Data Length if DLM = 1
LINIR.IDCHR[5] LINIR.IDCHR[4] Response Data Length [bytes]
0 0 2
0 1 2
1 0 4
1 1 8
25.6.10.11 Checksum
The last frame field is the checksum. It is configured by the Checksum Type (LINMR.CHKTYP),
and the Checksum Disable (LINMR.CHKDIS) bits. CSR.TXRDY will not be set after the last THR
data write if enabled. Writing a one to LINMR.CHKDIS will disable the automatic checksum gen-
eration/checking, and the user may send/check this last byte manually, disguised as a normal
data. The checksum is an inverted 8-bit sum with carry, either:
• Over all data bytes, called a classic checksum. This is used for LIN 1.3 compliant slaves, and
automatically managed when CHKDIS=0, and CHKTYP=1.
• Over all data bytes and the protected identifier, called an enhanced checksum. This is used
for LIN 2.0 compliant slaves, and automatically managed when CHKDIS=0, and CHKTYP=0.
25.6.10.12 Frame Slot Mode
A LIN master can be configured to use frame slots with a pre-defined minimum length. This
Frame Slot mode is enabled by default, and is disabled by writing a one to the Frame Slot Mode
Disable bit (LINMR.FSDIS). The Frame Slot mode will not allow CSR.TXRDY to be set after a
frame transfer until the entire frame slot duration has elapsed, in effect preventing the master
from sending a new header. The LIN Transfer Complete bit (CSR.LINTC) will still be set after the
checksum has been sent. An interrupt is generated if the LIN Transfer Complete bit in the Inter-
rupt Mask Register (IMR.LINTC) is set. Writing a one to CR.RSTSTA clears CSR.LINTC.
Figure 25-32. Frame Slot Mode with Automatic Checksum
Frame slot = TFrame_Maximum
Frame
Inter-
frame
Response
space
space
Header Data3 Response
Break Synch Protected Data 1 Data N-1 Data N Checksum
Identifier
TXRDY
Frame Slot Mode Frame Slot Mode
Disabled Enabled
Write
LINID
Write
THR Data 1 Data 2 Data 3 Data N
LINTC
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The minimum frame slot size is determined by TFrame_Maximum, and calculated below (all val-
ues in bit periods):
• THeader_Nominal = 34
• TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1)
Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specification 1.3)
If the Checksum is sent (CHKDIS=0):
• TResponse_Nominal = 10 x (NData + 1)
• TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1 + 1) + 1)
• TFrame_Maximum = 77 + 14 x DLC
If the Checksum is not sent (CHKDIS=1):
• TResponse_Nominal = 10 x NData
• TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1) + 1)
• TFrame_Maximum = 63 + 14 x DLC
25.6.10.13 LIN Errors
This section describes the errors generated in LIN mode, and the coresponding error bits in
CSR. The error bits are cleared by writing a one to CR.RSTSTA. An interrupt request is gener-
ated if the corresponding bit in the Interrupt Mask Register (IMR) is set. This bit is set by writing
a one to the corresponding bit in the Interrupt Enable Register (IER).
• Slave Not Responding Error (CSR.LINSNRE)
– This error is generated if no valid message appears within the TFrame_Maximum
time frame slot, while the USART is expecting a response from another node
(NACT=SUBSCRIBE).
• Checksum Error (CSR.LINCE)
– This error is generated if the received checksum is wrong. This error can only be
generated if the checksum feature is enabled (CHKDIS=0).
• Identifier Parity Error (CSR.LINIPE)
– This error is generated if the identifier parity is wrong. This error can only be
generated if parity is enabled (PARDIS=0).
• Inconsistent Sync Field Error (CSR.LINISFE)
– This error is generated in slave mode if the Sync Field character received is not
0x55. Synchronization procedure is aborted.
• Bit Error (CSR.LINBE)
– This error is generated if the value transmitted by the USART on Tx differs from the
value sampled on Rx. If a bit error is detected, the transmission is aborted at the
next byte border.
25.6.11 LIN Frame Handling
25.6.11.1 Master Node Configuration
• Configure the baud rate by writing to BRGR.CD and BRGR.FP
• Configure the frame transfer by writing to the LINMR fields NACT, PARDIS, CHKDIS,
CHKTYPE, DLM, FSDIS, and DLC
• Select LIN mode and master node by writing 0xA to MR.MODE
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• Write a one to CR.TXEN and CR.RXEN to enable both transmitter and receiver
• Wait until CSR.TXRDY is one
• Send the header by writing to LINIR.IDCHR
The following procedure depends on the LINMR.NACT setting:
• Case 1: LINMR.NACT is 0x0 (PUBLISH, the USART transmits the response)
– Wait until CSR.TXRDY is one
– Send a byte by writing to THR.TXCHR
– Repeat the two previous steps until there is no more data to send
– Wait until CSR.LINTC is one
– Check for LIN errors
• Case 2: LINMR.NACT is 0x1 (SUBSCRIBE, the USART receives the response)
– Wait until CSR.RXRDY is one
– Read RHR.RXCHR
– Repeat the two previous steps until there is no more data to read
– Wait until CSR.LINTC is one
– Check for LIN errors
• Case 3: LINMR.NACT is 0x2 (IGNORE, the USART is not concerned by a response)
– Wait until CSR.LINTC is one
– Check for LIN errors
Figure 25-33. Master Node Configuration, LINMR.NACT is 0x0 (PUBLISH)
Frame slot = TFrame_Maximum
Frame
Inter-
frame
Response space
space
Header Data3 Response
Break Synch Protected Data 1 Data N-1 Data N Checksum
Identifier
TXRDY
FSDIS=1 FSDIS=0
RXRDY
Write
LINIR
Write
THR Data 1 Data 2 Data 3 Data N
LINTC
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Figure 25-34. Master Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE)
Frame slot = TFrame_Maximum
Frame Inter-
frame
Response space
space
Header Data3 Response
Break Synch Protected Data 1 Data N-1 Data N Checksum
Identifier
TXRDY
FSDIS=1 FSDIS=0
RXRDY
Write
LINIR
Read
RHR Data 1 Data N-2 Data N-1 Data N
LINTC
Figure 25-35. Master Node Configuration, LINMR.NACT is 0x2 (IGNORE)
Frame slot = TFrame_Maximum
Frame Inter-
frame
Response space
space
Header Data3 Response
Break Synch Protected Data 1 Data N-1 Data N Checksum
Identifier
TXRDY
FSDIS=1 FSDIS=0
RXRDY
Write
LINIR
LINTC
25.6.11.2 Slave Node Configuration
• Configure the baud rate by writing to BRGR.CD and BRGR.FP
• Configure the frame transfer by writing to LINMR fields NACT, PARDIS, CHKDIS, CHKTYPE,
DLM, and DLC
• Select LIN mode and slave node by writing 0xB to MR.MODE
• Write a one to CR.TXEN and CR.RXEN to enable both transmitter and receiver
• Wait until CSR.LINIR is one
• Check for CSR.LINISFE and CSR.LINPE errors, clear errors and CSR.LINIR by writing a one
to CR.RSTSTA
• Read LINIR.IDCHR
IMPORTANT: If LINMR.NACT is 0x0 (PUBLISH), and this field is already correct, the LINMR
register must still be written with this value in order to set CSR.TXRDY, and to request the corre-
sponding Peripheral DMA Controller write transfer.
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The different LINMR.NACT settings result in the same procedure as for the master node, see
page 574.
Figure 25-36. Slave Node Configuration, LINMR.NACT is 0x0 (PUBLISH)
Break Synch Protected Data 1 Data N-1 Data N Checksum
Identifier
TXRDY
RXRDY
LINIDRX
Read
LINID
Write
THR Data 1 Data 2 Data 3 Data N
LINTC
Figure 25-37. Slave Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE)
Break Synch Protected Data 1 Data N-1 Data N Checksum
Identifier
TXRDY
RXRDY
LINIDRX
Read
LINID
Read
RHR Data 1 Data N-2 Data N-1 Data N
LINTC
Figure 25-38. Slave Node Configuration, LINMR.NACT is 0x2 (IGNORE)
Break Synch Protected Data 1 Data N-1 Data N Checksum
Identifier
TXRDY
RXRDY
LINIDRX
Read
LINID
Read
RHR
LINTC
25.6.12 LIN Frame Handling With The Peripheral DMA Controller
The USART can be used together with the Peripheral DMA Controller in order to transfer data
without processor intervention. The Peripheral DMA Controller uses the CSR.TXRDY and
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CSR.RXRDY bits to trigger one byte writes or reads. It always writes to THR, and it always reads
RHR.
25.6.12.1 Master Node Configuration
The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration:
• LINMR.PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write
buffer.
• LINMR.PDCM=1: LIN configuration is written by the Peripheral DMA Controller to THR, and
is stored in the write buffer. Since data transfer size is a byte, the transfer is split into two
accesses. The first writes the NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS bits in the
LINMR register, while the second writes the LINMR.DLC field. If LINMR.NACT=PUBLISH,
the write buffer will also contain the Identifier.
When LINMR.NACT=SUBSCRIBE, the read buffer contains the data.
Figure 25-39. Master Node with Peripheral DMA Controller (LINMR.PDCM=0)
WRITE BUFFER
DATA 0
NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE
Peripheral Peripheral
bus bus
DATA 1
READ BUFFER
Peripheral DMA USART LIN Peripheral DMA USART LIN
Controller CONTROLLER Controller RXRDY CONTROLLER
| DATA 0
| RXRDY
|
| TXRDY
|
|
DATA N |
|
DATA N
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Figure 25-40. Master Node with Peripheral DMA Controller (LINMR.PDCM=1)
WRITE BUFFER WRITE BUFFER
NACT NACT
PARDIS PARDIS
CHKDIS CHKDIS
CHKTYP CHKTYP
DLM DLM
FSDIS FSDIS
DLC DLC
Peripheral NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE
IDENTIFIER Peripheral
bus bus
IDENTIFIER
Peripheral DMA USART LIN
Peripheral DMA USART LIN READ BUFFER CONTROLLER
CONTROLLER Controller RXRDY
Controller
RXRDY
DATA 0
DATA 0 TXRDY
|
|
|
|
|
| |
|
DATA N
DATA N
25.6.12.2 Slave Node Configuration
In this mode, the Peripheral DMA Controller transfers only data. The user reads the Identifier
from LINIR, and selects LIN mode by writing to LINMR. When NACT=PUBLISH the data is in the
write buffer, while the read buffer contains the data when NACT=SUBSCRIBE.
IMPORTANT: If in slave mode, LINMR.NACT is already configured correctly as PUBLISH, the
LINMR register must still be written with this value in order to set CSR.TXRDY, and to request
the corresponding Peripheral DMA Controller write transfer.
Figure 25-41. Slave Node with Peripheral DMA Controller
WRITE BUFFER READ BUFFER
DATA 0 DATA 0 NACT = SUBSCRIBE
Peripheral Peripheral
bus Bus
| |
| Peripheral DMA USART LIN | Peripheral DMA USART LIN
|
Controller CONTROLLER |
Controller CONTROLLER
| |
TXRDY RXRDY
DATA N DATA N
25.6.13 Wake-up Request
Any node in a sleeping LIN cluster may request a wake-up. By writing to the Wakeup Signal
Type bit (LINMR.WKUPTYP), the user can choose to send either a LIN 1.3 (WKUPTYP is one )
or a LIN 2.0 (WKUPTYP is zero) compliant wakeup request. Writing a one to the Send LIN
Wakeup Signal bit (CR.LINWKUP), transmits a wakeup, and when completed, sets CSR.LINTC.
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According to LIN 1.3, the wakeup request should be generated with the character 0x80 in order
to impose eight successive dominant bits.
According to LIN 2.0, the wakeup request is issued by forcing the bus into the dominant state for
250µs to 5ms. Sending the character 0xF0 does this, regardless of baud rate.
• Baud rate max = 20 kbit/s -> one bit period = 50µs -> five bit periods = 250µs
• Baud rate min = 1 kbit/s -> one bit period = 1ms -> five bit periods = 5ms
25.6.14 Bus Idle Time-out
LIN bus inactivity should eventually cause slaves to time out and enter sleep mode. LIN 1.3
specifies this to 25000 bit periods, whilst LIN 2.0 specifies 4 seconds. For the time-out counter
operation see Section 25.6.3.4 ”Receiver Time-out” on page 556.
Table 25-15. Receiver Time-out Values (RTOR.TO)
LIN Specification Baud Rate Time-out period TO
1 000 bit/s 4 000
2 400 bit/s 9 600
2.0 9 600 bit/s 4s 38 400
19 200 bit/s 76 800
20 000 bit/s 80 000
1.3 - 25 000 bit periods 25 000
25.6.15 SPI Mode
The USART features a Serial Peripheral Interface (SPI) link compliant mode, supporting syn-
chronous, full-duplex communication in both master and slave mode. Writing 0xE (master) or
0xF (slave) to MR.MODE will enable this mode. An SPI in master mode controls the data flow to
and from the other SPI devices, which are in slave mode. It is possible to let devices take turns
being masters (aka multi-master protocol), and one master may shift data simultaneously into
several slaves, but only one slave may respond at a time. A slave is selected when its slave
select (NSS) signal has been raised by the master. The USART can only generate one NSS sig-
nal, and it is possible to use standard I/O lines to address more than one slave.
25.6.15.1 Modes of Operation
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This line supplies the data shifted from master to slave. In
master mode this is connected to TXD, and in slave mode to RXD.
• Master In Slave Out (MISO): This line supplies the data shifted from slave to master. In
master mode this is connected to RXD, and in slave mode to TXD.
• Serial Clock (CLK): This is controlled by the master. One period per bit transmission. In both
modes this is connected to CLK.
• Slave Select (NSS): This control line allows the master to select or deselect a slave. In
master mode this is connected to RTS, and in slave mode to CTS.
Changing SPI mode after initial configuration must be followed by a transceiver software reset in
order to avoid unpredictable behavior.
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25.6.15.2 Baud Rate
The baud rate generator operates as described in ”Baud Rate in Synchronous and SPI Mode”
on page 560, with the following requirements:
In SPI Master Mode:
• External clock CLK must not be selected as clock (the Clock Selection field (MR.USCLKS)
must not equal 0x3).
• The USART must drive the CLK pin (MR.CLKO must be one).
• The BRGR.CD field must be at least 0x4.
• If the internal divided clock, CLK_USART/DIV, is selected (MR.USCLKS is one), the value in
BRGR.CD must be even, ensuring a 50:50 duty cycle.
In SPI Slave Mode:
• The frequency of the external clock CLK must be at least four times lower than the system
clock.
25.6.15.3 Data Transfer
Up to nine data bits are successively shifted out on the TXD pin at each edge. There are no
start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL), and
SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits are
shifted and sampled, resulting in four non-interoperable protocol modes, see Table 25-16. If
MR.CPOL is zero, the inactive state value of CLK is logic level zero, and if MR.CPOL is one, the
inactive state value of CLK is logic level one. If MR.CPHA is zero, data is changed on the lead-
ing edge of CLK, and captured on the following edge of CLK. If MR.CPHA is one, data is
captured on the leading edge of CLK, and changed on the following edge of CLK. A mas-
ter/slave pair must use the same configuration, and the master must be reconfigured if it is to
communicate with slaves using different configurations. See Figures 25-42 and 25-43.
Table 25-16. SPI Bus Protocol Modes
MR.CPOL MR.CPHA SPI Bus Protocol Mode
0 1 0
0 0 1
1 1 2
1 0 3
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Figure 25-42. SPI Transfer Format (CPHA=1, 8 bits per transfer)
CLK cycle (for reference) 1 2 3 4 5 6 7 8
C LK
(C POL= 0)
C LK
(CPO L= 1)
M O SI
SPI M aster ->TXD M SB 6 5 4 3 2 1 LSB
SPI Slave ->RXD
M ISO
SPI M aster ->RXD M SB 6 5 4 3 2 1 LSB
SPI Slave ->TXD
NSS
SPI M aster ->RTS
SPI Slave ->CTS
Figure 25-43. SPI Transfer Format (CPHA=0, 8 bits per transfer)
CLK cycle (for reference) 1 2 3 4 5 6 7 8
CLK
(CPOL= 0)
CLK
(CPOL= 1)
M O SI
SPI M aster -> TXD M SB 6 5 4 3 2 1 LSB
SPI Slave -> RXD
M ISO
SPI M aster -> RXD M SB 6 5 4 3 2 1 LSB
SPI Slave -> TXD
NSS
SPI M aster -> RTS
SPI Slave -> CTS
25.6.15.4 Receiver and Transmitter Control
See ”Manchester Encoder” on page 583, and ”Receiver Status” on page 553.
25.6.15.5 Character Transmission and Reception
In SPI master mode, the slave select line (NSS) is asserted low one bit period before the start of
transmission, and released high one bit period after every character transmission. A delay for at
least three bit periods is always inserted in between characters. In order to address slave
devices supporting the Chip Select Active After Transfer (CSAAT) mode, NSS can be forced low
by writing a one to the Force SPI Chip Select bit (CR.RTSEN/FCS). Releasing NSS when FCS
is one is only possible by writing a one to the Release SPI Chip Select bit (CR.RTSDIS/RCS).
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In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a
transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a character must be sent
while THR is empty, and TXD will be high during character transmission, as if 0xFF was being
sent. An interrupt request is generated if the Underrun Error bit in the Interrupt Mask Register
(IMR.UNRE) is set. If a new character is written to THR it will be sent correctly during the next
transmission slot. Writing a one to CR.RSTSTA will clear CSR.UNRE. To ensure correct behav-
ior of the receiver in SPI slave mode, the master device sending the frame must ensure a
minimum delay of one bit period in between each character transmission.
25.6.15.6 Receiver Time-out
Receiver Time-outs are not possible in SPI mode as the Baud Rate Clock is only active during
data transfers.
25.6.16 Manchester Encoder/Decoder
Writing a one to the Manchester Encoder/Decoder bit in the Mode Register (MR.MAN) enables
the Manchester Encoder/Decoder. When the Manchester Encoder/Decoder is used, characters
transmitted through the USART are encoded in Manchester II Biphase format. Depending on
polarity configuration, selected by the Transmission Manchester Polarity bit in the Manchester
Configuration Register (MAN.TX_MOPL), a logic level (zero or one) is transmitted as the transi-
tion from high -to-low or low-to-high during the middle of each bit period. This consumes twice
the bandwidth of the simpler NRZ coding schemes, but the receiver has more error control since
the expected input has a transition at every mid-bit period.
25.6.16.1 Manchester Encoder
An example of a Manchester encoded sequence is the byte 0xB1 (10110001) being encoded to
10 01 10 10 01 01 01 10, assuming default encoder polarity. Figure 25-44 illustrates this coding
scheme.
Figure 25-44. NRZ to Manchester Encoding
NRZ 1 0 1 1 0 0 0 1
encoded
data
Manchester
encoded Txd
data
A Manchester encoded character can be preceded by both a preamble sequence and a start
frame delimiter. The preamble sequence is a pre-defined pattern with a configurable length from
1 to 15 bit periods. If the preamble length is zero, the preamble waveform is not generated. The
preamble length is selected by writing to the Transmitter Preamble Length field (MAN.TX_PL).
The available preamble sequence patterns are:
• ALL_ONE
• ALL_ZERO
• ONE_ZERO
• ZERO_ONE
and are selected by writing to the Transmitter Preamble Pattern field (MAN.TX_PP). Figure 25-
45 illustrates the supported patterns.
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Figure 25-45. Preamble Patterns, Default Polarity Assumed
Manchester
encoded SFD DATA
data Txd
8 bit width "ALL_ONE" Preamble
Manchester
encoded SFD DATA
data Txd
8 bit width "ALL_ZERO" Preamble
Manchester
encoded SFD
Txd DATA
data
8 bit width "ZERO_ONE" Preamble
Manchester
encoded SFD DATA
data Txd
8 bit width "ONE_ZERO" Preamble
The Start Frame Delimiter Selector bit (MR.ONEBIT) configures the Manchester start bit pattern
following the preamble. If MR.ONEBIT is one, a Manchester encoded zero is transmitted to indi-
cate that a new character is about to be sent. If MR.ONEBIT is zero, a synchronization pattern is
sent for the duration of three bit periods to inaugurate the new character. The sync pattern wave-
form by itself is an invalid Manchester encoding, since the transition only occurs at the middle of
the second bit period.
The Manchester Synchronization Mode bit (MR.MODSYNC) selects sync pattern, and this also
defines if the character is data (MODSYNC=0) with a zero to one transition, or a command
(MODSYNC=1) with a one to zero transition. When direct memory access is used, the sync pat-
tern can be updated on-the-fly with a modified character located in memory. To enable this
mode the Variable Synchronization of Command/Data Sync Start Frame Delimiter bit
(MR.VAR_SYNC) must be written to one. In this case, MODSYNC is bypassed and
THR.TXSYNH selects the sync type to be included. Figure 25-46 illustrates supported patterns.
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Figure 25-46. Start Frame Delimiter
Preamble Length
is set to 0
SFD
Manchester
encoded DATA
data Txd
One bit start frame delimiter
SFD
Manchester
encoded DATA
Txd
data
Command Sync
start frame delimiter
SFD
Manchester
encoded DATA
data Txd
Data Sync
start frame delimiter
Manchester Drift Compensation
The Drift Compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery
system that allows for sub-optimal clock drifts without further user intervention. Drift compensa-
tion is only available in 16x oversampling mode (MR.OVER is zero). If the RXD event is one 16th
clock cycle from the expected edge, it is considered as normal jitter and no corrective action will
be taken. If the event is two to four 16th’s early, the current period will be shortened by a 16th. If
the event is two to three 16th’s after the expected edge, the current period will be prolonged by a
16th.
Figure 25-47. Bit Resynchronization
Oversampling
16x Clock
RXD
Sampling
point
Expected edge
Synchro. Tolerance Sync Synchro.
Synchro. Jump Jump Error
Error
25.6.16.2 Manchester Decoder
The Manchester decoder can detect selectable preamble sequences and start frame delimiters.
The Receiver Manchester Polarity bit in the “Manchester Configuration Register”
(MAN.RX_MPOL) selects input stream polarity. The Receiver Preamble Length field
(MAN.RX_PL) specifies the length characteristics of detectable preambles. If MAN.RX_PL is
zero, the preamble pattern detection will be disabled. The Receiver Preamble Pattern field
(MAN.RX_PP) selects the pattern to be detected. See Figure 25-45 for available preamble pat-
terns. Figure 25-48 illustrates two types of Manchester preamble pattern mismatches.
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The Manchester endec uses the same Start Frame Delimiter Selector (MR.ONEBIT) for both
encoder and decoder. If ONEBIT is one, only a Manchester encoded zero will be accepted as a
valid start frame delimiter. If ONEBIT is zero, a data or command sync pattern will be expected.
The Received Sync bit in the Receive Holding Register (RHR.RXSYNH) will be zero if the last
character received is a data sync, and a one if it is a command sync.
Figure 25-48. Preamble Pattern Mismatch
Preamble Mismatch Preamble Mismatch
Manchester coding error invalid pattern
Manchester
encoded SFD DATA
data Txd
Preamble Length is set to 8
The receiver samples the RXD line in continuos bit period quarters, making the smallest time
frame in which to assume a bit value three quarters. A start bit is assumed if RXD is zero during
one of these quarters, see Figure 25-49.
Figure 25-49. Asynchronous Start Bit Detection
Sampling
Clock
(16 x)
Manchester
encoded
data Txd
Start
Detection
1 2 3 4
If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding
with the same synchronization. If a non-valid preamble pattern or a start frame delimiter is
detected, the receiver re-synchronizes at the next valid edge. When a valid start sequence has
been detected, the decoded data is passed to the USART and the user will be notified of any
incoming Manchester encoding violations by the Manchester Error bit (CSR.MANERR). An inter-
rupt request is generated if one of the Manchester Error bits in the Interrupt Mask Register
(IMR.MANE or IMR.MANEA) is set. CSR.MANERR is cleared by writing a one to the Reset Sta-
tus bits in the Control Register (CR.RSTSTA). A violation occurs when there is no transition in
the middle of a bit period. See Figure 25-50 for an illustration of a violation causing the Man-
chester Error bit to be set.
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Figure 25-50. Manchester Error
Preamble Length
is set to 4
Elementary character bit time
SFD
Manchester
encoded
Txd
data
Entering USART character area
sampling points
Preamble subpacket Manchester
and Start Frame Delimiter Coding Error
were successfully detected
decoded
25.6.16.3 Radio Interface: Manchester Endec Application
This section describes low data rate, full duplex, dual frequency, RF systems integrated with a
Manchester endec, that support ASK and/or FSK modulation schemes. See Figure 25-51.
Figure 25-51. Manchester Encoded Characters RF Transmission
Fup frequency Carrier
ASK/FSK
Upstream Receiver
Upstream
LNA Serial
Emitter VCO Configuration
RF filter Interface
Demod
control Manchester USART
Fdown frequency Carrier bi-dir decoder Receiver
line
ASK/FSK
downstream transmitter
Manchester USART
Downstream encoder Emitter
Receiver PA
RF filter
Mod
VCO
control
To transmit downstream, encoded data is sent serially to the RF modulator and then through
space to the RF receiver. To receive, another frequency carrier is used and the RF demodulator
does a bit-checking search for valid patterns before it switches to a receiving mode and forwards
data to the decoder. Defining preambles to help distinguish between noise and valid data has to
be done in conjunction with the RF module, and may sometimes be filtered away from the endec
stream. Using the ASK modulation scheme, a one is transmitted as an RF signal at the down-
stream frequency, while a zero is transmitted as no signal. See Figure 25-52. The FSK
modulation scheme uses two different frequencies to transmit data. A one is sent as a signal on
one frequency, and a zero on the other. See Figure 25-53.
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Figure 25-52. ASK Modulator Output
1 0 0 1
NRZ stream
Manchester
encoded
data
default polarity Txd
unipolar output
ASK Modulator
Output
Uptstream Frequency F0
Figure 25-53. FSK Modulator Output
1 0 0 1
NRZ stream
Manchester
encoded
data Txd
default polarity
unipolar output
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
25.6.17 Test Modes
The internal loopback feature enables on-board diagnostics, and allows the USART to operate
in three different test modes, with reconfigured pin functionality, as shown below.
25.6.17.1 Normal Mode
During normal operation, a receiver RXD pin is connected to a transmitter TXD pin.
Figure 25-54. Normal Mode Configuration
RXD
Receiver
TXD
Transmitter
25.6.17.2 Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it
is also sent to the TXD pin, as shown in Figure 25-55. Transmitter configuration has no effect.
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Figure 25-55. Automatic Echo Mode Configuration
RXD
Receiver
TXD
Transmitter
25.6.17.3 Local Loopback Mode
Local loopback mode connects the output of the transmitter directly to the input of the receiver,
as shown in Figure 25-56. The TXD and RXD pins are not used. The RXD pin has no effect on
the receiver and the TXD pin is continuously driven high, as in idle state.
Figure 25-56. Local Loopback Mode Configuration
RXD
Receiver
TXD
Transmitter 1
25.6.17.4 Remote Loopback Mode
Remote loopback mode connects the RXD pin to the TXD pin, as shown in Figure 25-57. The
transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit
retransmission.
Figure 25-57. Remote Loopback Mode Configuration
RXD
Receiver 1
TXD
Transmitter
25.6.18 Interrupts
– – MANEA
23 22 21 20 19 18 17 16
– – – MANE CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
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7 6 5 4 3 2 1 0
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
The USART has the following interrupt sources:
• LINSNRE: LIN Slave Not Responding Error
– A LIN Slave Not Responding Error has been detected
• LINCE: LIN Checksum Error
– A LIN Checksum Error has been detected
• LINIPE: LIN Identifier Parity Error
– A LIN Identifier Parity Error has been detected
• LINISFE: LIN Inconsistent Sync Field Error
– The USART is configured as a Slave node and a LIN Inconsistent Sync Field Error
has been detected since the last RSTSTA.
• LINBE: LIN Bit Error
– A Bit Error has been detected since the last RSTSTA.
• MANERR: Manchester Error
– At least one Manchester error has been detected since the last RSTSTA.
• CTSIC: Clear to Send Input Change Flag
– At least one change has been detected on the CTS pin since the last CSR read.
• DCDIC: Data Carrier Detect Input Change Flag
– A change has been detected on the DCD pin
• DSRIC: Data Set Ready Input Change Flag
– A change has been detected on the DSR pin
• RIIC: Ring Indicator Input Change Flag
– A change has been detected on the RI pin
• LINTC: LIN Transfer Completed
– A LIN transfer has been completed
• LINIDR: LIN Identifier
– A LIN Identifier has been sent (master) or received (slave)
• NACK: Non Acknowledge
– At least one Non Acknowledge has been detected
• RXBUFF: Reception Buffer Full
– The Buffer Full signal from the Peripheral DMA Controller channel is active.
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
– IF USART does not operate in SPI slave mode: Maximum number of repetitions has
been reached since the last RSTSTA.
– If USART operates in SPI slave mode: At least one SPI underrun error has occurred
since the last RSTSTA.
• TXEMPTY: Transmitter Empty
– There are no characters in neither THR, nor in the transmit shift register.
• TIMEOUT: Receiver Time-out
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– There has been a time-out since the last Start Time-out command.
• PARE: Parity Error
– Either at least one parity error has been detected, or the parity bit is a one in
multidrop mode, since the last RSTSTA.
• FRAME: Framing Error
– At least one stop bit has been found as low since the last RSTSTA.
• OVRE: Overrun Error
– At least one overrun error has occurred since the last RSTSTA.
• RXBRK: Break Received/End of Break
– Break received or End of Break detected since the last RSTSTA.
• TXRDY: Transmitter Ready
– There is no character in the THR.
• RXRDY: Receiver Ready
– At least one complete character has been received and RHR has not yet been read.
An interrupt source will set a corresponding bit in the Channel Status Register (CSR). The inter-
rupt sources will generate an interrupt request if the corresponding bit in the Interrupt Mask
Register (IMR) is set. The interrupt sources are ORed together to form one interrupt request.
The USART will generate an interrupt request if at least one of the bits in IMR is set. Bits in IMR
are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and
cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The
interrupt request remains active until the corresponding bit in CSR is cleared. The clearing of the
bits in CSR is described in ”Channel Status Register” on page 602. Because all the interrupt
sources are ORed together, the interrupt request from the USART will remain active until all the
bits in CSR are cleared.
25.6.19 Using the Peripheral DMA Controller
25.6.20 Write Protection Registers
To prevent single software errors from corrupting USART behavior, certain address spaces can
be write-protected by writing the correct Write Protect KEY and writing a one to the Write Protect
Enable bit in the Write Protect Mode Register (WPMR.WPKEY and WPMR.WPEN). Disabling
the write protection is done by writing the correct key to WPMR.WPKEY and a zero to
WPMR.WPEN.
Write attempts to a write-protected register are detected and the Write Protect Violation Status
bit in the Write Protect Status Register (WPSR.WPVS) is set. The Write Protect Violation Source
field (WPSR.WPVSRC) indicates the target register. Writing the correct key to the Write Protect
KEY bit (WPMR.WPKEY) clears WPSR. WPVSRC and WPSR.WPVS.
The protected registers are:
• ”Mode Register” on page 596
• ”Baud Rate Generator Register” on page 607
• ”Receiver Time-out Register” on page 609
• ”Transmitter Timeguard Register” on page 610
• ”FI DI Ratio Register” on page 611
• ”IrDA Filter Register” on page 613
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• ”Manchester Configuration Register” on page 614
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25.7 User Interface
Table 25-17. USART Register Memory Map
Offset Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read-write 0x00000000
0x08 Interrupt Enable Register IER Write-only 0x00000000
0x0C Interrupt Disable Register IDR Write-only 0x00000000
0x010 Interrupt Mask Register IMR Read-only 0x00000000
0x14 Channel Status Register CSR Read-only 0x00000000
0x18 Receiver Holding Register RHR Read-only 0x00000000
0x1C Transmitter Holding Register THR Write-only 0x00000000
0x20 Baud Rate Generator Register BRGR Read-write 0x00000000
0x24 Receiver Time-out Register RTOR Read-write 0x00000000
0x28 Transmitter Timeguard Register TTGR Read-write 0x00000000
0x40 FI DI Ratio Register FIDI Read-write 0x00000174
0x44 Number of Errors Register NER Read-only 0x00000000
0x4C IrDA Filter Register IFR Read-write 0x00000000
0x50 Manchester Configuration Register MAN Read-write 0x30011004
0x54 LIN Mode Register LINMR Read-write 0x00000000
0x58 LIN Identifier Register LINIR Read-write 0x00000000
0xE4 Write Protect Mode Register WPMR Read-write 0x00000000
0xE8 Write Protect Status Register WPSR Read-only 0x00000000
0xFC Version Register VERSION Read-only -(1)
Note: 1. Values in the Version Register vary with the version of the IP block implementation.
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25.7.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – LINWKUP LINABT RTSDIS/RCS RTSEN/FCS DTRDIS DTREN
15 14 13 12 11 10 9 8
RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA
7 6 5 4 3 2 1 0
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
• LINWKUP: Send LIN Wakeup Signal
Writing a zero to this bit has no effect.
Writing a one to this bit will send a wakeup signal on the LIN bus.
• LINABT: Abort LIN Transmission
Writing a zero to this bit has no effect.
Writing a one to this bit will abort the current LIN transmission.
• RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS high.
Writing a one to this bit when USART is in SPI master mode releases NSS (RTS pin).
• RTSEN/FCS: Request to Send Enable/Force SPI Chip Select
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS low.
Writing a one to this bit when USART is in SPI master mode forces NSS (RTS pin) low, even if USART is not transmitting, in
order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer).
• DTRDIS: Data Terminal Ready Disable
Writing a zero to this bit has no effect.
Writing a one to this bit drives DTR high.
• DTREN: Data Terminal Ready Enable
Writing a zero to this bit has no effect.
Writing a one to this bit drives DTR low.
• RETTO: Rearm Time-out
Writing a zero to this bit has no effect.
Writing a one to this bit reloads the time-out counter and clears CSR.TIMEOUT.
• RSTNACK: Reset Non Acknowledge
Writing a zero to this bit has no effect.
Writing a one to this bit clears CSR.NACK.
• RSTIT: Reset Iterations
Writing a zero to this bit has no effect.
Writing a one to this bit clears CSR.ITER if ISO7816 is enabled (MR.MODE is 0x4 or 0x6)
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• SENDA: Send Address
Writing a zero to this bit has no effect.
Writing a one to this bit will in multidrop mode send the next character written to THR as an address.
• STTTO: Start Time-out
Writing a zero to this bit has no effect.
Writing a one to this bit will abort any current time-out count down, and trigger a new count down when the next character has
been received. CSR.TIMEOUT is also cleared.
• STPBRK: Stop Break
Writing a zero to this bit has no effect.
Writing a one to this bit will stop the generation of break signal characters, and then send ones for TTGR.TG duration, or at least
12 bit periods. No effect if no break is being transmitted.
• STTBRK: Start Break
Writing a zero to this bit has no effect.
Writing a one to this bit will start transmission of break characters when current characters present in THR and the transmit shift
register have been sent. No effect if a break signal is already being generated. CSR.TXRDY and CSR.TXEMPTY will be
cleared.
• RSTSTA: Reset Status Bits
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the following bits in CSR: PARE, FRAME, OVRE, MANERR, LINBE, LINISFE, LINIPE, LINCE,
LINSNRE, LINTC, LINIR, UNRE, and RXBRK.
• TXDIS: Transmitter Disable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the transmitter.
• TXEN: Transmitter Enable
Writing a zero to this bit has no effect.
Writing a one to this bit enables the transmitter if TXDIS is zero.
• RXDIS: Receiver Disable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the receiver.
• RXEN: Receiver Enable
Writing a zero to this bit has no effect.
Writing a one to this bit enables the receiver if RXDIS is zero.
• RSTTX: Reset Transmitter
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the transmitter.
• RSTRX: Reset Receiver
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the receiver.
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25.7.2 Mode Register
Name: MR
Access Type: Read-write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
ONEBIT MODSYNC MAN FILTER – MAX_ITERATION
23 22 21 20 19 18 17 16
– VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF/CPOL
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR SYNC/CPHA
7 6 5 4 3 2 1 0
CHRL USCLKS MODE
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
• ONEBIT: Start Frame Delimiter Selector
0: The start frame delimiter is a command or data sync, as defined by MODSYNC.
1: The start frame delimiter is a normal start bit, as defined by MODSYNC.
• MODSYNC: Manchester Synchronization Mode
0: The manchester start bit is either a 0-to-1 transition, or a data sync.
1: The manchester start bit is either a 1-to-0 transition, or a command sync.
• MAN: Manchester Encoder/Decoder Enable
0: Manchester endec is disabled.
1: Manchester endec is enabled.
• FILTER: Infrared Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line by doing three consecutive samples and uses the majority value.
• MAX_ITERATION
This field determines the number of acceptable consecutive NACKs when in protocol T=0.
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
0: Sync pattern according to MODSYNC.
1: Sync pattern according to THR.TXSYNH.
• DSNACK: Disable Successive NACK
0: NACKs are handled as normal, unless disabled by INACK.
1: The receiver restricts the amount of consecutive NACKs by MAX_ITERATION value. If MAX_ITERATION=0 no NACK will be
issued and the first erroneous message is accepted as a valid character, setting CSR.ITER.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• OVER: Oversampling Mode
0: Oversampling at 16 times the baud rate.
1: Oversampling at 8 times the baud rate.
• CLKO: Clock Output Select
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin unless USCLKS selects the external clock.
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• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
• MSBF/CPOL: Bit Order or SPI Clock Polarity
If USART does not operate in SPI Mode:
MSBF=0: Least Significant Bit is sent/received first.
MSBF=1: Most Significant Bit is sent/received first.
If USART operates in SPI Mode, CPOL is used with CPHA to produce the required clock/data relationship between devices.
CPOL=0: The inactive state value of CLK is logic level zero.
CPOL=1: The inactive state value of CLK is logic level one.
• CHMODE: Channel Mode
Table 25-18.
CHMODE Mode Description
0 0 Normal Mode
0 1 Automatic Echo. Receiver input is connected to the TXD pin.
1 0 Local Loopback. Transmitter output is connected to the Receiver input.
1 1 Remote Loopback. RXD pin is internally connected to the TXD pin.
• NBSTOP: Number of Stop Bits
Table 25-19.
NBSTOP Asynchronous (SYNC=0) Synchronous (SYNC=1)
0 0 1 stop bit 1 stop bit
0 1 1.5 stop bits Reserved
1 0 2 stop bits 2 stop bits
1 1 Reserved Reserved
• PAR: Parity Type
Table 25-20.
PAR Parity Type
0 0 0 Even parity
0 0 1 Odd parity
0 1 0 Parity forced to 0 (Space)
0 1 1 Parity forced to 1 (Mark)
1 0 x No parity
1 1 x Multidrop mode
• SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase
If USART does not operate in SPI Mode (MR.MODE is not equal to 0xE or 0xF):
SYNC = 0: USART operates in Asynchronous mode.
SYNC = 1: USART operates in Synchronous mode.
If USART operates in SPI Mode, CPHA determines which edge of CLK causes data to change and which edge causes data to
be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.
CPHA = 0: Data is changed on the leading edge of CLK and captured on the following edge of CLK.
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CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK.
• CHRL: Character Length.
Table 25-21.
CHRL Character Length
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
• USCLKS: Clock Selection
Table 25-22.
USCLKS Selected Clock
0 0 CLK_USART
0 1 CLK_USART/DIV(1)
1 0 Reserved
1 1 CLK
Note: 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter.
• MODE
Table 25-23.
MODE Mode of the USART
0 0 0 0 Normal
0 0 0 1 RS485
0 0 1 0 Hardware Handshaking
0 0 1 1 Modem
0 1 0 0 IS07816 Protocol: T = 0
0 1 1 0 IS07816 Protocol: T = 1
1 0 0 0 IrDA
1 0 1 0 LIN Master
1 0 1 1 LIN Slave
1 1 1 0 SPI Master
1 1 1 1 SPI Slave
Others Reserved
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25.7.3 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x08
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – LINSNRE LINCE LINIPE LINISFE LINBE MANEA
23 22 21 20 19 18 17 16
– – – MANE CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
7 6 5 4 3 2 1 0
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
• LINSNRE: LIN Slave Not Responding Error
• LINCE: LIN Checksum Error
• LINIPE: LIN Identifier Parity Error
• LINISFE: LIN Inconsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Input Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has
the same effect. The corresponding bit in CSR and the corresponding interrupt request are named MANERR.
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25.7.4 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x0C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – LINSNRE LINCE LINIPE LINISFE LINBE MANEA
23 22 21 20 19 18 17 16
– – – MANE CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
7 6 5 4 3 2 1 0
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
• LINSNRE: LIN Slave Not Responding Error
• LINCE: LIN Checksum Error
• LINIPE: LIN Identifier Parity Error
• LINISFE: LIN Inconsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Input Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has
the same effect. The corresponding bit in CSR and the corresponding interrupt request are named MANERR.
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25.7.5 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – LINSNRE LINCE LINIPE LINISFE LINBE MANEA
23 22 21 20 19 18 17 16
– – – MANE CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
7 6 5 4 3 2 1 0
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
• LINSNRE: LIN Slave Not Responding Error
• LINCE: LIN Checksum Error
• LINIPE: LIN Identifier Parity Error
• LINISFE: LIN Inconsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Input Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Reading either one or the other
has the same effect. The corresponding bit in CSR and the corresponding interrupt request are named MANERR.
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25.7.6 Channel Status Register
Name: CSR
Access Type: Read-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – LINSNRE LINCE LINIPE LINISFE LINBE MANERR
23 22 21 20 19 18 17 16
CTS DCD DSR RI CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
7 6 5 4 3 2 1 0
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
• LINSNRE: LIN Slave Not Responding Error
0: No LIN Slave Not Responding Error has been detected since the last RSTSTA.
1: A LIN Slave Not Responding Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• LINCE: LIN Checksum Error
0: No LIN Checksum Error has been detected since the last RSTSTA.
1: A LIN Checksum Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• LINIPE: LIN Identifier Parity Error
0: No LIN Identifier Parity Error has been detected since the last RSTSTA.
1: A LIN Identifier Parity Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• LINISFE: LIN Inconsistent Sync Field Error
0: No LIN Inconsistent Sync Field Error has been detected since the last RSTSTA
1: The USART is configured as a Slave node and a LIN Inconsistent Sync Field Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• LINBE: LIN Bit Error
0: No Bit Error has been detected since the last RSTSTA.
1: A Bit Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• MANERR: Manchester Error
0: No Manchester error has been detected since the last RSTSTA.
1: At least one Manchester error has been detected since the last RSTSTA.
• CTS: Image of CTS Input
0: CTS is low.
1: CTS is high.
• DCD: Image of DCD Input
0: DCD is low.
1: DCD is high.
• DSR: Image of DSR Input
0: DSR is low.
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1: DSR is high.
• RI: Image of RI Input
0: RI is low.
1: RI is high.
• CTSIC: Clear to Send Input Change Flag
0: No change has been detected on the CTS pin since the last CSR read.
1: At least one change has been detected on the CTS pin since the last CSR read.
This bit is cleared when reading CSR.
• DCDIC: Data Carrier Detect Input Change Flag
0: No change has been detected on the DCD pin since the last CSR read.
1: At least one change has been detected on the DCD pin since the last CSR read.
This bit is cleared when reading CSR.
• DSRIC: Data Set Ready Input Change Flag
0: No change has been detected on the DSR pin since the last CSR read.
1: At least one change has been detected on the DSR pin since the last CSR read.
This bit is cleared when reading CSR.
• RIIC: Ring Indicator Input Change Flag
0: No change has been detected on the RI pin since the last CSR read.
1: At least one change has been detected on the RI pin since the last CSR read.
This bit is cleared when reading CSR.
• LINTC: LIN Transfer Completed
0: The USART is either idle or a LIN transfer is ongoing.
1: A LIN transfer has been completed since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA:
• LINIR: LIN Identifier
0: No LIN Identifier has been sent or received.
1: A LIN Identifier has been sent (master) or received (slave), since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA:
• NACK: Non Acknowledge
0: No Non Acknowledge has been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
This bit is cleared by writing a one to CR.RSTNACK.
• RXBUFF: Reception Buffer Full
0: The Buffer Full signal from the Peripheral DMA Controller channel is inactive.
1: The Buffer Full signal from the Peripheral DMA Controller channel is active.
• ITER/UNRE: Max Number of Repetitions Reached or SPI Underrun Error
If USART operates in SPI Slave Mode:
UNRE = 0: No SPI underrun error has occurred since the last RSTSTA.
UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA.
If USART does not operate in SPI Slave Mode, no functionality is associated to UNRE. The bit will behave as ITER if the USART
is in ISO7816 mode:
ITER = 0: Maximum number of repetitions has not been reached since the last RSTSTA.
ITER = 1: Maximum number of repetitions has been reached since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• TXEMPTY: Transmitter Empty
0: The transmitter is either disabled or there are characters in THR, or in the transmit shift register.
1: There are no characters in neither THR, nor in the transmit shift register.
This bit is cleared by writing a one to CR.STTBRK.
• TIMEOUT: Receiver Time-out
0: There has not been a time-out since the last Start Time-out command (CR.STTTO), or RTOR.TO is zero.
1: There has been a time-out since the last Start Time-out command.
This bit is cleared by writing a one to CR.STTTO or CR.RETTO.
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• PARE: Parity Error
0: Either no parity error has been detected, or the parity bit is a zero in multidrop mode, since the last RSTSTA.
1: Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• FRAME: Framing Error
0: No stop bit has been found as low since the last RSTSTA.
1: At least one stop bit has been found as low since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• RXBRK: Break Received/End of Break
0: No Break received or End of Break detected since the last RSTSTA.
1: Break received or End of Break detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• TXRDY: Transmitter Ready
0: The transmitter is either disabled, or a character in THR is waiting to be transferred to the transmit shift register, or an
STTBRK command has been requested. As soon as the transmitter is enabled, TXRDY is set.
1: There is no character in the THR.
This bit is cleared by writing a one to CR.STTBRK.
• RXRDY: Receiver Ready
0: The receiver is either disabled, or no complete character has been received since the last read of RHR. If characters were
being received when the receiver was disabled, RXRDY is set when the receiver is enabled.
1: At least one complete character has been received and RHR has not yet been read.
This bit is cleared when the Receive Holding Register (RHR) is read.
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25.7.7 Receiver Holding Register
Name: RHR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
RXSYNH – – – – – – RXCHR[8]
7 6 5 4 3 2 1 0
RXCHR[7:0]
Reading this register will clear the CSR.RXRDY bit.
• RXSYNH: Received Sync
0: Last character received is a data sync.
1: Last character received is a command sync.
• RXCHR: Received Character
Last received character.
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25.7.8 Transmitter Holding Register
Name: THR
Access Type: Write-only
Offset: 0x1C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
TXSYNH – – – – – – TXCHR[8]
7 6 5 4 3 2 1 0
TXCHR[7:0]
• TXSYNH: Sync Field to be transmitted
0: If MR.VARSYNC is one, the next character sent is encoded as data, and the start frame delimiter is a data sync.
1: If MR.VARSYNC is one, the next character sent is encoded as a command, and the start frame delimiter is a command sync.
• TXCHR: Character to be Transmitted
If TXRDY is zero this field contains the next character to be transmitted.
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25.7.9 Baud Rate Generator Register
Name: BRGR
Access Type: Read-write
Offset: 0x20
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – FP
15 14 13 12 11 10 9 8
CD[15:8]
7 6 5 4 3 2 1 0
CD[7:0]
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
• FP: Fractional Part
0: Fractional divider is disabled.
1 - 7: Baud rate resolution, defined by FP x 1/8.
• CD: Clock Divider
Table 25-24. Baud Rate in Asynchronous Mode (MR.SYNC is 0)
CD OVER = 0 OVER = 1
0 Baud Rate Clock Disabled
Baud Rate = Selected Clock- Baud Rate = Selected
1 to 65535 Clock-
--------------------------------------- ---------------------------------------
16 ⋅ CD 8 ⋅ CD
Table 25-25. Baud Rate in Synchronous Mode (MR.SYNC is 1) and SPI Mode(MR.MODE is 0xE or 0xF)
CD Baud Rate
0 Baud Rate Clock Disabled
Baud Rate = Selected
1 to 65535 Clock-
---------------------------------------
CD
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Table 25-26. Baud Rate in ISO7816 Mode
CD Baud Rate
0 Baud Rate Clock Disabled
1 to 65535 Selected Clock -
Baud Rate = ------------------------------------------------
FI_DI_RATIO ⋅ CD
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25.7.10 Receiver Time-out Register
Name: RTOR
Access Type: Read-write
Offset: 0x24
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – TO[16]
15 14 13 12 11 10 9 8
TO[15:8]
7 6 5 4 3 2 1 0
TO[7:0]
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
• TO: Time-out Value
0: The receiver Time-out is disabled.
1 - 131071: The receiver Time-out is enabled and the time-out delay is TO x bit period.
Note that the size of the TO counter is device dependent, please refer to the Module Configuration section.
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25.7.11 Transmitter Timeguard Register
Name: TTGR
Access Type: Read-write
Offset: 0x28
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
TG
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
• TG: Timeguard Value
0: The transmitter Timeguard is disabled.
1 - 255: The transmitter timeguard is enabled and the timeguard delay is TG bit periods.
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25.7.12 FI DI Ratio Register
Name: FIDI
Access Type: Read-write
Offset: 0x40
Reset Value: 0x00000174
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – FI_DI_RATIO[10:8]
7 6 5 4 3 2 1 0
FI_DI_RATIO[7:0]
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the baud rate generator does not generate a signal.
1 - 2047: If ISO7816 mode is selected, the baud rate is the clock provided on CLK divided by FI_DI_RATIO.
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25.7.13 Number of Errors Register
Name: NER
Access Type: Read-only
Offset: 0x44
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
NB_ERRORS
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. This register is automatically cleared when read.
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25.7.14 IrDA Filter Register
Name: IFR
Access Type: Read-write
Offset: 0x4C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
IRDA_FILTER
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
• IRDA_FILTER: IrDA Filter
Configures the IrDA demodulator filter.
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25.7.15 Manchester Configuration Register
Name: MAN
Access Type: Read-write
Offset: 0x50
Reset Value: 0x30011004
31 30 29 28 27 26 25 24
– DRIFT 1 RX_MPOL – – RX_PP
23 22 21 20 19 18 17 16
– – – – RX_PL
15 14 13 12 11 10 9 8
– – – TX_MPOL – – TX_PP
7 6 5 4 3 2 1 0
– – – – TX_PL
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
• DRIFT: Drift cCompensation
0: The USART can not recover from a clock drift.
1: The USART can recover from clock drift (only available in 16x oversampling mode).
• RX_MPOL: Receiver Manchester Polarity
0: Zeroes are encoded as zero-to-one transitions, and ones are encoded as a one-to-zero transitions.
1: Zeroes are encoded as one-to-zero transitions, and ones are encoded as a zero-to-one transitions.
• RX_PP: Receiver Preamble Pattern detected
Table 25-27.
RX_PP Preamble Pattern default polarity assumed (RX_MPOL field not set)
0 0 ALL_ONE
0 1 ALL_ZERO
1 0 ZERO_ONE
1 1 ONE_ZERO
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled.
1 - 15: The detected preamble length is RX_PL bit periods.
• TX_MPOL: Transmitter Manchester Polarity
0: Zeroes are encoded as zero-to-one transitions, and ones are encoded as a one-to-zero transitions.
1: Zeroes are encoded as one-to-zero transitions, and ones are encoded as a zero-to-one transitions.
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• TX_PP: Transmitter Preamble Pattern
Table 25-28.
TX_PP Preamble Pattern default polarity assumed (TX_MPOL field not set)
0 0 ALL_ONE
0 1 ALL_ZERO
1 0 ZERO_ONE
1 1 ONE_ZERO
• TX_PL: Transmitter Preamble Length
0: The transmitter preamble pattern generation is disabled.
1 - 15: The preamble length is TX_PL bit periods.
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25.7.16 LIN Mode Register
Name: LINMR
Access Type: Read-write
Offset: 0x54
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – PDCM
15 14 13 12 11 10 9 8
DLC
7 6 5 4 3 2 1 0
WKUPTYP FSDIS DLM CHKTYP CHKDIS PARDIS NACT
• PDCM: Peripheral DMA Controller Mode
0: The LIN mode register is not written by the Peripheral DMA Controller.
1: The LIN mode register, except for this bit, is written by the Peripheral DMA Controller.
• DLC: Data Length Control
0 - 255: If DLM=0 this field defines the response data length to DLC+1 bytes.
• WKUPTYP: Wakeup Signal Type
0: Writing a one to CR.LINWKUP will send a LIN 2.0 wakeup signal.
1: Writing a one to CR.LINWKUP will send a LIN 1.3 wakeup signal.
• FSDIS: Frame Slot Mode Disable
0: The Frame Slot mode is enabled.
1: The Frame Slot mode is disabled.
• DLM: Data Length Mode
0: The response data length is defined by DLC.
1: The response data length is defined by bits 4 and 5 of the Identifier (LINIR.IDCHR).
• CHKTYP: Checksum Type
0: LIN 2.0 “Enhanced” checksum
1: LIN 1.3 “Classic” checksum
• CHKDIS: Checksum Disable
0: Checksum is automatically computed and sent when master, and checked when slave.
1: Checksum is not computed and sent, nor checked.
• PARDIS: Parity Disable
0: Identifier parity is automatically computed and sent when master, and checked when slave.
1: Identifier parity is not computed and sent, nor checked.
• NACT: LIN Node Action
Table 25-29.
NACT Mode Description
0 0 PUBLISH: The USART transmits the response.
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Table 25-29.
0 1 SUBSCRIBE: The USART receives the response.
1 0 IGNORE: The USART does not transmit and does not receive the response.
1 1 Reserved
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25.7.17 LIN Identifier Register
Name: LINIR
Access Type: Read-write or Read-only
Offset: 0x58
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
IDCHR
• IDCHR: Identifier Character
If USART is in LIN master mode, the IDCHR field is read-write, and its value is the Identifier character to be transmitted.
If USART is in LIN slave mode, the IDCHR field is read-only, and its value is the last received Identifier character.
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25.7.18 Write Protect Mode Register
Register Name: WPMR
Access Type: Read-write
Offset: 0xE4
Reset Value: See Table 25-17
31 30 29 28 27 26 25 24
WPKEY[23:16]
23 22 21 20 19 18 17 16
WPKEY[15:8]
15 14 13 12 11 10 9 8
WPKEY[7:0]
7 6 5 4 3 2 1 0
- - - - - - - WPEN
• WPKEY: Write Protect KEY
Has to be written to 0x555341 (“USA” in ASCII) in order to successfully write WPEN. This bit always reads as zero. Writing the
correct key to this field clears WPSR.WPVSRC and WPSR.WPVS.
• WPEN: Write Protect Enable
0: Write protection disabled.
1: Write protection enabled.
Protects the registers:
• ”Mode Register” on page 596
• ”Baud Rate Generator Register” on page 607
• ”Receiver Time-out Register” on page 609
• ”Transmitter Timeguard Register” on page 610
• ”FI DI Ratio Register” on page 611
• ”IrDA Filter Register” on page 613
• ”Manchester Configuration Register” on page 614
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25.7.19 Write Protect Status Register
Register Name: WPSR
Access Type: Read-only
Offset: 0xE8
Reset Value: See Table 25-17
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
WPVSRC[15:8]
15 14 13 12 11 10 9 8
WPVSRC[7:0]
7 6 5 4 3 2 1 0
- - - - - - - WPVS
• WPVSRC: Write Protect Violation Source
If WPVS is one, this field indicates which write-protected register was unsuccessfully written to, either by address offset or code.
• WPVS: Write Protect Violation Status
0: No write protect violation has occurred since the last WPSR read.
1: A write protect violation has occurred since the last WPSR read.
Note: Reading WPSR automatically clears all fields. Writing the correct key to WPSR.WPKEY clears all fields.
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25.7.20 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - MFN
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• MFN
Reserved. No functionality associated.
• VERSION
Version of the module. No functionality associated.
26.
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26.1 Module Configuration
The specific configuration for each USART instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
Table 26-1. Module Configuration
USART0
USART2
Feature USART3 USART1
SPI Logic Implemented Implemented
LIN Logic Implemented Implemented
Manchester Logic Not Implemented Implemented
Modem Logic Not Implemented Implemented
IRDA Logic Not Implemented Implemented
RS485 Logic Not Implemented Implemented
Fractional Baudrate Implemented Implemented
ISO7816 Not Implemented Implemented
DIV value for divided CLK_USART 8 8
Receiver Time-out Counter Size
8-bits 17-bits
(Size of the RTOR.TO field)
Table 26-2. Module Clock Name
Module name Clock name Description
USART0 CLK_USART0 Peripheral Bus clock from the PBA clock domain
USART1 CLK_USART1 Peripheral Bus clock from the PBA clock domain
USART2 CLK_USART2 Peripheral Bus clock from the PBA clock domain
USART3 CLK_USART3 Peripheral Bus clock from the PBA clock domain
26.1.1 Clock Connections
Each USART can be connected to an internally divided clock:
Table 26-3. USART Clock Connections
USART Source Name Connection
0 PBA Clock / 8 (CLK_PBA_USART_DIV)
1 PBA Clock / 8 (CLK_PBA_USART_DIV)
Internal CLK_DIV
2 PBA Clock / 8 (CLK_PBA_USART_DIV)
3 PBA Clock / 8 (CLK_PBA_USART_DIV)
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26.1.2 Register Reset Values
Table 26-4. Register Reset Values
Register Reset Value
VERSION 0x00000420
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27. Hi-Speed USB Interface (USBB)
Rev: 3.2.0.18
27.1 Features
• Compatible with the USB 2.0 specification
• Supports High (480Mbit/s), Full (12Mbit/s) and Low (1.5Mbit/s) speed Device and Embedded Host
• eight pipes/endpoints
• 2368bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints
• Up to 2 memory banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)
• Flexible Pipe/Endpoint configuration and management with dedicated DMA channels
• On-Chip UTMI transceiver including Pull-Ups/Pull-downs
• On-Chip pad including VBUS analog comparator
27.2 Overview
The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0
specification, in all speeds.
Each pipe/endpoint can be configured in one of several transfer types. It can be associated with
one or more banks of a dual-port RAM (DPRAM) used to store the current data payload. If sev-
eral banks are used (“ping-pong” mode), then one DPRAM bank is read or written by the CPU or
the DMA while the other is read or written by the USBB core. This feature is mandatory for iso-
chronous pipes/endpoints.
Table 27-1 on page 624 describes the hardware configuration of the USB MCU device.
Table 27-1. Description of USB Pipes/Endpoints
Pipe/Endpoint Mnemonic Max. Size Max. Nb. Banks DMA Type
0 PEP0 64 bytes 1 N Control
1 PEP1 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
2 PEP2 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
3 PEP3 512 bytes 2 Y Isochronous/Bulk/Interrupt
4 PEP4 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
5 PEP5 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
6 PEP6 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
7 PEP7 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
The theoretical maximal pipe/endpoint configuration (3648bytes) exceeds the real DPRAM size
(2368bytes). The user needs to be aware of this when configuring pipes/endpoints. To fully use
the 2368bytes of DPRAM, the user could for example use the configuration described inTable
27-2 on page 624.
Table 27-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM
Pipe/Endpoint Mnemonic Size Nb. Banks
0 PEP0 64 bytes 1
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Table 27-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM
Pipe/Endpoint Mnemonic Size Nb. Banks
1 PEP1 512 bytes 2
2 PEP2 512 bytes 2
3 PEP3 256 bytes 1
27.3 Block Diagram
The USBB provides a hardware device to interface a USB link to a data flow stored in a dual-port
RAM (DPRAM).
The UTMI transceiver requires an external 12MHz clock as a reference to its internal 480MHz
PLL. The internal 480MHz PLL is used to clock an internal DLL module to recover the USB dif-
ferential data at 480Mbit/s.
Figure 27-1. USBB Block Diagram
HSB Local HSB DPRAM
Slave
Slave
Slave Interface
HSB Mux
Master HSB0
PEP
DMA
Master Allocation
HSB1
USB_VBUS
USB_ID
I/O
USB
User Controller
USB_VBOF
PB Interface
2.0 Core
DMFS
DPFS
UTMI
DMHS
DPHS
GCLK_USBB
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27.4 Application Block Diagram
Depending on the USB operating mode (device-only, reduced-host modes) and the power
source (bus-powered or self-powered), there are different typical hardware implementations.
27.4.1 Device Mode
27.4.1.1 Bus-Powered device
Figure 27-2. Bus-Powered Device Application Block Diagram
VDD
3.3 V
Regulator
USB
USB_VBUS Connector
I/O USB_ID VBus
USB Controller
USB_VBOF
ID
2.0 Core
DMFS 39 ohms
D-
DPFS 39 ohms
UTMI
D+
DMHS
DPHS GND
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27.4.1.2 Self-Powered device
Figure 27-3. Self-powered Device Application Block Diagram
USB
USB_VBUS Connector
I/O
USB_ID VBus
USB Controller
USB_VBOF
ID
2.0 Core
DMFS 39 ohms
D-
DPFS 39 ohms
UTMI
D+
DMHS
DPHS GND
27.4.2 Host Mode
Figure 27-4. Host Application Block Diagram
VDD
5V DC/DC
Generator
USB
USB_VBUS Connector
USB_ID VBus
I/O
USB Controller
USB_VBOF
ID
2.0 Core
DMFS 39 ohms
D-
DPFS 39 ohms
UTMI
D+
DMHS
DPHS GND
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27.5 I/O Lines Description
Table 27-3. I/O Lines Description
PIn Name Pin Description Type Active Level
USB_VBOF USB VBus On/Off: Bus Power Control Port Output VBUSPO
USB_VBUS VBus: Bus Power Measurement Port Input
DMFS FS Data -: Full-Speed Differential Data Line - Port Input/Output
DPFS FS Data +: Full-Speed Differential Data Line + Port Input/Output
DMHS HS Data -: Hi-Speed Differential Data Line - Port Input/Output
DPHS HS Data +: Hi-Speed Differential Data Line + Port Input/Output
Low: Mini-A plug
USB_ID USB Identification: Mini Connector Identification Port Input
High Z: Mini-B plug
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27.6 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
27.6.1 I/O Lines
The USB_VBOF and USB_ID pins are multiplexed with I/O Controller lines and may also be
multiplexed with lines of other peripherals. In order to use them with the USB, the user must first
configure the I/O Controller to assign them to their USB peripheral functions.
If USB_ID is used, the I/O Controller must be configured to enable the internal pull-up resistor of
its pin.
If USB_VBOF or USB_ID is not used by the application, the corresponding pin can be used for
other purposes by the I/O Controller or by other peripherals.
27.6.2 Clocks
The clock for the USBB bus interface (CLK_USBB) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the USBB before disabling the clock, to avoid freezing the USBB in an undefined state.
The UTMI transceiver needs a 12MHz clock as a clock reference for its internal 480MHz PLL.
Before using the USB, the user must ensure that this 12 MHz clock is available. The 12 MHz
input is connected to a Generic Clock (GCLK_USBB) provided by the Power Manager.
27.6.3 Interrupts
The USBB interrupt request line is connected to the interrupt controller. Using the USBB inter-
rupt requires the interrupt controller to be programmed first.
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27.7 Functional Description
27.7.1 USB General Operation
27.7.1.1 Introduction
After a hardware reset, the USBB is disabled. When enabled, the USBB runs either in device
mode or in host mode according to the ID detection.
If the USB_ID pin is not connected to ground, the USB_ID Pin State bit in the General Status
register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by
the I/O Controller) and device mode is engaged.
The USBSTA.ID bit is cleared when a low level has been detected on the USB_ID pin. Host
mode is then engaged.
27.7.1.2 Power-On and reset
Figure 27-5 on page 630 describes the USBB main states.
Figure 27-5. General States
Macro off: <any
USBE = 0 USBE = 0 other
Clock stopped: state>
FRZCLK = 1
Reset HW
RESET
USBE = 1
ID = 1
USBE = 0 USBE = 1
ID = 0
Device USBE = 0
Host
After a hardware reset, the USBB is in the Reset state. In this state:
• The macro is disabled. The USBB Enable bit in the General Control register
(USBCON.USBE) is zero.
• The macro clock is stopped in order to minimize power consumption. The Freeze USB Clock
bit in USBCON (USBON.FRZCLK) is set.
• The UTMI is in suspend mode.
• The internal states and registers of the device and host modes are reset.
• The DPRAM is not cleared and is accessible.
• The USBSTA.ID bit and the VBus Level bit in the UBSTA (UBSTA.VBUS) reflect the states of
the USB_ID and USB_VBUS input pins.
• The OTG Pad Enable (OTGPADE) bit, the VBus Polarity (VBUSPO) bit, the FRZCLK bit, the
USBE bit, the USB_ID Pin Enable (UIDE) bit, the USBB Mode (UIMOD) bit in USBCON, and
the Low-Speed Mode Force bit in the Device General Control (UDCON.LS) register can be
written by software, so that the user can program pads and speed before enabling the macro,
but their value is only taken into account once the macro is enabled and unfrozen.
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After writing a one to USBCON.USBE, the USBB enters the Device or the Host mode (according
to the ID detection) in idle state.
The USBB can be disabled at any time by writing a zero to USBCON.USBE. In fact, writing a
zero to USBCON.USBE acts as a hardware reset, except that the OTGPADE, VBUSPO,
FRZCLK, UIDE, UIMOD and, LS bits are not reset.
27.7.1.3 Interrupts
One interrupt vector is assigned to the USB interface. Figure 27-6 on page 632 shows the struc-
ture of the USB interrupt system.
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Figure 27-6. Interrupt System
USBSTA.IDTI
USBCON.IDTE
USBSTA.VBUSTI
USBCON.VBUSTE
USBSTA.SRPI
UESTAX.TXINI
USBCON.SRPE
UECONX.TXINE USBSTA.VBERRI
UESTAX.RXOUTI USB General
USBCON.VBERRE
UECONX.RXOUTE USBSTA.BCERRI Interrupt
UESTAX.RXSTPI
USBCON.BCERRE
UECONX.RXSTPE USBSTA.ROLEEXI
UESTAX.UNDERFI
USBCON.ROLEEXE
UECONX.UNDERFE USBSTA.HNPERRI
UESTAX.NAKOUTI
USBCON.HNPERRE
UECONX.NAKOUTE USBSTA.STOI
UESTAX.HBISOINERRI
USBCON.STOE
UECONX.HBISOINERRE
UESTAX.NAKINI
UECONX.NAKINE
UESTAX.HBISOFLUSHI
UECONX.HBISOFLUSHE
UESTAX.OVERFI USB Device
Endpoint X
UECONX.OVERFE
Interrupt
UESTAX.STALLEDI
UECONX.STALLEDE
UESTAX.CRCERRI
UECONX.CRCERRE
UESTAX.SHORTPACKET
UECONX.SHORTPACKETE UDINT.MSOF
UESTAX.DTSEQ=MDATA & UESTAX.RXOUTI UDINTE.MSOFE
UECONX.MDATAE UDINT.SUSP
UESTAX.DTSEQ=DATAX & UESTAX.RXOUTI UDINTE.SUSPE
UECONX.DATAXE UDINT.SOF
UESTAX.TRANSERR UDINTE.SOFE
UECONX.TRANSERRE UDINT.EORST USB
UESTAX.NBUSYBK UDINTE.EORSTE Interrupt
UECONX.NBUSYBKE UDINT.WAKEUP
UDINTE.WAKEUPE USB Device
UDINT.EORSM Interrupt
UDINTE.EORSME
UDINT.UPRSM
UDINTE.UPRSME
UDDMAX_STATUS.EOT_STA UDINT.EPXINT
UDDMAX_CONTROL.EOT_IRQ_EN UDINTE.EPXINTE
UDDMAX_STATUS.EOCH_BUFF_STA UDINT.DMAXINT
UDDMAX_CONTROL.EOBUFF_IRQ_EN USB Device UDINTE.DMAXINTE
UDDMAX_STATUS.DESC_LD_STA DMA Channel X
UDDMAX_CONTROL.DESC_LD_IRQ_EN Interrupt
UPSTAX.RXINI
UPCONX.RXINE
UPSTAX.TXOUTI
UPCONX.TXOUTE
UPSTAX.TXSTPI
UPCONX.TXSTPE
UPSTAX.UNDERFI
UPCONX.UNDERFIE
UPSTAX.PERRI
UPCONX.PERRE UHINT.DCONNI
UPSTAX.NAKEDI UHINTE.DCONNIE
UPCONX.NAKEDE UHINT.DDISCI
UPSTAX.OVERFI UHINTE.DDISCIE
UPCONX.OVERFIE UHINT.RSTI
UPSTAX.RXSTALLDI UHINTE.RSTIE
UPCONX.RXSTALLDE UHINT.RSMEDI
UPSTAX.CRCERRI USB Host
Pipe X UHINTE.RSMEDIE
UPCONX.CRCERRE UHINT.RXRSMI USB Host
Interrupt Interrupt
UPSTAX.SHORTPACKETI UHINTE.RXRSMIE
UPCONX.SHORTPACKETIE UHINT.HSOFI
UPSTAX.NBUSYBK UHINTE.HSOFIE
UPCONX.NBUSYBKE UHINT.HWUPI
UHINTE.HWUPIE
UHDMAX_STATUS.EOT_STA UHINT.PXINT
UHDMAX_CONTROL.EOT_IRQ_EN UHINTE.PXINTE
UHDMAX_STATUS.EOCH_BUFF_STA UHINT.DMAXINT
UHDMAX_CONTROL.EOBUFF_IRQ_EN USB Host
DMA Channel X UHINTE.DMAXINTE
UHDMAX_STATUS.DESC_LD_STA
Interrupt
UHDMAX_CONTROL.DESC_LD_IRQ_EN
Asynchronous interrupt source
See Section 27.7.2.19 and Section 27.7.3.13 for further details about device and host interrupts.
There are two kinds of general interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
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The processing general interrupts are:
• The ID Transition Interrupt (IDTI)
• The VBus Transition Interrupt (VBUSTI)
• The Role Exchange Interrupt (ROLEEXI)
The exception general interrupts are:
• The VBus Error Interrupt (VBERRI)
• The B-Connection Error Interrupt (BCERRI)
• The Suspend Time-Out Interrupt (STOI)
27.7.1.4 MCU Power modes
•Run mode
In this mode, all MCU clocks can run, including the USB clock.
•Idle mode
In this mode, the CPU is halted, i.e. the CPU clock is stopped. The Idle mode is entered what-
ever the state of the USBB. The MCU wakes up on any USB interrupt.
•Frozen mode
Same as the Idle mode, except that the HSB module is stopped, so the USB DMA, which is an
HSB master, can not be used. Moreover, the USB DMA must be stopped before entering this
sleep mode in order to avoid erratic behavior. The MCU wakes up on any USB interrupt.
•Standby, Stop, DeepStop and Static modes
Same as the Frozen mode, except that the USB generic clock and other clocks are stopped, so
the USB macro is frozen. Only the asynchronous USB interrupt sources can wake up the MCU
in these modes (1). The Power Manager (PM) may have to be configured to enable asynchro-
nous wake up from USB. The USB module must be frozen by writing a one to the FRZCLK bit.
Note: 1. When entering a sleep mode deeper or equal to DeepStop, the VBus asynchronous interrupt can not be triggered because
the bandgap voltage reference is off. Thus this interrupt should be disabled (USBCON.VBUSTE = 0).
•USB clock frozen
In the run, idle and frozen MCU modes, the USBB can be frozen when the USB line is in the sus-
pend mode, by writing a one to the FRZCLK bit, what reduces power consumption.
In deeper MCU power modes (from StandBy mode), the USBC must be frozen.
In this case, it is still possible to access the following elements, but only in Run mode:
• The OTGPADE, VBUSPO, FRZCLK, USBE, UIDE, UIMOD and LS bits in the USBCON
register
• The DPRAM (through the USB Pipe/Endpoint n FIFO Data (USBFIFOnDATA) registers, but
not through USB bus transfers which are frozen)
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Moreover, when FRZCLK is written to one, only the asynchronous interrupt sources may trigger
the USB interrupt:
• The ID Transition Interrupt (IDTI)
• The VBus Transition Interrupt (VBUSTI)
• The Wake-up Interrupt (WAKEUP)
• The Host Wake-up Interrupt (HWUPI)
•USB Suspend mode
In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register
(UDINT.SUSP)indicates that the USB line is in the suspend mode. In this case, the transceiver
is automatically set in suspend mode to reduce the consumption.The 480MHz internal PLL is
stopped. The USBSTA.CLKUSABLE bit is cleared.
27.7.1.5 Speed control
•Device mode
When the USB interface is in device mode, the speed selection (full-speed or high-speed) is per-
formed automatically by the USBB during the USB reset according to the host speed capability.
At the end of the USB reset, the USBB enables or disables high-speed terminations and pull-up.
It is possible to restraint the USBB to full-speed or low-speed mode by handling the LS and the
Speed Configuration (SPDCONF) bits in UDCON.
•Host mode
When the USB interface is in host mode, internal pull-down resistors are connected on both D+
and D- and the interface detects the speed of the connected device, which is reflected by the
Speed Status (SPEED) field in USBSTA.
27.7.1.6 DPRAM management
Pipes and endpoints can only be allocated in ascending order (from the pipe/endpoint 0 to the
last pipe/endpoint to be allocated). The user shall therefore configure them in the same order.
The allocation of a pipe/endpoint n starts when the Endpoint Memory Allocate bit in the Endpoint
n Configuration register (UECFGn.ALLOC) is written to one. Then, the hardware allocates a
memory area in the DPRAM and inserts it between the n-1 and n+1 pipes/endpoints. The n+1
pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/end-
point memory windows (from n+2) do not slide.
Disabling a pipe, by writing a zero to the Pipe n Enable bit in the Pipe Enable/Reset register
(UPRST.PENn), or disabling an endpoint, by writing a zero to the Endpoint n Enable bit in the
Endpoint Enable/Reset register (UERST.EPENn), resets neither the UECFGn.ALLOC bit nor its
configuration (the Pipe Banks (PBK) field, the Pipe Size (PSIZE) field, the Pipe Token (PTO-
KEN) field, the Pipe Type (PTYPE) field, the Pipe Endpoint Number (PEPNUM) field, and the
Pipe Interrupt Request Frequency (INTFRQ) field in the Pipe n Configuration (UPCFGn) regis-
ter/the Endpoint Banks (EPBK) field, the Endpoint Size (EPSIZE) field, the Endpoint Direction
(EPDIR) field, and the Endpoint Type (EPTYPE) field in UECFGn).
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To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+1 pipe/end-
point memory window then slides down and its data is lost. Note that the following pipe/endpoint
memory windows (from n+2) does not slide.
Figure 27-7 on page 635 illustrates the allocation and reorganization of the DPRAM in a typical
example.
Figure 27-7. Allocation and Reorganization of the DPRAM
Free Memory Free Memory Free Memory Free Memory
PEP5 PEP5 PEP5 PEP5
PEP4 Conflict
PEP4 PEP4 PEP4 Lost Memory
PEP3 PEP3 (larger size)
PEP3 (ALLOC stays at 1) PEP4
PEP2 PEP2 PEP2 PEP2
PEP1 PEP1 PEP1 PEP1
PEP0 PEP0 PEP0 PEP0
U(P/E)RST.(E)PENn = 1 U(P/E)RST.(E)PEN3 = 0 U(P/E)CFG3.ALLOC = 0 U(P/E)RST.(E)PEN3 = 1
U(P/E)CFGn.ALLOC = 1 U(P/E)CFG3.ALLOC = 1
Pipes/Endpoints 0..5 Pipe/Endpoint 3 Pipe/Endpoint 3 Pipe/Endpoint 3
Activated Disabled Memory Freed Activated
1. The pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order.
Each pipe/endpoint then owns a memory area in the DPRAM.
2. The pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller.
3. In order to free its memory, its ALLOC bit is written to zero. The pipe/endpoint 4 mem-
ory window slides down, but the pipe/endpoint 5 does not move.
4. If the user chooses to reconfigure the pipe/endpoint 3 with a larger size, the controller
allocates a memory area after the pipe/endpoint 2 memory area and automatically
slides up the pipe/endpoint 4 memory window. The pipe/endpoint 5 does not move and
a memory conflict appears as the memory windows of the pipes/endpoints 4 and 5
overlap. The data of these pipes/endpoints is potentially lost.
Note that:
• There is no way the data of the pipe/endpoint 0 can be lost (except if it is de-allocated) as
memory allocation and de-allocation may affect only higher pipes/endpoints.
• Deactivating then reactivating a same pipe/endpoint with the same configuration only
modifies temporarily the controller DPRAM pointer and size for this pipe/endpoint, but
nothing changes in the DPRAM, so higher endpoints seem to not have been moved and their
data is preserved as far as nothing has been written or received into them while changing the
allocation state of the first pipe/endpoint.
• When the user write a one to the ALLOC bit, the Configuration OK Status bit in the Endpoint
n Status register (UESTAn.CFGOK) is set only if the configured size and number of banks
are correct compared to their maximal allowed values for the endpoint and to the maximal
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FIFO size (i.e. the DPRAM size), so the value of CFGOK does not consider memory
allocation conflicts.
27.7.1.7 Pad Suspend
Figure 27-8 on page 636 shows the pad behavior.
Figure 27-8. Pad Behavior
USBE = 1
& DETACH = 0
Idle & Suspend
USBE = 0 Active
| DETACH = 1
| Suspend
• In the Idle state, the pad is put in low power consumption mode, i.e., the differential receiver
of the USB pad is off, and internal pull-down with strong value(15K) are set in both DP/DM to
avoid floating lines.
• In the Active state, the pad is working.
Figure 27-9 on page 636 illustrates the pad events leading to a PAD state change.
Figure 27-9. Pad Events
SUSP Suspend detected Cleared on wake-up
WAKEUP Wake-up detected Cleared by software to acknowledge the interrupt
PAD State
Active Idle Active
The SUSP bit is set and the Wake-Up Interrupt (WAKEUP) bit in UDINT is cleared when a USB
“Suspend” state has been detected on the USB bus. This event automatically puts the USB pad
in the Idle state. The detection of a non-idle event sets WAKEUP, clears SUSP and wakes up
the USB pad.
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Moreover, the pad goes to the Idle state if the macro is disabled or if the DETACH bit is written to
one. It returns to the Active state when USBE is written to one and DETACH is written to zero.
27.7.1.8 Plug-In detection
The USB connection is detected from the USB_VBUS pad. Figure 27-10 on page 637 shows the
architecture of the plug-in detector.
Figure 27-10. Plug-In Detection Input Block Diagram
VDD
VBus_pulsing
RPU
Session_valid
USB_VBUS Logic VBUS VBUSTI
Va_Vbus_valid
USBSTA USBSTA
RPD
VBus_discharge
GND
Pad Logic
The control logic of the USB_VBUS pad outputs two signals:
• The Session_valid signal is high when the voltage on the USB_VBUS pad is higher than or
equal to 1.4V.
• The Va_Vbus_valid signal is high when the voltage on the USB_VBUS pad is higher than or
equal to 4.4V.
In device mode, the USBSTA.VBUS bit follows the Session_valid comparator output:
• It is set when the voltage on the USB_VBUS pad is higher than or equal to 1.4V.
• It is cleared when the voltage on the VBUS pad is lower than 1.4V.
In host mode, the USBSTA.VBUS bit follows an hysteresis based on Session_valid and
Va_Vbus_valid:
• It is set when the voltage on the USB_VBUS pad is higher than or equal to 4.4V.
• It is cleared when the voltage on the USB_VBUS pad is lower than 1.4V.
The VBus Transition interrupt (VBUSTI) bit in USBSTA is set on each transition of the USB-
STA.VBUS bit.
The USBSTA.VBUS bit is effective whether the USBB is enabled or not.
27.7.1.9 ID detection
Figure 27-11 on page 638 shows how the ID transitions are detected.
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Figure 27-11. ID Detection Input Block Diagram
VDD
RPU
1
USB_ID
0 ID IDTI
UIMOD USBSTA USBSTA
USBCON
UIDE
USBCON
I/O Controller
The USB mode (device or host) can be either detected from the USB_ID pin or software
selected by writing to the UIMOD bit, according to the UIDE bit. This allows the USB_ID pin to be
used as a general purpose I/O pin even when the USB interface is enabled.
By default, the USB_ID pin is selected (UIDE is written to one) and the USBB is in device mode
(UBSTA.ID is one), what corresponds to the case where no Mini-A plug is connected, i.e. no
plug or a Mini-B plug is connected and the USB_ID pin is kept high by the internal pull-up resis-
tor from the I/O Controller (which must be enabled if USB_ID is used).
The ID Transition Interrupt (IDTI) bit in USBSTA is set on each transition of the ID bit, i.e. when a
Mini-A plug (host mode) is connected or disconnected. This does not occur when a Mini-B plug
(device mode) is connected or disconnected.
The USBSTA.ID bit is effective whether the USBB is enabled or not.
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27.7.2 USB Device Operation
27.7.2.1 Introduction
In device mode, the USBB supports hi- full- and low-speed data transfers.
In addition to the default control endpoint, seven endpoints are provided, which can be config-
ured with the types isochronous, bulk or interrupt, as described in .Table 27-1 on page 624.
The device mode starts in the Idle state, so the pad consumption is reduced to the minimum.
27.7.2.2 Power-On and reset
Figure 27-12 on page 639 describes the USBB device mode main states.
Figure 27-12. Device Mode States
<any
other
USBE = 0 state>
| ID = 0
USBE = 0
| ID = 0 Idle
Reset USBE = 1
& ID = 1
HW
RESET
After a hardware reset, the USBB device mode is in the Reset state. In this state:
• The macro clock is stopped in order to minimize power consumption (FRZCLK is written to
one).
• The internal registers of the device mode are reset.
• The endpoint banks are de-allocated.
• Neither D+ nor D- is pulled up (DETACH is written to one).
D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written
to zero and VBus is present. See “Device mode” for further details.
When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode
state goes to the Idle state with minimal power consumption. This does not require the USB
clock to be activated.
The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing
a zero to USBE) or when host mode is engaged (ID is zero).
27.7.2.3 USB reset
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the
controller:
• All the endpoints are disabled, except the default control endpoint.
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• The default control endpoint is reset (see Section 27.7.2.4 for more details).
• The data toggle sequence of the default control endpoint is cleared.
• At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set.
• During a reset, the USBB automatically switches to the Hi-Speed mode if the host is Hi-
Speed capable (the reset is called a Hi-Speed reset). The user should observe the
USBSTA.SPEED field to know the speed running at the end of the reset (EORST is one).
27.7.2.4 Endpoint reset
An endpoint can be reset at any time by writing a one to the Endpoint n Reset (EPRSTn) bit in
the UERST register. This is recommended before using an endpoint upon hardware reset or
when a USB bus reset has been received. This resets:
• The internal state machine of this endpoint.
• The receive and transmit bank FIFO counters.
• All the registers of this endpoint (UECFGn, UESTAn, the Endpoint n Control (UECONn)
register), except its configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and the Data
Toggle Sequence (DTSEQ) field of the UESTAn register.
Note that the interrupt sources located in the UESTAn register are not cleared when a USB bus
reset has been received.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle sequence as an answer to
the CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data
Toggle Set bit in the Endpoint n Control Set register (UECONnSET.RSTDTS).(This will set the
Reset Data Toggle (RSTD) bit in UECONn).
In the end, the user has to write a zero to the EPRSTn bit to complete the reset operation and to
start using the FIFO.
27.7.2.5 Endpoint activation
The endpoint is maintained inactive and reset (see Section 27.7.2.4 for more details) as long as
it is disabled (EPENn is written to zero). DTSEQ is also reset.
The algorithm represented on Figure 27-13 on page 641 must be followed in order to activate an
endpoint.
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Figure 27-13. Endpoint Activation Algorithm
Endpoint
Activation
EPENn = 1 Enable the endpoint.
Configure the endpoint:
UECFGn - type
EPTYPE
EPDIR - direction
EPSIZE - size
EPBK - number of banks
ALLOC
Allocate the configured DPRAM banks.
CFGOK == Test if the endpoint configuration is correct.
1? No
Yes
Endpoint
ERROR
Activated
As long as the endpoint is not correctly configured (CFGOK is zero), the controller does not
acknowledge the packets sent by the host to this endpoint.
The CFGOK bit is set only if the configured size and number of banks are correct compared to
their maximal allowed values for the endpoint (see Table 27-1 on page 624) and to the maximal
FIFO size (i.e. the DPRAM size).
See Section 27.7.1.6 for more details about DPRAM management.
27.7.2.6 Address setup
The USB device address is set up according to the USB protocol.
• After all kinds of resets, the USB device address is 0.
• The host starts a SETUP transaction with a SET_ADDRESS(addr) request.
• The user write this address to the USB Address (UADD) field in UDCON, and write a zero to
the Address Enable (ADDEN) bit in UDCON, so the actual address is still 0.
• The user sends a zero-length IN packet from the control endpoint.
• The user enables the recorded USB device address by writing a one to ADDEN.
Once the USB device address is configured, the controller filters the packets to only accept
those targeting the address stored in UADD.
UADD and ADDEN shall not be written all at once.
UADD and ADDEN are cleared:
• On a hardware reset.
• When the USBB is disabled (USBE written to zero).
• When a USB reset is detected.
When UADD or ADDEN is cleared, the default device address 0 is used.
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27.7.2.7 Suspend and wake-up
When an idle USB bus state has been detected for 3 ms, the controller set the Suspend (SUSP)
interrupt bit in UDINT. The user may then write a one to the FRZCLK bit to reduce power con-
sumption. The MCU can also enter the Idle or Frozen sleep mode to lower again power
consumption.
To recover from the Suspend mode, the user shall wait for the Wake-Up (WAKEUP) interrupt bit,
which is set when a non-idle event is detected, then write a zero to FRZCLK.
As the WAKEUP interrupt bit in UDINT is set when a non-idle event is detected, it can occur
whether the controller is in the Suspend mode or not. The SUSP and WAKEUP interrupts are
thus independent of each other except that one bit is cleared when the other is set.
27.7.2.8 Detach
The reset value of the DETACH bit is one.
It is possible to initiate a device re-enumeration simply by writing a one then a zero to DETACH.
DETACH acts on the pull-up connections of the D+ and D- pads. See “Device mode” for further
details.
27.7.2.9 Remote wake-up
The Remote Wake-Up request (also known as Upstream Resume) is the only one the device
may send on its own initiative, but the device should have beforehand been allowed to by a
DEVICE_REMOTE_WAKEUP request from the host.
• First, the USBB must have detected a “Suspend” state on the bus, i.e. the Remote Wake-Up
request can only be sent after a SUSP interrupt has been set.
• The user may then write a one to the Remote Wake-Up (RMWKUP) bit in UDCON to send an
upstream resume to the host for a remote wake-up. This will automatically be done by the
controller after 5ms of inactivity on the USB bus.
• When the controller sends the upstream resume, the Upstream Resume (UPRSM) interrupt
is set and SUSP is cleared.
• RMWKUP is cleared at the end of the upstream resume.
• If the controller detects a valid “End of Resume” signal from the host, the End of Resume
(EORSM) interrupt is set.
27.7.2.10 STALL request
For each endpoint, the STALL management is performed using:
• The STALL Request (STALLRQ) bit in UECONn to initiate a STALL request.
• The STALLed Interrupt (STALLEDI) bit in UESTAn is set when a STALL handshake has been
sent.
To answer the next request with a STALL handshake, STALLRQ has to be set by writing a one
to the STALL Request Set (STALLRQS) bit. All following requests will be discarded (RXOUTI,
etc. will not be set) and handshaked with a STALL until the STALLRQ bit is cleared, what is
done when a new SETUP packet is received (for control endpoints) or when the STALL Request
Clear (STALLRQC) bit is written to one.
Each time a STALL handshake is sent, the STALLEDI bit is set by the USBB and the EPnINT
interrupt is set.
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•Special considerations for control endpoints
If a SETUP packet is received into a control endpoint for which a STALL is requested, the
Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are
cleared. The SETUP has to be ACKed.
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the user requests a STALL and can return to the main task, waiting
for the next SETUP request.
•STALL handshake and retry mechanism
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ bit is set and if there is no retry required.
27.7.2.11 Management of control endpoints
•Overview
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in
UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these
endpoints. When read, their value are always zero.
Control endpoints are managed using:
• The RXSTPI bit which is set when a new SETUP packet is received and which shall be
cleared by firmware to acknowledge the packet and to free the bank.
• The RXOUTI bit which is set when a new OUT packet is received and which shall be cleared
by firmware to acknowledge the packet and to free the bank.
• The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to
accept a new IN packet and which shall be cleared by firmware to send the packet.
•Control write
Figure 27-14 on page 644 shows a control write transaction. During the status stage, the control-
ler will not necessarily send a NAK on the first IN token:
• If the user knows the exact number of descriptor bytes that must be read, it can then
anticipate the status stage and send a zero-length packet after the next IN token.
• Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the
bytes have been sent by the host and that the transaction is now in the status stage.
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Figure 27-14. Control Write
SETUP DATA STATUS
USB Bus SETUP OUT OUT IN IN
NAK
RXSTPI HW SW
RXOUTI HW SW HW SW
TXINI SW
•Control read
Figure 27-15 on page 644 shows a control read transaction. The USBB has to manage the
simultaneous write requests from the CPU and the USB host.
Figure 27-15. Control Read
SETUP DATA STATUS
USB Bus SETUP IN IN OUT OUT
NAK
RXSTPI HW SW
RXOUTI HW SW
TXINI SW HW SW
Wr Enable
HOST
Wr Enable
CPU
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all the data written by the CPU are lost and clear-
ing TXINI has no effect.
The user checks if the transmission or the reception is complete.
The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the
following software algorithm:
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
Once the OUT status stage has been received, the USBB waits for a SETUP request. The
SETUP request has priority over any other request and has to be ACKed. This means that any
other bit should be cleared and the FIFO reset when a SETUP is received.
The user has to take care of the fact that the byte counter is reset when a zero-length OUT
packet is received.
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27.7.2.12 Management of IN endpoints
•Overview
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be written which acknowledges or not the bank when it is full.
The endpoint must be configured first.
The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers
an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable
Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the
interrupt, what has no effect on the endpoint FIFO.
The user then writes into the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
DATA)” on page 747) and write a one to the FIFO Control Clear (FIFOCONC) bit in
UECONnCLR to clear the FIFOCON bit. This allows the USBB to send the data. If the IN end-
point is composed of multiple banks, this also switches to the next bank. The TXINI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWALL bit is set when the current bank is not full, i.e. the software can write further data
into the FIFO.
Figure 27-16. Example of an IN Endpoint with 1 Data Bank
NAK DATA
IN ACK IN
(bank 0)
HW
TXINI SW SW
FIFOCON write data to CPU SW write data to CPU SW
BANK 0 BANK 0
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Figure 27-17. Example of an IN Endpoint with 2 Data Banks
DATA DATA
IN ACK IN ACK
(bank 0) (bank 1)
HW
TXINI SW SW SW
FIFOCON write data to CPU SW write data to CPU SW write data to CPU
BANK 0 BANK 1 BANK0
•Detailed description
The data is written, following the next flow:
• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if
TXINE is one.
• The user acknowledges the interrupt by clearing TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
virtual segment (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page
747), until all the data frame is written or the bank is full (in which case RWALL is cleared and
the Byte Count (BYCT) field in UESTAn reaches the endpoint size).
• The user allows the controller to send the bank and switches to the next bank (if any) by
clearing FIFOCON.
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears FIFOCON, the following bank may already
be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on Figure 27-18 on page 647. See ”Endpoint n Control Register” on page 706 to have
more details about the KILLBK bit.
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Figure 27-18. Abort Algorithm
Endpoint
Abort
Disable the TXINI interrupt.
TXINEC = 1
NBUSYBK Abort is based on the fact
No
== 0? that no bank is busy, i.e.,
Yes that nothing has to be sent
EPRSTn = 1 KILLBKS = 1 Kill the last written bank.
KILLBK Wait for the end of the
Yes == 1? procedure
No
Abort Done
27.7.2.13 Management of OUT endpoints
•Overview
OUT packets are sent by the host. All the data can be read which acknowledges or not the bank
when it is empty.
The endpoint must be configured first.
The RXOUTI bit is set at the same time as FIFOCON when the current bank is full. This triggers
an EPnINT interrupt if the Received OUT Data Interrupt Enable (RXOUTE) bit in UECONn is
one.
RXOUTI shall be cleared by software (by writing a one to the Received OUT Data Interrupt Clear
(RXOUTIC) bit) to acknowledge the interrupt, what has no effect on the endpoint FIFO.
The user then reads from the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
DATA)” on page 747) and clears the FIFOCON bit to free the bank. If the OUT endpoint is
composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON
bits are updated in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWALL bit is set when the current bank is not empty, i.e. the software can read further data
from the FIFO.
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Figure 27-19. Example of an OUT Endpoint with one Data Bank
DATA NAK DATA
OUT ACK OUT ACK
(bank 0) (bank 0)
HW HW
RXOUTI SW SW
FIFOCON read data from CPU SW read data from CPU
BANK 0 BANK 0
Figure 27-20. Example of an OUT Endpoint with two Data Banks
DATA ACK OUT DATA
OUT ACK
(bank 0) (bank 1)
HW
HW
RXOUTI SW SW
FIFOCON read data from CPU SW read data from CPU
BANK 0 BANK 1
•Detailed description
The data is read, following the next flow:
• When the bank is full, RXOUTI and FIFOCON are set, what triggers an EPnINT interrupt if
RXOUTE is one.
• The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI.
• The user can read the byte count of the current bank from BYCT to know how many bytes to
read, rather than polling RWALL.
• The user reads the data from the current bank by using the USBFIFOnDATA register (see
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page 747), until all the
expected data frame is read or the bank is empty (in which case RWALL is cleared and BYCT
reaches zero).
• The user frees the bank and switches to the next bank (if any) by clearing FIFOCON.
If the endpoint uses several banks, the current one can be read while the following one is being
written by the host. Then, when the user clears FIFOCON, the following bank may already be
ready and RXOUTI is set immediately.
In Hi-Speed mode, the PING and NYET protocol is handled by the USBB. For single bank, a
NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the current
packet is acknowledged but there is no room for the next one. For double bank, the USBB
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responds to the OUT/DATA transaction with an ACK handshake when the endpoint accepted
the data successfully and has room for another data payload (the second bank is free).
27.7.2.14 Underflow
This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt
(UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable
(UNDERFE) bit is one.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-
length packet is then automatically sent by the USBB.
An underflow can not occur during OUT stage on a CPU action, since the user may read only if
the bank is not empty (RXOUTI is one or RWALL is one).
An underflow can also occur during OUT stage if the host sends a packet while the bank is
already full. Typically, the CPU is not fast enough. The packet is lost.
An underflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).
27.7.2.15 Overflow
This error exists for all endpoint types. It set the Overflow interrupt (OVERFI) bit in UESTAn,
what triggers an EPnINT interrupt if the Overflow Interrupt Enable (OVERFE) bit is one.
An overflow can occur during OUT stage if the host attempts to write into a bank that is too small
for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
An overflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).
27.7.2.16 HB IsoIn error
This error exists only for high-bandwidth isochronous IN endpoints if the high-bandwidth isochro-
nous feature is supported by the device (see the UFEATURES register for this).
At the end of the micro-frame, if at least one packet has been sent to the host, if less banks than
expected has been validated (by clearing the FIFOCON) for this micro-frame, it set the
HBISOINERRORI bit in UESTAn, what triggers an EPnINT interrupt if the High Bandwidth Iso-
chronous IN Error Interrupt Enable (HBISOINERRORE) bit is one.
For instance, if the Number of Transaction per MicroFrame for Isochronous Endpoint
(NBTRANS field in UECFGn is three (three transactions per micro-frame), only two banks are
filled by the CPU (three expected) for the current micro-frame. Then, the HBISOINERRI interrupt
is generated at the end of the micro-frame. Note that an UNDERFI interrupt is also generated
(with an automatic zero-length-packet), except in the case of a missing IN token.
27.7.2.17 HB IsoFlush
This error exists only for high-bandwidth isochronous IN endpoints if the high-bandwidth isochro-
nous feature is supported by the device (see the UFEATURES register for this).
At the end of the micro-frame, if at least one packet has been sent to the host, if there is missing
IN token during this micro-frame, the bank(s) destined to this micro-frame is/are flushed out to
ensure a good data synchronization between the host and the device.
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For instance, if NBTRANS is three (three transactions per micro-frame), if only the first IN token
(among 3) is well received by the USBB, then the two last banks will be discarded.
27.7.2.18 CRC error
This error exists only for isochronous OUT endpoints. It set the CRC Error Interrupt (CRCERRI)
bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE)
bit is one.
A CRC error can occur during OUT stage if the USBB detects a corrupted received packet. The
OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is set).
27.7.2.19 Interrupts
See the structure of the USB device interrupt system on Figure 27-6 on page 632.
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
•Global interrupts
The processing device global interrupts are:
• The Suspend (SUSP) interrupt
• The Start of Frame (SOF) interrupt with no frame number CRC error (the Frame Number
CRC Error (FNCERR) bit in the Device Frame Number (UDFNUM) register is zero)
• The Micro Start of Frame (MSOF) interrupt with no CRC error.
• The End of Reset (EORST) interrupt
• The Wake-Up (WAKEUP) interrupt
• The End of Resume (EORSM) interrupt
• The Upstream Resume (UPRSM) interrupt
• The Endpoint n (EPnINT) interrupt
• The DMA Channel n (DMAnINT) interrupt
The exception device global interrupts are:
• The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one)
• The Micro Start of Frame (MSOF) interrupt with a CRC error
•Endpoint interrupts
The processing device endpoint interrupts are:
• The Transmitted IN Data Interrupt (TXINI)
• The Received OUT Data Interrupt (RXOUTI)
• The Received SETUP Interrupt (RXSTPI)
• The Short Packet (SHORTPACKET) interrupt
• The Number of Busy Banks (NBUSYBK) interrupt
• The Received OUT isochronous Multiple Data Interrupt (MDATAI)
• The Received OUT isochronous DataX Interrupt (DATAXI)
The exception device endpoint interrupts are:
• The Underflow Interrupt (UNDERFI)
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• The NAKed OUT Interrupt (NAKOUTI)
• The High-bandwidth isochronous IN error Interrupt (HBISOINERRI) if the high-bandwidth
isochronous feature is supported by the device (see the UFEATURES register for this)
• The NAKed IN Interrupt (NAKINI)
• The High-bandwidth isochronous IN Flush error Interrupt (HBISOFLUSHI) if the high-
bandwidth isochronous feature is supported by the device (see the UFEATURES register for
this)
• The Overflow Interrupt (OVERFI)
• The STALLed Interrupt (STALLEDI)
• The CRC Error Interrupt (CRCERRI)
• The Transaction error (ERRORTRANS) interrupt if the high-bandwidth isochronous feature is
supported by the device (see the UFEATURES register for this)
•DMA interrupts
The processing device DMA interrupts are:
• The End of USB Transfer Status (EOTSTA) interrupt
• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt
• The Descriptor Loaded Status (DESCLDSTA) interrupt
There is no exception device DMA interrupt.
27.7.2.20 Test Modes
When written to one, the UDCON.TSTPCKT bit switches the USB device controller in a “test
packet”mode:
The transceiver repeatedly transmit the packet stored in the current bank. TSTPCKT must be
written to zero to exit the “test-packet” mode. The endpoint shall be reset by software after a
“test-packet” mode.
This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic
waveform specifications.
The flow control used to send the packets is as follows:
• TSTPCKT=1;
• Store data in an endpoint bank
• Write a zero to FifoCON bit
To stop the test-packet mode, just write a zero to the TSTPCKT bit.
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27.7.3 USB Host Operation
27.7.3.1 Description of pipes
For the USBB in host mode, the term “pipe” is used instead of “endpoint” (used in device mode).
A host pipe corresponds to a device endpoint, as described by the Figure 27-21 on page 652
from the USB specification.
Figure 27-21. USB Communication Flow
In host mode, the USBB associates a pipe to a device endpoint, considering the device configu-
ration descriptors.
27.7.3.2 Power-On and reset
Figure 27-22 on page 652 describes the USBB host mode main states.
Figure 27-22. Host Mode States
Device <any
Macro off other
Clock stopped Disconnection
state>
Idle
Device
Connection
Device
Disconnection
Ready
SOFE = 0
SOFE = 1 Suspend
After a hardware reset, the USBB host mode is in the Reset state.
When the USBB is enabled (USBE is one) in host mode (ID is zero), its host mode state goes to
the Idle state. In this state, the controller waits for device connection with minimal power con-
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sumption. The USB pad should be in the Idle state. Once a device is connected, the macro
enters the Ready state, what does not require the USB clock to be activated.
The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when
the host mode does not generate the “Start of Frame (SOF)”. In this state, the USB consumption
is minimal. The host mode exits the Suspend state when starting to generate the SOF over the
USB line.
27.7.3.3 Device detection
A device is detected by the USBB host mode when D+ or D- is no longer tied low, i.e., when the
device D+ or D- pull-up resistor is connected. To enable this detection, the host controller has to
provide the VBus power supply to the device by setting the VBUSRQ bit (by writing a one to the
VBUSRQS bit).
The device disconnection is detected by the host controller when both D+ and D- are pulled
down.
27.7.3.4 USB reset
The USBB sends a USB bus reset when the user write a one to the Send USB Reset bit in the
Host General Control register (UHCON.RESET). The USB Reset Sent Interrupt bit in the Host
Global Interrupt register (UHINT.RSTI) is set when the USB reset has been sent. In this case, all
the pipes are disabled and de-allocated.
If the bus was previously in a “Suspend” state (the Start of Frame Generation Enable (SOFE) bit
in UHCON is zero), the USBB automatically switches it to the “Resume” state, the Host Wake-
Up Interrupt (HWUPI) bit in UHINT is set and the SOFE bit is set in order to generate SOFs or
micro SOFs immediately after the USB reset.
At the end of the reset, the user should check the USBSTA.SPEED field to know the speed run-
ning according to the peripheral capability (LS.FS/HS)
27.7.3.5 Pipe reset
A pipe can be reset at any time by writing a one to the Pipe n Reset (PRSTn) bit in the UPRST
register. This is recommended before using a pipe upon hardware reset or when a USB bus
reset has been sent. This resets:
• The internal state machine of this pipe
• The receive and transmit bank FIFO counters
• All the registers of this pipe (UPCFGn, UPSTAn, UPCONn), except its configuration (ALLOC,
PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ in UPCFGn) and its Data Toggle
Sequence field in the Pipe n Status register (UPSTAn.DTSEQ).
The pipe configuration remains active and the pipe is still enabled.
The pipe reset may be associated with a clear of the data toggle sequence. This can be
achieved by setting the Reset Data Toggle bit in the Pipe n Control register (UPCONn.RSTDT)
(by writing a one to the Reset Data Toggle Set bit in the Pipe n Control Set register
(UPCONnSET.RSTDTS)).
In the end, the user has to write a zero to the PRSTn bit to complete the reset operation and to
start using the FIFO.
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27.7.3.6 Pipe activation
The pipe is maintained inactive and reset (see Section 27.7.3.5 for more details) as long as it is
disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset.
The algorithm represented on Figure 27-23 on page 654 must be followed in order to activate a
pipe.
Figure 27-23. Pipe Activation Algorithm
Pipe
Activation
PENn = 1 Enable the pipe.
Configure the pipe:
UPCFGn - interrupt request frequency
INTFRQ
PEPNUM - endpoint number
PTYPE - type
PTOKEN
PSIZE
- size
PBK - number of banks
ALLOC Allocate the configured DPRAM banks.
CFGOK == Test if the pipe configuration is
1? No correct.
Yes
Pipe Activated ERROR
As long as the pipe is not correctly configured (UPSTAn.CFGOK is zero), the controller can not
send packets to the device through this pipe.
The UPSTAn.CFGOK bit is set only if the configured size and number of banks are correct com-
pared to their maximal allowed values for the pipe (see Table 27-1 on page 624) and to the
maximal FIFO size (i.e. the DPRAM size).
See Section 27.7.1.6 for more details about DPRAM management.
Once the pipe is correctly configured (UPSTAn.CFGOK is zero), only the PTOKEN and INTFRQ
fields can be written by software. INTFRQ is meaningless for non-interrupt pipes.
When starting an enumeration, the user gets the device descriptor by sending a
GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the
device default control endpoint (bMaxPacketSize0) and the user re-configures the size of the
default control pipe with this size parameter.
27.7.3.7 Address setup
Once the device has answered the first host requests with the default device address 0, the host
assigns a new address to the device. The host controller has to send an USB reset to the device
and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the
device. Once this SETUP transaction is over, the user writes the new address into the USB Host
Address for Pipe n field in the USB Host Device Address register (UHADDR.UHADDRPn). All
following requests, on all pipes, will be performed using this new address.
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When the host controller sends an USB reset, the UHADDRPn field is reset by hardware and the
following host requests will be performed using the default device address 0.
27.7.3.8 Remote wake-up
The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to
zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend
state 3ms later.
The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).
When the host controller detects a non-idle state on the USB bus, it set the Host Wake-Up inter-
rupt (HWUPI) bit in UHINT. If the non-idle bus state corresponds to an Upstream Resume (K
state), the Upstream Resume Received Interrupt (RXRSMI) bit in UHINT is set. The user has to
generate a Downstream Resume within 1ms and for at least 20ms by writing a one to the Send
USB Resume (RESUME) bit in UHCON. It is mandatory to write a one to UHCON.SOFE before
writing a one to UHCON.RESUME to enter the Ready state, else UHCON.RESUME will have no
effect.
27.7.3.9 Management of control pipes
A control transaction is composed of three stages:
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
The user has to change the pipe token according to each stage.
For the control pipe, and only for it, each token is assigned a specific initial data toggle
sequence:
• SETUP: Data0
• IN: Data1
• OUT: Data1
27.7.3.10 Management of IN pipes
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be read which acknowledges or not the bank when it is empty.
The pipe must be configured first.
When the host requires data from the device, the user has to select beforehand the IN request
mode with the IN Request Mode bit in the Pipe n IN Request register (UPINRQn.INMODE):
• When INMODE is written to zero, the USBB will perform (INRQ + 1) IN requests before
freezing the pipe.
• When INMODE is written to one, the USBB will perform IN requests endlessly when the pipe
is not frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (PFREEZE)
field in UPCONn is zero).
The Received IN Data Interrupt (RXINI) bit in UPSTAn is set at the same time as the FIFO Con-
trol (FIFOCON) bit in UPCONn when the current bank is full. This triggers a PnINT interrupt if the
Received IN Data Interrupt Enable (RXINE) bit in UPCONn is one.
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RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit
in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what
has no effect on the pipe FIFO.
The user then reads from the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
DATA)” on page 747) and clears the FIFOCON bit (by writing a one to the FIFO Control Clear
(FIFOCONC) bit in UPCONnCLR) to free the bank. If the IN pipe is composed of multiple banks,
this also switches to the next bank. The RXINI and FIFOCON bits are updated in accordance
with the status of the next bank.
RXINI shall always be cleared before clearing FIFOCON.
The Read/Write Allowed (RWALL) bit in UPSTAn is set when the current bank is not empty, i.e.,
the software can read further data from the FIFO.
Figure 27-24. Example of an IN Pipe with 1 Data Bank
DATA DATA
IN ACK IN ACK
(bank 0) (bank 0)
HW HW
RXINI SW SW
FIFOCON read data from CPU SW read data from CPU
BANK 0 BANK 0
Figure 27-25. Example of an IN Pipe with 2 Data Banks
DATA DATA
IN ACK IN ACK
(bank 0) (bank 1)
HW HW
RXINI SW SW
FIFOCON read data from CPU SW read data from CPU
BANK 0 BANK 1
27.7.3.11 Management of OUT pipes
OUT packets are sent by the host. All the data can be written which acknowledges or not the
bank when it is full.
The pipe must be configured and unfrozen first.
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The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFO-
CON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data
Interrupt Enable (TXOUTE) bit in UPCONn is one.
TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt
Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the
pipe FIFO.
The user then writes into the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
DATA)” on page 747) and clears the FIFOCON bit to allow the USBB to send the data. If the
OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXOUTI shall always be cleared before clearing FIFOCON.
The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write fur-
ther data into the FIFO.
Note that if the user decides to switch to the Suspend state (by writing a zero to the
UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and
the bank is sent.
Note that in High-Speed operating mode, the host controller automatically manages the PING
protocol to maximize the USB bandwidth. The user can tune the PING protocol by handling the
Ping Enable (PINGEN) bit and the bInterval Parameter for the Bulk-Out/Ping Transaction
(BINTERVALL) field in UPCFGn. See the Section 27.8.3.12 for more details.
Figure 27-26. Example of an OUT Pipe with one Data Bank
DATA
OUT ACK OUT
(bank 0)
HW
TXOUTI SW SW
FIFOCON write data to CPU SW write data to CPU SW
BANK 0 BANK 0
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Figure 27-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
DATA DATA
OUT ACK OUT ACK
(bank 0) (bank 1)
HW
TXOUTI SW SW SW
FIFOCON write data to CPU SW write data to CPU write data to CPU
BANK 0 BANK 1 SW BANK0
Figure 27-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay
DATA DATA
OUT ACK OUT ACK
(bank 0) (bank 1)
HW
TXOUTI SW SW SW
FIFOCON write data to CPU SW write data to CPU SW write data to CPU
BANK 0 BANK 1 BANK0
27.7.3.12 CRC error
This error exists only for isochronous IN pipes. It set the CRC Error Interrupt (CRCERRI) bit,
what triggers a PnINT interrupt if then the CRC Error Interrupt Enable (CRCERRE) bit in
UPCONn is one.
A CRC error can occur during IN stage if the USBB detects a corrupted received packet. The IN
packet is stored in the bank as if no CRC error had occurred (RXINI is set).
27.7.3.13 Interrupts
See the structure of the USB host interrupt system on Figure 27-6 on page 632.
There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors (not related to CPU exceptions).
•Global interrupts
The processing host global interrupts are:
• The Device Connection Interrupt (DCONNI)
• The Device Disconnection Interrupt (DDISCI)
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• The USB Reset Sent Interrupt (RSTI)
• The Downstream Resume Sent Interrupt (RSMEDI)
• The Upstream Resume Received Interrupt (RXRSMI)
• The Host Start of Frame Interrupt (HSOFI)
• The Host Wake-Up Interrupt (HWUPI)
• The Pipe n Interrupt (PnINT)
• The DMA Channel n Interrupt (DMAnINT)
There is no exception host global interrupt.
•Pipe interrupts
The processing host pipe interrupts are:
• The Received IN Data Interrupt (RXINI)
• The Transmitted OUT Data Interrupt (TXOUTI)
• The Transmitted SETUP Interrupt (TXSTPI)
• The Short Packet Interrupt (SHORTPACKETI)
• The Number of Busy Banks (NBUSYBK) interrupt
The exception host pipe interrupts are:
• The Underflow Interrupt (UNDERFI)
• The Pipe Error Interrupt (PERRI)
• The NAKed Interrupt (NAKEDI)
• The Overflow Interrupt (OVERFI)
• The Received STALLed Interrupt (RXSTALLDI)
• The CRC Error Interrupt (CRCERRI)
•DMA interrupts
The processing host DMA interrupts are:
• The End of USB Transfer Status (EOTSTA) interrupt
• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt
• The Descriptor Loaded Status (DESCLDSTA) interrupt
There is no exception host DMA interrupt.
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27.7.4 USB DMA Operation
27.7.4.1 Introduction
USB packets of any length may be transferred when required by the USBB. These transfers
always feature sequential addressing. These two characteristics mean that in case of high
USBB throughput, both HSB ports will benefit from “incrementing burst of unspecified length”
since the average access latency of HSB slaves can then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data
transfers and channel descriptor loading. A burst may last on the HSB busses for the duration of
a whole USB packet transfer, unless otherwise broken by the HSB arbitration or the HSB 1kbyte
boundary crossing.
Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus band-
width performance boost with paged memories. This is because these memories row (or bank)
changes, which are very clock-cycle consuming, will then likely not occur or occur once instead
of dozens of times during a single big USB packet DMA transfer in case other HSB masters
address the memory. This means up to 128 words single cycle unbroken HSB bursts for bulk
pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints.
This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size
(PSIZE/EPSIZE) and the Channel Byte Length (CHBYTELENGTH) field in the Device DMA
Channel n Control (UDDMAnCONTROL) register.
The USBB average throughput may be up to nearly 53 Mbyte/s. Its average access latency
decreases as burst length increases due to the zero wait-state side effect of unchanged
pipe/endpoint. Word access allows reducing the HSB bandwidth required for the USB by four
compared to native byte access. If at least 0 wait-state word burst capability is also provided by
the other DMA HSB bus slaves, each of both DMA HSB busses need less than 60% bandwidth
allocation for full USB bandwidth usage at 33MHz, and less than 30% at 66MHz.
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Figure 27-29. Example of DMA Chained List
Transfer Descriptor
USB DMA Channel X Registers
(Current Transfer Descriptor) Next Descriptor Address
HSB Address Transfer Descriptor
Next Descriptor Address
Control Next Descriptor Address
HSB Address Transfer Descriptor
HSB Address
Control Next Descriptor Address
Control
HSB Address
Status
Control
NULL
Memory Area
Data Buffer 1
Data Buffer 2
Data Buffer 3
27.7.4.2 DMA Channel descriptor
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as
described below:
• Offset 0:
– The address must be aligned: 0xXXXX0
– DMA Channel n Next Descriptor Address Register: DMAnNXTDESCADDR
• Offset 4:
– The address must be aligned: 0xXXXX4
– DMA Channel n HSB Address Register: DMAnADDR
• Offset 8:
– The address must be aligned: 0xXXXX8
– DMA Channel n Control Register: DMAnCONTROL
27.7.4.3 Programming a chanel:
Each DMA transfer is unidirectionnal. Direction depends on the type of the associated endpoint
(IN or OUT).
Three registers, the UDDMAnNEXTDESC, the UDDMAnADDR and UDDMAnCONTROL need
to be programmed to set up wether single or multiple transfer is used.
The following example refers to OUT endpoint. For IN endpoint, the programming is symmetric.
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•Single-block transfer programming example for OUT transfer :
The following sequence may be used:
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
for this endpoint in the UECFGn register to handle multiple OUT packet.
• Write the starting destination address in the UDDMAnADDR register.
• There is no need to program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 2 as shown in Figure 27-6 on page 714
to set up a single block transfer.
The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.
Once the DMA channel is completed (i.e : the channel byte length is reached), after one or mul-
tiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence,
the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTATUS.EOCHBUFFSTA bit
is set indicating a end of dma channel. If the UDDMAnCONTROL.DMAENDEN bit was set, the
last endpoint bank will be properly released even if there are some residual datas inside, i.e:
OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an
integral multiple of the endpoint size.
•Programming example for single-block dma transfer with automatic closure for OUT transfer :
The idea is to automatically close the DMA transfer at the end of the OUT transaction (received
short packet). The following sequence may be used:
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
for this endpoint in the UECFGn register to handle multiple OUT packet.
• Write the starting destination address in the UDDMAnADDR register.
• There is no need to program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 2 as shown in Figure 27-6 on page 714
to set up a single block transfer.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty. Once the endpoint is empty, the
UDDMAnSTATUS.CHACTIVE bit is cleared.
After one or multiple processed OUT packet, the DMA channel is completed after sourcing a
short packet. Then, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few
cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTA-
TUS.EOTSTA bit is set indicating that the DMA was closed by a end of USB transaction.
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•Programming example for multi-block dma transfer : run and link at end of buffer
The idea is to run first a single block transfer followed automatically by a linked list of DMA. The
following sequence may be used:
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
for this endpoint in the UECFGn register to handle multiple OUT packet.
• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items
: channel next descriptor address, channel destination address and channel control. The last
descriptor should be programmed according to row 2 as shown in Figure 27-6 on page 714.
• Write the starting destination address in the UDDMAnADDR register.
• Program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Optionnaly set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 4 as shown in Figure 27-6 on page 714.
The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.
Once the first DMA channel is completed (i.e : the channel byte length is reached), after one or
multiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, the UDDMAnSTATUS.CHEN bit is also cleared, and the
UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAn-
CONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if
there are some residual datas inside, i.e: OUT packet truncation at the end of DMA buffer when
the dma channel byte lenght is not an integral multiple of the endpoint size. Note that the
UDDMAnCONTROL.LDNXTCH bit remains to one indicating that a linked descriptor will be
loaded.
Once the new descriptor is loaded from the UDDMAnNEXTDESC memory address, the UDDM-
AnSTATUS.DESCLDSTA bit is set, and the UDDMAnCONTROL register is updated from the
memory. As a consequence, the UDDMAnSTATUS.CHEN bit is set, and the UDDMAnSTA-
TUS.CHACTIVE is set as soon as the endpoint is ready to be sourced by the DMA (received
OUT data packet).
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected according to row 2 as shown in Figure 27-6 on page 714.
At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
•Programming example for multi-block dma transfer : load next descriptor now
The idea is to directly run first a linked list of DMA. The following sequence may be used: The
following sequence may be used:
• Configure the targerted endpoint (source) as OUT type, and set the automatic bank switching
for this endpoint in the UECFGn register to handle multiple OUT packet.
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• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items
: channel next descriptor address, channel destination address and channel control. The last
descriptor should be programmed according to row 2 as shown in Figure 27-6 on page 714.
• Program the UDDMAnNEXTDESC register.
• Program the UDDMAnCONTROL according to Row 3 as shown in Figure 27-6 on page 714.
The UDDMAnSTATUS.CHEN bit is 0 and the UDDMAnSTATUS.LDNXTCHDESCEN is set indi-
cating that the DMA channel is pending until the endpoint is ready (received OUT packet).
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one. Then after a few cycle latency, the new descriptor is loaded from the memory and
the UDDMAnSTATUS.DESCLDSTA is set.
At the end of this DMA (for instance when the channel byte length has reached 0), the
UDDMAnCONTROL.CHEN bit is cleared, and then the UDDMAnSTATUS.CHEN bit is also
cleared. If the UDDMAnCONTROL.LDNXTCH value is one, a new descriptor is loaded.
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected according to row 2 as shown in Figure 27-6 on page 714.
At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
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27.8 User Interface
Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
0x0000 Device General Control Register UDCON Read/Write 0x00000100
0x0004 Device Global Interrupt Register UDINT Read-Only 0x00000000
0x0008 Device Global Interrupt Clear Register UDINTCLR Write-Only 0x00000000
0x000C Device Global Interrupt Set Register UDINTSET Write-Only 0x00000000
0x0010 Device Global Interrupt Enable Register UDINTE Read-Only 0x00000000
0x0014 Device Global Interrupt Enable Clear Register UDINTECLR Write-Only 0x00000000
0x0018 Device Global Interrupt Enable Set Register UDINTESET Write-Only 0x00000000
0x001C Endpoint Enable/Reset Register UERST Read/Write 0x00000000
0x0020 Device Frame Number Register UDFNUM Read-Only 0x00000000
0x0100 Endpoint 0 Configuration Register UECFG0 Read/Write 0x00002000
0x0104 Endpoint 1 Configuration Register UECFG1 Read/Write 0x00002000
0x0108 Endpoint 2 Configuration Register UECFG2 Read/Write 0x00002000
0x010C Endpoint 3 Configuration Register UECFG3 Read/Write 0x00002000
0x0110 Endpoint 4 Configuration Register UECFG4 Read/Write 0x00002000
0x0114 Endpoint 5 Configuration Register UECFG5 Read/Write 0x00002000
0x0118 Endpoint 6 Configuration Register UECFG6 Read/Write 0x00002000
0x011C Endpoint 7Configuration Register UECFG7 Read/Write 0x00002000
0x0130 Endpoint 0 Status Register UESTA0 Read-Only 0x00000100
0x0134 Endpoint 1 Status Register UESTA1 Read-Only 0x00000100
0x0138 Endpoint 2 Status Register UESTA2 Read-Only 0x00000100
0x013C Endpoint 3 Status Register UESTA3 Read-Only 0x00000100
0x0140 Endpoint 4 Status Register UESTA4 Read-Only 0x00000100
0x0144 Endpoint 5 Status Register UESTA5 Read-Only 0x00000100
0x0148 Endpoint 6 Status Register UESTA6 Read-Only 0x00000100
0x014C Endpoint 7Status Register UESTA7 Read-Only 0x00000100
0x0160 Endpoint 0 Status Clear Register UESTA0CLR Write-Only 0x00000000
0x0164 Endpoint 1 Status Clear Register UESTA1CLR Write-Only 0x00000000
0x0168 Endpoint 2 Status Clear Register UESTA2CLR Write-Only 0x00000000
0x016C Endpoint 3 Status Clear Register UESTA3CLR Write-Only 0x00000000
0x0170 Endpoint 4 Status Clear Register UESTA4CLR Write-Only 0x00000000
0x0174 Endpoint 5 Status Clear Register UESTA5CLR Write-Only 0x00000000
0x0178 Endpoint 6 Status Clear Register UESTA6CLR Write-Only 0x00000000
0x017C Endpoint 7 Status Clear Register UESTA7CLR Write-Only 0x00000000
0x0190 Endpoint 0 Status Set Register UESTA0SET Write-Only 0x00000000
0x0194 Endpoint 1 Status Set Register UESTA1SET Write-Only 0x00000000
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Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
0x0198 Endpoint 2 Status Set Register UESTA2SET Write-Only 0x00000000
0x019C Endpoint 3 Status Set Register UESTA3SET Write-Only 0x00000000
0x01A0 Endpoint 4 Status Set Register UESTA4SET Write-Only 0x00000000
0x01A4 Endpoint 5 Status Set Register UESTA5SET Write-Only 0x00000000
0x01A8 Endpoint 6 Status Set Register UESTA6SET Write-Only 0x00000000
0x01AC Endpoint 7 Status Set Register UESTA7SET Write-Only 0x00000000
0x01C0 Endpoint 0 Control Register UECON0 Read-Only 0x00000000
0x01C4 Endpoint 1 Control Register UECON1 Read-Only 0x00000000
0x01C8 Endpoint 2 Control Register UECON2 Read-Only 0x00000000
0x01CC Endpoint 3 Control Register UECON3 Read-Only 0x00000000
0x01D0 Endpoint 4 Control Register UECON4 Read-Only 0x00000000
0x01D4 Endpoint 5 Control Register UECON5 Read-Only 0x00000000
0x01D8 Endpoint 6 Control Register UECON6 Read-Only 0x00000000
0x01DC Endpoint 7 Control Register UECON7 Read-Only 0x00000000
0x01F0 Endpoint 0 Control Set Register UECON0SET Write-Only 0x00000000
0x01F4 Endpoint 1 Control Set Register UECON1SET Write-Only 0x00000000
0x01F8 Endpoint 2 Control Set Register UECON2SET Write-Only 0x00000000
0x01FC Endpoint 3 Control Set Register UECON3SET Write-Only 0x00000000
0x0200 Endpoint 4 Control Set Register UECON4SET Write-Only 0x00000000
0x0204 Endpoint 5 Control Set Register UECON5SET Write-Only 0x00000000
0x0208 Endpoint 6 Control Set Register UECON6SET Write-Only 0x00000000
0x020C Endpoint 7 Control Set Register UECON7SET Write-Only 0x00000000
0x0220 Endpoint 0 Control Clear Register UECON0CLR Write-Only 0x00000000
0x0224 Endpoint 1 Control Clear Register UECON1CLR Write-Only 0x00000000
0x0228 Endpoint 2 Control Clear Register UECON2CLR Write-Only 0x00000000
0x022C Endpoint 3 Control Clear Register UECON3CLR Write-Only 0x00000000
0x0230 Endpoint 4 Control Clear Register UECON4CLR Write-Only 0x00000000
0x0234 Endpoint 5 Control Clear Register UECON5CLR Write-Only 0x00000000
0x0238 Endpoint 6 Control Clear Register UECON6CLR Write-Only 0x00000000
0x023C Endpoint 7 Control Clear Register UECON7CLR Write-Only 0x00000000
Device DMA Channel 1 Next Descriptor UDDMA1
0x0310 Read/Write 0x00000000
Address Register NEXTDESC
UDDMA1
0x0314 Device DMA Channel 1 HSB Address Register Read/Write 0x00000000
ADDR
UDDMA1
0x0318 Device DMA Channel 1 Control Register Read/Write 0x00000000
CONTROL
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Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
UDDMA1
0x031C Device DMA Channel 1 Status Register Read/Write 0x00000000
STATUS
Device DMA Channel 2 Next Descriptor UDDMA2
0x0320 Read/Write 0x00000000
Address Register NEXTDESC
UDDMA2
0x0324 Device DMA Channel 2 HSB Address Register Read/Write 0x00000000
ADDR
UDDMA2
0x0328 Device DMA Channel 2 Control Register Read/Write 0x00000000
CONTROL
UDDMA2
0x032C Device DMA Channel 2 Status Register Read/Write 0x00000000
STATUS
Device DMA Channel 3 Next Descriptor UDDMA3
0x0330 Read/Write 0x00000000
Address Register NEXTDESC
UDDMA3
0x0334 Device DMA Channel 3 HSB Address Register Read/Write 0x00000000
ADDR
UDDMA3
0x0338 Device DMA Channel 3 Control Register Read/Write 0x00000000
CONTROL
UDDMA3
0x033C Device DMA Channel 3 Status Register Read/Write 0x00000000
STATUS
Device DMA Channel 4 Next Descriptor UDDMA4
0x0340 Read/Write 0x00000000
Address Register NEXTDESC
UDDMA4
0x0344 Device DMA Channel 4 HSB Address Register Read/Write 0x00000000
ADDR
UDDMA4
0x0348 Device DMA Channel 4 Control Register Read/Write 0x00000000
CONTROL
UDDMA4
0x034C Device DMA Channel 4 Status Register Read/Write 0x00000000
STATUS
Device DMA Channel 5 Next Descriptor UDDMA5
0x0350 Read/Write 0x00000000
Address Register NEXTDESC
UDDMA5
0x0354 Device DMA Channel 5 HSB Address Register Read/Write 0x00000000
ADDR
UDDMA5
0x0358 Device DMA Channel 5 Control Register Read/Write 0x00000000
CONTROL
UDDMA5
0x035C Device DMA Channel 5 Status Register Read/Write 0x00000000
STATUS
Device DMA Channel 6 Next Descriptor UDDMA6
0x0360 Read/Write 0x00000000
Address Register NEXTDESC
UDDMA6
0x0364 Device DMA Channel 6 HSB Address Register Read/Write 0x00000000
ADDR
UDDMA6
0x0368 Device DMA Channel 6 Control Register Read/Write 0x00000000
CONTROL
UDDMA6
0x036C Device DMA Channel 6 Status Register Read/Write 0x00000000
STATUS
Device DMA Channel 7 Next Descriptor UDDMA7
0x0370 Read/Write 0x00000000
Address Register NEXTDESC
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Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
UDDMA7
0x0374 Device DMA Channel 7 HSB Address Register Read/Write 0x00000000
ADDR
UDDMA7
0x0378 Device DMA Channel 7 Control Register Read/Write 0x00000000
CONTROL
UDDMA7
0x037C Device DMA Channel 7Status Register Read/Write 0x00000000
STATUS
0x0400 Host General Control Register UHCON Read/Write 0x00000000
0x0404 Host Global Interrupt Register UHINT Read-Only 0x00000000
0x0408 Host Global Interrupt Clear Register UHINTCLR Write-Only 0x00000000
0x040C Host Global Interrupt Set Register UHINTSET Write-Only 0x00000000
0x0410 Host Global Interrupt Enable Register UHINTE Read-Only 0x00000000
0x0414 Host Global Interrupt Enable Clear Register UHINTECLR Write-Only 0x00000000
0x0418 Host Global Interrupt Enable Set Register UHINTESET Write-Only 0x00000000
0x0041C Pipe Enable/Reset Register UPRST Read/Write 0x00000000
0x0420 Host Frame Number Register UHFNUM Read/Write 0x00000000
0x0424 Host Address 1 Register UHADDR1 Read/Write 0x00000000
0x0428 Host Address 2 Register UHADDR2 Read/Write 0x00000000
0x0500 Pipe 0 Configuration Register UPCFG0 Read/Write 0x00000000
0x0504 Pipe 1 Configuration Register UPCFG1 Read/Write 0x00000000
0x0508 Pipe 2 Configuration Register UPCFG2 Read/Write 0x00000000
0x050C Pipe 3 Configuration Register UPCFG3 Read/Write 0x00000000
0x0510 Pipe 4 Configuration Register UPCFG4 Read/Write 0x00000000
0x0514 Pipe 5 Configuration Register UPCFG5 Read/Write 0x00000000
0x0518 Pipe 6 Configuration Register UPCFG6 Read/Write 0x00000000
0x051C Pipe 7 Configuration Register UPCFG7 Read/Write 0x00000000
0x0530 Pipe 0 Status Register UPSTA0 Read-Only 0x00000000
0x0534 Pipe 1 Status Register UPSTA1 Read-Only 0x00000000
0x0538 Pipe 2 Status Register UPSTA2 Read-Only 0x00000000
0x053C Pipe 3 Status Register UPSTA3 Read-Only 0x00000000
0x0540 Pipe 4 Status Register UPSTA4 Read-Only 0x00000000
0x0544 Pipe 5 Status Register UPSTA5 Read-Only 0x00000000
0x0548 Pipe 6 Status Register UPSTA6 Read-Only 0x00000000
0x054C Pipe 7Status Register UPSTA7 Read-Only 0x00000000
0x0560 Pipe 0 Status Clear Register UPSTA0CLR Write-Only 0x00000000
0x0564 Pipe 1 Status Clear Register UPSTA1CLR Write-Only 0x00000000
0x0568 Pipe 2 Status Clear Register UPSTA2CLR Write-Only 0x00000000
0x056C Pipe 3 Status Clear Register UPSTA3CLR Write-Only 0x00000000
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Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
0x0570 Pipe 4 Status Clear Register UPSTA4CLR Write-Only 0x00000000
0x0574 Pipe 5 Status Clear Register UPSTA5CLR Write-Only 0x00000000
0x0578 Pipe 6 Status Clear Register UPSTA6CLR Write-Only 0x00000000
0x057C Pipe 7 Status Clear Register UPSTA7CLR Write-Only 0x00000000
0x0590 Pipe 0 Status Set Register UPSTA0SET Write-Only 0x00000000
0x0594 Pipe 1 Status Set Register UPSTA1SET Write-Only 0x00000000
0x0598 Pipe 2 Status Set Register UPSTA2SET Write-Only 0x00000000
0x059C Pipe 3 Status Set Register UPSTA3SET Write-Only 0x00000000
0x05A0 Pipe 4 Status Set Register UPSTA4SET Write-Only 0x00000000
0x05A4 Pipe 5 Status Set Register UPSTA5SET Write-Only 0x00000000
0x05A8 Pipe 6 Status Set Register UPSTA6SET Write-Only 0x00000000
0x05AC Pipe 7 Status Set Register UPSTA7SET Write-Only 0x00000000
0x05C0 Pipe 0 Control Register UPCON0 Read-Only 0x00000000
0x05C4 Pipe 1 Control Register UPCON1 Read-Only 0x00000000
0x05C8 Pipe 2 Control Register UPCON2 Read-Only 0x00000000
0x05CC Pipe 3 Control Register UPCON3 Read-Only 0x00000000
0x05D0 Pipe 4 Control Register UPCON4 Read-Only 0x00000000
0x05D4 Pipe 5 Control Register UPCON5 Read-Only 0x00000000
0x05D8 Pipe 6 Control Register UPCON6 Read-Only 0x00000000
0x05DC Pipe 7 Control Register UPCON7 Read-Only 0x00000000
0x05F0 Pipe 0 Control Set Register UPCON0SET Write-Only 0x00000000
0x05F4 Pipe 1 Control Set Register UPCON1SET Write-Only 0x00000000
0x05F8 Pipe 2 Control Set Register UPCON2SET Write-Only 0x00000000
0x05FC Pipe 3 Control Set Register UPCON3SET Write-Only 0x00000000
0x0600 Pipe 4 Control Set Register UPCON4SET Write-Only 0x00000000
0x0604 Pipe 5 Control Set Register UPCON5SET Write-Only 0x00000000
0x0608 Pipe 6 Control Set Register UPCON6SET Write-Only 0x00000000
0x060C Pipe 7 Control Set Register UPCON7SET Write-Only 0x00000000
0x0620 Pipe 0 Control Clear Register UPCON0CLR Write-Only 0x00000000
0x0624 Pipe 1 Control Clear Register UPCON1CLR Write-Only 0x00000000
0x0628 Pipe 2 Control Clear Register UPCON2CLR Write-Only 0x00000000
0x062C Pipe 3 Control Clear Register UPCON3CLR Write-Only 0x00000000
0x0630 Pipe 4 Control Clear Register UPCON4CLR Write-Only 0x00000000
0x0634 Pipe 5 Control Clear Register UPCON5CLR Write-Only 0x00000000
0x0638 Pipe 6 Control Clear Register UPCON6CLR Write-Only 0x00000000
0x063C Pipe 7 Control Clear Register UPCON7CLR Write-Only 0x00000000
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Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
0x0650 Pipe 0 IN Request Register UPINRQ0 Read/Write 0x00000000
0x0654 Pipe 1 IN Request Register UPINRQ1 Read/Write 0x00000000
0x0658 Pipe 2 IN Request Register UPINRQ2 Read/Write 0x00000000
0x065C Pipe 3 IN Request Register UPINRQ3 Read/Write 0x00000000
0x0660 Pipe 4 IN Request Register UPINRQ4 Read/Write 0x00000000
0x0664 Pipe 5 IN Request Register UPINRQ5 Read/Write 0x00000000
0x0668 Pipe 6 IN Request Register UPINRQ6 Read/Write 0x00000000
0x066C Pipe 7 IN Request Register UPINRQ7 Read/Write 0x00000000
0x0680 Pipe 0 Error Register UPERR0 Read/Write 0x00000000
0x0684 Pipe 1 Error Register UPERR1 Read/Write 0x00000000
0x0688 Pipe 2 Error Register UPERR2 Read/Write 0x00000000
0x068C Pipe 3 Error Register UPERR3 Read/Write 0x00000000
0x0690 Pipe 4 Error Register UPERR4 Read/Write 0x00000000
0x0694 Pipe 5 Error Register UPERR5 Read/Write 0x00000000
0x0698 Pipe 6 Error Register UPERR6 Read/Write 0x00000000
0x069C Pipe 7 Error Register UPERR7 Read/Write 0x00000000
Host DMA Channel 1 Next Descriptor Address UHDMA1
0x0710 Read/Write 0x00000000
Register NEXTDESC
UHDMA1
0x0714 Host DMA Channel 1 HSB Address Register Read/Write 0x00000000
ADDR
UHDMA1
0x0718 Host DMA Channel 1 Control Register Read/Write 0x00000000
CONTROL
UHDMA1
0x071C Host DMA Channel 1 Status Register Read/Write 0x00000000
STATUS
Host DMA Channel 2 Next Descriptor Address UHDMA2
0x0720 Read/Write 0x00000000
Register NEXTDESC
UHDMA2
0x0724 Host DMA Channel 2 HSB Address Register Read/Write 0x00000000
ADDR
UHDMA2
0x0728 Host DMA Channel 2 Control Register Read/Write 0x00000000
CONTROL
UHDMA2
0x072C Host DMA Channel 2 Status Register Read/Write 0x00000000
STATUS
Host DMA Channel 3 Next Descriptor Address UHDMA3
0x0730 Read/Write 0x00000000
Register NEXTDESC
UHDMA3
0x0734 Host DMA Channel 3 HSB Address Register Read/Write 0x00000000
ADDR
UHDMA3
0x0738 Host DMA Channel 3 Control Register Read/Write 0x00000000
CONTROL
UHDMA3
0x073C Host DMA Channel 3Status Register Read/Write 0x00000000
STATUS
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Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
Host DMA Channel 4 Next Descriptor Address UHDMA4
0x0740 Read/Write 0x00000000
Register NEXTDESC
UHDMA4
0x0744 Host DMA Channel 4 HSB Address Register Read/Write 0x00000000
ADDR
UHDMA4
0x0748 Host DMA Channel 4 Control Register Read/Write 0x00000000
CONTROL
UHDMA4
0x074C Host DMA Channel 4 Status Register Read/Write 0x00000000
STATUS
Host DMA Channel 5 Next Descriptor Address UHDMA5
0x0750 Read/Write 0x00000000
Register NEXTDESC
UHDMA5
0x0754 Host DMA Channel 5 HSB Address Register Read/Write 0x00000000
ADDR
UHDMA5
0x0758 Host DMA Channel 5 Control Register Read/Write 0x00000000
CONTROL
UHDMA5
0x075C Host DMA Channel 5 Status Register Read/Write 0x00000000
STATUS
Host DMA Channel 6 Next Descriptor Address UHDMA6
0x0760 Read/Write 0x00000000
Register NEXTDESC
UHDMA6
0x0764 Host DMA Channel 6 HSB Address Register Read/Write 0x00000000
ADDR
UHDMA6
0x0768 Host DMA Channel 6 Control Register Read/Write 0x00000000
CONTROL
UHDMA6
0x076C Host DMA Channel 6 Status Register Read/Write 0x00000000
STATUS
Host DMA Channel 7 Next Descriptor Address UHDMA7
0x0770 Read/Write 0x00000000
Register NEXTDESC
UHDMA7
0x0774 Host DMA Channel 7 HSB Address Register Read/Write 0x00000000
ADDR
UHDMA7
0x0778 Host DMA Channel 7 Control Register Read/Write 0x00000000
CONTROL
UHDMA7
0x077C Host DMA Channel 7 Status Register Read/Write 0x00000000
STATUS
0x0800 General Control Register USBCON Read/Write 0x03004000
0x0804 General Status Register USBSTA Read-Only 0x00000400
0x0808 General Status Clear Register USBSTACLR Write-Only 0x00000000
0x080C General Status Set Register USBSTASET Write-Only 0x00000000
0x0818 IP Version Register UVERS Read-Only -(1)
0x081C IP Features Register UFEATURES Read-Only -(1)
0x0820 IP PB Address Size Register UADDRSIZE Read-Only -(1)
0x0824 IP Name Register 1 UNAME1 Read-Only -(1)
0x0828 IP Name Register 2 UNAME2 Read-Only -(1)
0x082C USB Finite State Machine Status Register USBFSM Read-Only 0x00000009
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Table 27-5. USB HSB Memory Map
Offset Register Name Access Reset Value
0x00000 - USB
Pipe/Endpoint 0 FIFO Data Register Read/Write Undefined
0x0FFFC FIFO0DATA
0x10000 - USB
Pipe/Endpoint 1 FIFO Data Register Read/Write Undefined
0x1FFFC FIFO1DATA
0x20000 - USB
Pipe/Endpoint 2 FIFO Data Register Read/Write Undefined
0x2FFFC FIFO2DATA
0x30000 - USB
Pipe/Endpoint 3 FIFO Data Register Read/Write Undefined
0x3FFFC FIFO3DATA
0x40000 - USB
Pipe/Endpoint 4 FIFO Data Register Read/Write Undefined
0x4FFFC FIFO4DATA
0x50000 - USB
Pipe/Endpoint 5 FIFO Data Register Read/Write Undefined
0x5FFFC FIFO5DATA
0x60000 - USB
Pipe/Endpoint 6 FIFO Data Register Read/Write Undefined
0x6FFFC FIFO6DATA
0x70000 - USB
Pipe/Endpoint 7 FIFO Data Register Read/Write Undefined
0x7FFFC FIFO7DATA
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
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27.8.1 USB General Registers
27.8.1.1 General Control Register
Name: USBCON
Access Type: Read/Write
Offset: 0x0800
Reset Value: 0x03004000
31 30 29 28 27 26 25 24
- - - - - - UIMOD UIDE
23 22 21 20 19 18 17 16
- UNLOCK TIMPAGE - - TIMVALUE
15 14 13 12 11 10 9 8
USBE FRZCLK VBUSPO OTGPADE VBUSHWC
7 6 5 4 3 2 1 0
STOE ROLEEXE BCERRE VBERRE VBUSTE IDTE
• UIMOD: USBB Mode
This bit has no effect when UIDE is one (USB_ID input pin activated).
0: The module is in USB host mode.
1: The module is in USB device mode.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• UIDE: USB_ID Pin Enable
0: The USB mode (device/host) is selected from the UIMOD bit.
1: The USB mode (device/host) is selected from the USB_ID input pin.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• UNLOCK: Timer Access Unlock
1: The TIMPAGE and TIMVALUE fields are unlocked.
0: The TIMPAGE and TIMVALUE fields are locked.
The TIMPAGE and TIMVALUE fields can always be read, whatever the value of UNLOCK.
• TIMPAGE: Timer Page
This field contains the page value to access a special timer register.
• TIMVALUE: Timer Value
This field selects the timer value that is written to the special time register selected by TIMPAGE. See Section 27.7.1.8 for
details.
• USBE: USBB Enable
Writing a zero to this bit will reset the USBB, disable the USB transceiver and, disable the USBB clock inputs. Unless explicitly
stated, all registers then will become read-only and will be reset.
1: The USBB is enabled.
0: The USBB is disabled.
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This bit can be written even if FRZCLK is one.
• FRZCLK: Freeze USB Clock
1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated, all
registers then become read-only.
0: The clock inputs are enabled.
This bit can be written even if USBE is zero. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit, but
this freezes the clock inputs whatever its value.
• VBUSPO: VBus Polarity
1: The USB_VBOF output signal is inverted (active low).
0: The USB_VBOF output signal is in its default mode (active high).
To be generic. May be useful to control an external VBus power module.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• OTGPADE: OTG Pad Enable
1: The OTG pad is enabled.
0: The OTG pad is disabled.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• VBUSHWC: VBus Hardware Control
1: The hardware control over the USB_VBOF output pin is disabled.
0: The hardware control over the USB_VBOF output pin is enabled. The USBB resets the USB_VBOF output pin when a VBUS
problem occurs.
• STOE: Suspend Time-Out Interrupt Enable
1: The Suspend Time-Out Interrupt (STOI) is enabled.
0: The Suspend Time-Out Interrupt (STOI) is disabled.
• ROLEEXE: Role Exchange Interrupt Enable
1: The Role Exchange Interrupt (ROLEEXI) is enabled.
0: The Role Exchange Interrupt (ROLEEXI) is disabled.
• BCERRE: B-Connection Error Interrupt Enable
1: The B-Connection Error Interrupt (BCERRI) is enabled.
0: The B-Connection Error Interrupt (BCERRI) is disabled.
• VBERRE: VBus Error Interrupt Enable
1: The VBus Error Interrupt (VBERRI) is enabled.
0: The VBus Error Interrupt (VBERRI) is disabled.
• VBUSTE: VBus Transition Interrupt Enable
1: The VBus Transition Interrupt (VBUSTI) is enabled.
0: The VBus Transition Interrupt (VBUSTI) is disabled.
• IDTE: ID Transition Interrupt Enable
1: The ID Transition interrupt (IDTI) is enabled.
0: The ID Transition interrupt (IDTI) is disabled.
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27.8.1.2 General Status Register
Register Name: USBSTA
Access Type: Read-Only
Offset: 0x0804
Reset Value: 0x00000400
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- CLKUSABLE SPEED VBUS ID VBUSRQ -
7 6 5 4 3 2 1 0
STOI ROLEEXI BCERRI VBERRI VBUSTI IDTI
• CLKUSABLE: UTMI Clock Usable
This bit is set when the UTMI 30MHz is usable.
This bit is cleared when the UTMI 30MHz is not usable.
• SPEED: Speed Status
This field is set according to the controller speed mode..
SPEED Speed Status
0 0 Full-Speed mode
1 0 Low-Speed mode
0 1 High-Speed mode
1 1 Reserved
• VBUS: VBus Level
This bit is set when the VBus line level is high.
This bit is cleared when the VBus line level is low.
This bit can be used in either device or host mode to monitor the USB bus connection state of the application.
• ID: USB_ID Pin State
This bit is cleared when the USB_ID level is low, even if USBE is zero.
This bit is set when the USB_ID level is high, event if USBE is zero.
• VBUSRQ: VBus Request
This bit is set when the USBSTASET.VBUSRQS bit is written to one.
This bit is cleared when the USBSTACLR.VBUSRQC bit is written to one or when a VBus error occurs and VBUSHWC is zero.
1: The USB_VBOF output pin is driven high to enable the VBUS power supply generation.
0: The USB_VBOF output pin is driven low to disable the VBUS power supply generation.
This bit shall only be used in host mode.
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• STOI: Suspend Time-Out Interrupt
This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if
STOE is one.
This bit is cleared when the UBSTACLR.STOIC bit is written to one.
This bit shall only be used in host mode.
• ROLEEXI: Role Exchange Interrupt
This bit is set when the USBB has successfully switched its mode because of an negotiation (host to device or device to host).
This triggers a USB interrupt if ROLEEXE is one.
This bit is cleared when the UBSTACLR.ROLEEXIC bit is written to one.
• BCERRI: B-Connection Error Interrupt
This bit is set when an error occurs during the B-connection. This triggers a USB interrupt if BCERRE is one.
This bit is cleared when the UBSTACLR.BCERRIC bit is written to one.
This bit shall only be used in host mode.
• VBERRI: VBus Error Interrupt
This bit is set when a VBus drop has been detected. This triggers a USB interrupt if VBERRE is one.
This bit is cleared when the UBSTACLR.VBERRIC bit is written to one.
This bit shall only be used in host mode.
If a VBus problem occurs, then the VBERRI interrupt is generated even if the USBB does not go to an error state because of
VBUSHWC is one.
• VBUSTI: VBus Transition Interrupt
This bit is set when a transition (high to low, low to high) has been detected on the USB_VBUS pad. This triggers an USB
interrupt if VBUSTE is one.
This bit is cleared when the UBSTACLR.VBUSTIC bit is written to one.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
• IDTI: ID Transition Interrupt
This bit is set when a transition (high to low, low to high) has been detected on the USB_ID input pin. This triggers an USB
interrupt if IDTE is one.
This bit is cleared when the UBSTACLR.IDTIC bit is written to one.
This interrupt is generated even if the clock is frozen by the FRZCLK bit or pad is disable by USBCON.OTGPADE or the USBB
module is disabled by USBCON.USBE.
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27.8.1.3 General Status Clear Register
Register Name: USBSTACLR
Access Type: Write-Only
Offset: 0x0808
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - VBUSRQC -
7 6 5 4 3 2 1 0
STOIC ROLEEXIC BCERRIC VBERRIC VBUSTIC IDTIC
Writing a one to a bit in this register will clear the corresponding bit in UBSTA.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.1.4 General Status Set Register
Register Name: USBSTASET
Access Type: Write-Only
Offset: 0x080C
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - VBUSRQS -
7 6 5 4 3 2 1 0
STOIS ROLEEXIS BCERRIS VBERRIS VBUSTIS IDTIS
Writing a one to a bit in this register will set the corresponding bit in UBSTA, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.1.5 Version Register
Register Name: UVERS
Access Type: Read-Only
Offset: 0x0818
Read Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
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27.8.1.6 Features Register
Register Name: UFEATURES
Access Type: Read-Only
Offset: 0x081C
Read Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
ENHBISO7 ENHBISO6 ENHBISO5 ENHBISO4 ENHBISO3 ENHBISO2 ENHBISO1 DATABUS
15 14 13 12 11 10 9 8
BYTEWRITE
FIFOMAXSIZE DMAFIFOWORDDEPTH
DPRAM
7 6 5 4 3 2 1 0
DMABUFFE
DMACHANNELNBR EPTNBRMAX
RSIZE
• ENHBISOn: High Bandwidth Isochronous Feature for Endpoint n
1: The high bandwidth isochronous is supported.
0: The high bandwidth isochronous is not supported.
• DATABUS: Data Bus 16-8
1: The UTMI data bus is a 16-bit data path at 30MHz.
0: The UTMI data bus is a 8-bit data path at 60MHz.
• BYTEWRITEDPRAM: DPRAM Byte-Write Capability
1: The DPRAM is natively byte-write capable.
0: The DPRAM byte write lanes have shadow logic implemented in the USBB IP interface.
• FIFOMAXSIZE: Maximal FIFO Size
This field indicates the maximal FIFO size, i.e., the DPRAM size:
FIFOMAXSIZE Maximal FIFO Size
0 0 0 < 256 bytes
0 0 1 < 512 bytes
0 1 0 < 1024 bytes
0 1 1 < 2048 bytes
1 0 0 < 4096 bytes
1 0 1 < 8192 bytes
1 1 0 < 16384 bytes
1 1 1 >= 16384 bytes
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• DMAFIFOWORDDEPTH: DMA FIFO Depth in Words
This field indicates the DMA FIFO depth controller in words:
DMAFIFOWORDDEPTH DMA FIFO Depth in Words
0 0 0 0 16
0 0 0 1 1
0 0 1 0 2
...
1 1 1 1 15
• DMABUFFERSIZE: DMA Buffer Size
1: The DMA buffer size is 24bits.
0: The DMA buffer size is 16bits.
• DMACHANNELNBR: Number of DMA Channels
This field indicates the number of hardware-implemented DMA channels:
DMACHANNELNBR Number of DMA Channels
0 0 0 Reserved
0 0 1 1
0 1 0 2
...
1 1 1 7
• EPTNBRMAX: Maximal Number of Pipes/Endpoints
This field indicates the number of hardware-implemented pipes/endpoints:
EPTNBRMAX Maximal Number of Pipes/Endpoints
0 0 0 0 16
0 0 0 1 1
0 0 1 0 2
...
1 1 1 1 15
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27.8.1.7 Address Size Register
Register Name: UADDRSIZE
Access Type: Read-Only
Offset: 0x0820
Read Value: -
31 30 29 28 27 26 25 24
UADDRSIZE[31:24]
23 22 21 20 19 18 17 16
UADDRSIZE[23:16]
15 14 13 12 11 10 9 8
UADDRSIZE[15:8]
7 6 5 4 3 2 1 0
UADDRSIZE[7:0]
• UADDRSIZE: IP PB Address Size
This field indicates the size of the PB address space reserved for the USBB IP interface.
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27.8.1.8 Name Register 1
Register Name: UNAME1
Access Type: Read-Only
Offset: 0x0824
Read Value: -
31 30 29 28 27 26 25 24
UNAME1[31:24]
23 22 21 20 19 18 17 16
UNAME1[23:16]
15 14 13 12 11 10 9 8
UNAME1[15:8]
7 6 5 4 3 2 1 0
UNAME1[7:0]
• UNAME1: IP Name Part One
This field indicates the first part of the ASCII-encoded name of the USBB IP.
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27.8.1.9 Name Register 2
Register Name: UNAME2
Access Type: Read-Only
Offset: 0x0828
Read Value:
31 30 29 28 27 26 25 24
UNAME2[31:24]
23 22 21 20 19 18 17 16
UNAME2[23:16]
15 14 13 12 11 10 9 8
UNAME2[15:8]
7 6 5 4 3 2 1 0
UNAME2[7:0]
• UNAME2: IP Name Part Two
This field indicates the second part of the ASCII-encoded name of the USBB IP.
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27.8.1.10 Finite State Machine Status Register
Register Name: USBFSM
Access Type: Read-Only
Offset: 0x082C
Read Value: 0x00000009
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - DRDSTATE
• DRDSTATE
This field indicates the state of the USBB.
DRDSTATE Description
0 a_idle state: this is the start state for A-devices (when the ID pin is 0)
a_wait_vrise: In this state, the A-device waits for the voltage on VBus to rise above the A-
1
device VBus Valid threshold (4.4 V).
2 a_wait_bcon: In this state, the A-device waits for the B-device to signal a connection.
3 a_host: In this state, the A-device that operates in Host mode is operational.
4 a_suspend: The A-device operating as a host is in the suspend mode.
5 a_peripheral: The A-device operates as a peripheral.
a_wait_vfall: In this state, the A-device waits for the voltage on VBus to drop below the A-
6
device Session Valid threshold (1.4 V).
a_vbus_err: In this state, the A-device waits for recovery of the over-current condition that
7
caused it to enter this state.
8 a_wait_discharge: In this state, the A-device waits for the data usb line to discharge (100 us).
9 b_idle: this is the start state for B-device (when the ID pin is 1).
10 b_peripheral: In this state, the B-device acts as the peripheral.
b_wait_begin_hnp: In this state, the B-device is in suspend mode and waits until 3 ms before
11
initiating the HNP protocol if requested.
b_wait_discharge: In this state, the B-device waits for the data usb line to discharge (100 us)
12
before becoming Host.
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DRDSTATE Description
b_wait_acon: In this state, the B-device waits for the A-device to signal a connect before
13
becoming B-Host.
14 b_host: In this state, the B-device acts as the Host.
15 b_srp_init: In this state, the B-device attempts to start a session using the SRP protocol.
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27.8.2 USB Device Registers
27.8.2.1 Device General Control Register
Register Name: UDCON
Access Type: Read/Write
Offset: 0x0000
Reset Value: 0x00000100
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - OPMODE2
15 14 13 12 11 10 9 8
TSTPCKT TSTK TSTJ LS SPDCONF RMWKUP DETACH
7 6 5 4 3 2 1 0
ADDEN UADD
• OPMODE2: Specific Operational mode
1: The UTMI transceiver is in the «disable bit stuffing and NRZI encoding» operational mode for test purpose.
0: The UTMI transceiver is in normal operation mode.
• TSTPCKT: Test packet mode
1: The UTMI transceiver generates test packets for test purpose.
0: The UTMI transceiver is in normal operation mode.
• TSTK: Test mode K
1: The UTMI transceiver generates high-speed K state for test purpose.
0: The UTMI transceiver is in normal operation mode.
• TSTJ: Test mode J
1: The UTMI transceiver generates high-speed J state for test purpose.
0: The UTMI transceiver is in normal operation mode.
• LS: Low-Speed Mode Force
1: The low-speed mode is active.
0: The full-speed mode is active.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
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• SPDCONF: Speed Configuration
This field contains the peripheral speed.
SPDCONF Speed
Normal mode: the peripheral starts in full-speed mode and performs a high-speed reset to
0 0
switch to the high-speed mode if the host is high-speed capable.
0 1 reserved, do not use this configuration
1 0 reserved, do not use this configuration
1 1 Full-speed: the peripheral remains in full-speed mode whatever is the host speed capability.
• RMWKUP: Remote Wake-Up
Writing a one to this bit will send an upstream resume to the host for a remote wake-up.
Writing a zero to this bit has no effect.
This bit is cleared when the USBB receive a USB reset or once the upstream resume has been sent.
• DETACH: Detach
Writing a one to this bit will physically detach the device (disconnect internal pull-up resistor from D+ and D-).
Writing a zero to this bit will reconnect the device.
• ADDEN: Address Enable
Writing a one to this bit will activate the UADD field (USB address).
Writing a zero to this bit has no effect.
This bit is cleared when a USB reset is received.
• UADD: USB Address
This field contains the device address.
This field is cleared when a USB reset is received.
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27.8.2.2 Device Global Interrupt Register
Register Name: UDINT
Access Type: Read-Only
Offset: 0x0004
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INT DMA6INT DMA5INT DMA4INT DMA3INT DMA2INT DMA1INT -
23 22 21 20 19 18 17 16
- - - - EP7INT EP6INT EP5INT EP4INT
15 14 13 12 11 10 9 8
EP3INT EP2INT EP1INT EP0INT - - - -
7 6 5 4 3 2 1 0
- UPRSM EORSM WAKEUP EORST SOF MSOF SUSP
• DMAnINT: DMA Channel n Interrupt
This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one.
This bit is cleared when the UDDMAnSTATUS interrupt source is cleared.
• EPnINT: Endpoint n Interrupt
This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is
one.
This bit is cleared when the interrupt source is serviced.
• UPRSM: Upstream Resume Interrupt
This bit is set when the USBB sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is
one.
This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before).
• EORSM: End of Resume Interrupt
This bit is set when the USBB detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if
EORSME is one.
This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.
• WAKEUP: Wake-Up Interrupt
This bit is set when the USBB is reactivated by a filtered non-idle signal from the lines (not by an upstream resume). This
triggers an interrupt if WAKEUPE is one.
This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before).
This bit is cleared when the Suspend (SUSP) interrupt bit is set.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
• EORST: End of Reset Interrupt
This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one.
This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.
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• SOF: Start of Frame Interrupt
This bit is set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if SOFE is
one. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared.
This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt.
• MSOF: Micro Start of Frame Interrupt
This bit is set in High-speed mode when a USB “Micro Start of Frame” PID (SOF) has been detected (every 125 us). This
triggers a USB interrupt if MSOFE is one. The MFNUM field is updated. The FNUM field is unchanged.
This bit is cleared when the UDINTCLR.MSOFC bit is written to one to acknowledge the interrupt.
• SUSP: Suspend Interrupt
This bit is set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a
USB interrupt if SUSPE is one.
This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt.
This bit is cleared when the Wake-Up (WAKEUP) interrupt bit is set.
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27.8.2.3 Device Global Interrupt Clear Register
Register Name: UDINTCLR
Access Type: Write-Only
Offset: 0x0008
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- UPRSMC EORSMC WAKEUPC EORSTC SOFC MSOFC SUSPC
Writing a one to a bit in this register will clear the corresponding bit in UDINT.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.2.4 Device Global Interrupt Set Register
Register Name: UDINTSET
Access Type: Write-Only
Offset: 0x000C
Read Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INTS DMA6INTS DMA5INTS DMA4INTS DMA3INTS DMA2INTS DMA1INTS -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- UPRSMS EORSMS WAKEUPS EORSTS SOFS MSOFS SUSPS
Writing a one to a bit in this register will set the corresponding bit in UDINT, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.2.5 Device Global Interrupt Enable Register
Register Name: UDINTE
Access Type: Read-Only
Offset: 0x0010
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INTE DMA6INTE DMA5INTE DMA4INTE DMA3INTE DMA2INTE DMA1INTE -
23 22 21 20 19 18 17 16
- - - - EP7INTE EP6INTE EP5INTE EP4INTE
15 14 13 12 11 10 9 8
EP3INTE EP2INTE EP1INTE EP0INTE - - - -
7 6 5 4 3 2 1 0
- UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE
1: The corresponding interrupt is enabled.
0: The corresponding interrupt is disabled.
A bit in this register is set when the corresponding bit in UDINTESET is written to one.
A bit in this register is cleared when the corresponding bit in UDINTECLR is written to one.
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27.8.2.6 Device Global Interrupt Enable Clear Register
Register Name: UDINTECLR
Access Type: Write-Only
Offset: 0x0014
Read Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INTEC DMA6INTEC DMA5INTEC DMA4INTEC DMA3INTEC DMA2INTEC DMA1INTEC -
23 22 21 20 19 18 17 16
- - - - EP7INTEC EP6INTEC EP5INTEC EP4INTEC
15 14 13 12 11 10 9 8
EP3INTEC EP2INTEC EP1INTEC EP0INTEC - - - -
7 6 5 4 3 2 1 0
- UPRSMEC EORSMEC WAKEUPEC EORSTEC SOFEC MSOFEC SUSPEC
Writing a one to a bit in this register will clear the corresponding bit in UDINTE.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.2.7 Device Global Interrupt Enable Set Register
Register Name: UDINTESET
Access Type: Write-Only
Offset: 0x0018
Read Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INTES DMA6INTES DMA5INTES DMA4INTES DMA3INTES DMA2INTES DMA1INTES -
23 22 21 20 19 18 17 16
- - - - EP7INTES EP6INTES EP5INTES EP4INTES
15 14 13 12 11 10 9 8
EP3INTES EP2INTES EP1INTES EP0INTES - - - -
7 6 5 4 3 2 1 0
- UPRSMES EORSMES WAKEUPES EORSTES SOFES MSOFES SUSPES
Writing a one to a bit in this register will set the corresponding bit in UDINTE.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.2.8 Endpoint Enable/Reset Register
Register Name: UERST
Access Type: Read/Write
Offset: 0x001C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
EPRST7 EPRST6 EPRST5 EPRST4 EPRST3 EPRST2 EPRST1 EPRST0
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
EPEN7 EPEN6 EPEN5 EPEN4 EPEN3 EPEN2 EPEN1 EPEN0
• EPRSTn: Endpoint n Reset
Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus
reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration
(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field
(DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and start using the FIFO.
This bit is cleared upon receiving a USB reset.
• EPENn: Endpoint n Enable
1: The endpoint n is enabled.
0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint
n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
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27.8.2.9 Device Frame Number Register
Register Name: UDFNUM
Access Type: Read-Only
Offset: 0x0020
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
FNCERR - FNUM[10:5]
7 6 5 4 3 2 1 0
FNUM[4:0] MFNUM
• FNCERR: Frame Number CRC Error
This bit is set when a corrupted frame number (or micro-frame number) is received. This bit and the SOF (or MSOF) interrupt bit
are updated at the same time.
This bit is cleared upon receiving a USB reset.
• FNUM: Frame Number
This field contains the 11-bit frame number information. It is provided in the last received SOF packet.
This field is cleared upon receiving a USB reset.
FNUM is updated even if a corrupted SOF is received.
• MFNUM: Micro Frame Number
This field contains the 3-bit micro frame number information. It is provided in the last received MSOF packet.
This field is cleared at the beginning of each start of frame (SOF interrupt) or upon receiving a USB reset.
MFNUM is updated even if a corrupted MSOF is received.
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27.8.2.10 Endpoint n Configuration Register
Register Name: UECFGn, n in [0..7]
Access Type: Read/Write
Offset: 0x0100 + (n * 0x04)
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- NBTRANS EPTYPE - AUTOSW EPDIR
7 6 5 4 3 2 1 0
- EPSIZE EPBK ALLOC -
• NBTRANS: Number of transaction per microframe for isochronous endpoint
This field shall be written to the number of transaction per microframe to perform high-bandwidth isochronous transfer
This field can be written only for endpoint that have this capability (see UFEATURES register, ENHBISOn bit). This field is 0
otherwise.
This field is irrelevant for non-isochronous endpoint. Look at the UFEATURES register to know if the high-bandwidth
isochronous feature is supported by the device..
NBTRANS Number of transaction
0 0 reserved to endpoint that does not have the high-bandwidth isochronous capability.
0 1 default value: one transaction per micro-frame.
1 0 2 transactions per micro-frame. This endpoint should be configured as double-bank.
3 transactions per micro-frame. This endpoint should be configured as triple-bank if
1 1
supported (see Table 27-1 on page 624).
• EPTYPE: Endpoint Type
This field shall be written to select the endpoint type:
EPTYPE Endpoint Type
0 0 Control
0 1 Isochronous
1 0 Bulk
1 1 Interrupt
This field is cleared upon receiving a USB reset.
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• AUTOSW: Automatic Switch
This bit is cleared upon receiving a USB reset.
1: The automatic bank switching is enabled.
0: The automatic bank switching is disabled.
• EPDIR: Endpoint Direction
This bit is cleared upon receiving a USB reset.
1: The endpoint direction is IN (nor for control endpoints).
0: The endpoint direction is OUT.
• EPSIZE: Endpoint Size
This field shall be written to select the size of each endpoint bank. The maximum size of each endpoint is specified in Table 27-
1 on page 624.
EPSIZE Endpoint Size
0 0 0 8 bytes
0 0 1 16 bytes
0 1 0 32 bytes
0 1 1 64 bytes
1 0 0 128 bytes
1 0 1 256 bytes
1 1 0 512 bytes
This field is cleared upon receiving a USB reset (except for the endpoint 0).
• EPBK: Endpoint Banks
This field shall be written to select the number of banks for the endpoint:
EPBK Endpoint Banks
0 0 1 (single-bank endpoint)
0 1 2 (double-bank endpoint)
1 0 3 (triple-bank endpoint) if supported (see Table 27-1 on page 624).
1 1 Reserved
For control endpoints, a single-bank endpoint (0b00) shall be selected.
This field is cleared upon receiving a USB reset (except for the endpoint 0).
• ALLOC: Endpoint Memory Allocate
Writing a one to this bit will allocate the endpoint memory. The user should check the CFGOK bit to know whether the allocation
of this endpoint is correct.
Writing a zero to this bit will free the endpoint memory.
This bit is cleared upon receiving a USB reset (except for the endpoint 0).
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27.8.2.11 Endpoint n Status Register
Register Name: UESTAn, n in [0..7]
Access Type: Read-Only 0x0100
Offset: 0x0130 + (n * 0x04)
Reset Value: 0x00000100
31 30 29 28 27 26 25 24
- BYCT
23 22 21 20 19 18 17 16
BYCT - CFGOK CTRLDIR RWALL
15 14 13 12 11 10 9 8
CURRBK NBUSYBK - ERRORTRANS DTSEQ
7 6 5 4 3 2 1 0
SHORT STALLEDI/ NAKINI/ NAKOUTI/ RXSTPI/
OVERFI RXOUTI TXINI
PACKET CRCERRI HBISOFLUSHI HBISOINERRI UNDERFI
• BYCT: Byte Count
This field is set with the byte count of the FIFO.
For IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to
the host.
For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software
from the endpoint.
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
• CFGOK: Configuration OK Status
This bit is updated when the ALLOC bit is written to one.
This bit is set if the endpoint n number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal allowed
number of banks and size for this endpoint and to the maximal FIFO size (i.e. the DPRAM size).
If this bit is cleared, the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register.
• CTRLDIR: Control Direction
This bit is set after a SETUP packet to indicate that the following packet is an IN packet.
This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet.
Writing a zero or a one to this bit has no effect.
• RWALL: Read/Write Allowed
This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.
This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO.
This bit is never set if STALLRQ is one or in case of error.
This bit is cleared otherwise.
This bit shall not be used for control endpoints.
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• CURRBK: Current Bank
This bit is set for non-control endpoints, to indicate the current bank:
CURRBK Current Bank
0 0 Bank0
0 1 Bank1
1 0 Bank2 if supported (see Table 27-1 on page 624).
1 1 Reserved
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
• NBUSYBK: Number of Busy Banks
This field is set to indicate the number of busy banks:
NBUSYBK Number of Busy Banks
0 0 0 (all banks free)
0 1 1
1 0 2
1 1 3 if supported (see Table 27-1 on page 624).
For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this
triggers an EPnINT interrupt if NBUSYBKE is one.
For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this
triggers an EPnINT interrupt if NBUSYBKE is one.
When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or
three clock cycles later to calculate the address of the next bank.
An EPnINT interrupt is triggered if:
- for IN endpoint, NBUSYBKE is one and all the banks are free.
- for OUT endpoint, NBUSYBKE is one and all the banks are busy.
• ERRORTRANS: High-bandwidth isochronous OUT endpoint transaction error Interrupt
This bit is set when a transaction error occurs during the current micro-frame (the data toggle sequencing does not respect the
usb 2.0 standard). This triggers an EPnINT interrupt if ERRORTRANSE is one.
This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n=1,2 or 3) transferred during the
micro-frame. Shall be cleared by software by clearing (at least once) the FIFOCON bit to switch to the bank that belongs to the
next n-transactions (next micro-frame).
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
• DTSEQ: Data Toggle Sequence
This field is set to indicate the PID of the current bank:
DTSEQ Data Toggle Sequence
0 0 Data0
0 1 Data1
1 0 Data2 (for high-bandwidth isochronous endpoint)
1 1 MData (for high-bandwidth isochronous endpoint)
For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to the
current bank.
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For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence
should be Data0.
For High-bandwidth isochronous endpoint, an EPnINT interrupt is triggered if:
- MDATAE is one and a MData packet has been received (DTSEQ=MData and RXOUTI is one).
- DATAXE is one and a Data0/1/2 packet has been received (DTSEQ=Data0/1/2 and RXOUTI is one)
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
• SHORTPACKET: Short Packet Interrupt
This bit is set for non-control OUT endpoints, when a short packet has been received.
This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of
isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit and
the Automatic Switch (AUTOSW) bit are written to one.
This triggers an EPnINT interrupt if SHORTPACKETE is one.
This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt.
• STALLEDI: STALLed Interrupt
This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing a
one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one.
This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.
• CRCERRI: CRC Error Interrupt
This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the
bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one.
This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.
• OVERFI: Overflow Interrupt
This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the
packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first
bytes of the packet that fit in.
This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.
• NAKINI: NAKed IN Interrupt
This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT
interrupt if NAKINE is one.
This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.
• HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the micro-frame, if less than N
transaction has been completed by the USBB without underflow error. This may occur in case of a missing IN token. In this
case, the bank are flushed out to ensure the data synchronization between the host and the device. This triggers an EPnINT
interrupt if HBISOFLUSHE is one.
This bit is cleared when the HBISOFLUSHIC bit is written to one. This will acknowledge the interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
• NAKOUTI: NAKed OUT Interrupt
This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT
interrupt if NAKOUTE is one.
This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.
• HBISOINERRI: High bandwidth isochronous IN Underflow Error Interrupt
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the microframe, if less than N
bank was written by the cpu within this micro-frame. This triggers an EPnINT interrupt if HBISOINERRE is one.
This bit is cleared when the HBISOINERRIC bit is written to one. This will acknowledge the interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
• UNDERFI: Underflow Interrupt
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if
UNDERFE is one.
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An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then
automatically sent by the USBB.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not
fast enough. The packet is lost.
Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
• RXSTPI: Received SETUP Interrupt
This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers an EPnINT
interrupt if RXSTPE is one.
Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT endpoints.
• RXOUTI: Received OUT Data Interrupt
This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an
EPnINT interrupt if RXOUTE is one.
Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free the
bank.
This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full.
This triggers an EPnINT interrupt if RXOUTE is one.
Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge
the interrupt, what has no effect on the endpoint FIFO.
The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple
banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are set/cleared in accordance with the status of the
next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
• TXINI: Transmitted IN Data Interrupt
This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers an EPnINT interrupt
if TXINE is one.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet.
This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON when the current bank is free.
This triggers an EPnINT interrupt if TXINE is one.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the endpoint
FIFO.
The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the IN endpoint is
composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are set/cleared in accordance
with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.
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27.8.2.12 Endpoint n Status Clear Register
Register Name: UESTAnCLR, n in [0..7]
Access Type: Write-Only
Offset: 0x0160 + (n * 0x04)
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
SHORT STALLEDIC/ NAKINIC/ NAKOUTIC/ RXSTPIC/
OVERFIC RXOUTIC TXINIC
PACKETC CRCERRIC HBISOFLUSHIC HBISOINERRIC UNDERFIC
Writing a one to a bit in this register will clear the corresponding bit in UESTA.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.2.13 Endpoint n Status Set Register
Register Name: UESTAnSET, n in [0..7]
Access Type: Write-Only
Offset: 0x0190 + (n * 0x04)
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - NBUSYBKS - - -
7 6 5 4 3 2 1 0
SHORT STALLEDIS/ NAKINIS/ NAKOUTIS/ RXSTPIS/
OVERFIS RXOUTIS TXINIS
PACKETS CRCERRIS HBISOFLUSHIS HBISOINERRIS UNDERFIS
Writing a one to a bit in this register will set the corresponding bit in UESTA, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.2.14 Endpoint n Control Register
Register Name: UECONn, n in [0..7]
Access Type: Read-Only
Offset: 0x01C0 + (n * 0x04)
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - STALLRQ RSTDT NYETDIS EPDISHDMA
15 14 13 12 11 10 9 8
- FIFOCON KILLBK NBUSYBKE - ERRORTRANSE DATAXE MDATAE
7 6 5 4 3 2 1 0
SHORT STALLEDE/ NAKINE/ NAKOUTE/ RXSTPE/
OVERFE RXOUTE TXINE
PACKETE CRCERRE HBISOFLUSHE HBISOINERRE UNDERFE
• STALLRQ: STALL Request
This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host.
This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.
• RSTDT: Reset Data Toggle
This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle
sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.
This bit is cleared instantaneously.
The user does not have to wait for this bit to be cleared.
• NYETDIS: NYET token disable
This bit is set when the NYETDISS bit is written to one. This will send a ACK handshake instead of a NYET handshake in high-
speed mode.
This bit is cleared when the NYETDISC bit is written to one.This will let the USBB handling the high-speed handshake following
the usb 2.0 standard.
• EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable
This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transfer on any Endpoint n
interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE).
The user then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by writing a
one to the EPDISHDMAC bit) in order to complete the DMA transfer.
In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is
running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA
transfer will not start (not requested).
If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may
occur at any time and may immediately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a
DMA transfer by software after reception of a short packet, etc.
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• FIFOCON: FIFO Control
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read,
their value is always 0.
For IN endpoints:
This bit is set when the current bank is free, at the same time as TXINI.
This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
For OUT endpoints:
This bit is set when the current bank is full, at the same time as RXOUTI.
This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank.
• KILLBK: Kill IN Bank
This bit is set when the KILLBKS bit is written to one. This will kill the last written bank.
This bit is cleared by hardware after the completion of the “kill packet procedure”.
The user shall wait for this bit to be cleared before trying to process another IN packet.
Caution: The bank is cleared when the “kill packet” procedure is completed by the USBB core :
If the bank is really killed, the NBUSYBK field is decremented.
If the bank is not “killed” but sent (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case
can occur if at the same time an IN token is coming and the user wants to kill this bank.
Note : If two banks are ready to be sent, the above specific case can not occur, because the first bank is sent (IN transfer) while
the last bank is killed.
• NBUSYBKE: Number of Busy Banks Interrupt Enable
This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK).
This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt
(NBUSYBK).
• ERRORTRANSE: Transaction Error Interrupt Enable
This bit is set when the ERRORTRANSES bit is written to one. This will enable the transaction error interrupt (ERRORTRANS).
This bit is cleared when the ERRORTRANSEC bit is written to one. This will disable the transaction error interrupt
(ERRORTRANS).
• DATAXE: DataX Interrupt Enable
This bit is set when the DATAXES bit is written to one. This will enable the DATAX interrupt. (see DTSEQ bits)
This bit is cleared when the DATAXEC bit is written to one. This will disable the DATAX interrupt.
• MDATAE: MData Interrupt Enable
This bit is set when the MDATAES bit is written to one. This will enable the Multiple DATA interrupt. (see DTSEQ bits)
This bit is cleared when the MDATAEC bit is written to one. This will disable the Multiple DATA interrupt.
• SHORTPACKETE: Short Packet Interrupt Enable
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt
(SHORTPACKET).
• STALLEDE: STALLed Interrupt Enable
This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI).
This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI).
• CRCERRE: CRC Error Interrupt Enable
This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI).
This bit is cleared when the CRCERREC bit is written to one. This will disable the CRC Error interrupt (CRCERRI).
• OVERFE: Overflow Interrupt Enable
This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI).
This bit is cleared when the OVERFEC bit is written to one. This will disable the Overflow interrupt (OVERFI).
• NAKINE: NAKed IN Interrupt Enable
This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI).
This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI).
• HBISOFLUSHE: High Bandwidth Isochronous IN Flush Interrupt Enable
This bit is set when the HBISOFLUSHES bit is written to one. This will enable the HBISOFLUSHI interrupt.
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This bit is cleared when the HBISOFLUSHEC bit disable the HBISOFLUSHI interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
• NAKOUTE: NAKed OUT Interrupt Enable
This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI).
This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI).
• HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt Enable
This bit is set when the HBISOINERRES bit is written to one. This will enable the HBISOINERRI interrupt.
This bit is cleared when the HBISOINERREC bit disable the HBISOINERRI interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
• RXSTPE: Received SETUP Interrupt Enable
This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI).
This bit is cleared when the RXSTPEC bit is written to one. This will disable the Received SETUP interrupt (RXSTPI).
• UNDERFE: Underflow Interrupt Enable
This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI).
This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI).
• RXOUTE: Received OUT Data Interrupt Enable
This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT).
This bit is cleared when the RXOUTEC bit is written to one. This will disable the Received OUT Data interrupt (RXOUT).
• TXINE: Transmitted IN Data Interrupt Enable
This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interrupt (TXINI).
This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI).
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27.8.2.15 Endpoint n Control Clear Register
Register Name: UECONnCLR, n in [0..7]
Access Type: Write-Only
Offset: 0x0220 + (n * 0x04)
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - STALLRQC - NYETDISC EPDISHDMAC
15 14 13 12 11 10 9 8
- FIFOCONC - NBUSYBKEC - ERRORTRANSEC DATAXEC MDATEC
7 6 5 4 3 2 1 0
SHORT STALLEDEC/ NAKINEC/ NAKOUTEC/ RXSTPEC/
OVERFEC RXOUTEC TXINEC
PACKETEC CRCERREC HBISOFLUSHEC HBISOINERREC UNDERFEC
Writing a one to a bit in this register will clear the corresponding bit in UECONn.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.2.16 Endpoint n Control Set Register
Register Name: UECONnSET, n in [0..7]
Access Type: Write-Only
Offset: 0x01F0 + (n * 0x04)
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - STALLRQS RSTDTS NYETDISS EPDISHDMAS
15 14 13 12 11 10 9 8
- - KILLBKS NBUSYBKES - ERRORTRANSES DATAXES MDATES
7 6 5 4 3 2 1 0
SHORT STALLEDES/ NAKINES/ NAKOUTES/ RXSTPES/
OVERFES RXOUTES TXINES
PACKETES CRCERRES HBISOFLUSHES HBISOINERRES UNDERFES
Writing a one to a bit in this register will set the corresponding bit in UECONn.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.2.17 Device DMA Channel n Next Descriptor Address Register
Register Name: UDDMAnNEXTDESC, n in [1..7]
Access Type: Read/Write
Offset: 0x0310 + (n - 1) * 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
NXTDESCADDR[31:24]
23 22 21 20 19 18 17 16
NXTDESCADDR[23:16]
15 14 13 12 11 10 9 8
NXTDESCADDR[15:8]
7 6 5 4 3 2 1 0
NXTDESCADDR[7:4] - - - -
• NXTDESCADDR: Next Descriptor Address
This field contains the bits 31:4 of the 16-byte aligned address of the next channel descriptor to be processed.
This field is written either or by descriptor loading.
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27.8.2.18 Device DMA Channel n HSB Address Register
Register Name: UDDMAnADDR, n in [1..7]
Access Type: Read/Write
Offset: 0x0314 + (n - 1) * 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
HSBADDR[31:24]
23 22 21 20 19 18 17 16
HSBADDR[23:16]
15 14 13 12 11 10 9 8
HSBADDR[15:8]
7 6 5 4 3 2 1 0
HSBADDR[7:0]
• HSBADDR: HSB Address
This field determines the HSB bus current address of a channel transfer.
The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e.,
HSBADDR[1:0] is considered as 0b00 since only word accesses are performed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB access
byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written or loaded from the descriptor, whereas the channel end address is either determined by the
end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set.
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27.8.2.19 Device DMA Channel n Control Register
Register Name: UDDMAnCONTROL, n in [1..7]
Access Type: Read/Write
Offset: 0x0318 + (n - 1) * 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
CHBYTELENGTH[15:8]
23 22 21 20 19 18 17 16
CHBYTELENGTH[7:0]
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
BUFFCLOSE LDNXTCH
BURSTLOCKEN DESCLDIRQEN EOBUFFIRQEN EOTIRQEN DMAENDEN CHEN
INEN DESCEN
• CHBYTELENGTH: Channel Byte Length
This field determines the total number of bytes to be transferred for this buffer.
The maximum channel transfer size 64kB is reached when this field is zero (default value).
If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero.
This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is
ignored.
• BURSTLOCKEN: Burst Lock Enable
1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration.
0: The DMA never locks the HSB access.
• DESCLDIRQEN: Descriptor Loaded Interrupt Enable
1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system
bus.
0: The Descriptor Loaded interrupt is disabled.
• EOBUFFIRQEN: End of Buffer Interrupt Enable
1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero.
0: The end of buffer interrupt is disabled.
• EOTIRQEN: End of USB Transfer Interrupt Enable
1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set.
0: The end of usb OUT data transfer interrupt is disabled.
• DMAENDEN: End of DMA Buffer Output Enable
Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (but not a Zero Length Packet) will be sent to the USB line to properly closed the
usb transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.
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• BUFFCLOSEINEN: Buffer Close Input Enable
For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB
OUT data transfer (received short packet).
For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero.
For high-speed OUT isochronous, it may make sense. In that case, if BUFFCLOSEINEN is written to one, the current DMA
transfer is closed when the received PID packet is not MDATA.
Writing a zero to this bit to disable this feature.
• LDNXTCHDESCEN: Load Next Channel Descriptor Enable
1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDDMAnSTATUS.CHEN bit
is reset.
0: no channel register is loaded after the end of the channel transfer.
If the CHEN bit is written to zero, the next descriptor is immediately loaded upon transfer request (endpoint is free for IN
endpoint, or endpoint is full for OUT endpoint).
Table 27-6. DMA Channel Control Command Summary
LDNXTCHDES
CHEN
CEN Current Bank
0 0 stop now
0 1 Run and stop at end of buffer
1 0 Load next descriptor now
1 1 Run and link at end of buffer
• CHEN: Channel Enable
Writing this bit to zero will disabled the DMA channel and no transfer will occur upon request. If the LDNXTCHDESCEN bit is
written to zero, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both
UDDMAnSTATUS.CHEN and CHACTIVE bits are zero.
Writing this bit to one will set the UDDMAnSTATUS.CHEN bit and enable DMA channel data transfer. Then any pending request
will start the transfer. This may be used to start or resume any requested transfer.
This bit is cleared when the channel source bus is disabled at end of buffer. If the LDNXTCHDESCEN bit has been cleared by
descriptor loading, the user will have to write to one the corresponding CHEN bit to start the described transfer, if needed.
If a channel request is currently serviced when this bit is zero, the DMA FIFO buffer is drained until it is empty, then the
UDDMAnSTATUS.CHEN bit is cleared.
If the LDNXTCHDESCEN bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer
occurs) and the next descriptor is immediately loaded.
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27.8.2.20 Device DMA Channel n Status Register
Register Name: UDDMAnSTATUS, n in [1..7]
Access Type: Read/Write
Offset: 0x031C + (n - 1) * 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
CHBYTECNT[15:8]
23 22 21 20 19 18 17 16
CHBYTECNT[7:0]
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
DESCLD EOCHBUFF
- EOTSTA - - CHACTIVE CHEN
STA STA
• CHBYTECNT: Channel Byte Count
This field contains the current number of bytes still to be transferred for this buffer.
This field is decremented at each dma access.
This field is reliable (stable) only if the CHEN bit is zero.
• DESCLDSTA: Descriptor Loaded Status
This bit is set when a Descriptor has been loaded from the HSB bus.
This bit is cleared when read by the user.
• EOCHBUFFSTA: End of Channel Buffer Status
This bit is set when the Channel Byte Count counts down to zero.
This bit is automatically cleared when read by software.
• EOTSTA: End of USB Transfer Status
This bit is set when the completion of the usb data transfer has closed the dma transfer. It is valid only if
UDDMAnCONTROL.BUFFCLOSEINEN is one. Note that for OUT endpoint, if the UECFGn.AUTOSW is set, any received zero-
length-packet will be cancelled by the DMA, and the EOTSTA will be set whatever the UDDMAnCONTROL.CHEN bit is.
This bit is automatically cleared when read by software.
• CHACTIVE: Channel Active
0: the DMA channel is no longer trying to source the packet data.
1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a
packet transfer cannot be completed due to an EOCHBUFFSTA, this bit stays set during the next channel descriptor load (if any)
and potentially until USB packet transfer completion, if allowed by the new descriptor.
When programming a DMA by descriptor (Load next descriptor now), the CHACTIVE bit is set only once the DMA is running
(the endpoint is free for IN transaction, the endpoint is full for OUT transaction).
• CHEN: Channel Enabled
This bit is set (after one cycle latency) when the L.CHEN is written to one or when the descriptor is loaded.
This bit is cleared when any transfer is ended either due to an elapsed byte count or a USB device initiated transfer end.
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0: the DMA channel no longer transfers data, and may load the next descriptor if the UDDMAnCONTROL.LDNXTCHDESCEN
bit is zero.
1: the DMA channel is currently enabled and transfers data upon request.
If a channel request is currently serviced when the UDDMAnCONTROL.CHEN bit is written to zero, the DMA FIFO buffer is
drained until it is empty, then this status bit is cleared.
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27.8.3 USB Host Registers
27.8.3.1 Host General Control Register
Register Name: UHCON
Access Type: Read/Write
Offset: 0x0400
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - SPDCONF - RESUME RESET SOFE
7 6 5 4 3 2 1 0
- - - - - - - -
• SPDCONF: Speed Configuration
This field contains the host speed capability.
SPDCONF Speed
Normal mode: the host start in full-speed mode and perform a high-speed reset to switch to
0 0
the high-speed mode if the downstream peripheral is high-speed capable.
0 1 reserved, do not use this configuration
1 0 reserved, do not use this configuration
1 1 Full-speed: the host remains to full-speed mode whatever is the peripheral speed capability.
• RESUME: Send USB Resume
Writing a one to this bit will generate a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
Writing a zero to this bit has no effect.
This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one).
• RESET: Send USB Reset
Writing a one to this bit will generate a USB Reset on the USB bus.
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset
is being sent.
• SOFE: Start of Frame Generation Enable
Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode.
Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.RXRSMI).
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27.8.3.2 Host Global Interrupt Register
Register Name: UHINT
Access Type: Read-Only
Offset: 0x0404
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INT DMA6INT DMA5INT DMA4INT DMA3INT DMA2INT DMA1INT -
23 22 21 20 19 18 17 16
- - - - - - -
15 14 13 12 11 10 9 8
P7INT P6INT P5INT P4INT P3INT P2INT P1INT P0INT
7 6 5 4 3 2 1 0
- HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI
• DMAnINT: DMA Channel n Interrupt
This bit is set when an interrupt is triggered by the DMA channel n. This triggers a USB interrupt if the corresponding
DMAnINTE is one (UHINTE register).
This bit is cleared when the UHDMAnSTATUS interrupt source is cleared.
• PnINT: Pipe n Interrupt
This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe
interrupt enable bit is one (UHINTE register).
This bit is cleared when the interrupt source is served.
• HWUPI: Host Wake-Up Interrupt
This bit is set when the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is
detected.
This bit is set when the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected.
This bit is set when the host controller is in the Idle state (USBSTA.VBUSRQ is zero, no VBus is generated).
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
• HSOFI: Host Start of Frame Interrupt
This bit is set when a SOF is issued by the Host controller. This triggers a USB interrupt when HSOFE is one. When using the
host controller in low speed mode, this bit is also set when a keep-alive is sent.
This bit is cleared when the HSOFIC bit is written to one.
• RXRSMI: Upstream Resume Received Interrupt
This bit is set when an Upstream Resume has been received from the Device.
This bit is cleared when the RXRSMIC is written to one.
• RSMEDI: Downstream Resume Sent Interrupt
This bit set when a Downstream Resume has been sent to the Device.
This bit is cleared when the RSMEDIC bit is written to one.
• RSTI: USB Reset Sent Interrupt
This bit is set when a USB Reset has been sent to the device.
This bit is cleared when the RSTIC bit is written to one.
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• DDISCI: Device Disconnection Interrupt
This bit is set when the device has been removed from the USB bus.
This bit is cleared when the DDISCIC bit is written to one.
• DCONNI: Device Connection Interrupt
This bit is set when a new device has been connected to the USB bus.
This bit is cleared when the DCONNIC bit is written to one.
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27.8.3.3 Host Global Interrupt Clear Register
Register Name: UHINTCLR
Access Type: Write-Only
Offset: 0x0408
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- HWUPIC HSOFIC RXRSMIC RSMEDIC RSTIC DDISCIC DCONNIC
Writing a one to a bit in this register will clear the corresponding bit in UHINT.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.3.4 Host Global Interrupt Set Register
Register Name: UHINTSET
Access Type: Write-Only
Offset: 0x040C
Read Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INTS DMA6INTS DMA5INTS DMA4INTS DMA3INTS DMA2INTS DMA1INTS -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- HWUPIS HSOFIS RXRSMIS RSMEDIS RSTIS DDISCIS DCONNIS
Writing a one to a bit in this register will set the corresponding bit in UHINT, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.3.5 Host Global Interrupt Enable Register
Register Name: UHINTE
Access Type: Read-Only
Offset: 0x0410
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INTE DMA6INTE DMA5INTE DMA4INTE DMA3INTE DMA2INTE DMA1INTE -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
P7INTE P6INTE P5INTE P4INTE P3INTE P2INTE P1INTE P0INTE
7 6 5 4 3 2 1 0
- HWUPIE HSOFIE RXRSMIE RSMEDIE RSTIE DDISCIE DCONNIE
• DMAnINTE: DMA Channel n Interrupt Enable
This bit is set when the DMAnINTES bit is written to one. This will enable the DMA Channel n Interrupt (DMAnINT).
This bit is cleared when the DMAnINTEC bit is written to one. This will disable the DMA Channel n Interrupt (DMAnINT).
• PnINTE: Pipe n Interrupt Enable
This bit is set when the PnINTES bit is written to one. This will enable the Pipe n Interrupt (PnINT).
This bit is cleared when the PnINTEC bit is written to one. This will disable the Pipe n Interrupt (PnINT).
• HWUPIE: Host Wake-Up Interrupt Enable
This bit is set when the HWUPIES bit is written to one. This will enable the Host Wake-up Interrupt (HWUPI).
This bit is cleared when the HWUPIEC bit is written to one. This will disable the Host Wake-up Interrupt (HWUPI).
• HSOFIE: Host Start of Frame Interrupt Enable
This bit is set when the HSOFIES bit is written to one. This will enable the Host Start of Frame interrupt (HSOFI).
This bit is cleared when the HSOFIEC bit is written to one. This will disable the Host Start of Frame interrupt (HSOFI).
• RXRSMIE: Upstream Resume Received Interrupt Enable
This bit is set when the RXRSMIES bit is written to one. This will enable the Upstream Resume Received interrupt (RXRSMI).
This bit is cleared when the RXRSMIEC bit is written to one. This will disable the Downstream Resume interrupt (RXRSMI).
• RSMEDIE: Downstream Resume Sent Interrupt Enable
This bit is set when the RSMEDIES bit is written to one. This will enable the Downstream Resume interrupt (RSMEDI).
This bit is cleared when the RSMEDIEC bit is written to one. This will disable the Downstream Resume interrupt (RSMEDI).
• RSTIE: USB Reset Sent Interrupt Enable
This bit is set when the RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (RSTI).
This bit is cleared when the RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (RSTI).
• DDISCIE: Device Disconnection Interrupt Enable
This bit is set when the DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (DDISCI).
This bit is cleared when the DDISCIEC bit is written to one. This will disable the Device Disconnection interrupt (DDISCI).
• DCONNIE: Device Connection Interrupt Enable
This bit is set when the DCONNIES bit is written to one. This will enable the Device Connection interrupt (DCONNI).
This bit is cleared when the DCONNIEC bit is written to one. This will disable the Device Connection interrupt (DCONNI).
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27.8.3.6 Host Global Interrupt Enable Clear Register
Register Name: UHINTECLR
Access Type: Write-Only
Offset: 0x0414
Read Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INTEC DMA6INTEC DMA5INTEC DMA4INTEC DMA3INTEC DMA2INTEC DMA1INTEC -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
P7INTEC P6INTEC P5INTEC P4INTEC P3INTEC P2INTEC P1INTEC P0INTEC
7 6 5 4 3 2 1 0
- HWUPIEC HSOFIEC RXRSMIEC RSMEDIEC RSTIEC DDISCIEC DCONNIEC
Writing a one to a bit in this register will clear the corresponding bit in UHINTE.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.3.7 Host Global Interrupt Enable Set Register
Register Name: UHINTESET
Access Type: Write-Only
Offset: 0x0418
Read Value: 0x00000000
31 30 29 28 27 26 25 24
DMA7INTES DMA6INTES DMA5INTES DMA4INTES DMA3INTES DMA2INTES DMA1INTES -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
P7INTES P6INTES P5INTES P4INTES P3INTES P2INTES P1INTES P0INTES
7 6 5 4 3 2 1 0
- HWUPIES HSOFIES RXRSMIES RSMEDIES RSTIES DDISCIES DCONNIES
Writing a one to a bit in this register will set the corresponding bit in UHINT.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.3.8 Host Frame Number Register
Register Name: UHFNUM
Access Type: Read/Write
Offset: 0x0420
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
FLENHIGH
15 14 13 12 11 10 9 8
- - FNUM[10:5]
7 6 5 4 3 2 1 0
FNUM[4:0] MFNUM
• FLENHIGH: Frame Length
In Full speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is
30000 to ensure a SOF generation every 1 ms).
In High speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is
3750 to ensure a SOF generation every 125 us).
• FNUM: Frame Number
This field contains the current SOF number.
This field can be written. In this case, the MFNUM field is reset to zero.
• MFNUM: Micro Frame Number
This field contains the current Micro Frame number (can vary from 0 to 7) updated every 125us.
When operating in full-speed mode, this field is tied to zero.
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27.8.3.9 Host Address 1 Register
Register Name: UHADDR1
Access Type: Read/Write
Offset: 0x0424
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- UHADDRP3
23 22 21 20 19 18 17 16
- UHADDRP2
15 14 13 12 11 10 9 8
- UHADDRP1
7 6 5 4 3 2 1 0
- UHADDRP0
• UHADDRP3: USB Host Address
This field contains the address of the Pipe3 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP2: USB Host Address
This field contains the address of the Pipe2 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP1: USB Host Address
This field contains the address of the Pipe1 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP0: USB Host Address
This field contains the address of the Pipe0 of the USB Device.
This field is cleared when a USB reset is requested.
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27.8.3.10 Host Address 2 Register
Register Name: UHADDR2
Access Type: Read/Write
Offset: 0x0428
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- UHADDRP7
23 22 21 20 19 18 17 16
- UHADDRP6
15 14 13 12 11 10 9 8
- UHADDRP5
7 6 5 4 3 2 1 0
- UHADDRP4
• UHADDRP7: USB Host Address
This field contains the address of the Pipe7 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP6: USB Host Address
This field contains the address of the Pipe6 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP5: USB Host Address
This field contains the address of the Pipe5 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP4: USB Host Address
This field contains the address of the Pipe4 of the USB Device.
This field is cleared when a USB reset is requested.
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27.8.3.11 Pipe Enable/Reset Register
Register Name: UPRST
Access Type: Read/Write
Offset: 0x0041C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
PRST7 PRST6 PRST5 PRST4 PRST3 PRST2 PRST1 PRST0
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
• PRSTn: Pipe n Reset
Writing a one to this bit will reset the Pipe n FIFO.
This resets the endpoint n registers (UPCFGn, UPSTAn, UPCONn) but not the endpoint configuration (ALLOC, PBK, PSIZE,
PTOKEN, PTYPE, PEPNUM, INTFRQ).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management.
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and allow to start using the FIFO.
• PENn: Pipe n Enable
Writing a one to this bit will enable the Pipe n.
Writing a zero to this bit will disable the Pipe n, what forces the Pipe n state to inactive and resets the pipe n registers (UPCFGn,
UPSTAn, UPCONn) but not the pipe configuration (ALLOC, PBK, PSIZE).
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27.8.3.12 Pipe n Configuration Register
Register Name: UPCFGn, n in [0..7]
Access Type: Read/Write
Offset: 0x0500 + (n * 0x04)
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
INTFRQ/BINTERVAL
23 22 21 20 19 18 17 16
- - - PINGEN PEPNUM
15 14 13 12 11 10 9 8
- - PTYPE - AUTOSW PTOKEN
7 6 5 4 3 2 1 0
- PSIZE PBK ALLOC -
• INTFRQ: Pipe Interrupt Request Frequency
This field contains the maximum value in millisecond of the polling period for an Interrupt Pipe.
This value has no effect for a non-Interrupt Pipe.
This field is cleared upon sending a USB reset.
• BINTERVAL: bInterval parameter for the Bulk-Out/Ping transaction
This field contains the Ping/Bulk-out period.
If BINTERVAL>0 and PINGEN=1, one PING token is sent every BINTERVAL micro-frame until it is ACKed by the peripheral.
If BINTERVAL=0 and PINGEN=1, multiple consecutive PING token is sent in the same micro-frame until it is ACKed.
If BINTERVAL>0 and PINGEN=0, one OUT token is sent every BINTERVAL micro-frame until it is ACKed by the peripheral.
If BINTERVAL=0 and PINGEN=0, multiple consecutive OUT token is sent in the same micro-frame until it is ACKed.
This value must be in the range from 0 to 255.
• PINGEN: Ping Enable
This bit is relevant for High-speed Bulk-out transaction only (including the control data stage and the control status stage).
Writing a zero to this bit will disable the ping protocol.
Writing a one to this bit will enable the ping mechanism according to the usb 2.0 standard.
This bit is cleared upon sending a USB reset.
• PEPNUM: Pipe Endpoint Number
This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 15.
This field is cleared upon sending a USB reset.
• PTYPE: Pipe Type
This field contains the pipe type.
PTYPE Pipe Type
0 0 Control
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PTYPE Pipe Type
0 1 Isochronous
1 0 Bulk
1 1 Interrupt
This field is cleared upon sending a USB reset.
• AUTOSW: Automatic Switch
This bit is cleared upon sending a USB reset.
1: The automatic bank switching is enabled.
0: The automatic bank switching is disabled.
• PTOKEN: Pipe Token
This field contains the endpoint token.
PTOKEN Endpoint Direction
00 SETUP
01 IN
10 OUT
11 reserved
• PSIZE: Pipe Size
This field contains the size of each pipe bank.
PSIZE Endpoint Size
0 0 0 8 bytes
0 0 1 16 bytes
0 1 0 32 bytes
0 1 1 64 bytes
1 0 0 128 bytes
1 0 1 256 bytes
1 1 0 512 bytes
1 1 1 1024 bytes
This field is cleared upon sending a USB reset.
• PBK: Pipe Banks
This field contains the number of banks for the pipe.
PBK Endpoint Banks
0 0 1 (single-bank pipe)
0 1 2 (double-bank pipe)
1 0 3 (triple-bank pipe) if supported (see Table 27-1 on page 624).
1 1 Reserved
For control endpoints, a single-bank pipe (0b00) should be selected.
This field is cleared upon sending a USB reset.
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• ALLOC: Pipe Memory Allocate
Writing a one to this bit will allocate the pipe memory.
Writing a zero to this bit will free the pipe memory.
This bit is cleared when a USB Reset is requested.
Refer to the DPRAM Management chapter for more details.
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27.8.3.13 Pipe n Status Register
Register Name: UPSTAn, n in [0..7]
Access Type: Read-Only
Offset: 0x0530 + (n * 0x04)
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- PBYCT[10:4]
23 22 21 20 19 18 17 16
PBYCT[3:0] - CFGOK - RWALL
15 14 13 12 11 10 9 8
CURRBK NBUSYBK - - DTSEQ
7 6 5 4 3 2 1 0
SHORT RXSTALLDI/ TXSTPI/
OVERFI NAKEDI PERRI TXOUTI RXINI
PACKETI CRCERRI UNDERFI
• PBYCT: Pipe Byte Count
This field contains the byte count of the FIFO.
For OUT pipe, incremented after each byte written by the user into the pipe and decremented after each byte sent to the
peripheral.
For IN pipe, incremented after each byte received from the peripheral and decremented after each byte read by the user from
the pipe.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
• CFGOK: Configuration OK Status
This bit is set/cleared when the UPCFGn.ALLOC bit is set.
This bit is set if the pipe n number of banks (UPCFGn.PBK) and size (UPCFGn.PSIZE) are correct compared to the maximal
allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values ot the PBK and PSIZE field in the UPCFGn register.
• RWALL: Read/Write Allowed
For OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO.
This bit is cleared otherwise.
This bit is also cleared when the RXSTALL or the PERR bit is one.
• CURRBK: Current Bank
For non-control pipe, this field indicates the number of the current bank.
CURRBK Current Bank
0 0 Bank0
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CURRBK Current Bank
0 1 Bank1
1 0 Bank2 if supported (see Table 27-1 on page 624).
1 1 Reserved
This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit.
• NBUSYBK: Number of Busy Banks
This field indicates the number of busy bank.
For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are
busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this
triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
NBUSYBK Number of busy bank
0 0 All banks are free.
0 1 1 busy bank
1 0 2 busy banks if supported (see Table 27-1 on page 624).
1 1 reserved
• DTSEQ: Data Toggle Sequence
This field indicates the data PID of the current bank.
DTSEQ Data toggle sequence
0 0 Data0
0 1 Data1
1 0 reserved
1 1 reserved
For OUT pipe, this field indicates the data toggle of the next packet that will be sent.
For IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
• SHORTPACKETI: Short Packet Interrupt
This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).
This bit is cleared when the SHORTPACKETIC bit is written to one.
• RXSTALLDI: Received STALLed Interrupt
This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.
This bit is cleared when the RXSTALLDIC bit is written to one.
• CRCERRI: CRC Error Interrupt
This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if
the TXSTPE bit is one.
This bit is cleared when the CRCERRIC bit is written to one.
• OVERFI: Overflow Interrupt
This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is
triggered if the OVERFIE bit is one.
This bit is cleared when the OVERFIC bit is written to one.
• NAKEDI: NAKed Interrupt
This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.
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This bit is cleared when the NAKEDIC bit written to one.
• PERRI: Pipe Error Interrupt
This bit is set when an error occurs on the current bank of the pipe. This triggers an interrupt if the PERRE bit is set. Refers to
the UPERRn register to determine the source of the error.
This bit is cleared when the error source bit is cleared.
• TXSTPI: Transmitted SETUP Interrupt
This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the
TXSTPE bit is one.
This bit is cleared when the TXSTPIC bit is written to one.
• UNDERFI: Underflow Interrupt
This bit is set, for isochronous and Interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the UNDERFIE
bit is one.
This bit is set, for Isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe. (the pipe can’t
send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) will be sent instead of.
This bit is set, for Isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe. i.e, the current bank
of the pipe is not free whereas a new IN USB packet is received. This packet is not stored in the bank. For Interrupt pipe, the
overflowed packet is ACKed to respect the USB standard.
This bit is cleared when the UNDERFIEC bit is written to one.
• TXOUTI: Transmitted OUT Data Interrupt
This bit is set when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is one.
This bit is cleared when the TXOUTIC bit is written to one.
• RXINI: Received IN Data Interrupt
This bit is set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the RXINE bit is
one.
This bit is cleared when the RXINIC bit is written to one.
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27.8.3.14 Pipe n Status Clear Register
Register Name: UPSTAnCLR, n in [0..7]
Access Type: Write-Only
Offset: 0x0560 + (n * 0x04)
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
RXSTALLDI
SHORT TXSTPIC/
C/ OVERFIC NAKEDIC - TXOUTIC RXINIC
PACKETIC UNDERFIC
CRCERRIC
Writing a one to a bit in this register will clear the corresponding bit in UPSTAn.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.3.15 Pipe n Status Set Register
Register Name: UPSTAnSET, n in [0..7]
Access Type: Write-Only
Offset: 0x0590 + (n * 0x04)
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - NBUSYBKS - - - -
7 6 5 4 3 2 1 0
SHORT RXSTALLDIS/ TXSTPIS/
OVERFIS NAKEDIS PERRIS TXOUTIS RXINIS
PACKETIS CRCERRIS UNDERFIS
Writing a one to a bit in this register will set the corresponding bit in UPSTAn, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.3.16 Pipe n Control Register
Register Name: UPCONn, n in [0..7]
Access Type: Read-Only
Offset: 0x05C0 + (n * 0x04)
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - RSTDT PFREEZE PDISHDMA
15 14 13 12 11 10 9 8
- FIFOCON - NBUSYBKE - - - -
7 6 5 4 3 2 1 0
SHORT RXSTALLDE/ TXSTPE/
OVERFIE NAKEDE PERRE TXOUTE RXINE
PACKETIE CRCERRE UNDERFIE
• RSTDT: Reset Data Toggle
This bit is set when the RSTDTS bit is written to one. This will reset the Data Toggle to its initial value for the current Pipe.
This bit is cleared when proceed.
• PFREEZE: Pipe Freeze
This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has
been received on this Pipe or when an error occurs on the Pipe (PERR is one) or when (INRQ+1) In requests have been
processed or when after a Pipe reset (UPRST.PRSTn rising) or a Pipe Enable (UPRST.PEN rising). This will Freeze the Pipe
requests generation.
This bit is cleared when the PFREEZEC bit is written to one. This will enable the Pipe request generation.
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
See the UECONn.EPDISHDMA bit description.
• FIFOCON: FIFO Control
For OUT and SETUP Pipe:
This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI.
This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank.
For IN Pipe:
This bit is set when a new IN message is stored in the current bank, at the same time than RXINI.
This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank.
• NBUSYBKE: Number of Busy Banks Interrupt Enable
This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interrupt (NBUSYBKE).
• SHORTPACKETIE: Short Packet Interrupt Enable
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Transmitted IN Data IT (SHORTPACKETIE).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Transmitted IN Data IT
(SHORTPACKETE).
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• RXSTALLDE: Received STALLed Interrupt Enable
This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interrupt (RXSTALLDE).
This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitted IN Data interrupt
(RXSTALLDE).
• CRCERRE: CRC Error Interrupt Enable
This bit is set when the CRCERRES bit is written to one. This will enable the Transmitted IN Data interrupt (CRCERRE).
This bit is cleared when the CRCERREC bit is written to one. This will disable the Transmitted IN Data interrupt (CRCERRE).
• OVERFIE: Overflow Interrupt Enable
This bit is set when the OVERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (OVERFIE).
This bit is cleared when the OVERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (OVERFIE).
• NAKEDE: NAKed Interrupt Enable
This bit is set when the NAKEDES bit is written to one. This will enable the Transmitted IN Data interrupt (NAKEDE).
This bit is cleared when the NAKEDEC bit is written to one. This will disable the Transmitted IN Data interrupt (NAKEDE).
• PERRE: Pipe Error Interrupt Enable
This bit is set when the PERRES bit is written to one. This will enable the Transmitted IN Data interrupt (PERRE).
This bit is cleared when the PERREC bit is written to one. This will disable the Transmitted IN Data interrupt (PERRE).
• TXSTPE: Transmitted SETUP Interrupt Enable
This bit is set when the TXSTPES bit is written to one. This will enable the Transmitted IN Data interrupt (TXSTPE).
This bit is cleared when the TXSTPEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXSTPE).
• UNDERFIE: Underflow Interrupt Enable
This bit is set when the UNDERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (UNDERFIE).
This bit is cleared when the UNDERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (UNDERFIE).
• TXOUTE: Transmitted OUT Data Interrupt Enable
This bit is set when the TXOUTES bit is written to one. This will enable the Transmitted IN Data interrupt (TXOUTE).
This bit is cleared when the TXOUTEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXOUTE).
• RXINE: Received IN Data Interrupt Enable
This bit is set when the RXINES bit is written to one. This will enable the Transmitted IN Data interrupt (RXINE).
This bit is cleared when the RXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXINE).
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27.8.3.17 Pipe n Control Clear Register
Register Name: UPCONnCLR, n in [0..7]
Access Type: Write-Only
Offset: 0x0620 + (n * 0x04)
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - PFREEZEC PDISHDMAC
15 14 13 12 11 10 9 8
- FIFOCONC - NBUSYBKEC - - - -
7 6 5 4 3 2 1 0
SHORT RXSTALLDEC/ TXSTPEC/
OVERFIEC NAKEDEC PERREC TXOUTEC RXINEC
PACKETIEC CRCERREC UNDERFIEC
Writing a one to a bit in this register will clear the corresponding bit in UPCONn.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.3.18 Pipe n Control Set Register
Register Name: UPCONnSET, n in [0..7]
Access Type: Write-Only
Offset: 0x05F0 + (n * 0x04)
Read Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - RSTDTS PFREEZES PDISHDMAS
15 14 13 12 11 10 9 8
- - - NBUSYBKES - - - -
7 6 5 4 3 2 1 0
SHORT RXSTALLDES/ TXSTPES/
OVERFIES NAKEDES PERRES TXOUTES RXINES
PACKETIES CRCERRES UNDERFIES
Writing a one to a bit in this register will set the corresponding bit in UPCONn.
Writing a zero to a bit in this register has no effect.
This bit always reads as zero.
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27.8.3.19 Pipe n IN Request Register
Register Name: UPINRQn, n in [0..7]
Access Type: Read/Write
Offset: 0x0650 + (n * 0x04)
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - INMODE
7 6 5 4 3 2 1 0
INRQ
• INMODE: IN Request Mode
Writing a one to this bit will allow the USBB to perform infinite IN requests when the Pipe is not frozen.
Writing a zero to this bit will perform a pre-defined number of IN requests. This number is the INRQ field.
• INRQ: IN Request Number before Freeze
This field contains the number of IN transactions before the USBB freezes the pipe. The USBB will perform (INRQ+1) IN
requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully
performed.
This register has no effect when the INMODE bit is one (infinite IN requests generation till the pipe is not frozen).
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27.8.3.20 Pipe n Error Register
Register Name: UPERRn, n in [0..7]
Access Type: Read/Write
Offset: 0x0680 + (n * 0x04)
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- COUNTER CRC16 TIMEOUT PID DATAPID DATATGL
• COUNTER: Error Counter
This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL).
This field is cleared when receiving a good usb packet without any error.
When this field reaches 3 (i.e., 3 consecutive errors), this pipe is automatically frozen (UPCONn.PFREEZE is set).
Writing 0b00 to this field will clear the counter.
• CRC16: CRC16 Error
This bit is set when a CRC16 error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
• TIMEOUT: Time-Out Error
This bit is set when a Time-Out error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
• PID: PID Error
This bit is set when a PID error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
• DATAPID: Data PID Error
This bit is set when a Data PID error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
• DATATGL: Data Toggle Error
This bit is set when a Data Toggle error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
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27.8.3.21 Host DMA Channel n Next Descriptor Address Register
Register Name: UHDMAnNEXTDESC, n in [1..7]
Access Type: Read/Write
Offset: 0x0710 + (n - 1) * 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
NXTDESCADDR[31:24]
23 22 21 20 19 18 17 16
NXTDESCADDR[23:16]
15 14 13 12 11 10 9 8
NXTDESCADDR[15:8]
7 6 5 4 3 2 1 0
NXTDESCADDR[7:4] - - - -
Same as Section 27.8.2.17.
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27.8.3.22 Host DMA Channel n HSB Address Register
Register Name: UHDMAnADDR, n in [1..7]
Access Type: Read/Write
Offset: 0x0714 + (n - 1) * 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
HSBADDR[31:24]
23 22 21 20 19 18 17 16
HSBADDR[23:16]
15 14 13 12 11 10 9 8
HSBADDR[15:8]
7 6 5 4 3 2 1 0
HSBADDR[7:0]
Same as Section 27.8.2.18.
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27.8.3.23 USB Host DMA Channel n Control Register
Register Name: UHDMAnCONTROL, n in [1..7]
Access Type: Read/Write
Offset: 0x0718 + (n - 1) * 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
CHBYTELENGTH[15:8]
23 22 21 20 19 18 17 16
CHBYTELENGTH[7:0]
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
BURSTLOC DESCLD EOBUFF BUFFCLOSE LDNXTCHD
EOTIRQEN DMAENDEN CHEN
KEN IRQEN IRQEN INEN ESCEN
Same as Section 27.8.2.19.
(just replace the IN endpoint term by OUT endpoint, and vice-versa)
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27.8.3.24 USB Host DMA Channel n Status Register
Register Name: UHDMAnSTATUS, n in [1..7]
Access Type: Read/Write
Offset: 0x071C + (n - 1) * 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
CHBYTECNT[15:8]
23 22 21 20 19 18 17 16
CHBYTECNT[7:0]
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- DESCLD EOCHBUFFS EOTSTA - - CHACTIVE CHEN
STA TA
Same as Section 27.8.2.20.
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27.8.4 USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)
The application has access to the physical DPRAM reserved for the Endpoint/Pipe through a
64KB virtual address space. The application can access anywhere in the virtual 64KB segment
(linearly or fixedly) as the DPRAM Fifo address increment is fully handled by hardware. Byte,
half-word and word access are supported. Data should be access in a big-endian way.
For instance, if the application wants to write into the Endpoint/Pipe3, it can access anywhere in
the USBFIFO3DATA HSB segment address. i.e : an access to the 0x30000 offset, is strictly
equivalent to an access to the 0x3FFFC offset.
Note that the virtual address space size (64KB) has nothing to do with the Endpoint/Pipe size.
Disabling the USBB (by writing a zero to the USBE bit) does not reset the DPRAM.
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27.9 Module Configuration
The specific configuration for the USBB instance is listed in the following tables. The module bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
chapter for details.
Table 27-7. Module Clock Name
Module name Clock name Clock name
USBB CLK_USBB_HSB CLK_USBB_PB
Table 27-8. Register Reset Values
Register Reset Value
UVERS 0x00000320
UFEATURES 0x00014478
UADDRSIZE 0x00001000
UNAME1 0x48555342
UNAME2 0x004F5447
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28. Timer/Counter (TC)
Rev: 2.2.3.3
28.1 Features
• Three 16-bit Timer Counter channels
• A wide range of functions including:
– Frequency measurement
– Event counting
– Interval measurement
– Pulse generation
– Delay timing
– Pulse width modulation
– Up/down capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Internal interrupt signal
• Two global registers that act on all three TC channels
28.2 Overview
The Timer Counter (TC) includes three identical 16-bit Timer Counter channels.
Each channel can be independently programmed to perform a wide range of functions including
frequency measurement, event counting, interval measurement, pulse generation, delay timing,
and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs, and two multi-purpose
input/output signals which can be configured by the user. Each channel drives an internal inter-
rupt signal which can be programmed to generate processor interrupts.
The TC block has two global registers which act upon all three TC channels.
The Block Control Register (BCR) allows the three channels to be started simultaneously with
the same instruction.
The Block Mode Register (BMR) defines the external clock inputs for each channel, allowing
them to be chained.
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28.3 Block Diagram
Figure 28-1. TC Block Diagram
I/O
TIMER_CLOCK1 Contr oller
CLK0
TCLK0
CLK1
TIMER_CLOCK2
TIOA1 CLK2
TIMER_CLOCK3 TIOA2 XC0 Timer/Counter
TIOA
Channel 0 A0
TCLK1 XC1 TIOA0
TIMER_CLOCK4 TIOB B0
TCLK2 XC2 TIOB0
TIMER_CLOCK5 TC0XC0S SYNC INT0
TCLK0
TCLK1 XC0
Timer/Counter TIOA
XC1 Channel 1 A1
TIOA0 TIOA1
TIOB B1
TIOA2 XC2 TIOB1
TCLK2 SYNC INT1
TC1XC1S
TCLK0 XC0 Timer/Counter TIOA
Channel 2 A2
TCLK1 XC1 TIOA2
TIOB B2
TCLK2 XC2 TIOB2
TIOA0
SYNC INT2
TC2XC2S
TIOA1
Timer Count er
Interrupt
Controller
28.4 I/O Lines Description
Table 28-1. I/O Lines Description
Pin Name Description Type
CLK0-CLK2 External Clock Input Input
A0-A2 I/O Line A Input/Output
B0-B2 I/O Line B Input/Output
28.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
28.5.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.
The user must first program the I/O Controller to assign the TC pins to their peripheral functions.
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28.5.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning
and resume operation after the system wakes up from sleep mode.
28.5.3 Clocks
The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
TC before disabling the clock, to avoid freezing the TC in an undefined state.
28.5.4 Interrupts
The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt
requires the interrupt controller to be programmed first.
28.5.5 Debug Operation
The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps
peripherals running in debug operation.
28.6 Functional Description
28.6.1 TC Description
The three channels of the Timer Counter are independent and identical in operation. The regis-
ters for channel programming are listed in Figure 28-3 on page 766.
28.6.1.1 Channel I/O Signals
As described in Figure 28-1 on page 750, each Channel has the following I/O signals.
Table 28-2. Channel I/O Signals Description
Block/Channel Signal Name Description
XC0, XC1, XC2 External Clock Inputs
Capture mode: Timer Counter Input
TIOA
Waveform mode: Timer Counter Output
Channel Signal Capture mode: Timer Counter Input
TIOB
Waveform mode: Timer Counter Input/Output
INT Interrupt Signal Output
SYNC Synchronization Input Signal
28.6.1.2 16-bit counter
Each channel is organized around a 16-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Sta-
tus Register (SRn.COVFS) is set.
The current value of the counter is accessible in real time by reading the Channel n Counter
Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value
passes to 0x0000 on the next valid edge of the selected clock.
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28.6.1.3 Clock selection
At block level, input clock signals of each channel can either be connected to the external inputs
TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for
chaining by writing to the BMR register. See Figure 28-2 on page 752.
Each channel can independently select an internal or external clock source for its counter:
• Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,
TIMER_CLOCK4, TIMER_CLOCK5. See the Module Configuration Chapter for details about
the connection of these clock sources.
• External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details
about the connection of these clock sources.
This selection is made by the Clock Selection field in the Channel n Mode Register
(CMRn.TCCLKS).
The selected clock can be inverted with the Clock Invert bit in CMRn (CMRn.CLKI). This allows
counting on the opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The Burst
Signal Selection field in the CMRn register (CMRn.BURST) defines this signal.
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the
CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC.
Figure 28-2. Clock Selection
TCCLKS
TIMER_CLOCK1
TIMER_CLOCK2 CLKI
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5 Selected
XC0 Clock
XC1
XC2
BURST
28.6.1.4 Clock control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See Figure 28-3 on page 753.
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• The clock can be enabled or disabled by the user by writing to the Counter Clock
Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and
CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock
Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode,
it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare
bit in CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions
have no effect: only a CLKEN command in CCRn can re-enable the clock. When the clock is
enabled, the Clock Enabling Status bit is set in SRn (SRn.CLKSTA).
• The clock can also be started or stopped: a trigger (software, synchro, external or compare)
always starts the clock. In Capture mode the clock can be stopped by an RB load event if the
Counter Clock Stopped with RB Loading bit in CMRn is written to one (CMRn.LDBSTOP). In
Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped
with RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop
commands have effect only if the clock is enabled.
Figure 28-3. Clock Control
Selected
Clock Trigger
CLKSTA CLKEN CLKDIS
Q S
R
Q S
R
Stop Disable
Event Event
Counter
Clock
28.6.1.5 TC operating modes
Each channel can independently operate in two different modes:
• Capture mode provides measurement on signals.
• Waveform mode provides wave generation.
The TC operating mode selection is done by writing to the Wave bit in the CCRn register
(CCRn.WAVE).
In Capture mode, TIOA and TIOB are configured as inputs.
In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not
selected to be the external trigger.
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28.6.1.6 Trigger
A trigger resets the counter and starts the counter clock. Three types of triggers are common to
both modes, and a fourth external trigger is available to each mode.
The following triggers are common to both modes:
• Software Trigger: each channel has a software trigger, available by writing a one to the
Software Trigger Command bit in CCRn (CCRn.SWTRG).
• SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the
same effect as a software trigger. The SYNC signals of all channels are asserted
simultaneously by writing a one to the Synchro Command bit in the BCR register
(BCR.SYNC).
• Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the
counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn
(CMRn.CPCTRG) is written to one.
The channel can also be configured to have an external trigger. In Capture mode, the external
trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event
can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external
event can then be programmed to perform a trigger by writing a one to the External Event Trig-
ger Enable bit in CMRn (CMRn.ENETRG).
If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period
in order to be detected.
Regardless of the trigger used, it will be taken into account at the following active edge of the
selected clock. This means that the counter value can be read differently from zero just after a
trigger, especially when a low frequency signal is selected as the clock.
28.6.2 Capture Operating Mode
This mode is entered by writing a zero to the CMRn.WAVE bit.
Capture mode allows the TC channel to perform measurements such as pulse timing, fre-
quency, period, duty cycle and phase on TIOA and TIOB signals which are considered as
inputs.
Figure 28-4 on page 756 shows the configuration of the TC channel when programmed in Cap-
ture mode.
28.6.2.1 Capture registers A and B
Registers A and B (RA and RB) are used as capture registers. This means that they can be
loaded with the counter value when a programmable event occurs on the signal TIOA.
The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of
the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA
edge for the loading of the RB register.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in
SRn (SRn.LOVRS). In this case, the old value is overwritten.
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28.6.2.2 Trigger conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trig-
ger can be defined.
The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or
TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn
(CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trig-
ger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled.
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TCCLKS
CLKSTA CLKEN CLKDIS
CLKI
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TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3 Q S
TIMER_CLOCK4
TIMER_CLOCK5
R
Figure 28-4. Capture Mode
Q S
XC0
R
XC1
XC2
LDBSTOP LDBDIS
BURST
Register C
Capture Capture
1 Register A Register B Compare RC =
16-bit
SWTRG Counter
CLK
OVF
RESET
SYNC
Trig
ABETRG
ETRGEDG CPCTRG
MTIOB Edge
Detector
TIOB LDRA LDRB
SR
CPCS
COVFS
LOVRS
LDRBS
LDRAS
ETRGS
MTIOA Edge Edge
Detector Detector
If RA is not Loaded
or RB is Loaded If RA is Loaded
TIOA
IMR
Timer/Counter Channel
INT
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28.6.3 Waveform Operating Mode
Waveform operating mode is entered by writing a one to the CMRn.WAVE bit.
In Waveform operating mode the TC channel generates one or two PWM signals with the same
frequency and independently programmable duty cycles, or generates different types of one-
shot or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used
as an external event.
Figure 28-5 on page 758 shows the configuration of the TC channel when programmed in
Waveform operating mode.
28.6.3.1 Waveform selection
Depending on the Waveform Selection field in CMRn (CMRn.WAVSEL), the behavior of CVn
varies.
With any selection, RA, RB and RC can all be used as compare registers.
RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output
(if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.
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TCCLKS
CLKSTA CLKEN CLKDIS
TIMER_CLOCK1 ACPC
CLKI
TIMER_CLOCK2
TIMER_CLOCK3 Q S
TIMER_CLOCK4 CPCDIS MTIOA
R ACPA
TIMER_CLOCK5 Q S
XC0
R
XC1
XC2 CPCSTOP TIOA
AEEVT
O utput Contr oller
Figure 28-5. Waveform Mode
BURST Register A Register B Register C
WAVSEL
ASWTRG
1 Compare RA = Compare RB = Compare RC =
16-bit
Counter
CLK
OVF
RESET
SWTRG
BCPC
SYNC
Trig
BCPB MTIOB
WAVSEL
EEVT
TIOB
BEEVT
EEVTEDG
O utput Cont r oller
ENETRG
SR
CPBS
CPCS
CPAS
Edge
ETRGS
COVFS
Detector BSWTRG
TIOB
IMR
Timer/Counter Channel
INT
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28.6.3.2 WAVSEL = 0
When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once
0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and
the cycle continues. See Figure 28-6 on page 759.
An external event trigger or a software trigger can reset the value of CVn. It is important to note
that the trigger may occur at any time. See Figure 28-7 on page 760.
RC Compare cannot be programmed to generate a trigger in this configuration. At the same
time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter
clock (CMRn.CPCDIS = 1).
Figure 28-6. WAVSEL= 0 Without Trigger
Counter Value Counter cleared by compare match with
0xFFFF
0xFFFF
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
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Figure 28-7. WAVSEL= 0 With Trigger
Counter Value Counter cleared by compare match with 0xFFFF
0xFFFF
Counter cleared by trigger
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
28.6.3.3 WAVSEL = 2
When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC,
then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then
incremented and so on. See Figure 28-8 on page 761.
It is important to note that CVn can be reset at any time by an external event or a software trig-
ger if both are programmed correctly. See Figure 28-9 on page 761.
In addition, RC Compare can stop the counter clock (CMRn.CPCSTOP) and/or disable the
counter clock (CMRn.CPCDIS = 1).
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Figure 28-8. WAVSEL = 2 Without Trigger
Counter Value
0xFFFF
Counter cleared by compare match
with RC
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
Figure 28-9. WAVSEL = 2 With Trigger
Counter Value
0xFFFF
Counter cleared by compare match with RC Counter cleared by trigger
RC
RB
RA
Waveform Examples Time
TIOB
TIOA
28.6.3.4 WAVSEL = 1
When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF
is reached, the value of CVn is decremented to 0, then re-incremented to 0xFFFF and so on.
See Figure 28-10 on page 762.
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A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger
occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is
decrementing, CVn then increments. See Figure 28-11 on page 762.
RC Compare cannot be programmed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or dis-
able the counter clock (CMRn.CPCDIS = 1).
Figure 28-10. WAVSEL = 1 Without Trigger
Counter Value Counter decremented by compare match
with 0xFFFF
0xFFFF
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
Figure 28-11. WAVSEL = 1 With Trigger
Counter decremented by compare match with 0xFFFF
Counter Value
0xFFFF
Counter decremented by trigger
RC
RB
Counter incremented by trigger
RA
Waveform Examples Time
TIOB
TIOA
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28.6.3.5 WAVSEL = 3
When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is
reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See
Figure 28-12 on page 763.
A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger
occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is
decrementing, CVn then increments. See Figure 28-13 on page 764.
RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock
(CMRn.CPCDIS = 1).
Figure 28-12. WAVSEL = 3 Without Trigger
Counter Value
0xFFFF
Counter cleared by compare match with RC
RC
RB
RA
Waveform Examples Time
TIOB
TIOA
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Figure 28-13. WAVSEL = 3 With Trigger
Counter Value
0xFFFF
Counter decremented by compare match
with RC
RC
Counter decremented by trigger
RB
Counter incremented by trigger
RA
Time
Waveform Examples
TIOB
TIOA
28.6.3.6 External event/trigger conditions
An external event can be programmed to be detected on one of the clock sources (XC0, XC1,
XC2) or TIOB. The external event selected can then be used as a trigger.
The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger. The
External Event Edge Selection field in CMRn (CMRn.EEVTEDG) defines the trigger edge for
each of the possible external triggers (rising, falling or both). If CMRn.EEVTEDG is written to
zero, no external event is defined.
If TIOB is defined as an external event signal (CMRn.EEVT = 0), TIOB is no longer used as an
output and the compare register B is not used to generate waveforms and subsequently no
IRQs. In this case the TC channel can only generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by writing a one to the
CMRn.ENETRG bit.
As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC
Compare can also be used as a trigger depending on the CMRn.WAVSEL field.
28.6.3.7 Output controller
The output controller defines the output level changes on TIOA and TIOB following an event.
TIOB control is used only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB:
• software trigger
• external event
• RC compare
RA compare controls TIOA and RB compare controls TIOB. Each of these events can be pro-
grammed to set, clear or toggle the output as defined in the following fields in CMRn:
• RC Compare Effect on TIOB (CMRn.BCPC)
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• RB Compare Effect on TIOB (CMRn.BCPB)
• RC Compare Effect on TIOA (CMRn.ACPC)
• RA Compare Effect on TIOA (CMRn.ACPA)
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28.7 User Interface
Table 28-3. TC Register Memory Map
Offset Register Register Name Access Reset
0x00 Channel 0 Control Register CCR0 Write-only 0x00000000
0x04 Channel 0 Mode Register CMR0 Read/Write 0x00000000
0x10 Channel 0 Counter Value CV0 Read-only 0x00000000
0x14 Channel 0 Register A RA0 Read/Write(1) 0x00000000
0x18 Channel 0 Register B RB0 Read/Write(1) 0x00000000
0x1C Channel 0 Register C RC0 Read/Write 0x00000000
0x20 Channel 0 Status Register SR0 Read-only 0x00000000
0x24 Interrupt Enable Register IER0 Write-only 0x00000000
0x28 Channel 0 Interrupt Disable Register IDR0 Write-only 0x00000000
0x2C Channel 0 Interrupt Mask Register IMR0 Read-only 0x00000000
0x40 Channel 1 Control Register CCR1 Write-only 0x00000000
0x44 Channel 1 Mode Register CMR1 Read/Write 0x00000000
0x50 Channel 1 Counter Value CV1 Read-only 0x00000000
(1)
0x54 Channel 1 Register A RA1 Read/Write 0x00000000
(1)
0x58 Channel 1 Register B RB1 Read/Write 0x00000000
0x5C Channel 1 Register C RC1 Read/Write 0x00000000
0x60 Channel 1 Status Register SR1 Read-only 0x00000000
0x64 Channel 1 Interrupt Enable Register IER1 Write-only 0x00000000
0x68 Channel 1 Interrupt Disable Register IDR1 Write-only 0x00000000
0x6C Channel 1 Interrupt Mask Register IMR1 Read-only 0x00000000
0x80 Channel 2 Control Register CCR2 Write-only 0x00000000
0x84 Channel 2 Mode Register CMR2 Read/Write 0x00000000
0x90 Channel 2 Counter Value CV2 Read-only 0x00000000
0x94 Channel 2 Register A RA2 Read/Write(1) 0x00000000
0x98 Channel 2 Register B RB2 Read/Write(1) 0x00000000
0x9C Channel 2 Register C RC2 Read/Write 0x00000000
0xA0 Channel 2 Status Register SR2 Read-only 0x00000000
0xA4 Channel 2 Interrupt Enable Register IER2 Write-only 0x00000000
0xA8 Channel 2 Interrupt Disable Register IDR2 Write-only 0x00000000
0xAC Channel 2 Interrupt Mask Register IMR2 Read-only 0x00000000
0xC0 Block Control Register BCR Write-only 0x00000000
0xC4 Block Mode Register BMR Read/Write 0x00000000
0xF8 Features Register FEATURES Read-only -(2)
0xFC Version Register VERSION Read-only -(2)
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Notes: 1. Read-only if CMRn.WAVE is zero.
2. The reset values are device specific. Please refer to the Module Configuration section at the
end of this chapter.
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28.7.1 Channel Control Register
Name: CCR
Access Type: Write-only
Offset: 0x00 + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - SWTRG CLKDIS CLKEN
• SWTRG: Software Trigger Command
1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started.
0: Writing a zero to this bit has no effect.
• CLKDIS: Counter Clock Disable Command
1: Writing a one to this bit will disable the clock.
0: Writing a zero to this bit has no effect.
• CLKEN: Counter Clock Enable Command
1: Writing a one to this bit will enable the clock if CLKDIS is not one.
0: Writing a zero to this bit has no effect.
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28.7.2 Channel Mode Register: Capture Mode
Name: CMR
Access Type: Read/Write
Offset: 0x04 + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG - - - ABETRG ETRGEDG
7 6 5 4 3 2 1 0
LDBDIS LDBSTOP BURST CLKI TCCLKS
• LDRB: RB Loading Selection
LDRB Edge
0 none
1 rising edge of TIOA
2 falling edge of TIOA
3 each edge of TIOA
• LDRA: RA Loading Selection
LDRA Edge
0 none
1 rising edge of TIOA
2 falling edge of TIOA
3 each edge of TIOA
• WAVE
1: Capture mode is disabled (Waveform mode is enabled).
0: Capture mode is enabled.
• CPCTRG: RC Compare Trigger Enable
1: RC Compare resets the counter and starts the counter clock.
0: RC Compare has no effect on the counter and its clock.
• ABETRG: TIOA or TIOB External Trigger Selection
1: TIOA is used as an external trigger.
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0: TIOB is used as an external trigger.
• ETRGEDG: External Trigger Edge Selection
ETRGEDG Edge
0 none
1 rising edge
2 falling edge
3 each edge
• LDBDIS: Counter Clock Disable with RB Loading
1: Counter clock is disabled when RB loading occurs.
0: Counter clock is not disabled when RB loading occurs.
• LDBSTOP: Counter Clock Stopped with RB Loading
1: Counter clock is stopped when RB loading occurs.
0: Counter clock is not stopped when RB loading occurs.
• BURST: Burst Signal Selection
BURST Burst Signal Selection
0 The clock is not gated by an external signal
1 XC0 is ANDed with the selected clock
2 XC1 is ANDed with the selected clock
3 XC2 is ANDed with the selected clock
• CLKI: Clock Invert
1: The counter is incremented on falling edge of the clock.
0: The counter is incremented on rising edge of the clock.
• TCCLKS: Clock Selection
TCCLKS Clock Selected
0 TIMER_CLOCK1
1 TIMER_CLOCK2
2 TIMER_CLOCK3
3 TIMER_CLOCK4
4 TIMER_CLOCK5
5 XC0
6 XC1
7 XC2
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28.7.3 Channel Mode Register: Waveform Mode
Name: CMR
Access Type: Read/Write
Offset: 0x04 + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
7 6 5 4 3 2 1 0
CPCDIS CPCSTOP BURST CLKI TCCLKS
• BSWTRG: Software Trigger Effect on TIOB
BSWTRG Effect
0 none
1 set
2 clear
3 toggle
• BEEVT: External Event Effect on TIOB
BEEVT Effect
0 none
1 set
2 clear
3 toggle
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• BCPC: RC Compare Effect on TIOB
BCPC Effect
0 none
1 set
2 clear
3 toggle
• BCPB: RB Compare Effect on TIOB
BCPB Effect
0 none
1 set
2 clear
3 toggle
• ASWTRG: Software Trigger Effect on TIOA
ASWTRG Effect
0 none
1 set
2 clear
3 toggle
• AEEVT: External Event Effect on TIOA
AEEVT Effect
0 none
1 set
2 clear
3 toggle
• ACPC: RC Compare Effect on TIOA
ACPC Effect
0 none
1 set
2 clear
3 toggle
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• ACPA: RA Compare Effect on TIOA
ACPA Effect
0 none
1 set
2 clear
3 toggle
• WAVE
1: Waveform mode is enabled.
0: Waveform mode is disabled (Capture mode is enabled).
• WAVSEL: Waveform Selection
WAVSEL Effect
0 UP mode without automatic trigger on RC Compare
1 UPDOWN mode without automatic trigger on RC Compare
2 UP mode with automatic trigger on RC Compare
3 UPDOWN mode with automatic trigger on RC Compare
• ENETRG: External Event Trigger Enable
1: The external event resets the counter and starts the counter clock.
0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA
output.
• EEVT: External Event Selection
EEVT Signal selected as external event TIOB Direction
0 TIOB input(1)
1 XC0 output
2 XC1 output
3 XC2 output
Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subse-
quently no IRQs.
• EEVTEDG: External Event Edge Selection
EEVTEDG Edge
0 none
1 rising edge
2 falling edge
3 each edge
• CPCDIS: Counter Clock Disable with RC Compare
1: Counter clock is disabled when counter reaches RC.
0: Counter clock is not disabled when counter reaches RC.
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• CPCSTOP: Counter Clock Stopped with RC Compare
1: Counter clock is stopped when counter reaches RC.
0: Counter clock is not stopped when counter reaches RC.
• BURST: Burst Signal Selection
BURST Burst Signal Selection
0 The clock is not gated by an external signal.
1 XC0 is ANDed with the selected clock.
2 XC1 is ANDed with the selected clock.
3 XC2 is ANDed with the selected clock.
• CLKI: Clock Invert
1: Counter is incremented on falling edge of the clock.
0: Counter is incremented on rising edge of the clock.
• TCCLKS: Clock Selection
TCCLKS Clock Selected
0 TIMER_CLOCK1
1 TIMER_CLOCK2
2 TIMER_CLOCK3
3 TIMER_CLOCK4
4 TIMER_CLOCK5
5 XC0
6 XC1
7 XC2
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28.7.4 Channel Counter Value Register
Name: CV
Access Type: Read-only
Offset: 0x10 + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
CV[15:8]
7 6 5 4 3 2 1 0
CV[7:0]
• CV: Counter Value
CV contains the counter value in real time.
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28.7.5 Channel Register A
Name: RA
Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1
Offset: 0x14 + n * 0X40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
RA[15:8]
7 6 5 4 3 2 1 0
RA[7:0]
• RA: Register A
RA contains the Register A value in real time.
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28.7.6 Channel Register B
Name: RB
Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1
Offset: 0x18 + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
RB[15:8]
7 6 5 4 3 2 1 0
RB[7:0]
• RB: Register B
RB contains the Register B value in real time.
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28.7.7 Channel Register C
Name: RC
Access Type: Read/Write
Offset: 0x1C + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
RC[15:8]
7 6 5 4 3 2 1 0
RC[7:0]
• RC: Register C
RC contains the Register C value in real time.
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28.7.8 Channel Status Register
Name: SR
Access Type: Read-only
Offset: 0x20 + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
• MTIOB: TIOB Mirror
1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven
high.
0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven
low.
• MTIOA: TIOA Mirror
1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven
high.
0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven
low.
• CLKSTA: Clock Enabling Status
1: This bit is set when the clock is enabled.
0: This bit is cleared when the clock is disabled.
• ETRGS: External Trigger Status
1: This bit is set when an external trigger has occurred.
0: This bit is cleared when the SR register is read.
• LDRBS: RB Loading Status
1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
• LDRAS: RA Loading Status
1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
• CPCS: RC Compare Status
1: This bit is set when an RC Compare has occurred.
0: This bit is cleared when the SR register is read.
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• CPBS: RB Compare Status
1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one.
0: This bit is cleared when the SR register is read.
• CPAS: RA Compare Status
1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one.
0: This bit is cleared when the SR register is read.
• LOVRS: Load Overrun Status
1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and
CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
• COVFS: Counter Overflow Status
1: This bit is set when a counter overflow has occurred.
0: This bit is cleared when the SR register is read.
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28.7.9 Channel Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x24 + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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28.7.10 Channel Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x28 + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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28.7.11 Channel Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x2C + n * 0x40
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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28.7.12 Block Control Register
Name: BCR
Access Type: Write-only
Offset: 0xC0
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - SYNC
• SYNC: Synchro Command
1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
0: Writing a zero to this bit has no effect.
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28.7.13 Block Mode Register
Name: BMR
Access Type: Read/Write
Offset: 0xC4
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - TC2XC2S TC1XC1S TC0XC0S
• TC2XC2S: External Clock Signal 2 Selection
TC2XC2S Signal Connected to XC2
0 TCLK2
1 none
2 TIOA0
3 TIOA1
• TC1XC1S: External Clock Signal 1 Selection
TC1XC1S Signal Connected to XC1
0 TCLK1
1 none
2 TIOA0
3 TIOA2
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• TC0XC0S: External Clock Signal 0 Selection
TC0XC0S Signal Connected to XC0
0 TCLK0
1 none
2 TIOA1
3 TIOA2
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28.7.14 Features Register
Name: FEATURES
Access Type: Read-only
Offset: 0xF8
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - -
15 14 13 12 11 10 9 8
- - - - - - BRPBHSB UPDNIMPL
7 6 5 4 3 2 1 0
CTRSIZE
• BRPBHSB: Bridge type is PB to HSB
1: Bridge type is PB to HSB.
0: Bridge type is not PB to HSB.
• UPDNIMPL: Up/down is implemented
1: Up/down counter capability is implemented.
0: Up/down counter capability is not implemented.
• CTRSIZE: Counter size
This field indicates the size of the counter in bits.
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28.7.15 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant number
Reserved. No functionality associated.
• VERSION: Version number
Version number of the module. No functionality associated.
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28.8 Module Configuration
The specific configuration for each TC instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks according to the table in the Power
Manager section.
Table 28-4. Module Clock Name
Module name Clock name
TC0 CLK_TC0
TC1 CLK_TC1
28.8.1 Clock Connections
Each Timer/Counter channel can independently select an internal or external clock source for its
counter:
Table 28-5. Timer/Counter Internal Clock Connections
Name Connection
TIMER_CLOCK1 32 KHz clock
TIMER_CLOCK2 PBA Clock / 2
TIMER_CLOCK3 PBA Clock / 8
TIMER_CLOCK4 PBA Clock / 32
TIMER_CLOCK5 PBA Clock / 128
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29. Analog-to-Digital Converter (ADC)
Rev: 2.0.0.1
29.1 Features
• Integrated multiplexer offering up to eight independent analog inputs
• Individual enable and disable of each channel
• Hardware or software trigger
– External trigger pin
– Timer counter outputs (corresponding TIOA trigger)
• Peripheral DMA Controller support
• Possibility of ADC timings configuration
• Sleep mode and conversion sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all enabled
channels
29.2 Overview
The Analog-to-Digital Converter (ADC) is based on a Successive Approximation Register (SAR)
10-bit ADC. It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital
conversions of 8 analog lines. The conversions extend from 0V to VDDANA.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a
common register for all channels, as well as in a channel-dedicated register. Software trigger,
external trigger on rising edge of the TRIGGER pin, or internal triggers from timer counter out-
put(s) are configurable.
The ADC also integrates a sleep mode and a conversion sequencer and connects with a Periph-
eral DMA Controller channel. These features reduce both power consumption and processor
intervention.
Finally, the user can configure ADC timings, such as startup time and sample & hold time.
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29.3 Block Diagram
Figure 29-1. ADC Block Diagram
Timer
Counter
Channels
ADC
Trigger
TRIGGER Selection ADC Interrupt Interrupt
Control
Logic Controller
VDDANA
VREF
High Speed
Bus (HSB)
AD- Peripheral
Dedicated DMA
AD- Controller
Analog
Inputs User
Interface Peripheral Bridge
AD- Successive
Approximation
Register
AD- Analog-to-Digital
Analog Inputs Converter Peripheral Bus
Multiplexed AD- I/O (PB)
With I/O lines Controller
AD-
GND
29.4 I/O Lines Description
Table 29-1. ADC Pins Description
Pin Name Description
VDDANA Analog power supply
AD[0] - AD[7] Analog input channels
TRIGGER External trigger
29.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
29.5.1 I/O Lines
The TRIGGER pin may be shared with other peripheral functions through the I/O Controller.
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29.5.2 Power Management
In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is
small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the
ADC behavior.
29.5.3 Clocks
The clock for the ADC bus interface (CLK_ADC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
ADC before disabling the clock, to avoid freezing the ADC in an undefined state.
The CLK_ADC clock frequency must be in line with the ADC characteritics. Refer to Electrical
Characteristics section for details.
29.5.4 Interrupts
The ADC interrupt request line is connected to the interrupt controller. Using the ADC interrupt
requires the interrupt controller to be programmed first.
29.5.5 Analog Inputs
The analog input pins can be multiplexed with I/O lines. In this case, the assignment of the ADC
input is automatically done as soon as the corresponding I/O is configured through the I/O con-
toller. By default, after reset, the I/O line is configured as a logic input.
29.5.6 Timer Triggers
Timer Counters may or may not be used as hardware triggers depending on user requirements.
Thus, some or all of the timer counters may be non-connected.
29.6 Functional Description
29.6.1 Analog-to-digital Conversion
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-
bit digital data requires sample and hold clock cycles as defined in the Sample and Hold Time
field of the Mode Register (MR.SHTIM) and 10 ADC Clock cycles. The ADC Clock frequency is
selected in the Prescaler Rate Selection field of the MR register (MR.PRESCAL).
The ADC Clock range is between CLK_ADC/2, if the PRESCAL field is 0, and CLK_ADC/128, if
the PRESCAL field is 63 (0x3F). The PRESCAL field must be written in order to provide an ADC
Clock frequency according to the parameters given in the Electrical Characteristics chapter.
29.6.2 Conversion Reference
The conversion is performed on a full range between 0V and the reference voltage connected to
VDDANA. Analog input values between these voltages are converted to digital values based on
a linear conversion.
29.6.3 Conversion Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by writing a one to
the Resolution bit in the MR register (MR.LOWRES). By default, after a reset, the resolution is
the highest and the Converted Data field in the Channel Data Registers (CDRn.DATA) is fully
used. By writing a one to the LOWRES bit, the ADC switches in the lowest resolution and the
conversion results can be read in the eight lowest significant bits of the Channel Data Registers
(CDRn). The two highest bits of the DATA field in the corresponding CDRn register will be read
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as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Regis-
ter (LCDR.LDATA) will be read as zero too.
Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the
transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit
data transfers. In this case, the destination buffers are optimized.
29.6.4 Conversion Results
When a conversion is completed, the resulting 10-bit digital value is stored in the CDR register of
the current channel and in the LCDR register. Channels are enabled by writing a one to the
Channel n Enable bit (CHn) in the CHER register.
The corresponding channel End of Conversion bit in the Status Register (SR.EOCn) and the
Data Ready bit in the SR register (SR.DRDY) are set. In the case of a connected Peripheral
DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC or DRDY
can trigger an interrupt.
Reading one of the CDRn registers clears the corresponding EOC bit. Reading LCDR clears the
DRDY bit and the EOC bit corresponding to the last converted channel.
Figure 29-2. EOCn and DRDY Flag Behavior
Write CR Write CR
With START=1 Read CDRn Read LCDR
With START=1
CHn(CHSR)
EOCn(SR)
Conversion Time Conversion Time
DRDY(SR)
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If the CDR register is not read before further incoming data is converted, the corresponding
Overrun Error bit in the SR register (SR.OVREn) is set.
In the same way, new data converted when DRDY is high sets the General Overrun Error bit in
the SR register (SR.GOVRE).
The OVREn and GOVRE bits are automatically cleared when the SR register is read.
Figure 29-3. GOVRE and OVREn Flag Behavior
Read SR
TRIGGER
CH0(CHSR)
CH1(CHSR)
LCDR Undefined Data Data A Data B Data C
CRD0 Undefined Data Data A Data C
CRD1 Undefined Data Data B
Conversion
EOC0(SR) Conversion Read CDR0
EOC1(SR) Conversion Read CDR1
GOVRE(SR)
DRDY(ASR)
OVRE0(SR)
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and its corresponding EOC and OVRE
flags in SR are unpredictable.
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29.6.5 Conversion Triggers
Conversions of the active analog channels are started with a software or a hardware trigger. The
software trigger is provided by writing a one to the START bit in the Control Register
(CR.START).
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the
external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the Trigger
Selection field in the Mode Register (MR.TRIGSEL). The selected hardware trigger is enabled
by writing a one to the Trigger Enable bit in the Mode Register (MR.TRGEN).
If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the
selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel
must be programmed in Waveform Mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The
ADC hardware logic automatically performs the conversions on the active channels, then waits
for a new request. The Channel Enable (CHER) and Channel Disable (CHDR) Registers enable
the analog channels to be enabled or disabled independently.
If the ADC is used with a Peripheral DMA Controller, only the transfers of converted data from
enabled channels are performed and the resulting data buffers should be interpreted
accordingly.
Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if
a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or
the software trigger.
29.6.6 Sleep Mode and Conversion Sequencer
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is
not being used for conversions. Sleep Mode is selected by writing a one to the Sleep Mode bit in
the Mode Register (MR.SLEEP).
The SLEEP mode is automatically managed by a conversion sequencer, which can automati-
cally process the conversions of all channels at lowest power consumption.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell
requires a start-up time, the logic waits during this time and starts the conversion on the enabled
channels. When all conversions are complete, the ADC is deactivated until the next trigger. Trig-
gers occurring during the sequence are not taken into account.
The conversion sequencer allows automatic processing with minimum processor intervention
and optimized power consumption. Conversion sequences can be performed periodically using
a Timer/Counter output. The periodic acquisition of several samples can be processed automat-
ically without any intervention of the processor thanks to the Peripheral DMA Controller.
Note: The reference voltage pins always remain connected in normal mode as in sleep mode.
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29.6.7 ADC Timings
Each ADC has its own minimal startup time that is defined through the Start Up Time field in the
Mode Register (MR.STARTUP). This startup time is given in the Electrical Characteristics
chapter.
In the same way, a minimal sample and hold time is necessary for the ADC to guarantee the
best converted final value between two channels selection. This time has to be defined through
the Sample and Hold Time field in the Mode Register (MR.SHTIM). This time depends on the
input impedance of the analog input, but also on the output impedance of the driver providing the
signal to the analog input, as there is no input buffer amplifier.
29.6.8 Conversion Performances
For performance and electrical characteristics of the ADC, see the Electrical Characteristics
chapter.
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29.7 User Interface
Table 29-2. ADC Register Memory Map
Offset Register Name Access Reset State
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read/Write 0x00000000
0x10 Channel Enable Register CHER Write-only 0x00000000
0x14 Channel Disable Register CHDR Write-only 0x00000000
0x18 Channel Status Register CHSR Read-only 0x00000000
0x1C Status Register SR Read-only 0x000C0000
0x20 Last Converted Data Register LCDR Read-only 0x00000000
0x24 Interrupt Enable Register IER Write-only 0x00000000
0x28 Interrupt Disable Register IDR Write-only 0x00000000
0x2C Interrupt Mask Register IMR Read-only 0x00000000
0x30 Channel Data Register 0 CDR0 Read-only 0x00000000
... ...(if implemented) ... ... ...
0x4C Channel Data Register 7(if implemented) CDR7 Read-only 0x00000000
0xFC Version Register VERSION Read-only - (1)
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
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29.7.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – START SWRST
• START: Start Conversion
Writing a one to this bit will begin an analog-to-digital conversion.
Writing a zero to this bit has no effect.
This bit always reads zero.
• SWRST: Software Reset
Writing a one to this bit will reset the ADC.
Writing a zero to this bit has no effect.
This bit always reads zero.
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29.7.2 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – SHTIM
23 22 21 20 19 18 17 16
– STARTUP
15 14 13 12 11 10 9 8
PRESCAL
7 6 5 4 3 2 1 0
– – SLEEP LOWRES TRGSEL TRGEN
• SHTIM: Sample & Hold Time
Sample & Hold Time = (SHTIM+3) / ADCClock
• STARTUP: Start Up Time
Startup Time = (STARTUP+1) * 8 / ADCClock
This Time should respect a minimal value. Refer to Electrical Characteristics section for details.
• PRESCAL: Prescaler Rate Selection
ADCClock = CLK_ADC / ( (PRESCAL+1) * 2 )
• SLEEP: Sleep Mode
1: Sleep Mode is selected.
0: Normal Mode is selected.
• LOWRES: Resolution
1: 8-bit resolution is selected.
0: 10-bit resolution is selected.
• TRGSEL: Trigger Selection
TRGSEL Selected TRGSEL
0 0 0 Internal Trigger 0, depending of chip integration
0 0 1 Internal Trigger 1, depending of chip integration
0 1 0 Internal Trigger 2, depending of chip integration
0 1 1 Internal Trigger 3, depending of chip integration
1 0 0 Internal Trigger 4, depending of chip integration
1 0 1 Internal Trigger 5, depending of chip integration
1 1 0 External trigger
• TRGEN: Trigger Enable
1: The hardware trigger selected by the TRGSEL field is enabled.
0: The hardware triggers are disabled. Starting a conversion is only possible by software.
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29.7.3 Channel Enable Register
Name: CHER
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
• CHn: Channel n Enable
Writing a one to these bits will set the corresponding bit in CHSR.
Writing a zero to these bits has no effect.
These bits always read a zero.
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29.7.4 Channel Disable Register
Name: CHDR
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
• CHn: Channel n Disable
Writing a one to these bits will clear the corresponding bit in CHSR.
Writing a zero to these bits has no effect.
These bits always read a zero.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its
associated data and its corresponding EOC and OVRE flags in SR are unpredictable.
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29.7.5 Channel Status Register
Name: CHSR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
• CHn: Channel n Status
These bits are set when the corresponding bits in CHER is written to one.
These bits are cleared when the corresponding bits in CHDR is written to one.
1: The corresponding channel is enabled.
0: The corresponding channel is disabled.
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29.7.6 Status Register
Name: SR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x000C0000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – RXBUFF ENDRX GOVRE DRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
7 6 5 4 3 2 1 0
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
• RXBUFF: RX Buffer Full
This bit is set when the Buffer Full signal from the Peripheral DMA is active.
This bit is cleared when the Buffer Full signal from the Receive Peripheral DMA is inactive.
• ENDRX: End of RX Buffer
This bit is set when the End Receive signal from the Peripheral DMA is active.
This bit is cleared when the End Receive signal from the Peripheral DMA is inactive.
• GOVRE: General Overrun Error
This bit is set when a General Overrun Error has occurred.
This bit is cleared when the SR register is read.
1: At least one General Overrun Error has occurred since the last read of the SR register.
0: No General Overrun Error occurred since the last read of the SR register.
• DRDY: Data Ready
This bit is set when a data has been converted and is available in the LCDR register.
This bit is cleared when the LCDR register is read.
0: No data has been converted since the last read of the LCDR register.
1: At least one data has been converted and is available in the LCDR register.
• OVREn: Overrun Error n
These bits are set when an overrun error on the corresponding channel has occurred (if implemented).
These bits are cleared when the SR register is read.
0: No overrun error on the corresponding channel (if implemented) since the last read of SR.
1: There has been an overrun error on the corresponding channel (if implemented) since the last read of SR.
• EOCn: End of Conversion n
These bits are set when the corresponding conversion is complete.
These bits are cleared when the corresponding CDR or LCDR registers are read.
0: Corresponding analog channel (if implemented) is disabled, or the conversion is not finished.
1: Corresponding analog channel (if implemented) is enabled and conversion is complete.
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29.7.7 Last Converted Data Register
Name: LCDR
Access Type: Read-only
Offset: 0x20
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – LDATA[9:8]
7 6 5 4 3 2 1 0
LDATA[7:0]
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion
is completed.
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29.7.8 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x24
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – RXBUFF ENDRX GOVRE DRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
7 6 5 4 3 2 1 0
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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29.7.9 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x28
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – RXBUFF ENDRX GOVRE DRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
7 6 5 4 3 2 1 0
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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29.7.10 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x2C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – RXBUFF ENDRX GOVRE DRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
7 6 5 4 3 2 1 0
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is cleared when the corresponding bit in IER is written to one.
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29.7.11 Channel Data Register
Name: CDRx
Access Type: Read-only
Offset: 0x2C-0x4C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – DATA[9:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA: Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion
is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.
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29.7.12 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: –
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – VARIANT
15 14 13 12 11 10 9 8
– – – – VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
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29.8 Module Configuration
The specific configuration for the ADC instance is listed in the following tables.
Table 29-3. Module configuration
Feature ADC
ADC_NUM_CHANNELS 8
Internal Trigger 0 TIOA Ouput A of the Timer Counter 0 Channel 0
Internal Trigger 1 TIOB Ouput B of the Timer Counter 0 Channel 0
Internal Trigger 2 TIOA Ouput A of the Timer Counter 0 Channel 1
Internal Trigger 3 TIOB Ouput B of the Timer Counter 0 Channel 1
Internal Trigger 4 TIOA Ouput A of the Timer Counter 0 Channel 2
Internal Trigger 5 TIOB Ouput B of the Timer Counter 0 Channel 2
Table 29-4. Module Clock Name
Module name Clock name
ADC CLK_ADC
Table 29-5. Register Reset Values
Module name Reset Value
VERSION 0x00000200
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30. HSB Bus Performance Monitor (BUSMON)
Rev 1.0.0.0
30.1 Features
• Allows performance monitoring of High Speed Bus master interfaces
– Up to 4 masters can be monitored
– Peripheral Bus access to monitor registers
• The following is monitored
– Data transfer cycles
– Bus stall cycles
– Maximum access latency for a single transfer
• Automatic handling of event overflow
30.2 Overview
BUSMON allows the user to measure the activity and stall cycles on the High Speed Bus (HSB).
Up to 4 device-specific masters can be measured. Each of these masters is part of a measure-
ment channel. Which masters that are connected to a channel is device-specific. Devices may
choose not to implement all channels.
30.3 Block Diagram
Figure 30-1. BUSMON Block Diagram
Channel 0
Master A
Master B Slave 0
Master C Registers
Master D
Channel 1
Master E
Master F Slave 1
Master G Registers
Master H
Channel 2
Master I
Master J Slave 2
Master K Registers
Master L
Channel 3
Master M
Master N Slave 3
Master O Registers
Master P
Control
Peripheral Bus Interface
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30.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
30.4.1 Clocks
The clock for the BUSMON bus interface (CLK_BUSMON) is generated by the Power Manager.
This clock is enabled at reset and can be disabled in the Power Manager. It is recommended to
disable the BUSMON before disabling the clock, to avoid freezing the BUSMON in an undefined
state.
30.5 Functional Description
Three different parameters can be measured by each channel:
• The number of data transfer cycles since last channel reset
• The number of stall cycles since last channel reset
• The maximum continuous number of stall cycles since last channel reset (This approximates
the max latency in the transfers.)
These measurements can be extracted by software and used to generate indicators for bus
latency, bus load and maximum bus latency.
Each of the counters have a fixed width, and may therefore overflow. When overflow is encoun-
tered in either the Channel n Data Cycles (DATAn) register or the Channel n Stall Cycles
(STALLn) register of a channel, all registers in the channel are reset. This behavior is altered if
the Channel n Overflow Freeze (CHnOF) bit is set in the Control (CONTROL) register. If this bit
is written to one, the channel registers are frozen when either DATAn or STALLn reaches its
maximum value. This simplifies one-shot readout of the counter values.
The registers can also be manually reset by writing to the CONTROL register. The Channeln
Max Initiation Latency (LATn) register is saturating, when its max count is reached, it will be set
to its maximum value. The LATn register is reset whenever DATAn and STALLn are reset.
A counter must manually be enabled by writing to the CONTROL register.
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30.6 User interface
Table 30-1. BUSMON Register Memory Map
Offset Register Register Name Access Reset
0x00 Control register CONTROL Read/Write 0x00000000
0x10 Channel0 Data Cycles register DATA0 Read 0x00000000
0x14 Channel0 Stall Cycles register STALL0 Read 0x00000000
0x18 Channel0 Max Initiation Latency register LAT0 Read 0x00000000
0x20 Channel1 Data Cycles register DATA1 Read 0x00000000
0x24 Channel1 Stall Cycles register STALL1 Read 0x00000000
0x28 Channel1 Max Initiation Latency register LAT1 Read 0x00000000
0x30 Channel2 Data Cycles register DATA2 Read 0x00000000
0x34 Channel2 Stall Cycles register STALL2 Read 0x00000000
0x38 Channel2 Max Initiation Latency register LAT2 Read 0x00000000
0x40 Channel3 Data Cycles register DATA3 Read 0x00000000
0x44 Channel3 Stall Cycles register STALL3 Read 0x00000000
0x48 Channel3 Max Initiation Latency register LAT3 Read 0x00000000
0x50 Parameter register PARAMETER Read -(1)
0x54 Version register VERSION Read -(1)
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
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30.6.1 Control Register
Name: CONTROL
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - CH3RES CH2RES CH1RES CH0RES
15 14 13 12 11 10 9 8
- - - - CH3OF CH2OF CH1OF CH0OF
7 6 5 4 3 2 1 0
- - - - CH3EN CH2EN CH1EN CH0EN
• CHnRES: Channel Counter Reset
Writting a one to this bit will reset the counter in the channel n.
Writting a zero to this bit has no effect.
This bit always reads as zero.
• CHnOF: Channel Overflow Freeze
1: All channel n registers are frozen just before DATA or STALL overflows.
0: The channel n registers are reset if DATA or STALL overflows.
• CHnEN: Channel Enabled
1: The channel n is enabled.
0: The channel n is disabled.
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30.6.2 Channel n Data Cycles Register
Name: DATAn
Access Type: Read-Only
Offset: 0x10 + n*0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA:
Data cycles counted since the last reset.
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30.6.3 Channel n Stall Cycles Register
Name: STALLn
Access Type: Read-Only
Offset: 0x14 + n*0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
7 6 5 4 3 2 1 0
STALL[7:0]
• STALL:
Stall cycles counted since the last reset.
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30.6.4 Channel n Max Transfer Initiation Cycles Register
Name: LATn
Access Type: Read-Only
Offset: 0x18 + n*0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
LAT[31:24]
23 22 21 20 19 18 17 16
LAT[23:16]
15 14 13 12 11 10 9 8
LAT[15:8]
7 6 5 4 3 2 1 0
LAT[7:0]
• LAT:
This field is cleared whenever the DATA or STALL register is reset.
Maximum transfer initiation cycles counted since the last reset.
This counter is saturating.
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30.6.5 Parameter Register
Name: PARAMETER
Access Type: Read-only
Offset: 0x50
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - CH3IMPL CH2IMPL CH1IMPL CH0IMPL
• CHnIMP: Channel Implementation
1: The corresponding channel is implemented.
0: The corresponding channel is not implemented.
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30.6.6 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0x54
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
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30.7 Module Configuration
Table 30-2. Register Reset Values
Register Reset Value
VERSION 0x00000100
PARAMETER 0x0000000F
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31. MultiMedia Card Interface (MCI)
Rev. 4.1.0.0
31.1 Features
• Compatible with Multimedia Card specification version 4.3
• Compatible with SD Memory Card specification version 2.0
• Compatible with SDIO specification version 1.1
• Compatible with CE-ATA specification 1.1
• Cards clock rate up to master clock divided by two
• Boot Operation Mode support
• High Speed mode support
• Embedded power management to slow down clock rate when not used
• Supports 2
– Each slot for either a MultiMediaCard bus (up to 30 cards) or an SD Memory Card
• Support for stream, block and multi-block data read and write
• Supports connection to DMA Controller
– Minimizes processor intervention for large buffer transfers
• Built in FIFO (from 16 to 256 bytes) with large memory aperture supporting incremental access
• Support for CE-ATA completion cignal disable command
• Protection against unexpected modification on-the-Fly of the configuration registers
31.2 Overview
The Multimedia Card Interface (MCI) supports the MultiMedia Card (MMC) specification V4.3,
the SD Memory Card specification V2.0, the SDIO V1.1 specificationand CE-ATA specification
V1.1.
The MCI includes a Command Register (CMDR), Response Registers (RSPRn), data registers,
time-out counters and error detection logic that automatically handle the transmission of com-
mands and, when required, the reception of the associated responses and data with a limited
processor overhead.
The MCI supports stream, block and multi block data read and write, and is compatible with the
DMA Controller, minimizing processor intervention for large buffers transfers.
The MCI operates at a rate of up to CLK_MCI divided by 2 and supports the interfacing of 2.
Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD
Memory Card. Only one slot can be selected at a time (slots are multiplexed). The SDCard/SDIO
Slot Selection field in the SDCard/SDIO Register (SDCR.SDCSEL) performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command, four data
and three power lines) and the MultiMedia Card on a 7-pin to 13-pin nterface (clock, command,
one to eight data, three power lines and one reserved for future use).
The SD Memory Card interface also supports MultiMedia Card operations. The main differences
between SD and MultiMedia Cards are the initialization process and the bus topology.
MCI fully supports CE-ATA Revision 1.1, built on the MMC System specification V4.0. The mod-
ule includes dedicated hardware to issue the command completion signal and capture the host
command completion signal disable.
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31.3 Block Diagram
Figure 31-1. MCI Block Diagram
Peripheral Bus Brigde
DMA Controller
Peripheral
Bus
CLK
CMD
I/O
MCI Interface controller DATA
Power CLK_MCI
Manager
Interrupt Control
MCI Interrupt
Figure 31-2. Application Block Diagram
Application Layer
Ex: File System, Audio, Security, etc
Physical Layer
MCI Interface
12 34567
12 3 4 56 78
9
910 1213 8
MMC SDCard
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31.4 I/O Lines Description
Table 31-1. I/O Lines Description
Pin Name Pin Description Type (1) Comments
Input/Output/
CMD[1:0] Command/Response CMD of a MMC or SDCard/SDIO
PP/OD
CLK Clock Input/Output CLK of a MMC or SD Card/SDIO
DAT[0..7] of a MMC
DATA[7:0] Data 0..7 of Slot A Input/Output/PP
DAT[0..3] of a SD Card/SDIO
DAT[0..7] of a MMC
DATA[15:8] Data 0..7 of Slot B Input/Output/PP
DAT[0..3] of a SD Card/SDIO
1. PP: Push/Pull, OD: Open Drain
31.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
31.5.1 Power Management
If the CPU enters a sleep mode that disables clocks used by the MCI, the MCI will stop function-
ing and resume operation after the system wakes up from sleep mode.
31.5.2 I/O Lines
The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with GPIO
lines. User must first program the I/O controller to assign the peripheral functions to MCI pins.
31.5.3 Clocks
The clock for the MCI bus interface (CLK_MCI) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
MCI before disabling the clock, to avoid freezing the MCI in an undefined state.
31.5.4 Interrupt
The MCI interrupt request line is connected to the interrupt controller. Using the MCI interrupt
requires the interrupt controller to be programmed first.
31.6 Functional Description
31.6.1 Bus Topology
Figure 31-3. Multimedia Memory Card Bus Topology
12 34567
910 1213 8
MMC
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The MultiMedia Card communication is based on a 13-pin serial bus interface. It has three com-
munication lines and four supply lines.
Table 31-2. Bus Topology
Pin MCI Pin Name(2)
Number Name Type(1) Description (Slot z)
1 DAT[3] I/O/PP Data DATAz[3]
2 CMD I/O/PP/OD Command/response CMDz
3 VSS1 S Supply voltage ground VSS
4 VDD S Supply voltage VDD
5 CLK I/O Clock CLK
6 VSS2 S Supply voltage ground VSS
7 DAT[0] I/O/PP Data 0 DATAz[0]
8 DAT[1] I/O/PP Data 1 DATAz[1]
9 DAT[2] I/O/PP Data 2 DATAz[2]
10 DAT[4] I/O/PP Data 4 DATAz[4]
11 DAT[5] I/O/PP Data 5 DATAz[5]
12 DAT[6] I/O/PP Data 6 DATAz[6]
13 DAT[7] I/O/PP Data 7 DATAz[7]
Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
Figure 31-4. MMC Bus Connections (One Slot)
MCI
CMD
DATA[0]
CLK
12 34567 12 34567 12 34567
91011 1213 8 91011 1213 8 91011 1213 8
MMC1 MMC2 MMC3
Figure 31-5. SD Memory Card Bus Topology
12345678
9
SDCARD
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The SD Memory Card bus includes the signals listed in Table 31-3 on page 825.
Table 31-3. SD Memory Card Bus Signals
Pin MCI Pin Name(2)
(1)
Number Name Type Description (Slot z)
1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 DATAz[3]
2 CMD PP Command/response CMDz
3 VSS1 S Supply voltage ground VSS
4 VDD S Supply voltage VDD
5 CLK I/O Clock CLK
6 VSS2 S Supply voltage ground VSS
7 DAT[0] I/O/PP Data line Bit 0 DATAz[0]
8 DAT[1] I/O/PP Data line Bit 1 or Interrupt DATAz[1]
9 DAT[2] I/O/PP Data line Bit 2 DATAz[2]
Notes: 1. I: input, O: output, PP: Push Pull, OD: Open Drain.
Figure 31-6. SD Card Bus Connections with One Slot
1 2 34 5 6 78
DATA[3:0]
CLK SDCARD
CMD
9
Figure 31-7. SD Card Bus Connections with Two Slots 1 234 5678
DATA[3:0]
CLK SDCARD1
CMD[0]
9
1 234 5678
DATA[7:4]
CLK SDCARD2
CMD[1]
9
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Figure 31-8. Mixing MultiMedia and SD Memory Cards with Two Slots
DATA[7:0]
CMD[0]
CLK
12 34567 12 34567 12 34567
91011 1213 8 91011 1213 8 91011 1213 8
MMC1 MMC2 MMC3
DATA[11:8]
12 345 678
CLK SDCARD
CMD[1]
9
When the MCI is configured to operate with SD memory cards, the width of the data bus can be
selected in the SDCard /SDIO Bus Width field in the SDCR register (SDCR.SDCBUS). See Sec-
tion “31.7.4” on page 847. for details.
In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as
independent GPIOs.
When more than one card (MMC or SD) is plugged to the device, it is strongly recommended to
connect each card’s clock to a dedicate MCI CLK pin of the device. Otherwise, Compliance to
specifications is not guaranteed.
31.6.2 MultiMedia Card Operations
After a power-on reset, the cards are initialized by a special message-based MultiMedia Card
bus protocol. Each message is represented by one of the following tokens:
• Command: a command is a token that starts an operation. A command is sent from the host
either to a single card (addressed command) or to all connected cards (broadcast
command). a command is transferred serially on the CMD line.
• Response: a response is a token which is sent from an addressed card or (synchronously)
from all connected cards to the host as an answer to a previously received command. A
response is transferred serially on the CMD line.
• Data: data can be transferred from the card to the host or vice versa. Data is transferred via
the data line.
Card addressing is implemented using a session address assigned during the initialization
phase by the bus controller to all currently connected cards. Their unique CID number identifies
individual cards.
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The structure of commands, responses and data blocks is described in the MultiMedia-Card
System Specification. Refer also to Table 31-5 on page 828.
MultiMediaCard bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a
response token. In addition, some operations have a data token; the others transfer their infor-
mation directly within the command or response structure. In this case, no data token is present
in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the MCI
clock (CLK).
Two types of data transfer commands are defined:
• Sequential commands: these commands initiate a continuous data stream. They are
terminated only when a stop command follows on the CMD line. This mode reduces the
command overhead to an absolute minimum.
• Block-oriented commands: these commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the CMD line similarly to the
sequential read or when a multiple block transmission has a pre-defined block count (See Sec-
tion “31.6.3” on page 829.).
The MCI provides a set of registers to perform the entire range of MultiMedia Card operations.
31.6.2.1 Command - Response Operation
After reset, the MCI is disabled and becomes valid after setting the Multi-Media Interface Enable
bit in the Control Register (CR.MCIEN).
The Power Save Mode Enable bit in the CR register (CR.PWEN) saves power by dividing the
MCI clock (CLK) by 2PWSDIV + 1 when the bus is inactive. The Power Saving Divider field locates
in the Mode Register (MR.PWSDIV).
The two bits, Read Proof Enable and Write Proof Enable in the MR register (MR.RDPROOF and
MR.WRPROOF) allow stopping the MCI Clock (CLK) during read or write access if the internal
FIFO is full. This will guarantee data integrity, not bandwidth.
All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined
in the Command Register (CMDR). The CMDR register allows a command to be carried out.
For example, to perform an ALL_SEND_CID command
Table 31-4. ALL_SEND_CID command
Host Command NID Cycles CID
CMD S T Content CRC E Z ****** Z S T Content Z Z Z
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The command ALL_SEND_CID and the fields and values for CMDR register are described in
Table 31-5 on page 828 and Table 31-6 on page 828.
Table 31-5. ALL_SEND_CID Command Description
Command
CMD Index Type Argument Resp Abbreviation Description
Asks all cards to
send their CID
CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID
numbers on the
CMD line
Note: bcr means broadcast command with response.
Table 31-6. Fields and Values for the CMDR register
Field Value
CMDNB (command number) 2 (CMD2)
RSPTYP (response type) 2 (R2: 136 bits response)
SPCMD (special command) 0 (not a special command)
OPCMD (open drain command) 1
MAXLAT (max latency for command to
0 (NID cycles ==> 5 cycles)
response)
TRCMD (transfer command) 0 (No transfer)
TRDIR (transfer direction) X (available only in transfer command)
TRTYP (transfer type) X (available only in transfer command)
IOSPCMD (SDIO special command) 0 (not a special command)
The Argument Register (ARGR) contains the argument field of the command.
To send a command, the user must perform the following steps:
• Set the ARGR register with the command argument.
• Set the CMDR register (see Table 31-6 on page 828).
The command is sent immediately after writing the command register.
As soon as the command register is written, then the Command Ready bit in the Status Register
(SR.CMDRDY) is cleared.
It is released and the end of the card response.
If the command requires a response, it can be read in the Response Registers (RSPRn). The
response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds
an error detection to prevent any corrupted data during the transfer.
The following flowchart shows how to send a command to the card and read the response if
needed. In this example, the status register bits are polled but setting the appropriate bits in the
Interrupt Enable Register (IER) allows using an interrupt method.
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Figure 31-9. Command/Response Functional Flow Diagram
Set the command argument
ARGR = Argument(1)
Set the command
CMD = Command
Read the SR register
Wait for SR.CMDRY bit set 0
to one SR.CMDRDY
Yes
Check error bits in the
SR register(1) Status error bits?
Read response if required
RETURN ERROR(1)
RETURN OK
Note: 1. If the command is SEND_OP_COND, the CRC error bit is always present (refer to R3
response in the MultiMedia Card specification).
31.6.3 Data Transfer Operation
The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream,
etc.). These kind of transfers can be selected setting the Transfer Type field in the CMDR regis-
ter (CMDR.TRTYP).
These operations can be done using the features of the DMA Controller.
In all cases, the Data Block Length must be defined either in the Data Block Length field in the
MR register (MR.BLKLEN)), or in the Block Register (BLKR). This field determines the size of
the data block.
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Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions
are defined (the host can use either one at any time):
• Open-ended/Infinite Multiple block read (or write):
The number of blocks for the read (or write) multiple block operation is not defined. The card
will continuously transfer (or program) data blocks until a stop transmission command is
received.
• Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The card will transfer (or program) the requested number of data blocks and terminate the trans-
action. The stop command is not required at the end of this type of multiple block read (or write),
unless terminated with an error. In order to start a multiple block read (or write) with pre-defined
block count, the host must correctly set the BLKR register. Otherwise the card will start an open-
ended multiple block read. The MMC/SDIO Block Count - SDIO Byte Count field in the BLKR register
(BLKR.BCNT) defines the number of blocks to transfer (from 1 to 65535 blocks). Writing zero to
this field corresponds to an infinite block transfer.
31.6.4 Read/Write Operation
The following flowchart shows how to read a single block with or without use of DMA Controller
facilities. In this example (see Figure 31-10 on page 831), a polling method is used to wait for the
end of read. Similarly, the user can configure the IER register to trigger an interrupt at the end of
read.
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Figure 31-10. Read Functional Flow Diagram
Send SELECT/DESELECT_CARD
Command(1) to select the card
Send SET_BLOCKLEN command(1)
No Yes
Read with DMA
Write a zero in the DMA.DMAEN bit Write a one in the DMA.DMAEN bit
Write the BlockLenght in the MR.BLKLEN field(2) Write the BlockLenght in the MR.BLKLEN field(2)
Write the block count in the BLKR.BCNT field (if
necessary)
Configure the DMA channel X
write the Data Adress in the DMA Controller
Send READ_SINGLE_BLOCK write the (MR.BLKLEN)/4 for Transfer Size
command(1) in the DMA Controller
Number of words to read = (MR.BLKLEN)/4 Send READ_SINGLE_BLOCK
command(1)
Yes
Number of words to read = 0 ? Read the SR register
No
Read the SR register Yes
SR.XFRDONE = 0 ?
No
Yes
SR.RXRDY = 0 ?
RETURN
No
Read data in the RDR register
Number of words to read =
Number of words to read -1
RETURN
Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 829).
2. This field is also accessible in the BLKR register.
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In write operation, the Padding Value bit in the MR register (MR.PADV) is used to define the
padding value when writing non-multiple block size. When the MR.PADV is zero, then 0x00
value is used when padding data, otherwise 0xFF is used.
Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register
(DMA.DMAEN) enables DMA transfer.
The following flowchart shows how to write a single block with or without use of DMA facilities
(see Figure 31-11 on page 833). Polling or interrupt method can be used to wait for the end of
write according to the contents of the Interrupt Mask Register (IMR).
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Figure 31-11. Write Functional Flow Diagram
Send SELECT/DESELECT_CARD
Command(1) to select the card
Send SET_BLOCKLEN command(1)
No Yes
Write using DMA
Write a zero in the DMA.DMAEN bit Write a one in the DMA.DMAEN bit
Write the BlockLenght in the MR.BLKLEN field(2) Write the BlockLenght in the MR.BLKLEN field(2)
Write the block count in the BLKR.BCNT field (if
necessary)
Configure the DMA channel X
write the Data Adress in the DMA Controller
Send WRITE_SINGLE_BLOCK write the (MR.BLKLEN)/4 for Transfer Size in the
command(1) DMA Controller
Number of words to write = BlockLength/4 Send WRITE_SINGLE_BLOCK
command(1)
Enable the DMA channel X
Yes
Number of words to write = 0 ?
Read the SR register
No
Read the SR register
Yes
SR.NOTBUSY = 0 ?
Yes
SR.TXRDY = 0 ?
No
No
Write Data to transmit in the TDR register RETURN
Number of words to write =
Number of words to write - 1
RETURN
Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 829).
2. This field is also accessible in BLKR register.
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The following flowchart shows how to manage a multiple write block transfer with the DMA Con-
troller (see Figure 31-12 on page 835). Polling or interrupt method can be used to wait for the
end of write according to the contents of the IMR register.
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Figure 31-12. Multiple Write Functional Flow Diagram
Send SELECT/DESELECT_CARD
Command(1) to select the card
Send SET_BLOCKLEN command(1)
Write a zero in the DMA.DMAEN bit
Write the block lenght in the MR.BLKLEN field(2)
Write the block count in the BLKR.BCNT field (if
necessary)
Configure the DMA channel X
write the Data Adress in the DMA Controller
write the (MR.BLKLEN)/4 for Transfer Size in the
DMA Controller
Send WRITE_MULTIPLE_BLOCK command(1)
Enable the DMA channel X
Read the SR register
Yes
SR.BLKE = 0 ?
No
Send STOP_TRANSMISSION command(1)
Yes
SR.NOTBUSY = 0 ?
No
RETURN
Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 829).
2. This field is also accessible in BLKR register.
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31.6.4.1 WRITE_SINGLE_BLOCK operation using DMA Controller
1. Wait until the current command execution has successfully terminated.
c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
– Write the dma_offset to the DMA Write Buffer Offset field (DMA.OFFSET).
– Write the DMA Channel Read and Write Chunk Size field (DMA.CHKSIZE).
– Write a one to he DMA.DMAEN bit to enable DMA hardware handshaking in the
MCI.
6. Write a one to the DMA Transfer done bit in IER register (IER.DMADONE).
7. Issue a WRITE_SINGLE_BLOCK command.
8. Wait for DMA Transfer done bit in SR register (SR.DMADONE) is set.
31.6.4.2 READ_SINGLE_BLOCK operation using DMA Controller
1. Wait until the current command execution has successfully terminated.
d. Check that the SR.XFRDONE bit is set.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
– Write zero to the DMA.OFFSET field.
– Write the DMA.CHKSIZE field.
– Write to one the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI.
6. Write a one to the IER.DMADONE bit.
7. Issue a READ_SINGLE_BLOCK command.
8. Wait for SR.DMADONE bit is set.
31.6.4.3 WRITE_MULTIPLE_BLOCK
1. Wait until the current command execution has successfully terminated.
a. Check that the SR.XFRDONE bit is set.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one
block of data.
5. Program the DMA register with the following fields:
– Write the dma_offset in the DMA.OFFSET field.
– Write the DMA.CHKSIZE field.
– Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the
MCI.
6. Write a one to the IER.DMADONE bit.
7. Issue a WRITE_MULTIPLE_BLOCK command.
8. Wait for DMA chained buffer transfer complete interrupt.
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31.6.4.4 READ_MULTIPLE_BLOCK
1. Wait until the current command execution has successfully terminated.
a. Check that the SR.CMDRDY and the SR.NOTBUSY are set.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Program the DMA Controller to use a list of descriptors.
5. Write the DMA register with the following fields:
– Write zero to the DMA.OFFSET.
– Write the DMA.CHKSIZE.
– Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the
MCI.
6. Write a one to the IER.DMADONE bit.
7. Issue a READ_MULTIPLE_BLOCK command.
8. Wait for DMA end of chained buffer transfer interrupt.
31.6.5 SD/SDIO Card Operation
The MCI allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input
Output) Card commands.
SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly
thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental
overwriting and security features. The physical form factor, pin assignment and data transfer
protocol are forward-compatible with the MultiMedia Card with some additions. SD slots can
actually be used for more than flash memory cards. Devices that support SDIO can use small
devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters,
modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cameras and
more.
SD/SDIO is covered by numerous patents and trademarks, and licensing is only available
through the Secure Digital Card Association.
The SD/SDIO Card communication is based on a nine-pin interface (Clock, Command,
four Data and three Power lines). The communication protocol is defined as a part of this speci-
fication. The main difference between the SD/SDIO Card and the MultiMedia Card is the
initialization process.
The SD/SDIO Card Register (SDCR) allows selection of the Card Slot (SDCSEL) and the data
bus width (SDCBUS).
The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power
up, by default, the SD/SDIO Card uses only DAT[0] for data transfer. After initialization, the host
can change the bus width (number of active data lines).
31.6.5.1 SDIO Data Transfer Type
SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format
(1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The
CMDR.TRTYP field allows to choose between SDIO Byte or SDIO Block transfer.
The number of bytes/blocks to transfer is set through the BCNT field in the BLKR register. In
SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not
used in SDIO Byte mode.
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An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within
a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share
access to the SD bus. In order to allow the sharing of access to the host among multiple devices,
SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the
SDIO Specification for more details). To send a suspend or a resume command, the host must
set the SDIO Special Command field in CMDR register (CMDR.IOSPCMD).
31.6.5.2 SDIO Interrupts
Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO
Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt
function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO
interrupt on each slot can be enabled in the IER register. The SDIO interrupt is sampled regard-
less of the currently selected slot.
31.6.6 CE-ATA Operation
CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is
mapped onto MMC register space.
CE-ATA utilizes five MMC commands:
• GO_IDLE_STATE (CMD0): used for hard reset.
• STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be
aborted.
• FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, eight bit
access only.
• RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the
control/status registers.
• RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command.
CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC
devices.
31.6.6.1 Executing an ATA Polling Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of
DATA.
2. Read the ATA status register until DRQ is set.
3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
4. Read the ATA status register until DRQ && BSY are set to 0.
31.6.6.2 Executing an ATA Interrupt Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of
DATA with the IEN field written to zero to enable the command completion signal in the
device.
2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
3. Wait for Completion Signal Received Interrupt.
31.6.6.3 Aborting an ATA Command
If the host needs to abort an ATA command prior to the completion signal it must send a special
command to avoid potential collision on the command line. The Special Command field of
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CMDR register (CMDR.SPCMD) must be set to three to issue the CE-ATA completion Signal
Disable Command.
31.6.6.4 CE-ATA Error Recovery
Several methods of ATA command failure may occur, including:
• No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
• CRC is invalid for an MMC command or response.
• CRC16 is invalid for an MMC data packet.
• ATA Status register reflects an error by setting the ERR bit to one.
• The command completion signal does not arrive within a host specified time out period.
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism
may be used for each error event. The recommended error recovery procedure after a time-out
is:
• Issue the command completion signal disable if IEN was cleared to zero and the
RW_MULTIPLE_BLOCK (CMD61) response has been received.
• Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
• Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA com-
mands. However, if the error recovery procedure does not work as expected or there is another
time-out, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE
(CMD0) is a hard reset to the device and completely resets all device states.
Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed
again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command
with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA
command itself failed implying that the device could not complete the action requested, how-
ever, there was no communication or protocol failure. After the device signals an error by setting
the ERR bit to one in the ATA Status register, the host may attempt to retry the command.
31.6.7 MCI Boot Operation Mode
In boot operation mode, the processor can read boot data from the slave (MMC device) by keep-
ing the CMD line low after power-on before issuing CMD1. The data can be read from either
boot area or user area depending on register setting.
31.6.7.1 Boot Procedure, processor mode
1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR regis-
ter. The BOOT_BUS_WIDTH field located in the device Extended CSD register must
be set accordingly.
2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-
ing BLKLEN and BCNT fields of the MCI_BLKR Register.
3. Issue the Boot Operation Request command by writing to the MCI_CMDR register with
SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
4. The BOOT_ACK field located in the MCI_CMDR register must be set to one, if the
BOOT_ACK field of the MMC device located in the Extended CSD register is set to one.
5. Host processor can copy boot data sequentialy as soon as the RXRDY flag is asserted.
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6. When Data transfer is completed, host processor shall terminate the boot stream by
writing the MCI_CMDR register with SPCMD field set to BOOTEND.
31.6.7.2 Boot Procedure, dma mode
1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR regis-
ter. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set
accordingly.
2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-
ing BLKLEN and BCNT fields of the MCI_BLKR Register.
3. Enable DMA transfer in the MCI_DMA register.
4. Configure DMA controller, program the total amount of data to be transferred and
enable the relevant channel.
5. Issue the Boot Operation Request command by writing to the MCI_CMDR register with
SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.
6. DMA controller copies the boot partition to the memory.
7. When DMA transfer is completed, host processor shall terminate the boot stream by
writing the MCI_CMDR register with SPCMD field set to BOOTEND.
31.6.8 MCI Transfer Done Timings
31.6.8.1 Definition
The SR.XFRDONE bit indicates exactly when the read or write sequence is finished.
31.6.8.2 Read Access
During a read access, the SR.XFRDONE bit behaves as shown in Figure 31-13 on page 840.
Figure 31-13. SR.XFRDONE During a Read Access
CMD line
MCI read CMD Card response
The CMDRDY flag is released 8 tbit lafter the end of the card response.
CMDRDY flag
Data
1st Block Last Block
Not busy flag
XFRDONE flag
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31.6.8.3 Write Access
During a write access, the SR.XFRDONE bit behaves as shown in Figure 31-14 on page 841.
Figure 31-14. SR.XFRDONE During a Write Access
CMD line
MCI writeCMD Card response
CMDRDY flag The CMDRDY flag is released 8 tbit lafter the end of the card response.
D0 D0 is tied by the card
D0 is released
1st Block Last Block
Data bus - D0
1st Block Last Block
Not busy flag
XFRDONE flag
31.7 User Interface
Table 31-7. MCI Register Memory Map
Offset Register Name Access Reset
0x000 Control Register CR Write-only 0x00000000
0x004 Mode Register MR Read-write 0x00000000
0x008 Data Time-out Register DTOR Read-write 0x00000000
0x00C SD/SDIO Card Register SDCR Read-write 0x00000000
0x010 Argument Register ARGR Read-write 0x00000000
0x014 Command Register CMDR Write-only 0x00000000
0x018 Block Register BLKR Read-write 0x00000000
0x01C Completion Signal Time-out Register CSTOR Read-write 0x00000000
0x020 Response Register RSPR Read-only 0x00000000
0x024 Response Register RSPR1 Read-only 0x00000000
0x028 Response Register RSPR2 Read-only 0x00000000
0x02C Response Register RSPR3 Read-only 0x00000000
0x030 Receive Data Register RDR Read-only 0x00000000
0x034 Transmit Data Register TDR Write-only 0x00000000
0x040 Status Register SR Read-only 0x0C000025
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Table 31-7. MCI Register Memory Map
Offset Register Name Access Reset
0x044 Interrupt Enable Register IER Write-only 0x00000000
0x048 Interrupt Disable Register IDR Write-only 0x00000000
0x04C Interrupt Mask Register IMR Read-only 0x00000000
0x050 DMA Configuration Register DMA Read-write 0x00000000
0x054 Configuration Register CFG Read-write 0x00000000
0x0E4 Write Protection Mode Register WPMR Read-write 0x00000000
0x0E8 Write Protection Status Register WPSR Read-only 0x00000000
0x0FC Version Register VERSION Read-only - (1)
0x200-0x3FFC FIFO Memory Aperture – Read-write 0x00000000
1. The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter.
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31.7.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x000
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
SWRST - IOWAITDIS IOWAITEN PWSDIS PWSEN MCIDIS MCIEN
• SWRST: Software Reset
Writing a one to this bit will reset the MCI interface.
Writing a zero to this bit has no effect.
• IOWAITDIS: SDIO Read Wait Disable
Writing a one to this bit will disable the SDIO Read Wait Operation.
Writing a zero to this bit has no effect.
• IOWAITEN: SDIO Read Wait Enable
Writing a one to this bit will enable the SDIO Read Wait Operation.
Writing a zero to this bit has no effect.
• PWSDIS: Power Save Mode Disable
Writing a one to this bit will disable the Power Saving Mode.
Writing a zero to this bit has no effect.
• PWSEN: Power Save Mode Enable
Writing a one to this bit and a zero to PWSDIS will enable the Power Saving Mode.
Writing a one to this bit and a one to PWSDIS will disable the Power Saving Mode.
Writing a zero to this bit has no effect.
Warning: Before enabling this mode, the user must write a value different from 0 to the PWSDIV field.
• MCIDIS: Multi-Media Interface Disable
Writing a one to this bit will disable the Multi-Media Interface.
Writing a zero to this bit has no effect.
• MCIEN: Multi-Media Interface Enable
Writing a one to this bit and a zero to MCIDIS will enable the Multi-Media Interface.
Writing a one to this bit and a one to MCIDIS will disable the Multi-Media Interface.
Writing a zero to this bit has no effect.
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31.7.2 Mode Register
Name: MR
Access Type: Read-write
Offset: 0x004
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
BLKLEN[15:8]
23 22 21 20 19 18 17 16
BLKLEN[7:0]
15 14 13 12 11 10 9 8
- PADV FBYTE WRPROOF RDPROOF PWSDIV
7 6 5 4 3 2 1 0
CLKDIV
• BLKLEN[15:0]: Data Block Length
This field determines the size of the data block.
This field is also accessible in the BLKR register.
If FBYTE bit is zero, the BLKEN[1:0] field must be written to 0b00
Notes: 1. In SDIO Byte mode, BLKLEN field is not used.
2. BLKLEN should be written to one before sending the data transfer command. Otherwise,
Overrun may occur even if RDPROOF bit is one.
• PADV: Padding Value
0: 0x00 value is used when padding data in write transfer.
1: 0xFF value is used when padding data in write transfer.
PADV is used only in manual transfer.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allows byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
Writing a one to this bit will enable the Force Byte Transfer.
Writing a zero to this bit will disable the Force Byte Transfer.
• WRPROOF Write Proof Enable
Enabling Write Proof allows to stop the MCI Clock (CLK) during write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
Writing a one to this bit will enable the Write Proof mode.
Writing a zero to this bit will disable the Write Proof mode.
• RDPROOF Read Proof Enable
Enabling Read Proof allows to stop the MCI Clock (CLK) during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
Writing a one to this bit will enable the Read Proof mode.
Writing a zero to this bit will disable the Read Proof mode.
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• PWSDIV: Power Saving Divider
Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode.
Warning: This value must be different from zero before enabling the Power Save Mode in the CR register (CR.PWSEN).
• CLKDIV: Clock Divider
The Multimedia Card Interface Clock (CLK) is CLK_MCI divided by (2*(CLKDIV+1)).
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31.7.3 Data Time-out Register
Name: DTOR
Access Type: Read/Write
Offset: 0x008
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- DTOMUL DTOCYC
These two fields determine the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers.
It is equal to (DTOCYC x Multiplier).
If the data time-out defined by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error bit in the SR register
(SR.DTOE) is set.
• DTOMUL: Data Time-out Multiplier
Multiplier is defined by DTOMUL as shown in the following table
DTOMUL Multiplier
0 1
1 16
2 128
3 256
4 1024
5 4096
6 65536
7 1048576
• DTOCYC: Data Time-out Cycle Number
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31.7.4 SDCard/SDIO Register
Name: SDCR
Access Type: Read/Write
Offset: 0x00C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
SDCBUS – – – – SDCSEL
• SDCBUS: SDCard/SDIO Bus Width
SDCBUS BUS WIDTH
0 1 bit
1 Reserved
2 4 bits
3 8 bits
• SDCSEL: SDCard/SDIO Slot
SDCSEL SDCard/SDIO Slot
0 Slot A is selected.
1 Slot B is selected.
2 Reserved.
3 Reserved.
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31.7.5 Argument Register
Name: ARGR
Access Type: Read/Write
Offset: 0x010
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
ARG[31:24]
23 22 21 20 19 18 17 16
ARG[23:16]
15 14 13 12 11 10 9 8
ARG[15:8]
7 6 5 4 3 2 1 0
ARG[7:0]
• ARG[31:0]: Command Argument
this field contains the argument field of the command.
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31.7.6 Command Register
Name: CMDR
Access Type: Write-only
Offset: 0x014
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - BOOTACK ATACS IOSPCMD
23 22 21 20 19 18 17 16
- - TRTYP TRDIR TRCMD
15 14 13 12 11 10 9 8
- - - MAXLAT OPDCMD SPCMD
7 6 5 4 3 2 1 0
RSPTYP CMDNB
This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an
interrupt response (SPCMD field). This means that the current command execution cannot be interrupted or modified.
• BOOT_ACK: Boot Operation Acknowledge
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is isssued.
Writing a one to this bit indicates that a Boot acknolwedge is expected within a programmable amount of time defined with
DTOMUL and DTOCYC fields located in the DTOR register. If the acknowledge pattern is not received then an acknowledge
timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.
• ATACS: ATA with Command Completion Signal
Writing a one to this bit will configure ATA completion signal within a programmed amount of time in Completion Signal Time-out
Register (CSTOR).
Writing a zero to this bit will configure no ATA completion signal.
• IOSPCMD: SDIO Special Command
IOSPCMD SDIO Special Command Type
0 Not a SDIO Special Command
1 SDIO Suspend Command
2 SDIO Resume Command
3 Reserved
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• TRTYP: Transfer Type
TRTYP Transfer Type
0 MMC/SDCard Single Block
1 MMC/SDCard Multiple Block
2 MMC Stream
3 Reserved
4 SDIO Byte
5 SDIO Block
others Reserved
• TRDIR: Transfer Direction
Writing a zero to this bit will configure the transfer direction as write transfer.
Writing a one to this bit will configure the transfer direction as read transfer.
• TRCMD: Transfer Command
TRCMD Transfer Type
0 No data transfer
1 Start data transfer
2 Stop data transfer
3 Reserved
• MAXLAT: Max Latency for Command to Response
Writing a zero to this bit will configure a 5-cycle max latency.
Writing a one to this bit will configure a 64-cycle max latency.
• OPDCMD: Open Drain Command
Writing a zero to this bit will configure the push-pull command.
Writing a one to this bit will configure the open-drain command.
• SPCMD: Special Command
SPCMD Command
0 Not a special CMD.
Initialization CMD:
1
74 clock cycles for initialization sequence.
Synchronized CMD:
2
Wait for the end of the current data block transfer before sending the pending command.
CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the
3
command line.
Interrupt command:
4
Corresponds to the Interrupt Mode (CMD40).
Interrupt response:
5
Corresponds to the Interrupt Mode (CMD40).
others Reserved
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• RSPTYP: Response Type
RSP Response Type
0 No response.
1 48-bit response.
2 136-bit response.
3 R1b response type
• CMDNB: Command Number
The Command Number to transmit.
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31.7.7 Block Register
Name: BLKR
Access Type: Read/Write
Offset: 0x018
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
BLKLEN[15:8]
23 22 21 20 19 18 17 16
BLKLEN[7:0]
15 14 13 12 11 10 9 8
BCNT[15:8]
7 6 5 4 3 2 1 0
BCNT[7:0]
• BLKLEN: Data Block Length
This field determines the size of the data block.
This field is also accessible in the MR register.
If MR.FBYTE bit is zero, the BLKEN[17:16] field must be written to 0b00
Notes:
1. In SDIO Byte mode, BLKLEN field is not used.
2. BLKLEN should be specified before sending the data transfer command. Otherwise, Overrun
may occur (even if MR.RDPROOF bit is set).
• BCNT: MMC/SDIO Block Count - SDIO Byte Count
This field determines the number of data byte(s) or block(s) to transfer.
The transfer data type and the authorized values for BCNT field are determined by CMDR.TRTYP field:
TRTYP Type of Transfer BCNT Authorized Values
0 MMC/SDCard Multiple Block From 1 to 65535: Value 0 corresponds to an infinite block transfer.
From 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.
2 SDIO Byte
Values from 0x200 to 0xFFFF are forbidden.
From 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.
3 SDIO Block
Values from 0x200 to 0xFFFF are forbidden.
Others - Reserved.
Warning: In SDIO Byte and Block modes, writing to the seven last bits of BCNT field is forbidden and may lead to unpredictable
results.
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31.7.8 Completion Signal Time-out Register
Name: CSTOR
Access Type: Read-write
Offset: 0x01C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- CSTOMUL CSTOCYC
These two fields determines the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
These two fields also determine the maximum number of CLK_MCI cycles that the MCI waits between the end of the data
transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a
non-DATA ATA command is issued, the MCI starts waiting immediately after the end of the response until the completion signal.
If the data time-out defined by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error bit in the
SR register (SR.CSTOE) is set.
• CSTOMUL: Completion Signal Time-out Multiplier
Multiplier is defined by CSTOMUL as shown in the following table:
CSTOMUL Multiplier
0 1
1 16
2 128
3 256
4 1024
5 4096
6 65536
7 1048576
• CSTOCYC: Completion Signal Time-out Cycle Number
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31.7.9 Response Register n
Name: RSPRn
Access Type: Read-only
Offset: 0x020 + 0*0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
RSP[31:24]
23 22 21 20 19 18 17 16
RSP[23:16]
15 14 13 12 11 10 9 8
RSP[15:8]
7 6 5 4 3 2 1 0
RSP[7:0]
• RSP[31:0]: Response
The response register can be read by N access(es) at the same RSPRn or at consecutive addresses (0x20 + n*0x04).
N depends on the size of the response.
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31.7.10 Receive Data Register
Name: RDR
Access Type: Read-only
Offset: 0x030
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA[31:0]: Data to Read
The last data received.
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31.7.11 Transmit Data Register
Name: TDR
Access Type: Write-only
Offset: 0x034
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA[31:0]: Data to Write
The data to send.
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31.7.12 Status Register
Name: SR
Access Type: Read-only
Offset: 0x040
Reset Value: 0x0C000025
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT - - SDIOIRQB SDIOIRQA
7 6 5 4 3 2 1 0
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
• ACKRCVE: Boot Operation Acknowledge Error
This bit is set when a corrupted Boot Acknowlegde signal has been received.
This bit is cleared by reading the SR register.
• ACKRCV: Boot Operation Acknowledge Received
This bit is set when a Boot acknowledge signal has been received.
This bit is cleared by reading the SR register.
• UNRE: Underrun Error
This bit is set when at least one eight-bit data has been sent without valid information (not written).
This bit is cleared when sending a new data transfer command if the Flow Error bit reset control mode in Configuration Register
(CFG.FERRCTRL) is zero or when reading the SR register if CFG.FERRCTRL is one.
• OVRE: Overrun Error
This bit is set when at least one 8-bit received data has been lost (not read).
This bit is cleared when sending a new data transfer command if CFG.FERRCTRL is zero, or when reading the SR register if
CFG.FERRCTRL is one.
• XFRDONE: Transfer Done
This bit is set when the CR register is ready to operate and the data bus is in the idle state.
This bit is cleared when a transfer is in progress.
• FIFOEMPTY: FIFO empty
This bit is set when the FIFO is empty.
This bit is cleared when the FIFO contains at least one byte.
• DMADONE: DMA Transfer done
This bit is set when the DMA buffer transfer is completed.
This bit is cleared when reading the SR register.
• BLKOVRE: DMA Block Overrun Error
This bit is set when a new block of data is received and the DMA controller has not started to move the current pending block.
This bit is cleared when reading the SR register.
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• CSTOE: Completion Signal Time-out Error
This bit is set when the completion signal time-out defined by the CSTOR.CSTOCYC field and the CSTOR.CSTOMUL field is
reached.
This bit is cleared when reading the SR register.
• DTOE: Data Time-out Error
This bit is set when the data time-out defined by the DTOR.DTOCYC field and the DTOR.DTOMUL field is reached.
This bit is cleared when reading the SR register.
• DCRCE: Data CRC Error
This bit is set when a CRC16 error is detected in the last data block.
This bit is cleared when reading the SR register.
• RTOE: Response Time-out Error
This bit is set when the response time-out defined by the CMDR.MAXLAT bit is reached.
This bit is cleared when writing the CMDR register.
• RENDE: Response End Bit Error
This bit is set when the end bit of the response is not detected.
This bit is cleared when writing the CMDR register.
• RCRCE: Response CRC Error
This bit is set when a CRC7 error is detected in the response.
This bit is cleared when writing the CMDR register.
• RDIRE: Response Direction Error
This bit is set when the direction bit from card to host in the response is not detected.
This bit is cleared when writing the CMDR register.
• RINDE: Response Index Error
This bit is set when a mismatch is detected between the command index sent and the response index received.
This bit is cleared when writing the CMDR register.
• TXBUFE: TX Buffer Empty Status
This bit is set when the DMA Tx Buffer is empty.
This bit is cleared when the DMA Tx Buffer is not empty.
• RXBUFF: RX BUffer Full Status
This bit is set when the DMA Rx Buffer is full.
This bit is cleared when the DMA Rx Buffer is not full.
• CSRCV: CE-ATA Completion Signal Received
This bit is set when the device issues a command completion signal on the command line.
This bit is cleared when reading the SR register.
• SDIOWAIT: SDIO Read Wait Operation Status
This bit is set when the data bus has entered IO wait state.
This bit is cleared when normal bus operation.
• SDIOIRQB: SDIO Interrupt for Slot B
This bit is cleared when reading the SR register.
This bit is set when a SDIO interrupt on Slot B occurs.
• SDIOIRQA: SDIO Interrupt for Slot A
This bit is set when a SDIO interrupt on Slot A occurs.
This bit is cleared when reading the SR register.
• ENDTX: End of RX Buffer
This bit is set when the DMA Controller transmission is finished.
This bit is cleared when the DMA Controller transmission is not finished.
• ENDRX: End of RX Buffer
This bit is set when the DMA Controller reception is finished.
This bit is cleared when the DMA Controller reception is not finished.
• NOTBUSY: MCI Not Busy
This bit must be used only for write operations.
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A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data
transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line
(DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer
block length becomes free.
The NOTBUSY bit allows to deal with these different states.
1: MCI is ready for new data transfer.
0: MCI is not ready for new data transfer.
This bit is cleared at the end of the card response.
This bit is set when the busy state on the data line is ended. This corresponds to a free internal data receive buffer of the card.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
• DTIP: Data Transfer in Progress
This bit is set when the current data transfer is in progress.
This bit is cleared at the end of the CRC16 calculation
1: The current data transfer is still in progress.
0: No data transfer in progress.
• BLKE: Data Block Ended
This bit must be used only for Write Operations.
This bit is set when a data block transfer has ended.
This bit is cleared when reading SR.
1: a data block transfer has ended, including the CRC16 Status transmission, the bit is set for each transmitted CRC Status.
0: A data block transfer is not yet finished.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
• TXRDY: Transmit Ready
This bit is set when the last data written in the TDR register has been transferred.
This bit is cleared the last data written in the TDR register has not yet been transferred.
• RXRDY: Receiver Ready
This bit is set when the data has been received since the last read of the RDR register.
This bit is cleared when the data has not yet been received since the last read of the RDR register.
• CMDRDY: Command Ready
This bit is set when the last command has been sent.
This bit is cleared when writing the CMDR register
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31.7.13 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x044
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFF RXBUFF CSRCV SDIOWAIT - - SDIOIRQB SDIOIRQA
7 6 5 4 3 2 1 0
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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31.7.14 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x048
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFF RXBUFF CSRCV SDIOWAIT - - SDIOIRQB SDIOIRQA
7 6 5 4 3 2 1 0
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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31.7.15 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x04C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFF RXBUFF CSRCV SDIOWAIT - - SDIOIRQB SDIOIRQA
7 6 5 4 3 2 1 0
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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31.7.16 DMA Configuration Register
Name: DMA
Access Type: Read/Write
Offset: 0x050
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - DAMEN
7 6 5 4 3 2 1 0
- CHKSIZE - - OFFSET
• DMAEN: DMA Hardware Handshaking Enable
1: DMA Interface is enabled.
0: DMA interface is disabled.
To avoid unpredictable behavior, DMA hardware handshaking must be disabled when CPU transfers are performed.
To avoid data losses, the DMA register should be initialized before sending the data transfer command. This is also illustrated in
Figure 31-10 on page 831 or Figure 31-11 on page 833
• CHKSIZE: DMA Channel Read and Write Chunk Size
The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted.
CHKSIZE value Number of data transferred
0 1 Only available if FIFO_SIZE>= 16 bytes
1 4 Only available if FIFO_SIZE>= 32 bytes
2 8 Only available if FIFO_SIZE>= 64 bytes
3 16 Only available if FIFO_SIZE>= 128 bytes
4 32 Only available if FIFO_SIZE>= 256 bytes
others - Reserved
• OFFSET: DMA Write Buffer Offset
This field indicates the number of discarded bytes when the DMA writes the first word of the transfer.
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31.7.17 Configuration Register
Name: CFG
Access Type: Read/Write
Offset: 0x054
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - LSYNC - - - HSMODE
7 6 5 4 3 2 1 0
- - - FERRCTRL - - - FIFOMODE
• LSYNC: Synchronize on the last block
1: The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be
different from zero)
0: The pending command is sent at the end of the current data block.
This register needs to configured before sending the data transfer command.
• HSMODE: High Speed Mode
1: The host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the
high speed support in the card registers.
0: Default bus timing mode.
• FERRCTRL: Flow Error bit reset control mode
1: When an underflow/overflow condition bit is set, reading SR resets the bit.
0: When an underflow/overflow condition bit is set, a new Write/Read command is needed to reset the bit.
• FIFOMODE: MCI Internal FIFO control mode
1: A write transfer starts as soon as one data is written into the FIFO.
0: A write transfer starts when a sufficient amount of data is written into the FIFO.
When the block length is greater than or equal to 3/4 of the MCI internal FIFO size, then the write transfer starts as soon as half
the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as
soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the
internal FIFO.
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31.7.18 Write Protect Mode Register
Name: WPMR
Access Type: Read/Write
Offset: 0x0E4
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
WPKEY[23:16]
23 22 21 20 19 18 17 16
WPKEY[15:8]
15 14 13 12 11 10 9 8
WPKEY[7:0]
7 6 5 4 3 2 1 0
- - - - - - - WPEN
• WPKEY[23:0]: Write Protection Key password
This field should be written at value 0x4D4349 (ASCII code for “MCI”).
Writing any other value in this field has no effect.
• WPEN: Write Protection Enable
1: This bit enables the Write Protection if WPKEY corresponds.
0: This bit disables the Write Protection if WPKEY corresponds.
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31.7.19 Write Protect Status Register
Name: WPSR
Access Type: Read-only
Offset: 0x0E8
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
WPVSRC[15:8]
15 14 13 12 11 10 9 8
WPVSRC[7:0]
7 6 5 4 3 2 1 0
- - - - WPVS
• WPVSRC[15:0]: Write Protection Violation Source
This field contains address where the violation access occurs.
• WPVS: Write Protection Violation Status
WPVS Definition
No Write Protection Violation occurred since the last read of this
0
register (WPSR)
Write Protection detected unauthorized attempt to write a control
1
register had occurred (since the last read.)
Software reset had been performed while Write Protection was
2
enabled (since the last read).
Both Write Protection violation and software reset with Write
3
Protection enabled had occurred since the last read.
others Reserved
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31.7.20 Version Register
Name: VERSION
Access: Read-only
Offset: 0x0FC
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associate
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31.7.21 FIFO Memory Aperture
Name: -
Access: Read/Write
Offset: 0x200 - 0x3FFC
Reset Value: 0x000000000
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
7 6 5 4 3 2 1 0
DATA[7:0]
• DATA[31:0]:Data to read or Data to write
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31.8 Module Configuration
The specific configuration for the MCI instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks according to the table in the Power
Manager section.
Table 31-8. Module Clock Name
Module name Clock name
MCI CLK_MCI
Table 31-9. Parameter Value
Name Value
FIFO_SIZE 128
Table 31-10. Register Reset Values
Register Reset Value
VERSION 0x00000410
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32. Memory Stick Interface (MSI)
Rev: 2.1.0.0
32.1 Features
• Memory Stick ver. 1.x & Memory Stick PRO support
• Memory Stick serial clock (serial mode: 20 MHz max., parallel mode: 40 MHz max.)
• Data transmit/receive FIFO of 64 bits x 4
• 16 bits CRC circuit
• DMACA transfer support
• Card insertion/removal detection
32.2 Overview
The Memory Stick Interface (MSI) is a host controller that supports Memory Stick Version 1.X
and Memory Stick PRO.
The communication protocol with the Memory Stick is started by write from the CPU to the com-
mand register. When the protocol finishes, the CPU is notified that the protocol has ended by an
interrupt request. When the protocol is started and enters the data transfer state, data is
requested by issuing a DMA transfer request (via DMACA) or an interrupt request to the CPU.
The RDY time out time when the handshake state (BS2 in read protocol, BS3 for write protocol)
is established in communication with the Memory Stick can be designated as the number of
Memory Stick transfer clocks. When a time out occurs, the CPU is notified that the protocol has
ended due to a time out error by an interrupt request.
CRC circuit can be set off for test mode purpose. When CRC is off, CRC is not added to the data
transmitted to the Memory Stick.
An interrupt request can also be issued to the CPU when a Memory Stick is inserted or removed.
Figure 32-1. Read packet
BS0 BS1 BS2 BS3 BS0
BS
Memory Stick Host Memory Stick
SDIO / DATA[3:0] INT TPC RDY/BSY DATA CRC INT
SCLK
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Figure 32-2. Write packet
BS0 BS1 BS2 BS3 BS0
BS
Memory Stick Host Memory Stick
SDIO / DATA[3:0] INT TPC DATA CRC RDY/BSY INT
SCLK
32.3 Block Diagram
Figure 32-3. MSI block diagram
CLK_MSI
PB
÷ Registers
INS
SDIO / DATA0
DATA1
FIFO
DATA2 64 x 4
MS I/F
DATA3
SCLK
BS Data buffer
32.4 Product Dependencies
32.4.1 GPIO
SCLK, DATA[3..0], BS & INS are I/O lines, multiplexed with other I/O lines. The I/O controller
must be configured so that MSI can drive these I/O lines.
32.4.2 Power Manager
MSI is clocked through the Power Manager (PM), thus programmer must first configure the PM
to enable the CLK_MSI clock.
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32.4.3 Interrupt Controller
MSI interrupt line is connected to the Interrupt Controller. In order to handle interrupts, Interrupt
Controller(INTC) must be programmed before configuring MSI.
32.4.4 DMA Controller (DMACA)
Handshake signals are connected to DMACA. In order to accelerate transfer from/to flash card,
DMACA must be programmed before using MSI.
32.5 Connection to a Memory Stick
The Memory Stick serial clock (SCLK) is maximum 20 MHz in serial mode, and maxi-
mum 40 MHz in parallel mode. SCLK is derived from peripheral clock (CLK_MSI) :
f_SCLK = f_CLK_MSI / [2*(CLKDIV+1)] where CLKDIV = {0..255}.
Pin DATA[1] is a power supply for some Memory Stick version, so leaving the pull-
down resistor connected may result in wasteful current consumption. User should leave
the DATA[1] pin pull-down open when Memory Stick Ver. 1.x is inserted.
Table 32-1. Memory Stick pull-down configuration
Memory Stick 1.x Memory Stick PRO
Memory Stick inserted Pull-down open Pull-down enabled
Memory Stick removed Pull-down enabled Pull-down enabled
Figure 32-4. Memory Stick pull-down overview
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32.6 Functional Description
32.6.1 Reset Operation
An internal reset (initialization of the internal registers and operating sequence) is performed
when PB reset is active or by setting SYS.RST=1. RST bit is cleared to 0 after the internal reset
is completed.
The protocol currently being executed stops, and the internal operating sequence is initialized.
In addition, the FIFO is set to the empty state (SR.EMP=1, SR.FUL=0).
However, when the host controller is reset during communication with the Memory Stick, the
resulting bus state may differ from the Memory Stick. Therefore, when reset is performed during
communication, also power-on-reset the Memory Stick.
Internal registers are initialized to their initial value. However, some bits in following registers are
not affected by RST bit :
• SYS : CLKDIV[7:0],
• ISR : all bits but DRQ,
• SR : ISTA,
• IMR : all bits.
32.6.2 Communication with the Memory Stick
An example of communication with the Memory Stick is shown below. This example shows the
case when Transfer Protocol Command (TPC) SET_CMD is executed.
– Enable PEND and MSINT interrupt requests (write PEND=1, MSINT=1 in IER).
– Set FIFO direction to “CPU to MS” (write FDIR=1 in SYS).
– Write the command data to the FIFO (write DAT).
– Write the TPC and the data transfer size to the command register to start the
protocol (write CMD).
– After the protocol ends, an interrupt request is output from the host controller
(PEND=1 in ISR). To acknowledge this interrupt request, CPU must clear the source
of interrupt by writing PEND=1 in ISCR.
– Some TPC commands require additional time to be executed by Memory Stick
therefore INT can appear later after protocol end. After INT generation, an interrupt
request is output from the host controller (MSINT=1 in ISR). To acknowledge this
interrupt request, CPU must clear the source of interrupt by writing MSINT=1 in
ISCR.
When the command register is written, the communication protocol with the Memory Stick starts
and data transmit/receive is performed.
The data transfer direction is determined from TPC[3]. When TPC[3]=0, the read protocol is per-
formed, and when TPC[3]=1, the write protocole is performed. When TPC[3] and FDIR bit differ,
the TPC[3] value is reflected to system register bit FDIR when the protocol starts.
FIFO can be written after protocol start therefore data must be written each time ISR.DRQ=1.
Even when the data is less than 8 bytes, always read and write 8 bytes of data. All interrupt
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sources can be cleared by setting corresponding bit in ISCR but DRQ which is cleared once
FIFO has been read/written.
Figure 32-5. Communication example
CPU MSI
PEND=1, MSINT=1
Interrupt enable MSIER register
FDIR=1
FIFO direction setting MSSYS register
CMD
Write to FIFO MSDAT register
TPC = SET_CMD
TPC setting MSCMD register
Interrupt wait Protocol start
Communication
with Memory Stick
MSISR.PEND=1
Protocol end
PEND=1
Interrupt clear MSISCR register
Interrupt wait MS INT wait
INT from
Memory Stick
MSISR.MSINT=1
INT received
MSINT=1
Interrupt clear MSISCR register
32.6.3 Parallel Interface Mode Setting Procedure
Host controller supports parallel mode and must be set to parallel interface mode after the Mem-
ory Stick.
– Identify the Memory Stick media and confirm it is a Memory Stick PRO. For Memory
stick media identification, see “Memory Stick Standard Format Specifications ver.
1.X Appendix D” or “Memory Stick Standard Format Specifications ver. 2.0
Application Notes 1.3 Media Identification Process”.
– Set the Memory Stick to parallel interface mode by executing TPC commands
SET_R/W_REG_ADRS then WRITE_REG to set System Parameter bit PAM=1.
– Write SRAC=0 and REI=0 to the system register (SYS) to switch host controller to
parallel interface mode.
– Change serial clock (SCLK) while communication is not being performed with the
Memory Stick.
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Figure 32-6. Interface mode switching sequence
Serial Interface Mode
(MSSYS.SRAC=1, MSSYS.REI=1)
SET_R/W_REG_ADRS TPC
WRITE_REG TPC
system parameter
(PAM bit) Error
OK
Set Parallel Interface Mode
(MSSYS.SRAC=0, MSSYS.REI=0)
Change SCLK
(MSSYS.CLKDIV[7:0]=X)
32.6.4 Data transfer requests
After the communication protocol with the Memory Stick starts, a data transfer request is
asserted to the CPU (DRQ bit in ISR) and to DMACA (internal signals), until data transfer of the
amount indicated by DSZ (CMD) is finished. However, the data transfer request stops when the
internal FIFO becomes either empty or full.
Like CPU, DMACA uses Peripheral Bus to access FIFO so it is not recommended to access MSI
registers during transfer. It is also not recommended to enable DRQ interrupt because ISR.DRQ
bit is automatically cleared when FIFO is accessed.
DMACA channel should be configured first and the data size should be a multiple of 64 bits
(FIFO size is 4 * 64bits).
32.6.5 Interrupts
The interrupt sources of MSI are :
• PEND : protocol command ended without error.
• DRQ : data request, FIFO is full or empty.
• MSINT : interrupt received from Memory Stick.
• CRC : protocol ended with CRC error.
• TOE : protocol ended with time out error.
• CD : card detected (inserted or removed).
Each interrupt source can be enabled in Interrupt Enable register (IER) and disabled in Interrupt
Disable register (IDR). The enable status is read in Interrupt Mask register (IMR). The status of
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the interrupt source, even if the interrupt is masked, can be read in ISR.
DRQ interrupt request is cleared by reading (reception) or writing (transmission) FIFO, other
interrupt requests are cleared by writing 1 to the corresponding bit in Interrupt Status Clear Reg-
ister (ISCR).
32.6.6 OCD mode
There is no OCD mode for MSI.
32.7 User Interface
Table 32-2. MSI Register Memory Map
Offset Register Name Access Reset State
0x0000 Command register CMD Read/Write 0x00000000
0x0004 Data register DAT Read/Write 0x4C004C00
0x0008 Status register SR Read Only 0x00001020
0x000C System register SYS Read/Write 0x00004015
0x0010 Interrupt Status register ISR Read Only 0x00000000
0x0014 Interrupt Status Clear register ISCR Write Only 0x00000000
0x0018 Interrupt Enable register IER Write Only 0x00000000
0x001C Interrupt Disable register IDR Write Only 0x00000000
0x0020 Interrupt Mask register IMR Read Only 0x00000000
0x0024 Version register VERSION Read Only 0x00000210
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32.7.1 Command register
Name : CMD
Access Type : Read/Write
Offset : 0x00
Reset Value : 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TPC - DSL DSZ
7 6 5 4 3 2 1 0
DSZ
• TPC : Transfer Protocol Code.
code (dec) TPC Description
2 READ_LONG_DATA Transfer data from Data Buffer (512 bytes)
3 READ_SHORT_DATA Transfer data from Data Buffer (32~256 bytes)
4 READ_REG Read from a register
7 GET_INT Read from an INT register
8 SET_R/W_REG_ADRS Set an address of READ_REG/WRITE_REG
9 EX_SET_CMD Set command and parameters
11 WRITE_REG Write to a register
12 WRITE_SHORT_DATA Transfer data to Data Buffer (32~256 bytes)
13 WRITE_LONG_DATA Transfer data to Data Buffer (512 bytes)
14 SET_CMD Set command
other - Banned for use
TPC[3] indicates the transfer direction of data (1:write packet, 0:read packet)
• DSL : Data Select.
0 : Data is transmitted to and received from Memory Stick using the internal FIFO.
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1 : Reserved.
• DSZ : Data size.
Length can be set from 1 byte to 1024 bytes. However, 1024 bytes is set when DSZ=0.
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32.7.2 Data register
Name : DAT
Access Type : Read/Write
Offset : 0x04
Reset Value : 0x4C004C00
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
7 6 5 4 3 2 1 0
DATA
This register is used to acces internal FIFO.
Even when the data is less than 8 bytes, always read and write 8 bytes of data.
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32.7.3 Status register
Name : SR
Access Type : Read Only
Offset : 0x08
Reset Value : 0x00001020
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - ISTA
15 14 13 12 11 10 9 8
- - - RDY - - - -
7 6 5 4 3 2 1 0
- - EMP FUL CED ERR BRQ CNK
• ISTA : Insertion Status. It reflects the Memory Stick card presence. This is the inverse of INS pin.
0 : No card.
1 : Card is inserted.
• RDY : Ready. RDY goes to 1 when the protocol ends. This bit bit is cleared to 0 by write to the command register.
0 : Command receive disabled due to communication with the Memory Stick.
1 : Command received or protocol ended.
• EMP : FIFO Empty. This bit is set to 1 by writing system register bit FCLR=1.
0 : FIFO contains data.
1 : FIFO is empty.
• FUL : FIFO Full. This bit is cleared to 0 by writing system register bit FCLR=1.
0 : FIFO has empty space.
1 : FIFO is full.
• CED : MS Command End.
In parallel mode, this bit reflects the CED bit in the status register of a Memory Stick (INT). Indicates the end of a
command executed with SET_CMD TPC. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command
register (CMD).
• ERR : Memory Stick Error.
In parallel mode, this bit reflects the ERR bit in the status register of a Memory Stick (INT). It indicates the occurence
of an error. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD).
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• BRQ : MS Data Buffer Request.
In parallel mode, this bit reflects the BREQ bit in the status register of a Memory Stick (INT). It indicates that a host
has requested to access a Memory Sticks page buffer.In serial mode, this bit is always 0. It is cleared to 0 by writing to the
command register (CMD).
• CNK : MS Command No Acknowledge.
In parallel mode, this bit reflects the CMDNK bit in the status register of a Memory Stick (INT). It indicates that the
command cannot be executed. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register
(CMD).
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32.7.4 System register
Name : SYS
Access Type : Read/Write
Offset : 0x0C
Reset Value : 0x00004015
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
CLKDIV
15 14 13 12 11 10 9 8
RST SRAC - NOCRC - - FCLR FDIR
7 6 5 4 3 2 1 0
- - - REI REO BSY
• CLKDIV : Clock Division.
Write this field to change SCLK frequency = CLK_MSI / (2*(CLKDIV+1)).
• RST : Reset. When RST is written, internal synchronous reset is performed.
0 : This bit is cleared to 0 after the internal reset is completed.
1 : Writing a 1 starts reset operation.
• SRAC : Serial Access Mode. The SRAC cannot be changed during protocol execution.
0 : Write this bit to 0 to set parallel mode.
1 : Write this bit to 1 to set serial mode.
• NOCRC : No CRC computation.
0 : Write 0 to enable CRC output. During read protocol, the CRC check is performed as usual regardless of NOCRC.
1 : Write 1 to disable CRC output. When NOCRC=1, the write protocol is executed without adding the CRC data.
• FCLR : FIFO clear.
Write 1 to initialize FIFO data. This bit is cleared after the FIFO is initialized.
• FDIR : FIFO direction.
0 : Write 0 to set the FIFO direction to transmit.
1 : Write 1 to set the FIFO direction to receive.
• REI : Rising Edge Input. When setting parallel mode, set REI=0. This setting cannot be changed during protocol execution.
0 : Write 0 to sample data at the falling edge of SCLK.
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1 : Write 1 to sample data at the rising edge of SCLK.
• REO : Rising Edge output. This bit is used when not fixed hold time by the side of the Memory Stick in parallel
communication. This setting cannot be changed during protocol execution.
0 : Write 0 to synchronize outputs with the falling edge of SCLK.
1 : Write 1 to synchronize outputs with the rising edge of SCLK.
• BSY : Busy Count. This is the maximum BSY wait time until the RDY signal is output from the Memory Stick.
0 : Write a value to configure time out = BSY * 4 SCLK.
1 : Write 0 to disable time out detection.
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32.7.5 Interrupt Status register
Name : ISR
Access Type : Read Only
Offset : 0x10
Reset Value : 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - CD TOE CRC MSINT DRQ PEND
• CD : Card Detection.
0 : No card detected. This bit is cleared when the correponding bit in ISCR is set to 1.
1 : This bit is set to 1 when a Memory Stick card is inserted or removed.
• TOE : Time Out Error.
0 : This bit is cleared to 0 when the corresponding bit in ISCR it set to 1.
1 : This bit is set to 1 when protol ended with time out error.
• CRC : CRC error.
0 : No CRC error. This bit is cleared when the corresponding bit in ISCR is set to 1.
1 : This bit is set when protocol ends with CRC error.
• MSINT : Memory Stick interruption.
0 : This bit is cleared to 0 when the corresponding bit in ISCR is set to 1.
1 : This bit is set to 1 when an interrupt request INT is received from Memory Stick.
• DRQ : Data request, FIFO is full (reception) or empty (transmission).
0 : This bit is cleared to 0 when data access is no more required.
1 : This bit is set to 1 when data access is required (read or write).
• PEND : Protocol End.
0 : This bit is cleared to 0 when the corresponding bit in ISCR is set to 1.
1 : This bit is set to 1 when protol ended witout error.
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32.7.6 Interrupt Status Clear register
Name : ISCR
Access Type : Write Only
Offset : 0x14
Reset Value : 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - CD TOE CRC MSINT - PEND
• CD : Card Detection clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
• TOE : Time Out Error clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
• CRC : CRC error clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
• MSINT : Memory Stick interruption clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
• PEND : Protocol End clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
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32.7.7 Interrupt Enable register
Name : IER
Access Type : Write Only
Offset : 0x18
Reset Value : 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - CD TOE CRC MSINT DRQ PEND
• CD : Card Detection interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
• TOE : Time Out Error interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
• CRC : CRC error interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
• MSINT : Memory Stick interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
• DRQ : Data Request interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
• PEND : Protocol End interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
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32.7.8 Interrupt Disable register
Name : IDR
Access Type : Write Only
Offset : 0x1C
Reset Value : 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - CD TOE CRC MSINT DRQ PEND
• CD : Card Detection interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
• TOE : Time Out Error interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
• CRC : CRC error interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
• MSINT : Memory Stick interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
• DRQ : Data Request interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
• PEND : Protocol End interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
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32.7.9 Interrupt Mask register
Name : IMR
Access Type : Read Only
Offset : 0x20
Reset Value : 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - CD TOE CRC MSINT DRQ PEND
• CD : Card Detection interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
• TOE : Time Out Error interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
• CRC : CRC error interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
• MSINT : Memory Stick interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
• DRQ : Data Request interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
• PEND : Protocol End interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
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32.7.10 Version Register
Name : VERSION
Access Type : Read Only
Offset : 0x24
Reset Value : 0x00000210
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION : Version Number
Version number of the module. No functionality associated.
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33. Advanced Encryption Standard (AES)
Rev: 1.2.3.1
33.1 Features
• Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
• 128-bit/192-bit/256-bit cryptographic key
• 12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256-bit
cryptographic key
• Support of the five standard modes of operation specified in the NIST Special Publication 800-
38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques:
– Electronic Code Book (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
– Counter (CTR)
• 8-, 16-, 32-, 64- and 128-bit data size possible in CFB mode
• Last output data mode allows optimized Message Authentication Code (MAC) generation
• Hardware counter measures against differential power analysis attacks
• Connection to DMA Controller capabilities optimizes data transfers for all operating modes
33.2 Overview
The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Infor-
mation Processing Standard) Publication 197 specification.
The AES supports all five confidentiality modes of operation for symmetrical key block cipher
algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-
38A Recommendation. It is compatible with all these modes via DMA Controller, minimizing pro-
cessor intervention for large buffer transfers.
The 128-bit/192-bit/256-bit key is stored in write-only four/six/eight 32-bit KEY Word Registers
(KEYWnR) which are all write-only registers.
The 128-bit input data and initialization vector (for some modes) are each stored in 32-bit Input
Data Registers (IDATAnR) and in Initialization Vector Registers (VnR) which are all write-only
registers.
As soon as the initialization vector, the input data and the key are configured, the encryp-
tion/decryption process may be started. Then the encrypted/decrypted data is ready to be read
out on the four 32-bit Output Data Registers (ODATAnR) or through the DMA Controller.
33.3 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
33.3.1 Power Management
If the CPU enters a sleep mode that disables clocks used by the AES, the AES will stop function-
ing and resume operation after the system wakes up from sleep mode.
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33.3.2 Clocks
The clock for the AES bus interface (CLK_AES) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
AES before disabling the clock, to avoid freezing the AES in an undefined state.
33.3.3 Interrupts
The AES interrupt request line is connected to the interrupt controller. Using the AES interrupt
requires the interrupt controller to be programmed first.
33.4 Functional Description
The AES specifies a FIPS-approved cryptographic algorithm that can be used to protect elec-
tronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and
decrypt (decipher) information.
Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext
converts the data back into its original form, called plaintext. The Processing Mode bit in the
Mode Register (MR.CIPHER) allows selection between the encryption and the decryption
processes.
The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data
in blocks of 128 bits. This 128-bit/192-bit/256-bit key is defined in the KEYWnR Registers
(KEYWnR).
The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to
the plaintext, a 128-bit data block called the initialization vector, which must be writing in the Ini-
tialization Vector Registers (IVnR). The initialization vector is used in an initial step in the
encryption of a message and in the corresponding decryption of the message. The IVRnR regis-
ters are also used in the CTR mode to set the counter value.
33.4.1 Operation Modes
The AES supports the following modes of operation:
• ECB: Electronic Code Book
• CBC: Cipher Block Chaining
• OFB: Output Feedback
• CFB: Cipher Feedback
– CFB8 (CFB where the length of the data segment is 8 bits)
– CFB16 (CFB where the length of the data segment is 16 bits)
– CFB32 (CFB where the length of the data segment is 32 bits)
– CFB64 (CFB where the length of the data segment is 64 bits)
– CFB128 (CFB where the length of the data segment is 128 bits)
• CTR: Counter
The data pre-processing, post-processing and chaining for the concerned modes are automati-
cally performed. Refer to the NIST Special Publication 800-38A Recommendation for more
complete information.
These modes are selected by writing the Operation Mode field in the Mode Register
(MR.OPMOD).
In CFB mode, five data size are possible (8 bits, 16 bits, 32 bits, 64 bits or 128 bits).
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These sizes are selected by writing the Cipher Feedback Data Size field in the MR register
(MR.CFDS).
33.4.2 Start Modes
The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or
decryption) start mode.
33.4.2.1 Manual mode
The sequence is as follows:
• Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
• Write the initialization vector (or counter) in the IVnR registers.
Note: The Initialization Vector Registers concern all modes except ECB.
• Write the Data Ready bit in the Interrupt Enable Register (IER.DATRDY), depending on
whether an interrupt is required or not at the end of processing.
• Write the data to be encrypted/decrypted in the authorized Input Data Registers (IDATAnR).
Table 33-1. Authorized Input Data Registers
Operation Mode IDATAnR to Write
ECB All
CBC All
OFB All
128-bit CFB All
64-bit CFB IDATA1R and IDATA2R
32-bit CFB IDATA1R
16-bit CFB IDATA1R
8-bit CFB IDATA1R
CTR All
Note: In 64-bit CFB mode, writing to IDATA3R and IDATA4R registers is not allowed and may lead to
errors in processing.
Note: In 32-bit, 16-bit and 8-bit CFB modes, writing to IDATA2R, IDATA3R and IDATA4R registers is not
allowed and may lead to errors in processing.
• Write the START bit in the Control Register (CR.START) to begin the encryption or the
decryption process.
• When the processing completes, the DATRDY bit in the Interrupt Status Register
(ISR.DATRDY) is set.
• If an interrupt has been enabled by writing the IER.DATRDY bit, the interrupt line of the AES
is activated.
• When the software reads one of the Output Data Registers (ODATAxR), the ISR.DATRDY bit
is cleared.
33.4.2.2 Automatic mode
The automatic mode is similar to the manual one, except that in this mode, as soon as the cor-
rect number of IDATAnR Registers is written, processing is automatically started without any
action in the CR register.
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33.4.2.3 DMA mode
The DMA Controller can be used in association with the AES to perform an encryption/decryp-
tion of a buffer without any action by the software during processing.
In this starting mode, the type of the data transfer (byte, halfword or word) depends on the oper-
ation mode.
Table 33-2. Data Transfer Type for the Different Operation Modes
Operation Mode Data Transfer Type (DMA)
ECB word
CBC word
OFB word
CFB 128-bit word
CFB 64-bit word
CFB 32-bit word
CFB 16-bit halfword
CFB 8-bit byte
CTR word
The sequence is as follows:
• Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
• Write the initialization vector (or counter) in the IVnR registers.
Note: The Initialization Vector Registers concern all modes except ECB.
• Configure a channel of the DMA Controller with source address (data buffer to
encrypt/decrypt) and destination address set to register IDATA1R (index is automatically
incremented and rolled over to write IDATAnR). Then configure a second channel with source
address set to ODATA1R (index is automatically incremented and rolled over to read
ODATAnR) and destination address to write processed data.
Note: Transmit and receive buffers can be identical.
• Enable the DMA Controller in transmission and reception to start the processing.
• The processing completion should be monitored with the DMA Controller.
33.4.3 Last Output Data Mode
This mode is used to generate cryptographic checksums on data (MAC) by means of cipher
block chaining encryption algorithm (CBC-MAC algorithm for example).
After each end of encryption/decryption, the output data is available either on the ODATAnR
registers for manual and automatic mode or at the address specified in the receive buffer pointer
for DMA mode.
The Last Output Data bit in the Mode Register (MR.LOD) allows retrieval of only the last data of
several encryption/decryption processes.
Therefore, there is no need to define a read buffer in DMA mode.
This data is only available on the Output Data Registers (ODATAnR).
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33.4.3.1 Manual and automatic modes
• When MR.LOD is zero
The ISR.DATRDY bit is cleared when at least one of the ODATAnR registers is read.
Figure 33-1. Manual and Automatic Modes when MR.LOD is zero
Write CR.START (Manual mode)
Or
Write IDATAnR register(s) (Auto mode)
Read ODATAnR register(s)
ISR.DATRDY
Encryption or Decryption Process
If the user does not want to read the output data registers between each encryption/decryption,
the ISR.DATRDY bit will not be cleared. If the ISR.DATRDY bit is not cleared, the user cannot
know the end of the following encryptions/decryptions.
• When MR.LOD is one
The ISR.DATRDY bit is cleared when at least one IDATAnR register is written, so before the
start of a new transfer. No more ODATAnR register reads are necessary between consecutive
encryptions/decryptions.
Figure 33-2. Manual and Automatic Modes when MR.LOD is one
Write CR.START(Manual mode)
or
Write IDATAnR register(s) (Auto mode) Write IDATAnR register(s)
ISR.DATRDY
Encryption or Decryption Process
33.4.3.2 DMA mode
• when MR.LOD is zero
The end of the encryption/decryption should be monitored with the DMA Controller.
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Figure 33-3. DMA Mode when MR.LOD is zero
E n a b le D M A C o n tro lle r C h a n n e ls (R e c e iv e a n d T ra n s m it C h a n n e ls)
M u ltip le e n c ry p tio n o r d e c ry p tio n p ro c e s s e s
D M A C o n tro lle r In te rru p t
• when MR.LOD is one
The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that
the encryption/decryption is completed.
In this case, no receive buffers are required.
The output data is only available in ODATAnR registers.
Figure 33-4. DMA Mode when MR.LOD is one
Enable DMA Controller Channels (only Transmit Channel)
ISR.DATRDY
Multiple Encryption or Decryption Processes
DMA Controller Interrupt
Following table summarizes the different cases.
Table 33-3. Last Output Mode Behavior versus Start Modes
Manual and Automatic Modes DMA Mode
MR.LOD = 0 MR.LOD = 1 MR.LOD = 0 MR.LOD = 1
ISR.DATRDY bit Clearing At least one ODATAnR At least one IDATAnR Managed by the DMA
Not used
Condition(1) register must be read register must be written Controller
At the address
Encrypted/Decrypted specified in the
In ODATAnR registers In ODATAnR registers configuration of In ODATAnR registers
Data Result Location
DMA Controller
DMA Controller
End of DMA Controller
ISR.DATRDY ISR.DATRDY Interrupt then
Encryption/Decryption Interrupt
DATRDY.ISR
Note: 1. Depending on the mode, there are other ways of clearing the DATRDY.ISR bit. See the Interrupt Status Register (ISR)
definition.
Warning: In DMA mode, reading to the ODATAnR registers before the last data transfer may lead to unpredictable results.
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33.4.4 Security Features
33.4.4.1 Countermeasures
The AES also features hardware countermeasures that can be useful to protect data against Dif-
ferential Power Analysis (DPA) attacks.
These countermeasures can be enabled through the Countermeasure Type field in the MR reg-
ister (MR.CTYPE). This field is write-only, and all changes to it are taken into account if, at the
same time, the Countermeasure Key field in the Mode Register (MR.CKEY) is correctly written
(see the Mode Register (MR) description in Section 33.5.2).
Note: Enabling countermeasures has an impact on the AES encryption/decryption throughput.
By default, all the countermeasures are enabled.
The best throughput is achieved with all the countermeasures disabled. On the other hand, the
best protection is achieved with all of them enabled.
The Random Number Generator Seed Loading bit in the CR register (CR.LOADSEED) allows a
new seed to be loaded in the embedded random number generator used for the different
countermeasures.
33.4.4.2 Unspecified register access detection
When an unspecified register access occurs, the Unspecified Register Detection Status bit in
the ISR register (ISR.URAD) is set to one. Its source is then reported in the Unspecified Register
Access Type field in the ISR register (ISR.URAT). Only the last unspecified register access is
available through the ISR.URAT field.
Several kinds of unspecified register accesses can occur when:
• Writing the IDATAnR registers during the data processing in DMA mode
• Reading the ODATAnR registers during data processing
• Writing the MR register during data processing
• Reading the ODATAnR registers during sub-keys generation
• Writing the MR register during sub-keys generation
• Reading an write-only register
The ISR.URAD bit and the ISR.URAT field can only be reset by the Software Reset bit in the CR
register (CR.SWRST).
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33.5 User Interface
Table 33-4. AES Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read/Write 0x00000000
0x10 Interrupt Enable Register IER Write-only 0x00000000
0x14 Interrupt Disable Register IDR Write-only 0x00000000
0x18 Interrupt Mask Register IMR Read-only 0x00000000
0x1C Interrupt Status Register ISR Read-only 0x0000001E
0x20 Key Word 1 Register KEYW1R Write-only 0x00000000
0x24 Key Word 2 Register KEYW2R Write-only 0x00000000
0x28 Key Word 3 Register KEYW3R Write-only 0x00000000
0x2C Key Word 4 Register KEYW4R Write-only 0x00000000
0x30 Key Word 5 Register KEYW5R Write-only 0x00000000
0x34 Key Word 6 Register KEYW6R Write-only 0x00000000
0x38 Key Word 7 Register KEYW7R Write-only 0x00000000
0x3C Key Word 8 Register KEYW8R Write-only 0x00000000
0x40 Input Data 1 Register IDATA1R Write-only 0x00000000
0x44 Input Data 2 Register IDATA2R Write-only 0x00000000
0x48 Input Data 3 Register IDATA3R Write-only 0x00000000
0x4C Input Data 4 Register IDATA4R Write-only 0x00000000
0x50 Output Data 1 Register ODATA1R Read-only 0x00000000
0x54 Output Data 2 Register ODATA2R Read-only 0xC01F0000
0x58 Output Data 3 Register ODATA3R Read-only 0x00000000
0x5C Output Data 4 Register ODATA4R Read-only 0x00000000
0x60 Initialization Vector 1 Register IV1R Write-only 0x00000000
0x64 Initialization Vector 2 Register IV2R Write-only 0x00000000
0x68 Initialization Vector 3 Register IV3R Write-only 0x00000000
0x6C Initialization Vector 4 Register IV4R Write-only 0x00000000
0xFC Version Register VR Read-only -(1)
Note: 1. The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter.
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33.5.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - LOADSEED
15 14 13 12 11 10 9 8
- - - - - - - SWRST
7 6 5 4 3 2 1 0
- - - - - - - START
• LOADSEED: Random Number Generator Seed Loading
Writing a one to this bit will load a new seed in the embedded random number generator used for the different
countermeasures.
writing a zero to this bit has no effect.
• SWRST: Software Reset
Writing a one to this bit will reset the AES.
writing a zero to this bit has no effect.
• START: Start Processing
Writing a one to this bit will start manual encryption/decryption process.
writing a zero to this bit has no effect.
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33.5.2 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - CTYPE
23 22 21 20 19 18 17 16
CKEY - CFBS
15 14 13 12 11 10 9 8
LOD OPMOD KEYSIZE SMOD
7 6 5 4 3 2 1 0
PROCDLY - - - CIPHER
• CTYPE: Countermeasure Type
CTYPE Description
X X X X 0 Countermeasure type 1 is disabled
Add random spurious power consumption during some configuration
X X X X 1
settings
X X X 0 X Countermeasure type 2 is disabled
X X X 1 X Add randomly 1 cycle to processing.
X X 0 X X Countermeasure type 3 is disabled
X X 1 X X Add randomly 1 cycle to processing (other version)
X 0 X X X Countermeasure type 4 is disabled
X 1 X X X Add randomly up to /13/15 cycles (for /192/256-bit key) to processing
0 X X X X Countermeasure type 5 is disabled
Add random spurious power consumption during processing
1 X X X X
(recommended with DMA access)
All the countermeasures are enabled by default.
CTYPE field is write-only and can only be modified if CKEY is correctly set.
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• CKEY: Countermeasure Key
Writing the value 0xE to this field allows the CTYPE field to be modified.
Writing another value to this field has no effect.
This bit always reads as zero.
• CFBS: Cipher Feedback Data Size
CFBS Description
0 128-bit
1 64-bit
2 32-bit
3 16-bit
4 8-bit
Others Reserved
• LOD: Last Output Data Mode
Writing a one to this bit will enabled the LOD mode.
Writing a zero to this bit will disabled the LOD mode.
These mode is described in the Table 33-3 on page 895.
• OPMOD: Operation Mode
OPMOD Description
0 ECB: Electronic Code Book mode
1 CBC: Cipher Block Chaining mode
2 OFB: Output Feedback mode
3 CFB: Cipher Feedback mode
4 CTR: Counter mode
Others Reserved
• KEYSIZE: Key Size
KEYSIZE Description
0 AES Key Size is 128 bits
1 AES Key Size is 192 bits
Others AES Key Size is 256 bits
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• SMOD: Start Mode
SMOD Description
0 Manual mode
1 Automatic mode
DMA mode
• LOD = 0: The encrypted/decrypted data are available at the address specified in the
2
configuration of DMA Controller.
• LOD = 1: The encrypted/decrypted data are available in the ODATAnR registers.
3 Reserved
• PROCDLY: Processing Delay
The processing time represents the number of clock cycles that the AES needs in order to perform one encryption/decryption
with no countermeasures activated:
Processing Time = 12 × ( PROCDLY + 1 )
The best performance is achieved with PROCDLY equal to 0.
Writing a value to this field will update the processing time.
Reading this field will give the current processing delay.
• CIPHER: Processing Mode
0: Decrypts data is enabled.
1: Encrypts data is enabled.
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33.5.3 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - URAD
7 6 5 4 3 2 1 0
- - - - - - - DATRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
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33.5.4 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - URAD
7 6 5 4 3 2 1 0
- - - - - - - DATRDY
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
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33.5.5 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - URAD
7 6 5 4 3 2 1 0
- - - - - - - DATRDY
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
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33.5.6 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x0000001E
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
URAT - - - URAD
7 6 5 4 3 2 1 0
- - - - - - - DATRDY
• URAT: Unspecified Register Access Type:
URAT Description
0 The IDATAnR register during the data processing in DMA mode.
1 The ODATAnR register read during the data processing.
2 The MR register written during the data processing.
3 The ODATAnR register read during the sub-keys generation.
4 The MR register written during the sub-keys generation.
5 Write-only register read access.
Others Reserved
Only the last Unspecified Register Access Type is available through the URAT field.
This field is reset to 0 when SWRST bit in the Control Register is written to one.
• URAD: Unspecified Register Access Detection Status
This bit is set when at least one unspecified register access has been detected since the last software reset.
This bit is cleared when SWRST bit in the Control Register is set to one.
•
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• DATRDY: Data Ready
This bit is set/clear as described in the Table 33-3 on page 895.
This bit is also cleared when SWRST bit in the Control Register is set to one.
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33.5.7 Key Word n Register
Name: KEYWnR
Access Type: Write-only
Offset: 0x20 +(n-1)*0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
KEYWn[31:24]
23 22 21 20 19 18 17 16
KEYWn[23:16]
15 14 13 12 11 10 9 8
KEYWn[15:8]
7 6 5 4 3 2 1 0
KEYWn[7:0]
• KEYWn[31:0]: Key Word n
Writing the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption in the four/six/eight 32-bit Key Word
registers.
KEYW1 corresponds to the first word of the key and respectively KEYW4/KEYW6/KEYW8 to the last one.
This field always read as zero to prevent the key from being read by another application.
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33.5.8 Input Data n Register
Name: IDATAnR
Access Type: Write-only
Offset: 0x40 + (n-1)*0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
IDATAn[31:24]
23 22 21 20 19 18 17 16
IDATAn[23:16]
15 14 13 12 11 10 9 8
IDATAn[15:8]
7 6 5 4 3 2 1 0
IDATAn[7:0]
• IDATAn[31:0]: Input Data Word n
Writing the 128-bit data block used for encryption/decryption in the four 32-bit Input Data registers.
IDATA1 corresponds to the first word of the data to be encrypted/decrypted, and IDATA4 to the last one.
This field always read as zero to prevent the input data from being read by another application.
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33.5.9 Output Data n Register
Name: ODATAnR
Access Type: Read-only
Offset: 0x50 + (n-1)*0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
ODATAn[31:24]
23 22 21 20 19 18 17 16
ODATAn[23:16]
15 14 13 12 11 10 9 8
ODATAn[15:8]
7 6 5 4 3 2 1 0
ODATAn[7:0]
• ODATAn[31:0]: Output Data n
Reading the four 32-bit ODATAnR give the 128-bit data block that has been encrypted/decrypted.
ODATA1 corresponds to the first word, ODATA4 to the last one.
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33.5.10 Initialization Vector n Register
Name: IVnR
Access Type: Write-only
Offset: 0x60 + (n-1)*0x04
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
IVn[31:24]
23 22 21 20 19 18 17 16
IVn[23:16]
15 14 13 12 11 10 9 8
IVn[15:8]
7 6 5 4 3 2 1 0
IVn[7:0]
• IVn[31:0]: Initialization Vector n
The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of
operation as an additional initial input:
MODE(OPMODE. Description
CBC,OFB, CFB initialization vector
CTR counter value
ECB not used, must not be written
IV1 corresponds to the first word of the Initialization Vector, IV4 to the last one.
This field is always read as zero to prevent the Initialization Vector from being read by another application.
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33.5.11 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: -
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
7 6 5 4 3 2 1 0
VERSION[7:0]
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION[11:0]
Version number of the module. No functionality associated.
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33.6 Module Configuration
The specific configuration for each AES instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks according to the table in the System
Bus Clock Connections section.
Table 33-5. Module clock name
Module name Clock name
AES CLK_AES
Table 33-6. Register Reset Values
Register Reset Value
VERSION 0x00000123
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34. Audio Bitstream DAC (ABDAC)
Rev: 1.0.1.1
34.1 Features
• Digital Stereo DAC
• Oversampled D/A conversion architecture
– Oversampling ratio fixed 128x
– FIR equalization filter
– Digital interpolation filter: Comb4
– 3rd Order Sigma-Delta D/A converters
• Digital bitstream outputs
• Parallel interface
• Connected to DMA Controller for background transfer without CPU intervention
34.2 Overview
The Audio Bitstream DAC converts a 16-bit sample value to a digital bitstream with an average
value proportional to the sample value. Two channels are supported, making the Audio Bit-
stream DAC particularly suitable for stereo audio. Each channel has a pair of complementary
digital outputs, DATAn and DATANn, which can be connected to an external high input imped-
ance amplifier.
The output DATAn and DATANn should be as ideal as possible before filtering, to achieve the
best SNR and THD quality. The outputs can be connected to a class D amplifier output stage to
drive a speaker directly, or it can be low pass filtered and connected to a high input impedance
amplifier. A simple 1st order low pass filter that filters all the frequencies above 50kHz should be
adequate when applying the signal to a speaker or a bandlimited amplifier, as the speaker or
amplifier will act as a filter and remove high frequency components from the signal. In some
cases high frequency components might be folded down into the audible range, and in that case
a higher order filter is required. For performance measurements on digital equipment a minimum
of 4th order low pass filter should be used. This is to prevent aliasing in the measurements.
For the best performance when not using a class D amplifier approach, the two outputs DATAn
and DATANn, should be applied to a differential stage amplifier, as this will increase the SNR
and THD.
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34.3 Block Diagram
Figure 34-1. ABDAC Block Diagram
Audio Bitstream DAC
PM GCLK_ABDAC
bit_clk
Clock Generator
sample_clk
CHANNEL0[15:0] COMB Sigma-Delta
Equalization FIR DATA0
(INT=128) DA-MOD
User Interface
CHANNEL1[15:0]
COMB Sigma-Delta
Equalization FIR DATA1
(INT=128) DA-MOD
34.4 I/O Lines Description
Table 34-1. I/O Lines Description
Pin Name Pin Description Type
DATA0 Output from Audio Bitstream DAC Channel 0 Output
DATA1 Output from Audio Bitstream DAC Channel 1 Output
DATAN0 Inverted output from Audio Bitstream DAC Channel 0 Output
DATAN1 Inverted output from Audio Bitstream DAC Channel 1 Output
34.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
34.5.1 I/O Lines
The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed
with IO lines.
Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the
Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode.
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34.5.2 Clocks
The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before
using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is
enabled in the Power Manager.
The ABDAC needs a separate clock for the D/A conversion operation. This clock,
GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its fre-
quency must be as follow:
f GCLK = 256 × f S
where fs is the samping rate of the data stream to convert. For fs= 48 kHz this means that the
GCLK_ABDAC clock must have a frequency of 12.288MHz.
The two clocks, CLK_ABDAC and GCLK_ABDAC, must be in phase with each other.
34.5.3 Interrupts
The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC
interrupt requires the interrupt controller to be programmed first.
34.6 Functional Description
34.6.1 How to Initialize the Module
In order to use the Audio Bitstream DAC the product dependencies given in Section 34.5 on
page 914 must be resolved. Particular attention should be given to the configuration of clocks
and I/O lines in order to ensure correct operation of the Audio Bitstream DAC.
The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream
DAC Control Register (CR.EN).
The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be
set whenever the ABDAC is ready to receive a new sample. A new sample value should be writ-
ten to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the
Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writ-
ing one to the corresponding bits in the Interrupt Clear Register (ICR).
34.6.2 Data Format
The input data format is two’s complement. Two 16-bit sample values for channel 0 and 1 can
be written to the least and most significant halfword of the Sample Data Register (SDR),
respectively.
An input value of 0x7FFF will result in an output voltage of approximately:
38 38
V OUT ( 0x7FFF ) ≈ ---------- ⋅ VDDIO = ---------- ⋅ 3, 3 ≈ 0, 98V
128 128
An Input value of 0x8000 will result in an output value of approximately:
90 90
V OUT ( 0x8000 ) ≈ ---------- ⋅ VDDIO = ---------- ⋅ 3, 3 ≈ 2, 32V
128 128
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If one want to get coherence between the sign of the input data and the output voltage one can
use the DATAN signal or invert the sign of the input data by software.
34.6.3 Data Swapping
When the SWAP bit in the ABDAC Control Register (CR.SWAP) is written to one, writing to the
Sample Data Register (SDR) will cause the values written to the CHANNEL0 and CHANNEL1
fields to be swapped.
34.6.4 Peripheral DMA Controller
The Audio Bitstream DAC is connected to the Peripheral DMA Controller. The Peripheral DMA
Controller can be programmed to automatically transfer samples to the Audio Bitstream DAC
Sample Data Register (SDR) when the Audio Bitstream DAC is ready for new samples. In this
case only the CR.EN bit needs to be set in the Audio Bitstream DAC module. This enables the
Audio Bitstream DAC to operate without any CPU intervention such as polling the Interrupt Sta-
tus Register (ISR) or using interrupts. See the Peripheral DMA Controller documentation for
details on how to setup Peripheral DMA transfers.
34.6.5 Construction
The Audio Bitstream DAC is constructed of two 3rd order Sigma-Delta D/A converter with an
oversampling ratio of 128. The samples are upsampled with a 4th order Sinc interpolation filter
(Comb4) before being applied to the Sigma-Delta Modulator. In order to compensate for the
pass band frequency response of the interpolation filter and flatten the overall frequency
response, the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total
frequency response of the Equalization FIR filter and the interpolation filter is given in Figure 34-
2 on page 917. The digital output bitstreams from the Sigma-Delta Modulators should be low-
pass filtered to remove high frequency noise inserted by the modulation process.
34.6.6 Equalization Filter
The equalization filter is a simple 3-tap FIR filter. The purpose of this filter is to compensate for
the pass band frequency response of the sinc interpolation filter. The equalization filter makes
the pass band response more flat and moves the -3dB corner a little higher.
34.6.7 Interpolation Filter
The interpolation filter interpolates from fs to 128fs. This filter is a 4thorder Cascaded Integrator-
Comb filter, and the basic building blocks of this filter is a comb part and an integrator part.
34.6.8 Sigma-Delta Modulator
This part is a 3rdorder Sigma-Delta Modulator consisting of three differentiators (delta blocks),
three integrators (sigma blocks) and a one bit quantizer. The purpose of the integrators is to
shape the noise, so that the noise is reduced in the band of interest and increased at the higher
frequencies, where it can be filtered.
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34.6.9 Frequency Response
Figure 34-2. Frequency Response, EQ-FIR+COMB4
1 0
[d B ]
-1 0
A m p li t u d e -2 0
-3 0
-4 0
-5 0
-6 0
0 1 2 3 4 5 6 7 8 9 1 0
F re q u e n c y [F s ] 4
x 1 0
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34.7 User Interface
Table 34-2. ABDAC Register Memory Map
Offset Register Register Name Access Reset
0x00 Sample Data Register SDR Read/Write 0x00000000
0x08 Control Register CR Read/Write 0x00000000
0x0C Interrupt Mask Register IMR Read-only 0x00000000
0x10 Interrupt Enable Register IER Write-only 0x00000000
0x14 Interrupt Disable Register IDR Write-only 0x00000000
0x18 Interrupt Clear Register ICR Write-only 0x00000000
0x1C Interrupt Status Register ISR Read-only 0x00000000
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34.7.1 Sample Data Register
Name: SDR
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
CHANNEL1[15:8]
23 22 21 20 19 18 17 16
CHANNEL1[7:0]
15 14 13 12 11 10 9 8
CHANNEL0[15:8]
7 6 5 4 3 2 1 0
CHANNEL0[7:0]
• CHANNEL1: Sample Data for Channel 1
signed 16-bit Sample Data for channel 1.
• CHANNEL0: Signed 16-bit Sample Data for Channel 0
signed 16-bit Sample Data for channel 0.
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34.7.2 Control Register
Name: CR
Access Type: Read/Write
Offset: 0x08
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
EN SWAP - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -
• EN: Enable Audio Bitstream DAC
1: The module is enabled.
0: The module is disabled.
• SWAP: Swap Channels
1: The swap of CHANNEL0 and CHANNEL1 samples is enabled.
0: The swap of CHANNEL0 and CHANNEL1 samples is disabled.
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34.7.3 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x0C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - TXREADY UNDERRUN - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -
1: The corresponding interrupt is enabled.
0: The corresponding interrupt is disabled.
A bit in this register is set when the corresponding bit in IER is written to one.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
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34.7.4 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - TXREADY UNDERRUN - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -
Writing a one to a bit in this register will set the corresponding bit in IMR.
Writing a zero to a bit in this register has no effect.
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34.7.5 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - TXREADY UNDERRUN - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -
Writing a one to a bit in this register will clear the corresponding bit in IMR.
Writing a zero to a bit in this register has no effect.
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34.7.6 Interrupt Clear Register
Name: ICR
Access Type: Write-only
Offset: 0x18
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - TXREADY UNDERRUN - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -
Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request.
Writing a zero to a bit in this register has no effect.
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34.7.7 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
31 30 29 28 27 26 25 24
- - TXREADY UNDERRUN - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -
• TXREADY: TX Ready Interrupt Status
This bit is set when the Audio Bitstream DAC is ready to receive a new data in SDR.
This bit is cleared when the Audio Bitstream DAC is not ready to receive a new data in SDR.
• UNDERRUN: Underrun Interrupt Status
This bit is set when at least one Audio Bitstream DAC Underrun has occurred since the last time this bit was cleared (by reset or
by writing in ICR).
This bit is cleared when no Audio Bitstream DAC Underrun has occurred since the last time this bit was cleared (by reset or by
writing in ICR).
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35. Programming and Debugging
35.1 Overview
General description of programming and debug features, block diagram and introduction of main
concepts.
35.2 Service Access Bus
The AVR32 architecture offers a common interface for access to On-Chip Debug, programming,
and test functions. These are mapped on a common bus called the Service Access Bus (SAB),
which is linked to the JTAG port through a bus master module, which also handles synchroniza-
tion between the debugger and SAB clocks.
When accessing the SAB through the debugger there are no limitations on debugger frequency
compared to chip frequency, although there must be an active system clock in order for the SAB
accesses to complete. If the system clock is switched off in sleep mode, activity on the debugger
will restart the system clock automatically, without waking the device from sleep. Debuggers
may optimize the transfer rate by adjusting the frequency in relation to the system clock. This
ratio can be measured with debug protocol specific instructions.
The Service Access Bus uses 36 address bits to address memory or registers in any of the
slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or
words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses
must have the lowest address bit cleared, and word accesses must have the two lowest address
bits cleared.
35.2.1 SAB address map
The Service Access Bus (SAB) gives the user access to the internal address space and other
features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32
LSBs are decoded within the slave’s address space. The SAB slaves are shown in Table 35-1
on page 926.
Table 35-1. SAB Slaves, addresses and descriptions.
Slave Address [35:32] Description
Unallocated 0x0 Intentionally unallocated
OCD 0x1 OCD registers
HSB 0x4 HSB memory space, as seen by the CPU
Alternative mapping for HSB space, for compatibility with
HSB 0x5
other 32-bit AVR devices.
Memory Service
0x6 Memory Service Unit registers
Unit
Reserved Other Unused
35.2.2 SAB security restrictions
The Service Access bus can be restricted by internal security measures. A short description of
the security measures are found in the table below.
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35.2.2.1 Security measure and control location
A security measure is a mechanism to either block or allow SAB access to a certain address or
address range. A security measure is enabled or disabled by one or several control signals. This
is called the control location for the security measure.
These security measures can be used to prevent an end user from reading out the code pro-
grammed in the flash, for instance.
Table 35-2. SAB Security measures.
Security measure Control Location Description
FLASHC security Programming and debugging not possible, very restricted
Security bit
bit set access.
Restricts all access except parts of the flash and the flash
User code FLASHC UPROT controller for programming user code. Debugging is not
programming + security bit set possible unless an OS running from the secure part of the
flash supports it.
Below follows a more in depth description of what locations are accessible when the security
measures are active.
Table 35-3. Security bit SAB restrictions
Name Address start Address end Access
OCD DCCPU,
OCD DCEMU, 0x100000110 0x100000118 Read/Write
OCD DCSR
User page 0x580800000 0x581000000 Read
Other accesses - - Blocked
Table 35-4. User code programming SAB restrictions
Name Address start Address end Access
OCD DCCPU,
OCD DCEMU, 0x100000110 0x100000118 Read/Write
OCD DCSR
User page 0x580800000 0x581000000 Read
FLASHC PB
0x5FFFE0000 0x5FFFE0400 Read/Write
interface
FLASH pages
0x580000000 +
outside 0x580000000 + Flash size Read/Write
BOOTPROT size
BOOTPROT
Other accesses - - Blocked
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35.3 On-Chip Debug (OCD)
Rev: 1.4.2.1
35.3.1 Features
• Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
• JTAG access to all on-chip debug functions
• Advanced program, data, ownership, and watchpoint trace supported
• NanoTrace JTAG-based trace access
• Auxiliary port for high-speed trace information
• Hardware support for 6 program and 2 data breakpoints
• Unlimited number of software breakpoints supported
• Automatic CRC check of memory regions
35.3.2 Overview
Debugging on the AT32UC3A3 is facilitated by a powerful On-Chip Debug (OCD) system. The
user accesses this through an external debug tool which connects to the JTAG port and the Aux-
iliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based
debugger is sufficient for basic debugging.
The debug system is based on the Nexus 2.0 standard, class 2+, which includes:
• Basic run-time control
• Program breakpoints
• Data breakpoints
• Program trace
• Ownership trace
• Data trace
In addition to the mandatory Nexus debug features, the AT32UC3A3 implements several useful
OCD features, such as:
• Debug Communication Channel between CPU and JTAG
• Run-time PC monitoring
• CRC checking
• NanoTrace
• Software Quality Assurance (SQA) support
The OCD features are controlled by OCD registers, which can be accessed by JTAG when the
NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly
using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based
on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical
Reference Manual.
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35.3.3 Block Diagram
Figure 35-1. On-Chip Debug Block Diagram
JTAG
JTAG AUX
On-Chip Debug
Memory
Service Access Bus Service Transmit Queue Watchpoints
Unit
Debug PC
Program Ownership
Data Trace
Debug Trace Trace
Breakpoints
Instruction
Internal Memories and
CPU HSB Bus Matrix peripherals
SRAM
35.3.4 JTAG-based Debug Features
A debugger can control all OCD features by writing OCD registers over the JTAG interface.
Many of these do not depend on output on the AUX port, allowing a JTAG-based debugger to be
used.
A JTAG-based debugger should connect to the device through a standard 10-pin IDC connector
as described in the AVR32UC Technical Reference Manual.
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Figure 35-2. JTAG-based Debugger
PC
JTAG-based
debug tool
10-pin IDC
JTAG
AVR32
35.3.4.1 Debug Communication Channel
The Debug Communication Channel (DCC) consists of a pair OCD registers with associated
handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange
data between the CPU and the JTAG master, both runtime as well as in debug mode.
35.3.4.2 breakpoints
One of the most fundamental debug features is the ability to halt the CPU, to examine registers
and the state of the system. This is accomplished by breakpoints, of which many types are
available:
• Unconditional breakpoints are set by writing OCD registers by JTAG, halting the CPU
immediately.
• Program breakpoints halt the CPU when a specific address in the program is executed.
• Data breakpoints halt the CPU when a specific memory address is read or written, allowing
variables to be watched.
• Software breakpoints halt the CPU when the breakpoint instruction is executed.
When a breakpoint triggers, the CPU enters debug mode, and the D bit in the Status Register is
set. This is a privileged mode with dedicated return address and return status registers. All privi-
leged instructions are permitted. Debug mode can be entered as either OCD mode, running
instructions from JTAG, or monitor mode, running instructions from program memory.
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35.3.4.3 OCD mode
When a breakpoint triggers, the CPU enters OCD mode, and instructions are fetched from the
Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is
executed, allowing the JTAG to execute CPU instructions directly. The JTAG master can e.g.
read out the register file by issuing mtdr instructions to the CPU, writing each register to the
Debug Communication Channel OCD registers.
35.3.4.4 monitor mode
Since the OCD registers are directly accessible by the CPU, it is possible to build a software-
based debugger that runs on the CPU itself. Setting the Monitor Mode bit in the Development
Control register causes the CPU to enter monitor mode instead of OCD mode when a breakpoint
triggers. Monitor mode is similar to OCD mode, except that instructions are fetched from the
debug exception vector in regular program memory, instead of issued by JTAG.
35.3.4.5 program counter monitoring
Normally, the CPU would need to be halted for a JTAG-based debugger to examine the current
PC value. However, the AT32UC3A3 provides a Debug Program Counter OCD register, where
the debugger can continuously read the current PC without affecting the CPU. This allows the
debugger to generate a simple statistic of the time spent in various areas of the code, easing
code optimization.
35.3.5 Memory Service Unit
The Memory Service Unit (MSU) is a block dedicated to test and debug functionality. It is con-
trolled through a dedicated set of registers addressed through the MEMORY_SERVICE JTAG
command.
35.3.5.1 Cyclic Redundancy Check (CRC)
The MSU can be used to automatically calculate the CRC of a block of data in memory. The
OCD will then read out each word in the specified memory block and report the CRC32-value in
an OCD register.
35.3.5.2 NanoTrace
The MSU additionally supports NanoTrace. This is an AVR32-specific feature, in which trace
data is output to memory instead of the AUX port. This allows the trace data to be extracted by
JTAG MEMORY_ACCESS, enabling trace features for JTAG-based debuggers. The user must
write MSU registers to configure the address and size of the memory block to be used for Nano-
Trace. The NanoTrace buffer can be anywhere in the physical address range, including internal
and external RAM, through an EBI, if present. This area may not be used by the application run-
ning on the CPU.
35.3.6 AUX-based Debug Features
Utilizing the Auxiliary (AUX) port gives access to a wide range of advanced debug features. Of
prime importance are the trace features, which allow an external debugger to receive continuous
information on the program execution in the CPU. Additionally, Event In and Event Out pins
allow external events to be correlated with the program flow.
The AUX port contains a number of pins, as shown in Table 35-5 on page 932. These are multi-
plexed with I/O Controller lines, and must explicitly be enabled by writing OCD registers before
the debug session starts. The AUX port is mapped to two different locations, selectable by OCD
Registers, minimizing the chance that the AUX port will need to be shared with an application.
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Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mic-
tor-38 connector, as described in the AVR32UC Technical Reference manual. This connector
includes the JTAG signals and the RESET_N pin, giving full access to the programming and
debug features in the device.
Table 35-5. Auxiliary Port Signals
Signal Direction Description
MCKO Output Trace data output clock
MDO[5:0] Output Trace data output
MSEO[1:0] Output Trace frame control
EVTI_N Input Event In
EVTO_N Output Event Out
Figure 35-3. AUX+JTAG based Debugger
PC
A U X +JTA G
T ra c e b u ffe r
d e b u g to o l
M ic to r 3 8
AUX
JTAG
h ig h s p e e d
AVR32
35.3.6.1 trace operation
Trace features are enabled by writing OCD registers by JTAG. The OCD extracts the trace infor-
mation from the CPU, compresses this information and formats it into variable-length messages
according to the Nexus standard. The messages are buffered in a 16-frame transmit queue, and
are output on the AUX port one frame at a time.
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The trace features can be configured to be very selective, to reduce the bandwidth on the AUX
port. In case the transmit queue overflows, error messages are produced to indicate loss of
data. The transmit queue module can optionally be configured to halt the CPU when an overflow
occurs, to prevent the loss of messages, at the expense of longer run-time for the program.
35.3.6.2 program trace
Program trace allows the debugger to continuously monitor the program execution in the CPU.
Program trace messages are generated for every branch in the program, and contains com-
pressed information, which allows the debugger to correlate the message with the source code
to identify the branch instruction and target address.
35.3.6.3 data trace
Data trace outputs a message every time a specific location is read or written. The message
contains information about the type (read/write) and size of the access, as well as the address
and data of the accessed location. The AT32UC3A3 contains two data trace channels, each of
which are controlled by a pair of OCD registers which determine the range of addresses (or sin-
gle address) which should produce data trace messages.
35.3.6.4 ownership trace
Program and data trace operate on virtual addresses. In cases where an operating system runs
several processes in overlapping virtual memory segments, the Ownership Trace feature can be
used to identify the process switch. When the O/S activates a process, it will write the process ID
number to an OCD register, which produces an Ownership Trace Message, allowing the debug-
ger to switch context for the subsequent program and data trace messages. As the use of this
feature depends on the software running on the CPU, it can also be used to extract other types
of information from the system.
35.3.6.5 watchpoint messages
The breakpoint modules normally used to generate program and data breakpoints can also be
used to generate Watchpoint messages, allowing a debugger to monitor program and data
events without halting the CPU. Watchpoints can be enabled independently of breakpoints, so a
breakpoint module can optionally halt the CPU when the trigger condition occurs. Data trace
modules can also be configured to produce watchpoint messages instead of regular data trace
messages.
35.3.6.6 Event In and Event Out pins
The AUX port also contains an Event In pin (EVTI_N) and an Event Out pin (EVTO_N). EVTI_N
can be used to trigger a breakpoint when an external event occurs. It can also be used to trigger
specific program and data trace synchronization messages, allowing an external event to be
correlated to the program flow.
When the CPU enters debug mode, a Debug Status message is transmitted on the trace port.
All trace messages can be timestamped when they are received by the debug tool. However,
due to the latency of the transmit queue buffering, the timestamp will not be 100% accurate. To
improve this, EVTO_N can toggle every time a message is inserted into the transmit queue,
allowing trace messages to be timestamped precisely. EVTO_N can also toggle when a break-
point module triggers, or when the CPU enters debug mode, for any reason. This can be used to
measure precisely when the respective internal event occurs.
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35.3.6.7 Software Quality Analysis (SQA)
Software Quality Analysis (SQA) deals with two important issues regarding embedded software
development. Code coverage involves identifying untested parts of the embedded code, to
improve test procedures and thus the quality of the released software. Performance analysis
allows the developer to precisely quantify the time spent in various parts of the code, allowing
bottlenecks to be identified and optimized.
Program trace must be used to accomplish these tasks without instrumenting (altering) the code
to be examined. However, traditional program trace cannot reconstruct the current PC value
without correlating the trace information with the source code, which cannot be done on-the-fly.
This limits program trace to a relatively short time segment, determined by the size of the trace
buffer in the debug tool.
The OCD system in AT32UC3A3 extends program trace with SQA capabilities, allowing the
debug tool to reconstruct the PC value on-the-fly. Code coverage and performance analysis can
thus be reported for an unlimited execution sequence.
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35.4 JTAG and Boundary-scan (JTAG)
Rev: 2.0.0.4
35.4.1 Features
• IEEE1149.1 compliant JTAG Interface
• Boundary-scan Chain for board-level testing
• Direct memory access and programming capabilities through JTAG Interface
35.4.2 Overview
The JTAG Interface offers a four pin programming and debug solution, including boundary-scan
support for board-level testing.
Figure 35-4 on page 936 shows how the JTAG is connected in an 32-bit AVR device. The TAP
Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(shift register) between the TDI-input and TDO-output.
The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The
Device Identification Register, Bypass Register, and the boundary-scan chain are the Data Reg-
isters used for board-level testing. The Reset Register can be used to keep the device reset
during test or programming.
The Service Access Bus (SAB) interface contains address and data registers for the Service
Access Bus, which gives access to On-Chip Debug, programming, and other functions in the
device. The SAB offers several modes of access to the address and data registers, as described
in Section 35.4.10.
Section 35.5 lists the supported JTAG instructions, with references to the description in this
document.
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35.4.3 Block Diagram
Figure 35-4. JTAG and Boundary-scan Access
32-bit AVR device
JTAG
JTAG master
Boundary scan enable
TAP
TMS TCK TDO TDI Controller
TCK Instruction register
scan enable Data register
JTAG Pins
TMS scan enable
TDI
TDO
Instruction Register
TMS TCK TDO TDI
JTAG data registers
2nd JTAG Device Identification
Register
device
By-pass Register
Pins and analog blocks
Boundary Scan Chain
Reset Register
Part specific registers
...
Service Access Bus
interface
Internal I/O
SAB
lines
35.4.4 I/O Lines Description
Table 35-6. I/O Line Description
Pin Name Pin Description Type Active Level
TCK Test Clock Input. Fully asynchronous to system clock frequency. Input
TMS Test Mode Select, sampled on rising TCK. Input
TDI Test Data In, sampled on rising TCK. Input
TDO Test Data Out, driven on falling TCK. Output
35.4.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
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35.4.5.1 Power Management
When an instruction that accesses the SAB is loaded in the instruction register, before entering
a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This
can lead to a program behaving differently when debugging.
35.4.5.2 Clocks
The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by
the JTAG master.
Instructions that use the SAB bus requires the internal main clock to be running.
35.4.6 JTAG Interface
The JTAG Interface is accessed through the dedicated JTAG pins shown in Table 35-6 on page
936. The TMS control line navigates the TAP controller, as shown in Figure 35-5 on page 938.
The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data
is scanned into the selected instruction or data register on TDI, and out of the register on TDO,
in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is high-
Z in other states than Shift-IR and Shift-DR.
The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions
defined by the JTAG standard are supported, as described in Section 35.5.2, as well as a num-
ber of 32-bit AVR-specific private JTAG instructions described in Section 35.5.3. Each
instruction selects a specific data register for the Shift-DR path, as described for each
instruction.
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Figure 35-5. TAP Controller State Diagram
Test-Logic-
1
Reset
0
1
Run-Test/ Select-DR Select-IR
0 1 1
Idle Scan Scan
0 0
Capture-DR Capture-IR
1 1
0 0
Shift-DR 0 Shift-IR 0
1 1
Exit1-DR Exit1-IR
0 0
Pause-DR 0 Pause-IR 0
1 1 1 1
0 Exit2-DR 0 Exit2-IR
1 1
1 Update-DR 1 Update-IR
0 0
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35.4.7 How to Initialize the Module
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied
at the start of a JTAG session to bring the TAP Controller into a defined state before applying
JTAG commands. Applying a 0 on TMS for 1 TCK period brings the TAP Controller to the Run-
Test/Idle state, which is the starting point for JTAG operations.
35.4.8 Typical Sequence
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG Interface
follows.
35.4.8.1 Scanning in JTAG Instruction
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register (Shift-IR) state. While in this state, shift the 5 bits of the JTAG instructions
into the JTAG instruction register from the TDI input at the rising edge of TCK. During shifting,
the JTAG outputs status bits on TDO, refer to Section 35.5 for a description of these. The TMS
input must be held low during input of the 4 LSBs in order to remain in the Shift-IR state. The
JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls
the circuitry surrounding the selected Data Register.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR,
and Exit2-IR states are only used for navigating the state machine.
Figure 35-6. Scanning in JTAG Instruction
TCK
TAP State TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI
TMS
TDI Instruction
TDO ImplDefined
35.4.8.2 Scanning in/out Data
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data
Register (Shift-DR) state. While in this state, upload the selected Data Register (selected by the
present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge
of TCK. In order to remain in the Shift-DR state, the TMS input must be held low. While the Data
Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the
Capture-DR state is shifted out on the TDO pin.
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Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register
has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR,
Pause-DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting
JTAG instruction and using Data Registers.
35.4.9 Boundary-scan
The boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long shift register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, boundary-scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the 4 TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST can be used for testing the Printed Circuit Board. Initial scanning of the
data register path will show the ID-code of the device, since IDCODE is the default JTAG
instruction. It may be desirable to have the 32-bit AVR device in reset during test mode. If not
reset, inputs to the device may be determined by the scan operations, and the internal software
may be in an undetermined state when exiting the test mode. If needed, the BYPASS instruction
can be issued to make the shortest possible scan chain through the device. The device can be
set in the reset state either by pulling the external RESETn pin low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST
instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
When using the JTAG Interface for boundary-scan, the JTAG TCK clock is independent of the
internal chip clock. The internal chip clock is not required to run during boundary-scan
operations.
NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one
using boundary-scan, as this will create a current flowing from the 3,3V driver to the 5V pull-up
on the line. Optionally a series resistor can be added between the line and the pin to reduce the
current.
Details about the boundary-scan chain can be found in the BSDL file for the device. This can be
found on the Atmel website.
35.4.10 Service Access Bus
The AVR32 architecture offers a common interface for access to On-Chip Debug, programming,
and test functions. These are mapped on a common bus called the Service Access Bus (SAB),
which is linked to the JTAG through a bus master module, which also handles synchronization
between the TCK and SAB clocks.
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For more information about the SAB and a list of SAB slaves see the Service Access Bus
chapter.
35.4.10.1 SAB Address Mode
The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address
on the bus. MEMORY_WORD_ACCESS is a shorthand instruction for 32-bit accesses to any
36-bit address, while the NEXUS_ACCESS instruction is a Nexus-compliant shorthand instruc-
tion for accessing the 32-bit OCD registers in the 7-bit address space reserved for these. These
instructions require two passes through the Shift-DR TAP state: one for the address and control
information, and one for data.
35.4.10.2 Block Transfer
To increase the transfer rate, consecutive memory accesses can be accomplished by the
MEMORY_BLOCK_ACCESS instruction, which only requires a single pass through Shift-DR for
data transfer only. The address is automatically incremented according to the size of the last
SAB transfer.
35.4.10.3 Canceling a SAB Access
It is possible to abort an ongoing SAB access by the CANCEL_ACCESS instruction, to avoid
hanging the bus due to an extremely slow slave.
35.4.10.4 Busy Reporting
As the time taken to perform an access may vary depending on system activity and current chip
frequency, all the SAB access JTAG instructions can return a busy indicator. This indicates
whether a delay needs to be inserted, or an operation needs to be repeated in order to be suc-
cessful. If a new access is requested while the SAB is busy, the request is ignored.
The SAB becomes busy when:
• Entering Update-DR in the address phase of any read operation, e.g., after scanning in a
NEXUS_ACCESS address with the read bit set.
• Entering Update-DR in the data phase of any write operation, e.g., after scanning in data for
a NEXUS_ACCESS write.
• Entering Update-DR during a MEMORY_BLOCK_ACCESS.
• Entering Update-DR after scanning in a counter value for SYNC.
• Entering Update-IR after scanning in a MEMORY_BLOCK_ACCESS if the previous access
was a read and data was scanned after scanning the address.
The SAB becomes ready again when:
• A read or write operation completes.
• A SYNC countdown completed.
• A operation is cancelled by the CANCEL_ACCESS instruction.
What to do if the busy bit is set:
• During Shift-IR: The new instruction is selected, but the previous operation has not yet
completed and will continue (unless the new instruction is CANCEL_ACCESS). You may
continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting
data, you must be prepared that the data shift may also report busy.
• During Shift-DR of an address: The new address is ignored. The SAB stays in address mode,
so no data must be shifted. Repeat the address until the busy bit clears.
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• During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat
scanning until the busy bit clears.
• During Shift-DR of write data: The write data is ignored. The SAB stays in data mode. Repeat
scanning until the busy bit clears.
35.4.10.5 Error Reporting
The Service Access Bus may not be able to complete all accesses as requested. This may be
because the address is invalid, the addressed area is read-only or cannot handle byte/halfword
accesses, or because the chip is set in a protected mode where only limited accesses are
allowed.
The error bit is updated when an access completes, and is cleared when a new access starts.
What to do if the error bit is set:
• During Shift-IR: The new instruction is selected. The last operation performed using the old
instruction did not complete successfully.
• During Shift-DR of an address: The previous operation failed. The new address is accepted.
If the read bit is set, a read operation is started.
• During Shift-DR of read data: The read operation failed, and the read data is invalid.
• During Shift-DR of write data: The previous write operation failed. The new data is accepted
and a write operation started. This should only occur during block writes or stream writes. No
error can occur between scanning a write address and the following write data.
• While polling with CANCEL_ACCESS: The previous access was cancelled. It may or may not
have actually completed.
• After power-up: The error bit is set after power up, but there has been no previous SAB
instruction so this error can be discarded.
35.4.10.6 Protected Reporting
A protected status may be reported during Shift-IR or Shift-DR. This indicates that the security
bit in the Flash Controller is set and that the chip is locked for access, according to Section
35.5.1.
The protected state is reported when:
• The Flash Controller is under reset. This can be due to the AVR_RESET command or the
RESET_N line.
• The Flash Controller has not read the security bit from the flash yet (This will take a a few
ms). Happens after the Flash Controller reset has been released.
• The security bit in the Flash Controller is set.
What to do if the protected bit is set:
• Release all active AVR_RESET domains, if any.
• Release the RESET_N line.
• Wait a few ms for the security bit to clear. It can be set temporarily due to a reset.
• Perform a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the
non-volatile memory.
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35.5 JTAG Instruction Summary
The implemented JTAG instructions in the 32-bit AVR are shown in the table below.
Table 35-7. JTAG Instruction Summary
Instruction
OPCODE Instruction Description
0x01 IDCODE Select the 32-bit Device Identification register as data register.
0x02 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation.
Select boundary-scan chain as data register for testing circuitry external to
0x03 EXTEST
the device.
0x04 INTEST Select boundary-scan chain for internal testing of the device.
Bypass device through Bypass register, while driving outputs from boundary-
0x06 CLAMP
scan register.
0x0C AVR_RESET Apply or remove a static reset to the device
0x0F CHIP_ERASE Erase the device
Select the SAB Address and Data registers as data register for the TAP. The
0x10 NEXUS_ACCESS
registers are accessed in Nexus mode.
0x11 MEMORY_WORD_ACCESS Select the SAB Address and Data registers as data register for the TAP.
Select the SAB Data register as data register for the TAP. The address is
0x12 MEMORY_BLOCK_ACCESS
auto-incremented.
0x13 CANCEL_ACCESS Cancel an ongoing Nexus or Memory access.
Select the SAB Address and Data registers as data register for the TAP. The
0x14 MEMORY_SERVICE
registers are accessed in Memory Service mode.
0x15 MEMORY_SIZED_ACCESS Select the SAB Address and Data registers as data register for the TAP.
0x17 SYNC Synchronization counter
0x1C HALT Halt the CPU for safe programming.
0x1F BYPASS Bypass this device through the bypass register.
Others N/A Acts as BYPASS
35.5.1 Security Restrictions
When the security fuse in the Flash is programmed, the following JTAG instructions are
restricted:
• NEXUS_ACCESS
• MEMORY_WORD_ACCESS
• MEMORY_BLOCK_ACCESS
• MEMORY_SIZED_ACCESS
For description of what memory locations remain accessible, please refer to the SAB address
map.
Full access to these instructions is re-enabled when the security fuse is erased by the
CHIP_ERASE JTAG instruction.
Note that the security bit will read as programmed and block these instructions also if the Flash
Controller is statically reset.
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Other security mechanisms can also restrict these functions. If such mechanisms are present
they are listed in the SAB address map section.
35.5.1.1 Notation
Table 35-9 on page 944 shows bit patterns to be shifted in a format like "peb01". Each character
corresponds to one bit, and eight bits are grouped together for readability. The least significant-
bit is always shifted first, and the most significant bit shifted last. The symbols used are shown in
Table 35-8.
Table 35-8. Symbol Description
Symbol Description
0 Constant low value - always reads as zero.
1 Constant high value - always reads as one.
a An address bit - always scanned with the least significant bit first
A busy bit. Reads as one if the SAB was busy, or zero if it was not. See Section 35.4.10.4 for
b
details on how the busy reporting works.
d A data bit - always scanned with the least significant bit first.
An error bit. Reads as one if an error occurred, or zero if not. See Section 35.4.10.5 for
e
details on how the error reporting works.
The chip protected bit. Some devices may be set in a protected state where access to chip
p internals are severely restricted. See the documentation for the specific device for details.
On devices without this possibility, this bit always reads as zero.
r A direction bit. Set to one to request a read, set to zero to request a write.
s A size bit. The size encoding is described where used.
x A don’t care bit. Any value can be shifted in, and output data should be ignored.
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
bold text. I.e. given the pattern "aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is
34 bits, but the test or debug unit may choose to shift only 8 bits "aaaaaaar".
The following describes how to interpret the fields in the instruction description tables:
Table 35-9. Instruction Description
Instruction Description
Shows the bit pattern to shift into IR in the Shift-IR state in order to select this
instruction. The pattern is show both in binary and in hexadecimal form for
IR input value convenience.
Example: 10000 (0x10)
Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is
IR output value active.
Example: peb01
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Table 35-9. Instruction Description (Continued)
Instruction Description
Shows the number of bits in the data register chain when this instruction is active.
DR Size
Example: 34 bits
Shows which bit pattern to shift into the data register in the Shift-DR state when this
instruction is active. Multiple such lines may exist, e.g., to distinguish between
DR input value reads and writes.
Example: aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
Shows the bit pattern shifted out of the data register in the Shift-DR state when this
instruction is active. Multiple such lines may exist, e.g., to distinguish between
DR output value reads and writes.
Example: xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
35.5.2 Public JTAG Instructions
The JTAG standard defines a number of public JTAG instructions. These instructions are
described in the sections below.
35.5.2.1 IDCODE
This instruction selects the 32 bit Device Identification register (DID) as Data Register. The DID
register consists of a version number, a device number, and the manufacturer code chosen by
JEDEC. This is the default instruction after a JTAG reset. Details about the DID register can be
found in the module configuration section at the end of this chapter.
Starting in Run-Test/Idle, the Device Identification register is accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Capture-DR: The IDCODE value is latched into the shift register.
7. In Shift-DR: The IDCODE scan chain is shifted by the TCK input.
8. Return to Run-Test/Idle.
Table 35-10. IDCODE Details
Instructions Details
IR input value 00001 (0x01)
IR output value p0001
DR Size 32
DR input value xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DR output value Device Identification Register
35.5.2.2 SAMPLE_PRELOAD
This instruction takes a snap-shot of the input/output pins without affecting the system operation,
and pre-loading the scan chain without updating the DR-latch. The boundary-scan chain is
selected as Data Register.
Starting in Run-Test/Idle, the Device Identification register is accessed in the following way:
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1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan
chain.
7. In Shift-DR: The boundary-scan chain is shifted by the TCK input.
8. Return to Run-Test/Idle.
Table 35-11. SAMPLE_PRELOAD Details
Instructions Details
IR input value 00010 (0x02)
IR output value p0001
DR Size Depending on boundary-scan chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Depending on boundary-scan chain, see BSDL-file.
35.5.2.3 EXTEST
This instruction selects the boundary-scan chain as Data Register for testing circuitry external to
the 32-bit AVR package. The contents of the latched outputs of the boundary-scan chain is
driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.
Starting in Run-Test/Idle, the EXTEST instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the output pins.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: The data on the external pins is sampled into the boundary-scan chain.
8. In Shift-DR: The boundary-scan chain is shifted by the TCK input.
9. In Update-DR: The data from the scan chain is applied to the output pins.
10. Return to Run-Test/Idle.
Table 35-12. EXTEST Details
Instructions Details
IR input value 00011 (0x03)
IR output value p0001
DR Size Depending on boundary-scan chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Depending on boundary-scan chain, see BSDL-file.
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35.5.2.4 INTEST
This instruction selects the boundary-scan chain as Data Register for testing internal logic in the
device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are
captured by the boundary-scan chain. The device output pins are driven from the boundary-scan
chain.
Starting in Run-Test/Idle, the INTEST instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the internal logic
inputs.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: The data on the internal logic is sampled into the boundary-scan chain.
8. In Shift-DR: The boundary-scan chain is shifted by the TCK input.
9. In Update-DR: The data from the boundary-scan chain is applied to internal logic
inputs.
10. Return to Run-Test/Idle.
Table 35-13. INTEST Details
Instructions Details
IR input value 00100 (0x04)
IR output value p0001
DR Size Depending on boundary-scan chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Depending on boundary-scan chain, see BSDL-file.
35.5.2.5 CLAMP
This instruction selects the Bypass register as Data Register. The device output pins are driven
from the boundary-scan chain.
Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the output pins.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register.
8. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register.
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9. Return to Run-Test/Idle.
Table 35-14. CLAMP Details
Instructions Details
IR input value 00110 (0x06)
IR output value p0001
DR Size 1
DR input value x
DR output value x
35.5.2.6 BYPASS
This instruction selects the 1-bit Bypass Register as Data Register.
Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register.
7. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register.
8. Return to Run-Test/Idle.
Table 35-15. BYPASS Details
Instructions Details
IR input value 11111 (0x1F)
IR output value p0001
DR Size 1
DR input value x
DR output value x
35.5.3 Private JTAG Instructions
The 32-bit AVR defines a number of private JTAG instructions, not defined by the JTAG stan-
dard. Each instruction is briefly described in text, with details following in table form.
35.5.3.1 NEXUS_ACCESS
This instruction allows Nexus-compliant access to the On-Chip Debug registers through the
SAB. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through
the JTAG port.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the NEXUS_ACCESS instruction is selected, and
toggles between address and data mode each time a data scan completes with the busy bit
cleared.
NOTE: The polarity of the direction bit is inverse of the Nexus standard.
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Starting in Run-Test/Idle, OCD registers are accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the
OCD register.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a
write operation, scan in the new contents of the register.
9. Return to Run-Test/Idle.
For any operation, the full 7 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 35-16. NEXUS_ACCESS Details
Instructions Details
IR input value 10000 (0x10)
IR output value peb01
DR Size 34 bits
DR input value (Address phase) aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx
DR output value (Address phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
35.5.3.2 MEMORY_SERVICE
This instruction allows access to registers in an optional Memory Service Unit. The 7-bit register
index, a read/write control bit, and the 32-bit data is accessed through the JTAG port.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_SERVICE instruction is selected, and
toggles between address and data mode each time a data scan completes with the busy bit
cleared.
Starting in Run-Test/Idle, Memory Service registers are accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the
Memory Service register.
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7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a
write operation, scan in the new contents of the register.
9. Return to Run-Test/Idle.
For any operation, the full 7 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 35-17. MEMORY_SERVICE Details
Instructions Details
IR input value 10100 (0x14)
IR output value peb01
DR Size 34 bits
DR input value (Address phase) aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx
DR output value (Address phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
35.5.3.3 MEMORY_SIZED_ACCESS
This instruction allows access to the entire Service Access Bus data area. Data is accessed
through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. Not all units
mapped on the SAB bus may support all sizes of accesses, e.g., some may only support word
accesses.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_SIZED_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
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The size field is encoded as i Table 35-18.
Table 35-18. Size Field Semantics
Size field value Access size Data alignment
Address modulo 4 : data alignment
0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx
00 Byte (8 bits) 1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx
2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx
3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd
Address modulo 4 : data alignment
0: dddddddd dddddddd xxxxxxxx xxxxxxxx
01 Halfword (16 bits) 1: Not allowed
2: xxxxxxxx xxxxxxxx dddddddd dddddddd
3: Not allowed
Address modulo 4 : data alignment
0: dddddddd dddddddd dddddddd dddddddd
10 Word (32 bits) 1: Not allowed
2: Not allowed
3: Not allowed
11 Reserved N/A
Starting in Run-Test/Idle, SAB data is accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write), 2-bit access size, and the 36-bit
address of the data to access.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a
write operation, scan in the new contents of the area.
9. Return to Run-Test/Idle.
For any operation, the full 36 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 35-19. MEMORY_SIZED_ACCESS Details
Instructions Details
IR input value 10101 (0x15)
IR output value peb01
DR Size 39 bits
DR input value (Address phase) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xxxxxxx
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Table 35-19. MEMORY_SIZED_ACCESS Details (Continued)
Instructions Details
DR output value (Address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
DR output value (Data read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
35.5.3.4 MEMORY_WORD_ACCESS
This instruction allows access to the entire Service Access Bus data area. Data is accessed
through the 34 MSB of the SAB address, a direction bit, and 32 bits of data. This instruction is
identical to MEMORY_SIZED_ACCESS except that it always does word sized accesses. The
size field is implied, and the two lowest address bits are removed and not scanned in.
Note: This instruction was previously known as MEMORY_ACCESS, and is provided for back-
wards compatibility.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_WORD_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
Starting in Run-Test/Idle, SAB data is accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 34-bit address of the
data to access.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a
write operation, scan in the new contents of the area.
9. Return to Run-Test/Idle.
For any operation, the full 34 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 35-20. MEMORY_WORD_ACCESS Details
Instructions Details
IR input value 10001 (0x11)
IR output value peb01
DR Size 35 bits
DR input value (Address phase) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aar
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xxx
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Table 35-20. MEMORY_WORD_ACCESS Details (Continued)
Instructions Details
DR output value (Address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb
DR output value (Data read phase) xeb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
35.5.3.5 MEMORY_BLOCK_ACCESS
This instruction allows access to the entire SAB data area. Up to 32 bits of data is accessed at a
time, while the address is sequentially incremented from the previously used address.
In this mode, the SAB address, size, and access direction is not provided with each access.
Instead, the previous address is auto-incremented depending on the specified size and the pre-
vious operation repeated. The address must be set up in advance with
MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS. It is allowed, but not required, to
shift data after shifting the address.
This instruction is primarily intended to speed up large quantities of sequential word accesses. It
is possible to use it also for byte and halfword accesses, but the overhead in this is case much
larger as 32 bits must still be shifted for each access.
The following sequence should be used:
1. Use the MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS to read or write the
first location.
2. Return to Run-Test/Idle.
3. Select the IR Scan path.
4. In Capture-IR: The IR output value is latched into the shift register.
5. In Shift-IR: The instruction register is shifted by the TCK input.
6. Return to Run-Test/Idle.
7. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corre-
sponding to the next byte, halfword, or word location).
8. In Shift-DR: For a read operation, scan out the contents of the next addressed location.
For a write operation, scan in the new contents of the next addressed location.
9. Go to Update-DR.
10. If the block access is not complete, return to Select-DR Scan and repeat the access.
11. If the block access is complete, return to Run-Test/Idle.
For write operations, 32 data bits must be provided, or the result will be undefined. For read
operations, shifting may be terminated once the required number of bits have been acquired.
Table 35-21. MEMORY_BLOCK_ACCESS Details
Instructions Details
IR input value 10010 (0x12)
IR output value peb01
DR Size 34 bits
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
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Table 35-21. MEMORY_BLOCK_ACCESS Details (Continued)
Instructions Details
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx
DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% trans-
fer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency.
35.5.3.6 CANCEL_ACCESS
If a very slow memory location is accessed during a SAB memory access, it could take a very
long time until the busy bit is cleared, and the SAB becomes ready for the next operation. The
CANCEL_ACCESS instruction provides a possibility to abort an ongoing transfer and report a
timeout to the JTAG master.
When the CANCEL_ACCESS instruction is selected, the current access will be terminated as
soon as possible. There are no guarantees about how long this will take, as the hardware may
not always be able to cancel the access immediately. The SAB is ready to respond to a new
command when the busy bit clears.
Starting in Run-Test/Idle, CANCEL_ACCESS is accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
Table 35-22. CANCEL_ACCESS Details
Instructions Details
IR input value 10011 (0x13)
IR output value peb01
DR Size 1
DR input value x
DR output value 0
35.5.3.7 SYNC
This instruction allows external debuggers and testers to measure the ratio between the external
JTAG clock and the internal system clock. The SYNC data register is a 16-bit counter that
counts down to zero using the internal system clock. The busy bit stays high until the counter
reaches zero.
Starting in Run-Test/Idle, SYNC instruction is used in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
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6. Scan in an 16-bit counter value.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7.
9. Calculate an approximation to the internal clock speed using the elapsed time and the
counter value.
10. Return to Run-Test/Idle.
The full 16-bit counter value must be provided when starting the synch operation, or the result
will be undefined. When reading status, shifting may be terminated once the required number of
bits have been acquired.
Table 35-23. SYNC_ACCESS Details
Instructions Details
IR input value 10111 (0x17)
IR output value peb01
DR Size 16 bits
DR input value dddddddd dddddddd
DR output value xxxxxxxx xxxxxxeb
35.5.3.8 AVR_RESET
This instruction allows a debugger or tester to directly control separate reset domains inside the
chip. The shift register contains one bit for each controllable reset domain. Setting a bit to one
resets that domain and holds it in reset. Setting a bit to zero releases the reset for that domain.
The AVR_RESET instruction can be used in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the value corresponding to the reset domains the JTAG master
wants to reset into the data register.
7. Return to Run-Test/Idle.
8. Stay in run test idle for at least 10 TCK clock cycles to let the reset propagate to the
system.
See the device specific documentation for the number of reset domains, and what these
domains are.
For any operation, all bits must be provided or the result will be undefined.
Table 35-24. AVR_RESET Details
Instructions Details
IR input value 01100 (0x0C)
IR output value p0001
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Table 35-24. AVR_RESET Details (Continued)
Instructions Details
DR Size Device specific.
DR input value Device specific.
DR output value Device specific.
35.5.3.9 CHIP_ERASE
This instruction allows a programmer to completely erase all nonvolatile memories in a chip.
This will also clear any security bits that are set, so the device can be accessed normally. In
devices without non-volatile memories this instruction does nothing, and appears to complete
immediately.
The erasing of non-volatile memories starts as soon as the CHIP_ERASE instruction is selected.
The CHIP_ERASE instruction selects a 1 bit bypass data register.
A chip erase operation should be performed as:
1. Reset the system and stop the CPU from executing.
2. Select the IR Scan path.
3. In Capture-IR: The IR output value is latched into the shift register.
4. In Shift-IR: The instruction register is shifted by the TCK input.
5. Check the busy bit that was scanned out during Shift-IR. If the busy bit was set goto 2.
6. Return to Run-Test/Idle.
Table 35-25. CHIP_ERASE Details
Instructions Details
IR input value 01111 (0x0F)
p0b01
IR output value
Where b is the busy bit.
DR Size 1 bit
DR input value x
DR output value 0
35.5.3.10 HALT
This instruction allows a programmer to easily stop the CPU to ensure that it does not execute
invalid code during programming.
This instruction selects a 1-bit halt register. Setting this bit to one resets the device and halts the
CPU. Setting this bit to zero resets the device and releases the CPU to run normally. The value
shifted out from the data register is one if the CPU is halted.
The HALT instruction can be used in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
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6. In Shift-DR: Scan in the value 1 to halt the CPU, 0 to start CPU execution.
7. Return to Run-Test/Idle.
Table 35-26. HALT Details
Instructions Details
IR input value 11100 (0x1C)
IR output value p0001
DR Size 1 bit
DR input value d
DR output value d
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35.5.4 JTAG Data Registers
The following device specific registers can be selected as JTAG scan chain depending on the
instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly
described in the functional description of the relevant instructions.
35.5.4.1 Device Identification Register
The Device Identification Register contains a unique identifier for each product. The register is
selected by the IDCODE instruction, which is the default instruction after a JTAG reset.
MSB LSB
Bit 31 28 27 12 11 1 0
Device ID Revision Part Number Manufacturer ID 1
4 bits 16 bits 11 bits 1 bit
Revision This is a 4 bit number identifying the revision of the component.
Rev A = 0x0, B = 0x1, etc.
Part Number The part number is a 16 bit code identifying the component.
Manufacturer ID The Manufacturer ID is a 11 bit code identifying the manufacturer.
The JTAG manufacturer ID for ATMEL is 0x01F.
•Device specific ID codes
The different device configurations have different JTAG ID codes, as shown in Table 35-27.
Note that if the flash controller is statically reset, the ID code will be undefined.
Table 35-27. Device and JTAG ID
Device name JTAG ID code (r is the revision number)
AT32UC3A3256S 0xr202003F
AT32UC3A3128S 0xr202103F
AT32UC3A364S 0xr202203F
AT32UC3A3256 0xr202603F
AT32UC3A3128 0xr202703F
AT32UC3A364 0xr202803F
AT32UC3A4256S 0xr202903F
AT32UC3A4128S 0xr202a03F
AT32UC3A464S 0xr202b03F
AT32UC3A4256 0xr202c03F
AT32UC3A128 0xr202d03F
AT32UC3A64 0xr202e03F
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35.5.4.2 Reset register
The reset register is selected by the AVR_RESET instruction and contains one bit for each reset
domain in the device. Setting each bit to one will keep that domain reset until the bit is cleared.
LSB
Bit 4 3 2 1 0
Device ID OCD APP RESERVED RESERVED CPU
CPU CPU
APP HSB and PB buses
OCD On-Chip Debug logic and registers
RSERVED No effect
Note: This register is primarily intended for compatibility with other 32-bit AVR devices. Certain
operations may not function correctly when parts of the system are reset. It is generally recom-
mended to only write 0x11111 or 0x00000 to these bits to ensure no unintended side effects
occur.
35.5.4.3 Boundary-Scan Chain
The Boundary-Scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the
internal logic. Typically, output value, output enable, and input data are all available in the
boundary scan chain.
The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file
available at the Atmel web site.
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36. Electrical Characteristics
36.1 Absolute Maximum Ratings*
Operating Temperature.................................... -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -60°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or
Voltage on Input Pin other conditions beyond those indicated in the
with respect to Ground ........................................-0.3V to 3.6V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage (VDDCORE) ..................... 1.95V conditions for extended periods may affect
device reliability.
Maximum Operating Voltage (VDDIO).............................. 3.6V
Total DC Output Current on all I/O Pin
for TQFP144 package ................................................. 370 mA
for TFBGA144 package ............................................... 370 mA
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36.2 DC Characteristics
The following characteristics are applicable to the operating temperature range: T A = -40°C to 85°C, unless otherwise
specified and are certified for a junction temperature up toTJ = 100°C.
Table 36-1. DC Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VVDDIO DC Supply Peripheral I/Os 3.0 3.6 V
VVDDANA DC Analog Supply 3.0 3.6 V
All I/O pins except TWCK, TWD,
-0.3 +0.8 V
RESET_N, TCK, TDI
VIL Input Low-level Voltage VVDDIO VVDDIO
TWCK, TWD V
x0.7 +0.5
RESET_N, TCK, TDI +0.8V V
All I/O pins except TWCK, TWD 2.0 3.6 V
VIH Input High-level Voltage
TWCK, TWD V
IOL = -2mA for Pin drive x1
VOL Output Low-level Voltage IOL = -4mA for Pin drive x2 0.4 V
IOL = -8mA for Pin drive x3
IOH = 2mA for Pin drive x1
VVDDIO
VOH Output High-level Voltage IOH = 4mA for Pin drive x2 V
-0.4
IOH = 8mA for Pin drive x3
ILEAK Input Leakage Current Pullup resistors disabled 0.05 1 µA
CIN Input Capacitance 7 pF
All I/O pins except RESET_N, TCK,
9 15 25 KΩ
RPULLUP Pull-up Resistance TDI, TMS
RESET_N, TCK, TDI, TMS 5 25 KΩ
Output Current
IO Pin drive 1x 2.0 mA
Pin drive 2x 4.0
Pin drive 3x 8.0
On VVDDIN = 3.3V, TA = 25°C 30 µA
ISC Static Current
CPU in static mode TA = 85°C 175 µA
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36.2.1 I/O Pin Output Level Typical Characteristics
Figure 36-1. I/O Pin drive x2 Output Low Level Voltage (VOL) vs. Source Current
VddIo = 3.3V
1,8
90
1,6
25
1,4 -45
1,2
Voltage [V
1
0,8
0,6
0,4
0,2
0
0 5 10 15 20
Load current [mA]
Figure 36-2. I/O Pin drive x2 Output High Level Voltage (VOH) vs. Source Current
VddIo = 3.3V
3,5
2,5
Voltage [V
-45
2 25
90
1,5
0,5
0
0 5 10 15 20
Load current [mA]
36.3 I/O pin Characteristics
These parameters are given in the following conditions:
• VDDCORE = 1.8V
• VDDIO = 3.3V
• Ambient Temperature = 25°C
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Table 36-2. Normal I/O Pin Characteristics
Symbol Parameter Conditions drive x2 drive x2 drive x3 Unit
10pf 40 66 100 MHz
fMAX Output frequency 30pf 18.2 35.7 61.6 MHz
60pf 7.5 18.5 36.3 MHz
10pf 2.7 1.4 0.9 ns
tRISE Rise time 30pf 6.9 3.5 1.9 ns
60pf 13.4 6.7 3.5 ns
10pf 3.2 1.7 0.9 ns
tFALL Fall time 30pf 8.6 4.3 2.26 ns
60pf 16.5 8.3 4.3 ns
36.4 Regulator characteristics
Table 36-3. Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VVDDIN Supply voltage (input) 3.0 3.3 3.6 V
VVDDCORE Supply voltage (output) 1.75 1.85 1.95 V
IOUT Maximum DC output current VVDDIN = 3.3V 100 mA
Table 36-4. Decoupling Requirements
Symbol Parameter Conditions Typ. Technology Unit
CIN1 Input Regulator Capacitor 1 1 NPO nF
CIN2 Input Regulator Capacitor 2 4.7 X7R µF
COUT1 Output Regulator Capacitor 1 470 NPO pF
COUT2 Output Regulator Capacitor 2 2.2 X7R µF
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36.5 Analog characteristics
36.5.1 ADC
Table 36-5. Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VVDDANA Analog Power Supply 3.0 3.6 V
Table 36-6. Decoupling Requirements
Symbol Parameter Conditions Typ. Technology Unit
CVDDANA Power Supply Capacitor 100 NPO nF
36.5.2 BOD
Table 36-7. 1.8V BOD Level Values
Symbol Parameter Value Conditions Min. Typ. Max. Unit
00 1111b 1.79 V
01 0111b 1.70 V
BODLEVEL
01 1111b 1.61 V
10 0111b 1.52 V
Table 36-7 describes the values of the BODLEVEL field in the flash FGPFR register.
Table 36-8. 3.3V BOD Level Values
Symbol Parameter Value Conditions Min. Typ. Max. Unit
Reset value 2.71 V
1011 2.27 V
1010 2.37 V
1001 2.46 V
1000 2.56 V
0111 2.66 V
BOD33LEVEL 0110 2.76 V
0101 2.86 V
0100 2.96 V
0011 3.06 V
0010 3.15 V
0001 3.25 V
0000 3.35 V
Table 36-8 describes the values of the BOD33.LEVEL field in the PM module
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Table 36-9. BOD Timing
Symbol Parameter Conditions Min. Typ. Max. Unit
Minimum time with VDDCORE <
TBOD Falling VDDCORE from 1.8V to 1.1V 300 800 ns
VBOD to detect power failure
36.5.3 Reset Sequence
Table 36-10. Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VDDIN/VDDIO rise rate to ensure
VDDRR 0.8 V/ms
power-on-reset
Rising threshold voltage: voltage up
VPOR+ to which device is kept under reset by Rising VDDIN: VRESTART -> VPOR+ 2.7 V
POR on rising VDDIN
Falling threshold voltage: voltage
VPOR- when POR resets device on falling Falling VDDIN: 3.3V -> VPOR- 2.7 V
VDDIN
On falling VDDIN, voltage must go
down to this value before supply can
VRESTART Falling VDDIN: 3.3V -> VRESTART 0.2 V
rise again to ensure reset signal is
released at VPOR+
Time for Cold System Startup: Time
TSSU1 for CPU to fetch its first instruction 480 960 µs
(RCosc not calibrated)
Time for Hot System Startup: Time for
TSSU2 CPU to fetch its first instruction 420 µs
(RCosc calibrated)
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Figure 36-3. MCU Cold Start-Up
VDDIN VBOD33LEVEL VBOD33LEVEL
VDDIO
VRESTART
RESET_N
Internal
BOD33 Reset
TSSU1
Internal
MCU Reset
Figure 36-4. MCU Cold Start-Up RESET_N Externally Driven
VDDIN VBOD33LEVEL VBOD33LEVEL
VDDIO
VRESTART
RESET_N
Internal
BOD33 Reset
TSSU1
Internal
MCU Reset
Figure 36-5. MCU Hot Start-Up
VDDIN
VDDIO
RESET_N
BOD Reset
WDT Reset
TSSU2
Internal
MCU Reset
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36.5.4 RESET_N Characteristics
Table 36-11. RESET_N Waveform Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
tRESET RESET_N minimum pulse width 10 ns
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36.6 Power Consumption
The values in Table 36-12 and Table 36-13 on page 970 are measured values of power con-
sumption with operating conditions as follows:
•VDDIO = 3.3V
•TA = 25°C
•I/Os are configured in input, pull-up enabled.
Figure 36-6. Measurement Setup
VDDANA
VDDIO
VDDIN
Amp0
Internal
Voltage
Regulator
VDDCORE
GNDCORE
GNDPLL
These figures represent the power consumption measured on the power supplies
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36.6.1 Power Consumtion for Different Sleep Modes
Table 36-12. Power Consumption for Different Sleep Modes
Mode Conditions(1) Typ. Unit
- CPU running a recursive Fibonacci Algorithm from flash and clocked from PLL0
at f MHz.
- Flash High Speed mode disable (f < 66 MHz)
- Voltage regulator is on. 0.626xf(MHz)+2.257 mA/MHz
- XIN0: external clock. Xin1 Stopped. XIN32 stopped.
Active - All peripheral clocks activated with a division by 8.
- GPIOs are inactive with internal pull-up, JTAG unconnected with external
pullup and Input pins are connected to GND
Same conditions with Flash High Speed mode enable (66< f < 84 MHz) 0.670xf(MHz)+2.257 mA/MHz
Same conditions with Flash High Speed mode disable at 60 MHz 40 mA
Idle See Active mode conditions 0.349xf(MHz)+0.968 mA/MHz
Same conditions at 60 MHz 21.8 mA
Frozen See Active mode conditions 0.098xf(MHz)+1.012 mA/MHz
Same conditions at 60 MHz 6.6 mA
Standby See Active mode conditions 0.066xf(MHz)+1.010 mA/MHz
Same conditions at 60 MHz 4.6 mA
- CPU running in sleep mode
- XIN0, Xin1 and XIN32 are stopped.
Stop - All peripheral clocks are desactived. 96 µA
- GPIOs are inactive with internal pull-up, JTAG unconnected with external
pullup and Input pins are connected to GND.
Deepstop See Stop mode conditions 54 µA
TA = 25 °C
CPU is in static mode
GPIOs on internal pull-up
Static on Amp0 31 µA
All peripheral clocks de-activated
DM and DP pins connected to ground
XIN0, Xin1 and XIN32 are stopped
Notes: 1. Core frequency is generated from XIN0 using the PLL.
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Table 36-13. Typical Cuurent Consumption by Peripheral
Peripheral Typ. Unit
ADC 7
AES 80
ABDAC 10
DMACA 70
EBI 23
EIC 0.5
GPIO 37
INTC 3
MCI 40
MSI 10
PDCA 20
µA/MHz
SDRAM 5
SMC 9
SPI 6
SSC 10
RTC 5
TC 8
TWIM 2
TWIS 2
USART 10
USBB 90
WDT 2
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36.7 System Clock Characteristics
These parameters are given in the following conditions:
• VDDCORE = 1.8V
36.7.1 CPU/HSB Clock Characteristics
Table 36-14. Core Clock Waveform Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
1/(tCPCPU) CPU Clock Frequency -40°C < Ambient Temperature < 70°C 84 MHz
1/(tCPCPU) CPU Clock Frequency -40°C < Ambient Temperature < 85°C 66 MHz
36.7.2 PBA Clock Characteristics
Table 36-15. PBA Clock Waveform Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
1/(tCPPBA) PBA Clock Frequency -40°C < Ambient Temperature < 70°C 84 MHz
1/(tCPPBA) PBA Clock Frequency -40°C < Ambient Temperature < 85°C 66 MHz
36.7.3 PBB Clock Characteristics
Table 36-16. PBB Clock Waveform Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
1/(tCPPBB) PBB Clock Frequency -40°C < Ambient Temperature < 70°C 84 MHz
1/(tCPPBB) PBB Clock Frequency -40°C < Ambient Temperature < 85°C 66 MHz
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36.8 Oscillator Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of
power supply, unless otherwise specified.
36.8.1 Slow Clock RC Oscillator
Table 36-17. RC Oscillator Frequency
Symbol Parameter Conditions Min. Typ. Max. Unit
Calibration point: TA = 85°C 115.2 116 KHz
FRC RC Oscillator Frequency TA = 25°C 112 KHz
TA = -40°C 105 108 KHz
36.8.2 32 KHz Oscillator
Table 36-18. 32 KHz Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
External clock on XIN32 30 MHz
1/(tCP32KHz) Oscillator Frequency
Crystal 32 768 Hz
CL Equivalent Load Capacitance 6 12.5 pF
ESR Crystal Equivalent Series Resistance 100 KΩ
(1)
CL = 6pF 600
tST Startup Time ms
CL = 12.5pF(1) 1200
tCH XIN32 Clock High Half-period 0.4 tCP 0.6 tCP
tCL XIN32 Clock Low Half-period 0.4 tCP 0.6 tCP
CIN XIN32 Input Capacitance 5 pF
Active mode 1.8 µA
IOSC Current Consumption
Standby mode 0.1 µA
Note: 1. CL is the equivalent load capacitance.
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36.8.3 Main Oscillators
Table 36-19. Main Oscillators Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
External clock on XIN 50 MHz
1/(tCPMAIN) Oscillator Frequency
Crystal 0.4 20 MHz
CL1, CL2 Internal Load Capacitance (CL1 = CL2) 7 pF
ESR Crystal Equivalent Series Resistance 75 Ω
Duty Cycle 40 50 60 %
f = 400 KHz 25
f = 8 MHz 4
tST Startup Time ms
f = 16 MHz 1.4
f = 20 MHz 1
tCH XIN Clock High Half-period 0.4 tCP 0.6 tCP
tCL XIN Clock Low Half-period 0.4 tCP 0.6 tCP
CIN XIN Input Capacitance 7 pF
Active mode at 400 KHz. Gain = G0 30
Active mode at 8 MHz. Gain = G1 45
IOSC Current Consumption µA
Active mode at 16 MHz. Gain = G2 95
Active mode at 20 MHz. Gain = G3 205
36.8.4 Phase Lock Loop (PLL0, PLL1)
Table 36-20. PLL Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
FOUT VCO Output Frequency 80 240 MHz
FIN Input Frequency (after input divider) 4 16 MHz
Active mode (Fout=80 MHz) 250 µA
IPLL Current Consumption
Active mode (Fout=240 MHz) 600 µA
36.8.5 USB Hi-Speed Phase Lock Loop
Table 36-21. PLL Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
FOUT VCO Output Frequency 480 MHz
FIN Input Frequency 12 MHz
Input Frequency Accuracy (applicable
Delta FIN to Clock signal on XIN or to Quartz -500 +500 ppm
tolerance)
IPLL Current Consumption Active mode @480MHz @1.8V 2.5 mA
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36.9 ADC Characteristics
Table 36-22. Channel Conversion Time and ADC Clock
Parameter Conditions Min. Typ. Max. Unit
10-bit resolution mode 5 MHz
ADC Clock Frequency
8-bit resolution mode 8 MHz
Startup Time Return from Idle Mode 20 µs
Track and Hold Acquisition Time 600 ns
ADC Clock = 5 MHz 2 µs
Conversion Time
ADC Clock = 8 MHz 1.25 µs
ADC Clock = 5 MHz 384 (1) kSPS
Throughput Rate
ADC Clock = 8 MHz 533 (2) kSPS
1. Corresponds to 13 clock cycles: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
2. Corresponds to 15 clock cycles: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
Table 36-23. ADC Power Consumption
Parameter Conditions Min. Typ. Max. Unit
(1)
Current Consumption on VDDANA On 13 samples with ADC clock = 5 MHz 1.25 mA
1. Including internal reference input current
Table 36-24. Analog Inputs
Parameter Conditions Min. Typ. Max. Unit
Input Voltage Range 0 VDDANA V
Input Leakage Current 1 µA
Input Capacitance 7 pF
Input Resistance 350 850 Ohm
Table 36-25. Transfer Characteristics in 8-bit mode
Parameter Conditions Min. Typ. Max. Unit
Resolution 8 Bit
ADC Clock = 5 MHz 0.8 LSB
Absolute Accuracy
ADC Clock = 8 MHz 1.5 LSB
ADC Clock = 5 MHz 0.35 0.5 LSB
Integral Non-linearity
ADC Clock = 8 MHz 0.5 1.5 LSB
ADC Clock = 5 MHz 0.3 0.5 LSB
Differential Non-linearity
ADC Clock = 8 MHz 0.5 1.5 LSB
Offset Error ADC Clock = 5 MHz -1.5 1.5 LSB
Gain Error ADC Clock = 5 MHz -0.5 0.5 LSB
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Table 36-26. Transfer Characteristics in 10-bit mode
Parameter Conditions Min. Typ. Max. Unit
Resolution 10 Bit
Absolute Accuracy ADC Clock = 5 MHz 3 LSB
Integral Non-linearity ADC Clock = 5 MHz 1.5 2 LSB
ADC Clock = 5 MHz 1 2 LSB
Differential Non-linearity
ADC Clock = 2.5 MHz 0.6 1 LSB
Offset Error ADC Clock = 5 MHz -2 2 LSB
Gain Error ADC Clock = 5 MHz -2 2 LSB
36.10 USB Transceiver Characteristics
36.10.1 Electrical Characteristics
Table 36-27. Electrical Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
Recommended External USB Series In series with each USB pin with
REXT 39 Ω
Resistor ±5%
RBIAS VBIAS External Resistor (1) ±1% 6810 Ω
CBIAS VBIAS External Capcitor 10 pF
1. The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buf-
fers can be found within the USB 2.0 electrical specifications.
36.10.2 Static Power Consumption
Table 36-28. Static Power Consumption
Symbol Parameter Conditions Min. Typ. Max. Unit
IBIAS Bias current consumption on VBG 1 µA
HS Transceiver and I/O current
8 µA
consumption
IVDDUTMI If cable is connected, add 200µA
FS/HS Transceiver and I/O current
(typical) due to Pull-up/Pull-down 3 µA
consumption
current consumption
36.10.3 Dynamic Power Consumption
Table 36-29. Dynamic Power Consumption
Symbol Parameter Conditions Min. Typ. Max. Unit
IBIAS Bias current consumption on VBG 0.7 0.8 mA
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Table 36-29. Dynamic Power Consumption
Symbol Parameter Conditions Min. Typ. Max. Unit
HS Transceiver current consumption HS transmission 47 60 mA
HS Transceiver current consumption HS reception 18 27 mA
FS/HS Transceiver current
FS transmission 0m cable (1) 4 6 mA
consumption
IVDDUTMI
FS/HS Transceiver current
FS transmission 5m cable 26 30 mA
consumption
FS/HS Transceiver current
FS reception 3 4.5 mA
consumption
1. Including 1 mA due to Pull-up/Pull-down current consumption.
34.5.5 USB High Speed Design Guidelines
In order to facilitate hardware design, Atmel provides an application note on www.atmel.com.
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36.11 EBI Timings
36.11.1 SMC Signals
These timings are given for worst case process, T = 85⋅C, VDDIO = 3V and 40 pF load
capacitance.
Table 36-30. SMC Clock Signal
Symbol Parameter Max.(1) Unit
1/(tCPSMC) SMC Controller Clock Frequency 1/(tcpcpu) MHz
Note: 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
Table 36-31. SMC Read Signals with Hold Settings
Symbol Parameter Min. Unit
NRD Controlled (READ_MODE = 1)
SMC1 Data Setup before NRD High 12 ns
SMC2 Data Hold after NRD High 0 ns
SMC3 NRD High to NBS0/A0 Change(1) nrd hold length * tCPSMC - 1.3 ns
(1)
SMC4 NRD High to NBS1 Change nrd hold length * tCPSMC - 1.3 ns
(1)
SMC5 NRD High to NBS2/A1 Change nrd hold length * tCPSMC - 1.3 ns
SMC7 NRD High to A2 - A23 Change(1) nrd hold length * tCPSMC - 1.3 ns
(1)
SMC8 NRD High to NCS Inactive (nrd hold length - ncs rd hold length) * tCPSMC - 2.3 ns
SMC9 NRD Pulse Width nrd pulse length * tCPSMC - 1.4 ns
NRD Controlled (READ_MODE = 0)
SMC10 Data Setup before NCS High 11.5 ns
SMC11 Data Hold after NCS High 0 ns
(1)
SMC12 NCS High to NBS0/A0 Change ncs rd hold length * tCPSMC - 2.3 ns
(1)
SMC13 NCS High to NBS0/A0 Change ncs rd hold length * tCPSMC - 2.3 ns
SMC14 NCS High to NBS2/A1 Change(1) ncs rd hold length * tCPSMC - 2.3 ns
SMC16 NCS High to A2 - A23 Change(1) ncs rd hold length * tCPSMC - 4 ns
(1)
SMC17 NCS High to NRD Inactive ncs rd hold length - nrd hold length)* tCPSMC - 1.3 ns
SMC18 NCS Pulse Width ncs rd pulse length * tCPSMC - 3.6 ns
Note: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
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Table 36-32. SMC Read Signals with no Hold Settings
Symbol Parameter Min. Unit
NRD Controlled (READ_MODE = 1)
SMC19 Data Setup before NRD High 13.7 ns
SMC20 Data Hold after NRD High 1 ns
NRD Controlled (READ_MODE = 0)
SMC21 Data Setup before NCS High 13.3 ns
SMC22 Data Hold after NCS High 0 ns
Table 36-33. SMC Write Signals with Hold Settings
Symbol Parameter Min. Unit
NRD Controlled (READ_MODE = 1)
SMC23 Data Out Valid before NWE High (nwe pulse length - 1) * tCPSMC - 0.9 ns
SMC24 Data Out Valid after NWE High(1) nwe hold length * tCPSMC - 6 ns
(1)
SMC25 NWE High to NBS0/A0 Change nwe hold length * tCPSMC - 1.9 ns
(1)
SMC26 NWE High to NBS1 Change nwe hold length * tCPSMC - 1.9 ns
(1)
SMC29 NWE High to A1 Change nwe hold length * tCPSMC - 1.9 ns
SMC31 NWE High to A2 - A23 Change(1) nwe hold length * tCPSMC - 1.7 ns
(1)
SMC32 NWE High to NCS Inactive (nwe hold length - ncs wr hold length)* tCPSMC - 2.9 ns
SMC33 NWE Pulse Width nwe pulse length * tCPSMC - 0.9 ns
NRD Controlled (READ_MODE = 0)
SMC34 Data Out Valid before NCS High (ncs wr pulse length - 1)* tCPSMC - 4.6 ns
SMC35 Data Out Valid after NCS High(1) ncs wr hold length * tCPSMC - 5.8 ns
(1)
SMC36 NCS High to NWE Inactive (ncs wr hold length - nwe hold length)* tCPSMC - 0.6 ns
Note: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “nwe hold
length"
Table 36-34. SMC Write Signals with No Hold Settings (NWE Controlled only)
Symbol Parameter Min. Unit
SMC37 NWE Rising to A2-A25 Valid 5.4 ns
SMC38 NWE Rising to NBS0/A0 Valid 5 ns
SMC39 NWE Rising to NBS1 Change 5 ns
SMC40 NWE Rising to A1/NBS2 Change 5 ns
SMC41 NWE Rising to NBS3 Change 5 ns
SMC42 NWE Rising to NCS Rising 5.1 ns
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Table 36-34. SMC Write Signals with No Hold Settings (NWE Controlled only)
Symbol Parameter Min. Unit
SMC43 Data Out Valid before NWE Rising (nwe pulse length - 1) * tCPSMC - 1.2 ns
SMC44 Data Out Valid after NWE Rising 5 ns
SMC45 NWE Pulse Width nwe pulse length * tCPSMC - 0.9 ns
Figure 36-7. SMC Signals for NCS Controlled Accesses.
SMC16 SMC16 SMC16
A2-A25
SMC12 SMC12 SMC12
SMC13 SMC13 SMC13
SMC14 SMC14 SMC14
SMC15 SMC15 SMC15
A0/A1/NBS[3:0]
NRD
SMC17
SMC17
SMC18 SMC18 SMC18
NCS
SMC21 SMC22 SMC10 SMC11 SMC34 SMC35
D0 - D15
SMC36
NWE
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Figure 36-8. SMC Signals for NRD and NRW Controlled Accesses.
SMC7 SMC37 SMC7 SMC31
A2-A25
SMC3 SMC38 SMC3 SMC25
SMC4 SMC39 SMC4 SMC26
SMC5 SMC40 SMC5 SMC29
SMC6 SMC41 SMC6 SMC30
A0/A1/NBS[3:0]
SMC42 SMC8 SMC32
NCS
SMC8
SMC9 SMC9
NRD
SMC19 SMC20 SMC43 SMC44 SMC2 SMC23 SMC24
SMC1
D0 - D15
SMC45 SMC33
NWE
36.11.2 SDRAM Signals
These timings are given for 10 pF load on SDCK and 40 pF on other signals.
Table 36-35. SDRAM Clock Signal.
Symbol Parameter Conditions Min. Max.(1) Unit
1/(tCPSDCK) SDRAM Controller Clock Frequency 1/(tcpcpu) MHz
Note: 1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB.
Table 36-36. SDRAM Clock Signal
Symbol Parameter Conditions Min. Max. Unit
SDRAMC1 SDCKE High before SDCK Rising Edge 7.4 ns
SDRAMC2 SDCKE Low after SDCK Rising Edge 3.2 ns
SDRAMC3 SDCKE Low before SDCK Rising Edge 7 ns
SDRAMC4 SDCKE High after SDCK Rising Edge 2.9 ns
SDRAMC5 SDCS Low before SDCK Rising Edge 7.5 ns
SDRAMC6 SDCS High after SDCK Rising Edge 1.6 ns
SDRAMC7 RAS Low before SDCK Rising Edge 7.2 ns
SDRAMC8 RAS High after SDCK Rising Edge 2.3 ns
SDRAMC9 SDA10 Change before SDCK Rising Edge 7.6 ns
SDRAMC10 SDA10 Change after SDCK Rising Edge 1.9 ns
SDRAMC11 Address Change before SDCK Rising Edge 6.2 ns
SDRAMC12 Address Change after SDCK Rising Edge 2.2 ns
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Table 36-36. SDRAM Clock Signal
Symbol Parameter Conditions Min. Max. Unit
SDRAMC13 Bank Change before SDCK Rising Edge 6.3 ns
SDRAMC14 Bank Change after SDCK Rising Edge 2.4 ns
SDRAMC15 CAS Low before SDCK Rising Edge 7.4 ns
SDRAMC16 CAS High after SDCK Rising Edge 1.9 ns
SDRAMC17 DQM Change before SDCK Rising Edge 6.4 ns
SDRAMC18 DQM Change after SDCK Rising Edge 2.2 ns
SDRAMC19 D0-D15 in Setup before SDCK Rising Edge 9 ns
SDRAMC20 D0-D15 in Hold after SDCK Rising Edge 0 ns
SDRAMC23 SDWE Low before SDCK Rising Edge 7.6 ns
SDRAMC24 SDWE High after SDCK Rising Edge 1.8 ns
SDRAMC25 D0-D15 Out Valid before SDCK Rising Edge 7.1 ns
SDRAMC26 D0-D15 Out Valid after SDCK Rising Edge 1.5 ns
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Figure 36-9. SDRAMC Signals relative to SDCK.
SDCK
SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4
SDCKE
SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6
SDCS
SDRAMC7 SDRAMC8
RAS
SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16
CAS
SDRAMC23 SDRAMC24
SDWE
SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10
SDA10
SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12
A0 - A9,
A11 - A13
SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14
BA0/BA1
SDRAMC17 SDRAMC18 SDRAMC17 SDRAMC18
DQM0 -
DQM3
SDRAMC19 SDRAMC20
D0 - D15
Read
SDRAMC25 SDRAMC26
D0 - D15
to Write
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36.12 JTAG Characteristics
36.12.1 JTAG Interface Signals
Table 36-37. JTAG Interface Timing Specification
Symbol Parameter Conditions (1) Min. Max. Unit
JTAG0 TCK Low Half-period 6 ns
JTAG1 TCK High Half-period 3 ns
JTAG2 TCK Period 9 ns
JTAG3 TDI, TMS Setup before TCK High 1 ns
JTAG4 TDI, TMS Hold after TCK High 0 ns
JTAG5 TDO Hold Time 4 ns
JTAG6 TCK Low to TDO Valid 6 ns
JTAG7 Device Inputs Setup Time ns
JTAG8 Device Inputs Hold Time ns
JTAG9 Device Outputs Hold Time ns
JTAG10 TCK to Device Outputs Valid ns
1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF
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Figure 36-10. JTAG Interface Signals
JTAG2
TCK
JTAG JTAG1
0
TMS/TDI
JTAG3 JTAG4
TDO
JTAG5
JTAG6
Device
Inputs
JTAG7 JTAG8
Device
Outputs
JTAG9
JTAG10
36.13 SPI Characteristics
Figure 36-11. SPI Master mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
SPI0 SPI1
MISO
SPI2
MOSI
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Figure 36-12. SPI Master mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
SPI3 SPI4
MISO
SPI5
MOSI
Figure 36-13. SPI Slave mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
SPI6
MISO
SPI7 SPI8
MOSI
Figure 36-14. SPI Slave mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
SPI9
MISO
SPI10 SPI11
MOSI
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Table 36-38. SPI Timings
Symbol Parameter Conditions (1) Min. Max. Unit
MISO Setup time before SPCK rises 22 +
SPI0 3.3V domain ns
(master) (tCPMCK)/2 (2)
MISO Hold time after SPCK rises
SPI1 3.3V domain 0 ns
(master)
SPCK rising to MOSI Delay
SPI2 3.3V domain 7 ns
(master)
MISO Setup time before SPCK falls 22 +
SPI3 3.3V domain ns
(master) (tCPMCK)/2 (3)
MISO Hold time after SPCK falls
SPI4 3.3V domain 0 ns
(master)
SPCK falling to MOSI Delay
SPI5 3.3V domain 7 ns
master)
SPCK falling to MISO Delay
SPI6 3.3V domain 26.5 ns
(slave)
MOSI Setup time before SPCK rises
SPI7 3.3V domain 0 ns
(slave)
MOSI Hold time after SPCK rises
SPI8 3.3V domain 1.5 ns
(slave)
SPCK rising to MISO Delay
SPI9 3.3V domain 27 ns
(slave)
MOSI Setup time before SPCK falls
SPI10 3.3V domain 0 ns
(slave)
MOSI Hold time after SPCK falls
SPI11 3.3V domain 1 ns
(slave)
1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF
2. tCPMCK: Master Clock period in ns.
3. tCPMCK: Master Clock period in ns.
36.14 MCI
The High Speed MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specifi-
cation V4.2, the SD Memory Card Specification V2.0, the SDIO V1.1 specification and CE-ATA
V1.1.
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36.15 Flash Memory Characteristics
The following table gives the device maximum operating frequency depending on the field FWS
of the Flash FSR register. This field defines the number of wait states required to access the
Flash Memory. Flash operating frequency equals the CPU/HSB frequency.
Table 36-39. Flash Operating Frequency
Symbol Parameter Conditions Min. Typ. Max. Unit
FWS = 0
High Speed Read Mode Disable 36 MHz
-40°C < Ambient Temperature < 85°C
FWS = 1
High Speed Read Mode Disable 66 MHz
FFOP -40°C < Ambient Temperature < 85°C
Flash Operating Frequency
FWS = 0
High Speed Read Mode Enable 42 MHz
-40°C < Ambient Temperature < 70°C
FWS = 1
High Speed Read Mode Enable 84 MHz
-40°C < Ambient Temperature < 70°C
Table 36-40. Parts Programming Time
Symbol Parameter Conditions Min. Typ. Max. Unit
TFPP Page Programming Time 5 ms
TFFP Fuse Programming Time 0.5 ms
TFCE Chip erase Time 8 ms
Table 36-41. Flash Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
NFARRAY Flash Array Write/Erase cycle 100K cycle
NFFUSE General Purpose Fuses write cycle 1000 cycle
TFDR Flash Data Retention Time 15 year
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37. Mechanical Characteristics
37.1 Thermal Considerations
37.1.1 Thermal Data
Table 37-1 summarizes the thermal resistance data depending on the package.
Table 37-1. Thermal Resistance Data
Symbol Parameter Condition Package Typ Unit
θJA Junction-to-ambient thermal resistance Still Air TQFP144 40.3
°C/W
θJC Junction-to-case thermal resistance TQFP144 9.5
θJA Junction-to-ambient thermal resistance Still Air TFBGA144 28.5
°C/W
θJC Junction-to-case thermal resistance TFBGA144 6.9
θJA Junction-to-ambient thermal resistance Still Air VFBGA100 31.1
°C/W
θJC Junction-to-case thermal resistance VFBGA100 6.9
37.1.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1. T J = T A + ( P D × θ JA )
2. T J = T A + ( P D × ( θ HEATSINK + θ JC ) )
where:
• θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 37-1 on
page 988.
• θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in
Table 37-1 on page 988.
• θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
• PD = device power consumption (W) estimated from data provided in the section ”Regulator
characteristics” on page 963.
• TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second
equation should be used to compute the resulting average chip-junction temperature TJ in °C.
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37.2 Package Drawings
Figure 37-1. TFBGA 144 package drawing
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Figure 37-2. LQFP-144 package drawing
Table 37-2. Device and Package Maximum Weight
1300 mg
Table 37-3. Package Characteristics
Moisture Sensitivity Level MSL3
Table 37-4. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification E3
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Figure 37-3. VFBGA-100 package drawing
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37.3 Soldering Profile
Table 37-5 gives the recommended soldering profile from J-STD-20.
Table 37-5. Soldering Profile
Profile Feature Green Package
Average Ramp-up Rate (217°C to Peak) 3°C/Second max
Preheat Temperature 175°C ±25°C 150-200°C
Time Maintained Above 217°C 60-150 seconds
Time within 5°C of Actual Peak Temperature 30 seconds
Peak Temperature Range 260 (+0/-5°C)
Ramp-down Rate 6°C/Second max.
Time 25°C to Peak Temperature 8 minutes max
Note: It is recommended to apply a soldering temperature higher than 250°C.
A maximum of three reflow passes is allowed per component.
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38. Ordering Information
Temperature Operating
Device Ordering Code Package Conditioning Range
AT32UC3A3256S AT32UC3A3256S-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3256S-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3256S-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3256S-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3256 AT32UC3A3256-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3256-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3256-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3256-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3128S AT32UC3A3128S-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3128S-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3128S-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3128S-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3128 AT32UC3A3128-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3128-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3128-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3128-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A364S AT32UC3A364S-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A364S-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A364S-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A364S-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A364 AT32UC3A364-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A364-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A364-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A364-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A4256S AT32UC3A4256S-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A4256S-C1UR 100-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A4256 AT32UC3A4256-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A4256-C1UR 100-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A4128S AT32UC3A4128S-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A4128S-C1UR 100-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A4128 AT32UC3A4128-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A4128-C1UR 100-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A464S AT32UC3A464S-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A464S-C1UR 100-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A464 AT32UC3A464-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A464-C1UR 100-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
993
32072H–AVR32–10/2012
AT32UC3A3
39. Errata
39.1 Rev. H
39.1.1 General
Devices with Date Code lower than 1233 cannot operate with CPU frequency higher
than 66MHz in 1WS and 36MHz in 0WS in the whole temperature range
Fix/Workaround
None
DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal to
CTLx.DST_TR_WIDTH
Fix/Workaround
For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH.
39.1.2 Processor and Architecture
LDM instruction with PC in the register list and without ++ increments Rp
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlier or later instructions.
When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/Workaround
None.
MPU
Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
39.1.3 USB
UPCFGn.INTFRQ is irrelevant for isochronous pipe
As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or
every 125uS (High Speed).
Fix/Workaround
994
32072H–AVR32–10/2012
AT32UC3A3
For higher polling time, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
39.1.4 ADC
Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
39.1.5 USART
ISO7816 info register US_NER cannot be read
The NER register always returns zero.
Fix/Workaround
None.
The LIN ID is not transmitted in mode PDCM='0'
Fix/Workaround
Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first
address of the transmit buffer is not used. The LINID must be written in the LINIR register,
after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register
will start the transfer whenever the PDCA transfer is ready.
The LINID interrupt is only available for the header reception and not available for the
header transmission
Fix/Workaround
None.
USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set
to 1
If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never
starts.
Fix/Workaround
Only use PDCM=0 configuration with the PDCA transfer.
SPI
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
995
32072H–AVR32–10/2012
AT32UC3A3
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
Power Manager
OSC32 not functionnal in Crystal Modes (OSC32CTRL.MODE=1 or
OSC32CTRL.MODE=2)
OSC32 clock output is not active even if the oscillation signal is present on XIN32/XOUT32
pins.
OSC32RDY bit may still set even if the CLK32 is not active.
External clock mode (OSC32CTRL.MODE=0) is not affected.
Fix/Workaround
None.
Clock sources will not be stopped in STATIC sleep mode if the difference between
CPU and PBx division factor is too high
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will result in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequencies is less than or equal to 4.
PDCA
PCONTROL.CHxRES is non-functional
PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
AES
996
32072H–AVR32–10/2012
AT32UC3A3
URAD (Unspecified Register Access Detection Status) does not detect read accesses
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
39.1.6 HMATRIX
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
39.1.7 TWIM
TWIM SR.IDLE goes high immediately when NAK is received
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
TWIS
Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
TWIS stretch on Address match error
When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for
the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD
at the same time. This can cause a TWI timing violation.
997
32072H–AVR32–10/2012
AT32UC3A3
Fix/Workaround
None.
SSC
Frame Synchro and Frame Synchro Data are delayed by one clock cycle
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro.
39.1.8 FLASHC
Corrupted read in flash may happen after fuses write or erase operations (FLASHC
LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)
After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,
EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an
exception or to other errors derived from this corrupted read access.
Fix/Workaround
Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC
HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,
EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.
After these commands, read 3 times one flash page initialized to 00h. Disable the flash high
speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the
flash.
39.2 Rev. E
39.2.1 General
Devices cannot operate with CPU frequency higher than 66MHz in 1WS and 36MHz in
0WS
Fix/Workaround
None
Increased Power Consumption in VDDIO in sleep modes
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Fix/Workaround
Disable the OSC0 through the System Control Interface (SCIF) before going to any sleep
mode where the OSC0 is disabled, or pull down or up XIN0 and XOUT0 with 1 Mohm
resistor.
Power consumption in static mode The power consumption in static mode can be up
to 330µA on some parts (typical at 25°C)
Fix/Workaround
Set to 1b bit CORRS4 of the ECCHRS mode register (MD). In C-code: *((volatile int*)
(0xFFFE2404))= 0x400.
998
32072H–AVR32–10/2012
AT32UC3A3
DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal to
CTLx.DST_TR_WIDTH
Fix/Workaround
For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH.
3.3V supply monitor is not available
FGPFRLO[30:29] are reserved and should not be used by the application.
Fix/Workaround
None.
Service access bus (SAB) can not access DMACA registers
Fix/Workaround
None.
Processor and Architecture
LDM instruction with PC in the register list and without ++ increments Rp
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlier or later instructions.
When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/Workaround
None.
MPU
Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
39.2.2 USB
UPCFGn.INTFRQ is irrelevant for isochronous pipe
As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or
every 125uS (High Speed).
Fix/Workaround
For higher polling time, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
999
32072H–AVR32–10/2012
AT32UC3A3
39.2.3 ADC
Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
39.2.4 USART
ISO7816 info register US_NER cannot be read
The NER register always returns zero.
Fix/Workaround
None.
The LIN ID is not transmitted in mode PDCM='0'
Fix/Workaround
Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first
address of the transmit buffer is not used. The LINID must be written in the LINIR register,
after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register
will start the transfer whenever the PDCA transfer is ready.
The LINID interrupt is only available for the header reception and not available for the
header transmission
Fix/Workaround
None.
USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set
to 1
If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never
starts.
Fix/Workaround
Only use PDCM=0 configuration with the PDCA transfer.
The RTS output does not function correctly in hardware handshaking mode
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
ISO7816 Mode T1: RX impossible after any TX
RX impossible after any TX.
Fix/Workaround
SOFT_RESET on RX+ Config US_MR + Config_US_CR.
SPI
1000
32072H–AVR32–10/2012
AT32UC3A3
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
Power Manager
OSC32 not functionnal in Crystal Modes (OSC32CTRL.MODE=1 or
OSC32CTRL.MODE=2)
OSC32 clock output is not active even if the oscillation signal is present on XIN32/XOUT32
pins.
OSC32RDY bit may still set even if the CLK32 is not active.
External clock mode (OSC32CTRL.MODE=0) is not affected.
Fix/Workaround
None.
Clock sources will not be stopped in STATIC sleep mode if the difference between
CPU and PBx division factor is too high
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will result in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequencies is less than or equal to 4.
PDCA
1001
32072H–AVR32–10/2012
AT32UC3A3
PCONTROL.CHxRES is non-functional
PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
AES
URAD (Unspecified Register Access Detection Status) does not detect read accesses
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
39.2.5 HMATRIX
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
39.2.6 TWIM
TWIM SR.IDLE goes high immediately when NAK is received
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
1002
32072H–AVR32–10/2012
AT32UC3A3
TWIS
Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
TWIS stretch on Address match error
When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for
the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD
at the same time. This can cause a TWI timing violation.
Fix/Workaround
None.
MCI
MCI_CLK features is not available on PX12, PX13 and PX40
Fix/Workaround
MCI_CLK feature is available on PA27 only.
The busy signal of the responses R1b is not taken in account for CMD12
STOP_TRANSFER
It is not possible to know the busy status of the card during the response (R1b) for the com-
mands CMD12.
Fix/Workaround
The card busy line should be polled through the GPIO Input Value register (IVR) for com-
mands CMD12.
SSC
Frame Synchro and Frame Synchro Data are delayed by one clock cycle
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro.
39.2.7 FLASHC
Corrupted read in flash may happen after fuses write or erase operations (FLASHC
LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)
After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,
EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an
exception or to other errors derived from this corrupted read access.
Fix/Workaround
Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC
HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,
EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.
1003
32072H–AVR32–10/2012
AT32UC3A3
After these commands, read 3 times one flash page initialized to 00h. Disable the flash high
speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the
flash.
39.3 Rev. D
39.3.1 General
Devices cannot operate with CPU frequency higher than 66MHz in 1WS and 36MHz in
0WS
Fix/Workaround
None
DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal to
CTLx.DST_TR_WIDTH
Fix/Workaround
For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH.
3.3V supply monitor is not available
FGPFRLO[30:29] are reserved and should not be used by the application.
Fix/Workaround
None.
Service access bus (SAB) can not access DMACA registers
Fix/Workaround
None.
Processor and Architecture
LDM instruction with PC in the register list and without ++ increments Rp
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlier or later instructions.
When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/Workaround
None.
RETE instruction does not clear SREG[L] from interrupts
The RETE instruction clears SREG[L] as expected from exceptions.
Fix/Workaround
When using the STCOND instruction, clear SREG[L] in the stacked value of SR before
returning from interrupts with RETE.
1004
32072H–AVR32–10/2012
AT32UC3A3
RETS behaves incorrectly when MPU is enabled
RETS behaves incorrectly when MPU is enabled and MPU is configured so that system
stack is not readable in unprivileged mode.
Fix/Workaround
Make system stack readable in unprivileged mode, or return from supervisor mode using
rete instead of rets. This requires:
1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the
mode bits to the desired value must be done using a single mtsr instruction so it is done
atomically. Even if this step is generally described as not safe in the UC technical reference
manual, it is safe in this very specific case.
2. Execute the RETE instruction.
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
Multiply instructions do not work on RevD
All the multiply instructions do not work.
Fix/Workaround
Do not use the multiply instructions.
MPU
Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mode.
39.3.2 USB
UPCFGn.INTFRQ is irrelevant for isochronous pipe
As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or
every 125uS (High Speed).
Fix/Workaround
For higher polling time, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
39.3.3 ADC
Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
39.3.4 USART
ISO7816 info register US_NER cannot be read
The NER register always returns zero.
1005
32072H–AVR32–10/2012
AT32UC3A3
Fix/Workaround
None.
The LIN ID is not transmitted in mode PDCM='0'
Fix/Workaround
Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first
address of the transmit buffer is not used. The LINID must be written in the LINIR register,
after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register
will start the transfer whenever the PDCA transfer is ready.
The LINID interrupt is only available for the header reception and not available for the
header transmission
Fix/Workaround
None.
USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set
to 1
If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never
starts.
Fix/Workaround
Only use PDCM=0 configuration with the PDCA transfer.
The RTS output does not function correctly in hardware handshaking mode
The RTS signal is not generated properly when the USART receives data in hardware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
ISO7816 Mode T1: RX impossible after any TX
RX impossible after any TX.
Fix/Workaround
SOFT_RESET on RX+ Config US_MR + Config_US_CR.
SPI
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
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Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
Power Manager
OSC32 not functionnal in Crystal Modes (OSC32CTRL.MODE=1 or
OSC32CTRL.MODE=2)
OSC32 clock output is not active even if the oscillation signal is present on XIN32/XOUT32
pins.
OSC32RDY bit may still set even if the CLK32 is not active.
External clock mode (OSC32CTRL.MODE=0) is not affected.
Fix/Workaround
None.
Clock sources will not be stopped in STATIC sleep mode if the difference between
CPU and PBx division factor is too high
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will result in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequencies is less than or equal to 4.
PDCA
PCONTROL.CHxRES is non-functional
PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
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Fix/Workaround
Disable and then enable the peripheral after the transfer error.
AES
URAD (Unspecified Register Access Detection Status) does not detect read accesses
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
39.3.5 HMATRIX
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
39.3.6 TWIM
TWIM SR.IDLE goes high immediately when NAK is received
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
TWIS
TWIS Version Register reads zero
TWIS Version Register (VR) reads zero instead of 0x112.
Fix/Workaround
None.
39.3.7 MCI
The busy signal of the responses R1b is not taken in account for CMD12
STOP_TRANSFER
It is not possible to know the busy status of the card during the response (R1b) for the com-
mands CMD12.
Fix/Workaround
The card busy line should be polled through the GPIO Input Value register (IVR) for com-
mands CMD12.
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39.3.8 SSC
Frame Synchro and Frame Synchro Data are delayed by one clock cycle
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro.
39.3.9 FLASHC
Corrupted read in flash may happen after fuses write or erase operations (FLASHC
LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)
After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,
EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an
exception or to other errors derived from this corrupted read access.
Fix/Workaround
Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC
HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,
EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.
After these commands, read 3 times one flash page initialized to 00h. Disable the flash high
speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the
flash.
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40. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
40.1 Rev. H– 10/12
1. Updated max frequency
2. Added Flash Read High Speed Mode description in FLASHC chapter
3. Updated Electrical Characteristics accordingly to new max frequency
4. Fixed wrong description of PLLOPT[0] in PM chapter
5. Updated Errata section according to new maximum frequency
6. Added USB hi-speed PLL electrical characteristics
7 Added OSC32 Errata in Power Management sections for Rev D,E and H
40.2 Rev. G– 11/11
1. Add recommandation for MCI connection with more than 1 slot
40.3 Rev. F – 08/11
1. Final version
40.4 Rev. E – 06/11
1. Updated Errata for E and D
2. Updated FLASHC chapter with HSEN and HSDIS commands
40.5 Rev. D – 04/11
1. Updated Errata for revision H and E
2. Updated Reset Sequence
3. Updated Peripherals’ current consumption and others minor electrical charateristics
4. Updated Peripherals chapters
40.6 Rev. C – 03/10
1. Updated the datasheet with new revision H features.
1010
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40.7 Rev. B – 08/09
1. Updated the datasheet with new device AT32UC3A4.
40.8 Rev. A – 03/09
1. Initial revision.
1011
32072H–AVR32–10/2012
AT32UC3A3
Table of Contents
1 Description ............................................................................................... 3
2 Overview ................................................................................................... 4
2.1 Block Diagram ...................................................................................................4
2.2 Configuration Summary .....................................................................................5
3 Package and Pinout ................................................................................. 6
3.1 Package .............................................................................................................6
3.2 Peripheral Multiplexing on I/O lines ...................................................................9
3.3 Signal Descriptions ..........................................................................................14
3.4 I/O Line Considerations ...................................................................................19
3.5 Power Considerations .....................................................................................20
4 Processor and Architecture .................................................................. 21
4.1 Features ..........................................................................................................21
4.2 AVR32 Architecture .........................................................................................21
4.3 The AVR32UC CPU ........................................................................................22
4.4 Programming Model ........................................................................................26
4.5 Exceptions and Interrupts ................................................................................30
4.6 Module Configuration ......................................................................................34
5 Memories ................................................................................................ 35
5.1 Embedded Memories ......................................................................................35
5.2 Physical Memory Map .....................................................................................35
5.3 Peripheral Address Map ..................................................................................36
5.4 CPU Local Bus Mapping .................................................................................38
6 Boot Sequence ....................................................................................... 40
6.1 Starting of Clocks ............................................................................................40
6.2 Fetching of Initial Instructions ..........................................................................40
7 Power Manager (PM) .............................................................................. 41
7.1 Features ..........................................................................................................41
7.2 Overview ..........................................................................................................41
7.3 Block Diagram .................................................................................................42
7.4 Product Dependencies ....................................................................................43
7.5 Functional Description .....................................................................................43
7.6 User Interface ..................................................................................................55
1012
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8 Real Time Counter (RTC) ...................................................................... 80
8.1 Features ..........................................................................................................80
8.2 Overview ..........................................................................................................80
8.3 Block Diagram .................................................................................................80
8.4 Product Dependencies ....................................................................................80
8.5 Functional Description .....................................................................................81
8.6 User Interface ..................................................................................................83
9 Watchdog Timer (WDT) ......................................................................... 92
9.1 Features ..........................................................................................................92
9.2 Overview ..........................................................................................................92
9.3 Block Diagram .................................................................................................92
9.4 Product Dependencies ....................................................................................92
9.5 Functional Description .....................................................................................93
9.6 User Interface ..................................................................................................93
10 Interrupt Controller (INTC) .................................................................... 96
10.1 Features ..........................................................................................................96
10.2 Overview ..........................................................................................................96
10.3 Block Diagram .................................................................................................96
10.4 Product Dependencies ....................................................................................97
10.5 Functional Description .....................................................................................97
10.6 User Interface ................................................................................................100
10.7 Interrupt Request Signal Map ........................................................................104
11 External Interrupt Controller (EIC) ..................................................... 107
11.1 Features ........................................................................................................107
11.2 Overview ........................................................................................................107
11.3 Block Diagram ...............................................................................................108
11.4 I/O Lines Description .....................................................................................108
11.5 Product Dependencies ..................................................................................108
11.6 Functional Description ...................................................................................109
11.7 User Interface ................................................................................................113
11.8 Module Configuration ....................................................................................129
12 Flash Controller (FLASHC) ................................................................. 130
12.1 Features ........................................................................................................130
12.2 Overview ........................................................................................................130
12.3 Product dependencies ...................................................................................130
1013
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AT32UC3A3
12.4 Functional description ....................................................................................131
12.5 Flash commands ...........................................................................................134
12.6 General-purpose fuse bits .............................................................................136
12.7 Security bit .....................................................................................................138
12.8 User interface ................................................................................................139
12.9 Fuses Settings ...............................................................................................147
12.10 Serial number in the factory page ..................................................................148
12.11 Module configuration .....................................................................................148
13 HSB Bus Matrix (HMATRIX) ................................................................ 149
13.1 Features ........................................................................................................149
13.2 Overview ........................................................................................................149
13.3 Product Dependencies ..................................................................................149
13.4 Functional Description ...................................................................................149
13.5 User Interface ................................................................................................153
13.6 Bus Matrix Connections .................................................................................161
14 External Bus Interface (EBI) ................................................................ 163
14.1 Features ........................................................................................................163
14.2 Overview ........................................................................................................163
14.3 Block Diagram ...............................................................................................164
14.4 I/O Lines Description .....................................................................................165
14.5 Product Dependencies ..................................................................................166
14.6 Functional Description ...................................................................................168
14.7 Application Example ......................................................................................175
15 Static Memory Controller (SMC) ......................................................... 178
15.1 Features ........................................................................................................178
15.2 Overview ........................................................................................................178
15.3 Block Diagram ...............................................................................................179
15.4 I/O Lines Description .....................................................................................179
15.5 Product Dependencies ..................................................................................179
15.6 Functional Description ...................................................................................180
15.7 User Interface ................................................................................................212
16 SDRAM Controller (SDRAMC) ............................................................ 219
16.1 Features ........................................................................................................219
16.2 Overview ........................................................................................................219
16.3 Block Diagram ...............................................................................................220
1014
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AT32UC3A3
16.4 I/O Lines Description .....................................................................................220
16.5 Application Example ......................................................................................221
16.6 Product Dependencies ..................................................................................222
16.7 Functional Description ...................................................................................223
16.8 User Interface ................................................................................................232
17 Error Corrected Code Controller (ECCHRS) ...................................... 246
17.1 Features ........................................................................................................246
17.2 Overview ........................................................................................................246
17.3 Block Diagram ...............................................................................................247
17.4 Product Dependencies ..................................................................................247
17.5 Functional Description ...................................................................................248
17.6 User Interface ...............................................................................................254
17.7 Module Configuration ....................................................................................280
18 Peripheral DMA Controller (PDCA) .................................................... 281
18.1 Features ........................................................................................................281
18.2 Overview ........................................................................................................281
18.3 Block Diagram ...............................................................................................282
18.4 Product Dependencies ..................................................................................282
18.5 Functional Description ...................................................................................283
18.6 Performance Monitors ...................................................................................285
18.7 User Interface ................................................................................................286
18.8 Module Configuration ....................................................................................314
19 DMA Controller (DMACA) .................................................................... 316
19.1 Features ........................................................................................................316
19.2 Overview ........................................................................................................316
19.3 Block Diagram ...............................................................................................317
19.4 Product Dependencies ..................................................................................317
19.5 Functional Description ...................................................................................318
19.6 Arbitration for HSB Master Interface ..............................................................323
19.7 Memory Peripherals ......................................................................................323
19.8 Handshaking Interface ...................................................................................323
19.9 DMACA Transfer Types ................................................................................325
19.10 Programming a Channel ................................................................................329
19.11 Disabling a Channel Prior to Transfer Completion ........................................346
19.12 User Interface ................................................................................................348
1015
32072HAVR3210/2012
AT32UC3A3
19.13 Module Configuration ....................................................................................380
20 General-Purpose Input/Output Controller (GPIO) ............................. 381
20.1 Features ........................................................................................................381
20.2 Overview ........................................................................................................381
20.3 Block Diagram ...............................................................................................381
20.4 Product Dependencies ..................................................................................381
20.5 Functional Description ...................................................................................382
20.6 User Interface ................................................................................................386
20.7 Programming Examples ................................................................................401
20.8 Module configuration .....................................................................................403
21 Serial Peripheral Interface (SPI) ......................................................... 404
21.1 Features ........................................................................................................404
21.2 Overview ........................................................................................................404
21.3 Block Diagram ...............................................................................................405
21.4 Application Block Diagram .............................................................................405
21.5 I/O Lines Description .....................................................................................406
21.6 Product Dependencies ..................................................................................406
21.7 Functional Description ...................................................................................406
21.8 User Interface ................................................................................................417
21.9 Module Configuration ....................................................................................443
22 Two-wire Slave Interface (TWIS) ......................................................... 444
22.1 Features ........................................................................................................444
22.2 Overview ........................................................................................................444
22.3 List of Abbreviations ......................................................................................445
22.4 Block Diagram ...............................................................................................445
22.5 Application Block Diagram .............................................................................446
22.6 I/O Lines Description .....................................................................................446
22.7 Product Dependencies ..................................................................................446
22.8 Functional Description ...................................................................................447
22.9 User Interface ................................................................................................457
22.10 Module Configuration ....................................................................................473
23 Two-wire Master Interface (TWIM) ...................................................... 474
23.1 Features ........................................................................................................474
23.2 Overview ........................................................................................................474
23.3 List of Abbreviations ......................................................................................475
1016
32072HAVR3210/2012
AT32UC3A3
23.4 Block Diagram ...............................................................................................475
23.5 Application Block Diagram .............................................................................476
23.6 I/O Lines Description .....................................................................................476
23.7 Product Dependencies ..................................................................................476
23.8 Functional Description ...................................................................................478
23.9 User Interface ................................................................................................490
23.10 Module Configuration ....................................................................................507
24 Synchronous Serial Controller (SSC) ................................................ 508
24.1 Features ........................................................................................................508
24.2 Overview ........................................................................................................508
24.3 Block Diagram ...............................................................................................509
24.4 Application Block Diagram .............................................................................509
24.5 I/O Lines Description .....................................................................................510
24.6 Product Dependencies ..................................................................................510
24.7 Functional Description ...................................................................................510
24.8 SSC Application Examples ............................................................................522
24.9 User Interface ................................................................................................524
25 Universal Synchronous Asynchronous Receiver Transmitter (USART)
546
25.1 Features ........................................................................................................546
25.2 Overview ........................................................................................................546
25.3 Block Diagram ...............................................................................................547
25.4 I/O Lines Description ....................................................................................548
25.5 Product Dependencies ..................................................................................548
25.6 Functional Description ...................................................................................550
25.7 User Interface ................................................................................................593
26 ............................................................................................................... 621
26.1 Module Configuration ....................................................................................622
27 Hi-Speed USB Interface (USBB) ......................................................... 624
27.1 Features ........................................................................................................624
27.2 Overview ........................................................................................................624
27.3 Block Diagram ...............................................................................................625
27.4 Application Block Diagram .............................................................................626
27.5 I/O Lines Description .....................................................................................628
27.6 Product Dependencies ..................................................................................629
1017
32072HAVR3210/2012
AT32UC3A3
27.7 Functional Description ...................................................................................630
27.8 User Interface ................................................................................................665
27.9 Module Configuration ....................................................................................748
28 Timer/Counter (TC) .............................................................................. 749
28.1 Features ........................................................................................................749
28.2 Overview ........................................................................................................749
28.3 Block Diagram ...............................................................................................750
28.4 I/O Lines Description .....................................................................................750
28.5 Product Dependencies ..................................................................................750
28.6 Functional Description ...................................................................................751
28.7 User Interface ................................................................................................766
28.8 Module Configuration ....................................................................................789
29 Analog-to-Digital Converter (ADC) ..................................................... 790
29.1 Features ........................................................................................................790
29.2 Overview ........................................................................................................790
29.3 Block Diagram ...............................................................................................791
29.4 I/O Lines Description .....................................................................................791
29.5 Product Dependencies ..................................................................................791
29.6 Functional Description ...................................................................................792
29.7 User Interface ................................................................................................797
29.8 Module Configuration ....................................................................................810
30 HSB Bus Performance Monitor (BUSMON) ....................................... 811
30.1 Features ........................................................................................................811
30.2 Overview ........................................................................................................811
30.3 Block Diagram ...............................................................................................811
30.4 Product Dependencies ..................................................................................812
30.5 Functional Description ...................................................................................812
30.6 User interface ................................................................................................813
30.7 Module Configuration ....................................................................................820
31 MultiMedia Card Interface (MCI) ......................................................... 821
31.1 Features ........................................................................................................821
31.2 Overview ........................................................................................................821
31.3 Block Diagram ...............................................................................................822
31.4 I/O Lines Description .....................................................................................823
31.5 Product Dependencies ..................................................................................823
1018
32072HAVR3210/2012
AT32UC3A3
31.6 Functional Description ...................................................................................823
31.7 User Interface ................................................................................................841
31.8 Module Configuration ....................................................................................869
32 Memory Stick Interface (MSI) .............................................................. 870
32.1 Features ........................................................................................................870
32.2 Overview ........................................................................................................870
32.3 Block Diagram ...............................................................................................871
32.4 Product Dependencies ..................................................................................871
32.5 Connection to a Memory Stick .......................................................................872
32.6 Functional Description ...................................................................................873
32.7 User Interface ................................................................................................876
33 Advanced Encryption Standard (AES) ............................................... 890
33.1 Features ........................................................................................................890
33.2 Overview ........................................................................................................890
33.3 Product Dependencies ..................................................................................890
33.4 Functional Description ...................................................................................891
33.5 User Interface ................................................................................................897
33.6 Module Configuration ....................................................................................912
34 Audio Bitstream DAC (ABDAC) .......................................................... 913
34.1 Features ........................................................................................................913
34.2 Overview ........................................................................................................913
34.3 Block Diagram ...............................................................................................914
34.4 I/O Lines Description .....................................................................................914
34.5 Product Dependencies ..................................................................................914
34.6 Functional Description ...................................................................................915
34.7 User Interface ................................................................................................918
35 Programming and Debugging ............................................................ 926
35.1 Overview ........................................................................................................926
35.2 Service Access Bus .......................................................................................926
35.3 On-Chip Debug (OCD) ..................................................................................928
35.4 JTAG and Boundary-scan (JTAG) .................................................................935
35.5 JTAG Instruction Summary ...........................................................................943
36 Electrical Characteristics .................................................................... 960
36.1 Absolute Maximum Ratings* .........................................................................960
1019
32072HAVR3210/2012
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36.2 DC Characteristics .........................................................................................961
36.3 I/O pin Characteristics ...................................................................................962
36.4 Regulator characteristics ...............................................................................963
36.5 Analog characteristics ...................................................................................964
36.6 Power Consumption ......................................................................................968
36.7 System Clock Characteristics ........................................................................971
36.8 Oscillator Characteristics ...............................................................................972
36.9 ADC Characteristics ......................................................................................974
36.10 USB Transceiver Characteristics ...................................................................975
36.11 EBI Timings ...................................................................................................977
36.12 JTAG Characteristics .....................................................................................983
36.13 SPI Characteristics ........................................................................................984
36.14 MCI ................................................................................................................986
36.15 Flash Memory Characteristics .......................................................................987
37 Mechanical Characteristics ................................................................. 988
37.1 Thermal Considerations ................................................................................988
37.2 Package Drawings .........................................................................................989
37.3 Soldering Profile ............................................................................................992
38 Ordering Information ........................................................................... 993
39 Errata ..................................................................................................... 994
39.1 Rev. H ............................................................................................................994
39.2 Rev. E ............................................................................................................998
39.3 Rev. D ..........................................................................................................1004
40 Datasheet Revision History .............................................................. 1010
40.1 Rev. H– 10/12 ..............................................................................................1010
40.2 Rev. G– 11/11 .............................................................................................1010
40.3 Rev. F – 08/11 .............................................................................................1010
40.4 Rev. E – 06/11 .............................................................................................1010
40.5 Rev. D – 04/11 .............................................................................................1010
40.6 Rev. C – 03/10 .............................................................................................1010
40.7 Rev. B – 08/09 .............................................................................................1011
40.8 Rev. A – 03/09 .............................................................................................1011
1020
32072HAVR3210/2012
Atmel Corporation Atmel Asia Limited Atmel Munich GmbH Atmel Japan
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32072HAVR3210/2012
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