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(Before Press Power Button) : Power Sequence and Architecture Diagram

1. The document shows the power sequence and architecture diagram of a device's power management unit (PMU). 2. Key components include the USB-C port, battery charger, voltage regulators, power rails for different components (e.g. CPU, memory, storage), and power switches/controls. 3. The diagram illustrates how power from the USB-C port or battery is distributed to various parts of the device through the PMU and its voltage regulators.

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Yoho Y.
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0% found this document useful (0 votes)
248 views1 page

(Before Press Power Button) : Power Sequence and Architecture Diagram

1. The document shows the power sequence and architecture diagram of a device's power management unit (PMU). 2. Key components include the USB-C port, battery charger, voltage regulators, power rails for different components (e.g. CPU, memory, storage), and power switches/controls. 3. The diagram illustrates how power from the USB-C port or battery is distributed to various parts of the device through the PMU and its voltage regulators.

Uploaded by

Yoho Y.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Power sequence(before press power button)

and architecture diagram

23 PMU_PVDDMAIN_EN

PPDCIN_G3H 4 PP3V3_G3H
2 CHGR_EN_MVR
MOSFET
J3300(USB-C)
PP20V_USBC_XA_VBUS ACE 1 PPBUS_G3H PPVIN_G3H_P3V3G3HRTC EN 3
U3100 MOSFET U6960 PP3V3_G3H_RTC
VIN_RTC VOUT_RTC

PP20V_USBC_XB_VBUS PBUS Supply & VPWR_EN


Battery 19 PPVDDCPU_AWAKE
BUCK0 XO0
Charger 13 PPVDDCPUSRAM_AWAKE
BUCK1
U7000 EN 11 PP0V82_SLPDDR XI0 SOC_XTAL24M_IM
MOSFET PPVIN_G3H_P3V3G3H
EN1 EN2
BUCK2 17
5 PP1V8_SLPS2R
U7650 PP3V3_G3H_PMU
U7800_BUCKs BUCK3
ACE SW1 SW2 PP3V3_G3H _VDDMAIN VDD_MAIN
9 PP1V1_SLPS2R vcc 16
BUCK4 U7901
U3200 MOSFET2
24
ON PP1V1_SLPDDR
PPVIN_G3H_P5VG3S
BUCK5 14 PP0V9_SLPDDR
Q7065 MOSFET1
BUCK6
J6950(VBAT) PPVCC_PRIM_CORE
BUCK7
PP1V05_PRIM
BUCK8
PMU_VDD_HI 39 37
PP0V9_SSD SOC SSD_PMU_RESET_L
BUCK9
38 PP1V8_SSD
FAB#SC1105 BUCK10 U3900
25
35 30

10 PP0V8_SLPS2R

P3V3MAIN_PGOOD
LDO0_IN LDO0

P5VG3S_PGOOD
26

PP5V_G3S
PP3V_G3H
LDO1_IN LDO1
18
CPU
PP1V2_AWAKE
LDO2_IN LDO2
U7800_LDOs LDO3

LDO_CORE

8 PP1V8_SLPS2R_PMUVDDGPIO
12

V3P3_SW1 PP3V3_AWAKE
V3P3
V3P3_SW2 PP3V3_S5
7
PP1V8_AWAKE
BUCK3_SW1 ROM 38
BUCK3_SW2
PP1V8_SSD
BUCK3_IN BUCK0
PP1V8_S5 39
BUCK3_SW3 BUCK1
PP0V9_SSD
PP1V8_S3
U7800_Switch BUCK3_SW4 PP1V8_S0_CPU_OPVR
BUCK3_SW5
40 41
SSD0_OCARINA_WP_L SSD0_WP_L
VEN1 WP*
BUCK4_IN BUCK4_SW1 SSD0_VR_P2V7_EN
BUCK6_IN BUCK6_SW1

TP_PMU_BUCK8_SW 42
BUCK8_SW1 SSD0_OCARINA_PFN
BUCK8_IN PFN*
BUCK8_SW2
PP1V05_S0
43
SSD0_OCARINA_LPB_L SSD0_LPB_L
LPBN

OCARINA PMIC & NAND VCC VR 44


6
PMU_CLK32K_SOC_R SSD0_OCARINA_RESET_L SSD0_RESET_L
CLKOUT0_32K
27
U9000 RESET*
PMU_CLK32K_PCH_R
CLKOUT1_32K
36
CPU
CLKOUT2_32K PMU_CLK32K_WLANBT_R U3700(WIFI/BT) U8600/U8700/U8800
SSD
CLKOUT3_32K

CLKOUT4_32K

U7800_CLK&Control 20
RESET* PMU_COLD_RESET_L
21
SYS_ALIVE
PMU_SYS_ALIVE
22
ACTIVE_RDY PMU_ACTIVE_READY
28
PCH_RTC_RESET_L
LDO1_POK
CPU

GPIO1 VDD_GPIO GPIO14

GPIO15
GPIO2

GPIO3 GPIO16
VCC 29
P5VG3S_EN
U7610 GPIO4 GPIO17

GPIO18
GPIO5
GPIO19 42
VCC GPIO6
41
P2V7NAND_PGOOD
34 P1V8_G3S
U8220ON GPIO7 U7800_GPIO GPIO20
P2V7NAND_EN
EN
U9060
33 P1V8G3S_EN P2V7_NAND
GPIO8 GPIO21
VCC GPIO22
GPIO9

32 P3V3_G3S
U8210ON 31 P3V3G3S_EN GPIO23
40
GPIO10
NAND_Discharge_EN
GPIO11 GPIO24

GPIO25
GPIO12 P1V1_SLPDDR_SOCFET_EN
15
45 NAND_RESET_L
GPIO13

43 NAND_WP_L

PPBUS_G3H_SSD0

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