DEPARTMENT

OF
ELECTRONICS AND COMMUNICATION
ENGINNEERING

LABORATORY MANUAL

Analog Electronic Circuits

LABORATORY
P18ECL38
III Semester, BE (ECE)

P.E.S.COLLEGE OF ENGINEERING
Mandya– 571401, Karnataka
(An Autonomous Institution under VTU, Belgaum)
2018-2019
 Course Curriculum (Syllabus)

1. MOSFET drain and transfer characteristics

2. RC coupled single stage MOSFET amplifier and determination of the gain- frequency
response curve, input and output impedances.
3. Op-amp RC phase shift oscillator.
4. Hartley and Colpitts oscillator using MOSFET.
5. Determining the Characteristic parameters of Op-Amp 741 IC, design of Inverting
and Non-inverting amplifier using 741 IC
6. Op-amp as summer, subtractor and voltage follower
7. Op-amp as Integrator and Differentiator circuit
8. Precision half wave and full wave rectifier using 741 IC.
9. Design of Schmitt trigger and zero crossing detection using 741 IC
10. R-2R DAC using Op-amp.
11. Voltage regulator using LM 217 IC regulator
12. Clipping and clamping using 741 IC
 Contents

Exp no. Title of the experiment Page no.

1 MOSFET 1
2 RC-coupled single stage MOSFET amplifier 7

3 Op-amp RC phase shift oscillator 12

4 Hartley and Colpitts oscillator using MOSFET 15
5 Characteristics parameters of an OP- AMP 19

Design of Inverting and non inverting Op-Amp amplifier 26

6 OP AMP adder, Subtractor and voltage follower using IC 30
741

7 OP–AMP as Integrator and Differentiator circuit 35

8 Half wave and full wave precision rectifier using OPAMP 40

9 Schmitt trigger circuit and Zero crossing detector 44

10 R-2R ladder DAC using Op-amp IC 741 49

11 Voltage regulator using LM317 53

12 Clipping and clamping using 741 IC 57

13 APPENDIX A 63
14 APPENDIX B 65
 Analog Electronic Circuits Laboratory

EXPERIMENT NO.1

MOSFET.
a. Aim: To draw drain and transfer characteristics of MOSFET
b. Components required: n-channel MOSFET -IRF740 (Module)
DC Voltmeter (0-30V)
DC Ammeter (0-200mA)
DC Power supply (0-30V)

c. Theory:
The metal–oxide–semiconductor field-effect transistor (MOSFET) is a transistor used for
amplifying or switching electronic signals. Figure 1.6 shows the physical structure of the n - channel
enhancement - type MOSFET. The transistor is fabricated on a p -type substrate. Two heavily doped
n-type regions: the n+ source and the n+ drain regions are created in the substrate. A thin layer of
silicon dioxide (SiO2) of thickness tox (typically 2 - 50 nm) – an excellent electrical insulator, is
grown on the surface of the substrate, in the area between the source and drain regions. Metal is
deposited on top of the oxide layer to form the gate electrode. Metal contacts are also made to the
source region, the drain region, and the substrate, also known as the body. Thus four terminals are
brought out: the gate terminal (G), the source terminal (S), the drain terminal (D), and the substrate or
body terminal (B). A voltage applied to the gate of the MOSFET controls current flow between
source and drain. This current will flow in the longitudinal direction from drain to source in the
region labeled “channel region.” This region has a length L in the range of 0.1μm to 3μ, and a width
W in the range of 0.2μm to 100μm. The MOSFET is a symmetrical device ( ie its source and drain
can be interchanged with no change in device characteristics).

With no bias voltage applied to the gate, two back-to-back diodes exist in series between drain
and source. They prevent current conduction from drain to source when a voltage VDS is applied. The
path between drain and source has a very high resistance (of the order of 10 12Ω).

When the source and the drain are grounded and a positive voltage is applied to the gate, the
positive voltage on the gate causes the free holes (which are positive charged) to be repelled from the

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region of the substrate under the gate. These holes are pushed downward into the substrate, leaving
behind a carrier -depletion region. The positive gate voltage attracts electrons from the n+ source and
drain regions into the channel region. When a sufficient number of electrons accumulate near the
surface of the substrate under the gate, an n region is in effect created, connecting the source and
drain regions, as indicated in Fig. 1.6. This MOSFET is called an n-channel MOSFET or,
alternatively, an NMOS transistor. The induced channel is also called an inversion layer. The induced
n region thus forms a channel for current flow from drain to source. The value of VGS at which a
sufficient number of mobile electrons accumulate in the channel region to form a conducting channel
is called the threshold voltage and is denoted Vt. The value of Vt is controlled during device
fabrication and typically lies in the range of 0.5 V to 1.0V. Now if a voltage is applied between drain
and source, current flows through this induced n region. The gate and the channel region of the
MOSFET form a parallel-plate capacitor, with the oxide layer acting as the capacitor dielectric. An
electric field thus develops in the vertical direction. It is this field that controls the amount of charge
in the channel, and thus it determines the channel conductivity and, in turn, the current that will flow
through the channel when a voltage VDS is applied.

(a) : Equal drain and source voltages

(b): Unequal drain and source voltages

Fig 1.1: Structure of NMOS device

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N-channel MOSFETS start conducting only when Vgs>Vth i.e gate to source voltage must be
greater than threshold voltage (0.5 to 1V). Metal oxide semiconductor field effect transistor is a
voltage-controlled device. The terminals of MOSFET are gate, drain and source.

Drain Characteristics/output characteristic:

MOSFET output characteristics plot ID versus VDS for several values of VGS. The characteristics of an
nMOS transistor can be explained as follows. Let VGS be held constant at a value greater than Vt
(0.5V to 1V) and VDS appears as a voltage drop across the length of the channel. That is as we travel
along the channel from source to drain, the voltage (measured relative to the source)increases from 0
to VDS. Thus the voltage between the gate and points along the channel decreases from (VGS – 0)V at
the source end to (VGS – VDS) at the drain end. Since the channel depth depends on this voltage we
find that the channel is no longer of uniform depth; rather, the channel will take the tapered form
shown in fig 1.6(b), being deepest at the source end and shallowest at the drain end. As VDS is
increased, the channel becomes more tapered and its resistance increases correspondingly. When V DS
is increased to the value that reduces the voltage between gate and channel at the drain end to Vt( ie
VGS – VDS=Vt or VDS = VGS – Vt ) the channel depth at the drain end decreases to almost zero, and the
channel is said to be pinched off. Increasing VDS beyond this value (ie VDS > VGS -Vt ) has little effect
on the channel shape and the current through the channel remains constant. The drain current
saturates and the MOSFET is said to have entered the saturation region of operation. The voltage VDS
at which saturation occurs is denoted VDSSat (ie VDSSat = VGS – Vt). Thus VDS ≥ VDSSat the device
operates in the saturation region. For VDS ≤ VDSSat, the region is called triode region. This is shown in
fig 1.5(a). Finally find the values of forward resistance (rd) using the below equations
rd == ∆ VDS/∆ ID ῼ

Transconductance Characteristics
It is graph of ID versus VGS for a constant VDS. Initially drain current is very small (in terms of
micro amperes) as long as VGS < Vt. Once VGS is greater tha Vt drain current increases rapidly as
shown in fig 1.5 (b) . Finally find the values of transconductance (gm) using the below equations
gm= ∆ ID/∆VGS ℧

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d. Procedure
Drain Characteristics
1. Rig up the circuit as per in Fig1.2
2. Adjust the value of VGS slightly more than threshold voltage Vt
3. By varying V1, note down ID & VDS and are tabulated in the tabular column
4. Repeat the experiment for different values of VGS and note down ID v/s VDS
5. Draw the graph of ID v/s VDS for different values of VGS and find output resistance value

Transconductance Characteristics
1. Rig up the circuit as per in Fig1.2
2. Set VDS = say 0.6 V using V1
3. Slowly vary V2 (VGS) with a step of 0.5 volts, note down corresponding ID and VGS readings and
are tabulated in the tabular column
4. Repeat the experiment for different values of VDS & draw the graph of ID v/s VGS
5. Plot the graph of ID v/s VGS and find Transconductance value

Circuit diagram

Fig 1.2: Circuit diagram of MOSFET Characteristic

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Graph

Fig 1.3: MOSFET Drain and Tran conductance Characteristics

Table 1.1: Drain Characteristics

VGS=...............V
SL.NO ID(mA) VDS(V)
1
2
3
4
5
6
7
8

Table 1.2: Tran conductance Characteristics

VDS=..............V
SL.NO ID(mA) VGS(V)
1
2
3
4
5
6
7
8
9
10

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e. Result:
1. The drain and transfer cha4racteristics of JFET is studied and are plotted.
2. The drain characteristics and trans-conductance characteristics of n-channel Enhancement
MOSFET are obtained. Output resistance and Tran conductance value are find out.
f. Short questions:
1. What is JFET?
2. What are the applications of FET?
3. What are the difference between BJT and FET?
4. What is MOSFET?
5. What are the types of MOSFET?
6. What are the applications of MOSFET?
7. Compare FET and MOSFET.
8. Compare BJT and MOSFET.
9. What is the transfer characteristic of FET?
10. What is the Drain characteristic of MOSFET?
11. What is trans-conductance of MOSFET?

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EXPERIMENT NO.2

RC-coupled single stage MOSFET amplifier

a. Aim: To study the operation of common source n-Channel Enhancement Type MOSFET amplifier
to measure the gain, input and output impedance.

b. Components required: n-channel MOSFET (2N700)

Resistors-1MΩ,150KΩ,2.5KΩ,DRB
Capacitors-1µF
DC Power Supply (0-30V)
Signal Generator
CRO

c. Theory: Amplification is a process of increasing the signal strength by increasing the amplitude
of a given signal without changing its characteristics. An RC coupled amplifier is a part of a
multistage amplifier wherein different stages of amplifiers are connected using a combination of
resistor and a capacitor. An amplifier circuit is one of basic circuits in electronics. An amplifier which
is completely based on transistor is basically known as transistor amplifier. The input signal may be a
current signal, voltage signal or a power signal. An amplifier will amplify the signal without changing
its characteristics and the output will be a modified version of the input signal. Applications of
amplifiers are of wide range. They are mainly used in audio and video instruments, communications,
controllers, etc. The range of frequency that an amplifier circuit can amplify properly is known as the
bandwidth of that particular amplifier. The curve below represents the frequency response of the
single stage RC coupled amplifier.

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Fig 2.1 Frequency response of the single stage RC coupled amplifier.

The curve which represents the variation of gain of an amplifier with frequency is called
frequency response curve. The bandwidth is measured between the lower half power and upper half
power points. P1 point is lower half power and P2 is upper half power respectively. A good audio
amplifier must have bandwidth from 20 Hz to 20 kHz because that is the frequency range which is
audible. A good transistor amplifier must have the following parameters; high input impedance, high
band width, high gain, high slew rate, high linearity, high efficiency, high stability etc. Input
impedance is the impedance seen by the input voltage source when it is connected to the input of the
transistor amplifier. In order to prevent the transistor amplifier circuit from loading the input voltage
source, the transistor amplifier circuit must have high input impedance. The range of frequency that
an amplifier can amplify properly is called the bandwidth of that particular amplifier. Usually the
bandwidth is measured based on the half power points i.e. the points where the output power becomes
half the peak output power in the frequency Vs output graph. Gain of an amplifier is defined as the
ratio of output power to the input power. Gain can be expressed either in decibel (dB) or in numbers.
Gain represents how much an amplifier is able to amplify a signal given to it. Efficiency of an
amplifier represents how efficiently the amplifier utilizes the power supply. In simple words it is a
measure of how much power from the power supply is usefully converted to the output. Stability is
the capacity of an amplifier to resist oscillations. These oscillations may be high amplitude ones
masking the useful signal or very low amplitude. Usually stability problems occur during high
frequency operations, close to 20KHz in case of audio amplifiers. Slew rate of an amplifier is the
maximum rate of change of output per unit time. It represents how quickly the output of an amplifier

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can change in response to the input. In simple words, it represents the speed of an amplifier. Slew rate
is usually represented in V/μS and the equation is SR = dVo/dt. An amplifier is said to be linear if
there is a linear relationship between the input power and the output power. It represents the flatness
of the gain. 100% linearity is not possible practically as the amplifiers using active devices like BJTs,
JFETs or MOSFETs tend to lose gain at high frequencies due to internal parasitic capacitance. In
addition to this the input DC decoupling capacitors (seen in almost all practical audio amplifier
circuits) sets a lower cutoff frequency.
MOSFET is a three-terminal device. Three basic single-transistor amplifier configurations can
be formed, depending on which of the three transistor terminals is used as signal ground. These three
basic configurations are appropriately called common source, common drain (source follower), and
common gate. These three circuit configurations correspond to the common-emitter, emitter-follower,
and common-base configurations using BJTs. For n-channel MOSFET acts a common source
amplifier it must be biased to saturation region.

d. Procedure:
1. Connect the circuit as shown in Fig 2.2.
2. Set the signal generator output to sine wave with peak value of 500mVp-p and frequency of 1KHz.
3. Feed both the input and output signals to an oscilloscope.
4. Vary the frequency of input signal from 100Hz to 1MHz in a step of 50Hz or 100Hz, then note
down the corresponding amplitude of the output signal on CRO and find out the gain.
5. Then plot frequency V/S gain to obtain a frequency response for the common source amplifier.
6. To measure the input impedance, set the input voltage to 1Vp-p at 1 kHz and then connect the
DRB( Decade Resistance Box) in series with amplifier circuit, then increase DRB value until the
input voltage across the amplifier circuit is reduced to half. This is the input impedance.
7. To measure the output impedance, connect a DRB at the output of amplifier circuit and increase
its value until the output voltage becomes half.

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Circuit Diagram:

Fig 2.2: Circuit Diagram of RC coupled single stage n-Channel MOSFET amplifier

Circuit Component values:

RG1 =12/15KΩ
RG2 =5.7k(Variable)
RS =160Ω
RD =2.2KΩ
Ci = Co = 10 µF
Cs =47µF

Note: For Biasing VDS = VDD/2 = 5V

Table 2.1: Tabular column to find Gain
Vin = 500mV
SL. NO Frequency Output Voltage in Volts Gain = Vout/Vin Gain in dB
in Hz = 20log(Gain)

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e. Result: The frequency response of common source amplifier is plotted and the measured input
and output impedances are___________ and______________ respectively. The mid band Gain
is_________

f. Short questions:
1. Define an Amplifier?
2. What is an RC coupled amplifier?
3. What is the function of coupling capacitor?
4. What is the function of Bypass Capacitor?
5. Define Gain of an Amplifier?
6. What are the applications of RC coupled Amplifiers?
7. What is a common source Amplifier?
8. What is a Voltage Divider Biasing?
9. What is Q point?
10. What is the Biasing?

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 Analog Electronic Circuits Laboratory

EXPERIMENT NO.3

Op-Amp RC phase shift oscillator

a. Aim: Test the RC phase shift oscillator for the frequency of 1KHZ

b. Components required: Op-amp 741IC

Resistors-1.2KΩ, 1KΩx2, DRB (50KΩ)
Capacitors- 0.01µFX3
DC Power Supply (0-30V)
CRO
c. Theory:
Oscillators are circuits that produce periodic waveforms without any external input signal. In
oscillators, the only input requirement is of DC power supply which is required for operation of the
active device. The frequency of the generated waveforms may vary from a few Hz to several KHz. It
may be used to generate AC waveforms such as sinusoidal, rectangular or sawtooth depending upon
the type of oscillators used. They have wide range of applications such as in radios, Televisions,
communication systems, computers, industrial controlled applications, and laboratories, as a function
or signal generator.

Fig 3.1: Principle of operation

An oscillator consists of an amplifier and a feedback network as shown in above fig 3.1. Now, let
us see which basic components are required to obtain oscillations.
(1) Active device either Transistor or Op Amp is used as an amplifier.
(2) Feedback circuit with passive components such as R-C or L-C combinations.
To start the oscillation with the constant amplitude, positive feedback is not the only sufficient
condition. Oscillator circuit must satisfy the following two conditions known
as Barkhausen conditions:

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1. The first condition is that the magnitude of the loop gain (Aβ) must be unity. This means the
product of gain of amplifier 'A' and the gain of feedback network 'β' has to be unity.
2. The second condition is that the phase shift around the loop must be 360° or 0°. This means, the
phase shift through the amplifier and feedback network has to be 360° or 0°.
The RC phase shift oscillator utilizes three RC circuits each provide 60o phase shift to provide
a total 180º phase shift that when coupled with the 180º phase shift of the amplifier itself provides the
necessary feedback to sustain oscillations.
RC Phase-Shift Oscillator is a popular configuration for the generation of low-frequency sine
waves, starting at a few Hertz and up to about 100 kHz.
d. Procedure:
1. Rig up the circuit s shown in the figure 3.2.
2. Observe the sinusoidal output voltage.
3. Measure the frequency & compare with theoretical values.
Circuit Diagram

Fig 3.2 Circuit Diagram of Op-amp RC phase shift oscillator

Circuit Component values:

Ri= 1.2KΩ,
R=1KΩ
Rf=35Ω
C=0.01µFx3

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RC feedback network desig

Frequency of oscillation (F):

Gain of the Op Amp inverting amplifier (G):

Attenuation offered by the feedback RC network is 1/29, so the gain of inverting amplifier should be
29
Use Ri=1.2 KΩ
So, Rf=35KΩ
Use 50KΩ potentiometer and adjust its value to obtain output on CRO
e. Result:
Theoretical = 6.5 KHz
Practical = ______
f. Short questions
1. Define an Oscillator?
2. How oscillators are classified? Give one example for each classification.
3. What is Barkhausen‟s criterion?
4. What is the phase shift provided by RC networks in each RC Phase Shift Oscillator?
5. What is the minimum gain required at frequency of oscillations in RC Phase Shift
Oscillator?
6. What is the formula for frequency of oscillations in RC Phase Shift Oscillator?

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EXPERIMENT NO.4

Hartley and Colpitts oscillator using MOSFET

a. Aim: (i) To verify Hartley oscillator using MOSFET.

(ii) To verify Colpitts oscillator using MOSFET.

4(a). Hartley oscillator using MOSFET

b. Components required: n-channel MOSFET (2N700)

Resistors-1MΩ, 150KΩ, 2.5KΩ, DRB
Capacitors-1µF, DCB
DC Power Supply (0-30V)
CRO.
c. Theory:
The Hartley oscillator is a type of LC oscillator in which the oscillation frequency is
determined by a tuned circuit consisting of capacitors and inductors. The circuit was invented in 1915
by American engineer Ralph Hartley. The distinguishing feature of the Hartley oscillator is that the
tuned circuit consists of a single capacitor in parallel with two inductors in series (or a single tapped
inductor). The Hartley Oscillator is a particularly useful circuit for producing good quality sine wave
signals in the RF range, (30 kHz to 30MHz).

d. Procedure:
1. Rig up the circuit s shown in the figure 4.1.
2. Observe the sinusoidal output voltage.
3. Measure the frequency & compare with theoretical values.

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Circuit Diagram:

Fig 4.1: Circuit Diagram of Hartley oscillator using MOSFET

Circuit Component values:

RG1 =12/15KΩ
RG2 = 3kΩ (Variable)
RS =160Ω
RD =2.2KΩ
Ci = Co = 10 µF
Cs =47µF
Tank Circuit Design Equations

Design for 5 KHz

Let C=0.084µf
L1=10mH
L2=2mH
L=12mH
fo= 5.012 KHz

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4(b). Colpitts oscillator using MOSFET

e. Components required: n-channel MOSFET (2N700)

Resistors-1MΩ, 150KΩ, 2.5KΩ, DRB
Capacitors-1µF, DCB
DC Power Supply (0-30V)
CRO.

f. Theory: A Colpitts oscillator is also a type of LC oscillator in which the oscillation frequency is
determined by a tuned circuit consisting of capacitors and inductors. The circuit was invented in
1918 by American engineer Edwin H. Colpitts. The distinguishing feature of the colplitts oscillator is
that the tuned circuit consists of two capacitors in series across the inductor. The colplitts oscillator is
a particularly useful circuit for the generation of high frequency sinusoidal oscillations with the radio
frequencies typically ranging from 10 KHz to 300MHz.
g. Procedure:
4. Rig up the circuit as shown in the figure 4.2.
5. Observe the sinusoidal output voltage.
6. Measure the frequency and compare with theoretical values.

Circuit diagram:

Fig 4.2: Circuit diagram of Colpitts oscillator using MOSFET

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Circuit Component values:

RG1 =12/15KΩ
RG2 =3kΩ (Variable)
RS =160Ω
RD =2.2KΩ
Ci = Co = 10 µF
Cs =47µF

Tank Circuit Design equations:

Design for 5KHZ

Let L=10mH
C1=0.1µf
C2=0.6µf
C=0.08571µF

h. Result: (i) The Hartley oscillator waveforms have been verified for given oscillation frequency.
(ii) The Colpitts oscillator waveforms have been verified for given oscillation frequency.
i. Short questions:
1. What is an Hartley Oscillator?
2. What is Tank circuit?
3. What is the expression for frequency of oscillation in Hartley oscillator?
4. What is Colpitts oscillator?
5. What is the expression for Frequency of oscillation in Colpitts oscillator?
6. What are the applications of Hartley Oscillator?
7. What are the applications of Colpitts Oscillator?
8. Differentiate between Hartley and Colpitts oscillator.

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EXPERIMENT NO.5

Characteristics parameters of an OP- AMP

a. Aim: To conduct an experiment to determine the characteristics parameter of an op- amp.

a. To measure the input offset voltage of a 741 op-amp
b. To measure the slew rate of an op-amp
c. To measure the Common Mode Rejection Ratio (CMRR) of an op-amp
d. To measure the gain bandwidth product of an op-amp

b. Components Required: op-amp 741 IC

Resistors (47 Ω, 4.7 KΩ, 1KΩ, 10KΩ, 100KΩ, 2.2KΩ, and 22KΩ),
Breadboard
DC power supply (±12V)
DC Voltmeter
Signal generator
CRO
c. Theory: Op-amp is an amplifier with high gain, high input impedance and low output impedance.
Op-amp is a direct coupled differential amplifier. In this experiment basic characteristics of an op
amp are studied.
For the output voltage to be exactly equal to the input, transistors Q1 and Q2 need to be
perfectly matched. This requires the base-emitter voltage of the two transistors be exactly equal
(VBE1=VBE2). When this is not the case the voltage difference act as a DC input voltage which is
referred as input offset voltage.
The slew rate of an OP-AMP is the Maximum rate at which the output voltage can change.
When the SR is too slow for the input, distortion results. The success of the op-amp in rejecting
common mode input is defined in the CMRR. The gain-bandwidth product for an amplifier is the
product of the amplifier‟s bandwidth and the gain at which the bandwidth is measured.

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Fig 5.1. Internal circuit, Symbol and Pin diagram of 741 Op-Amp

5(a). To measure the input offset voltage of an 741 op-amp

d. Procedure:
1. Connect the circuit as shown in the Fig 5.2
2. Use DC voltmeter to measure the amplifier output (pin 6).
Vo=…………
3. Use the formula to calculate input offset voltage
Vio=Vo/ (1+Rf/Ri)
Vio =input offset voltage
Vo=amplifier output

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Fig 5.2 Circuit diagram to measure the input offset voltage

NOTE:- The Maximum input offset voltage is listed as 5mV on the 741 Datasheet
5(b). To measure the slew rate of an op-amp
e.Procedure
1. Connect the circuit as shown in the Fig 5.3
2. Set the signal generator to 10KHz, adjust the input signal level(voltage) to Saturate the op-amp,
use the oscilloscope and observe the output of op-amp(pin 6),
3. Adjust the oscilloscope timing to get a couple of cycle as shown in the wave form (Fig 5.3).
4. Measure the voltage change „∆V‟ and time change „∆T‟ of the waveform.
5. Calculate the slew rate using the formula
Slew rate=∆V/∆T v/µsec

Fig 5.3: Circuit diagram of Op-Amp to measure Slew rate

Circuit component value: R1=1KΩ, R2=10KΩ

NOTE:- The typical SR of the 741 IC is specified as 0.5 V/ µsec.

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5(c). To measure the CMRR( Common Mode Rejection Ratio) of an op-Amp

The CMRR is a measure of the amplifiers ability to reject a common mode input signal. Or the
success of the op-amp in rejecting common mode input is defined in the CMRR, the formula used to
calculate the CMRR is
` CMRR=20log (AD / ACM) db

Where AD=Differential Input Gain and ACM=Common Mode Gain

f. Procedure:
1. Connect the circuit as shown in the figure 5.4
2. Apply DC power to the circuit, set the function generator to provide an input sine wave of
1KHz.
3. Measure and record the peak to peak amplitude of the signal input and op-Amp output.
Vin(p-p)=……….
Vout(p-p)=……….
4. Calculate differential gain using
Gain(AD)=Vout/Vin
5. Turn off dc power supply, modify the circuit as shown in the figure 5.5
6. Re apply dc power, set the function generator to provide an input sine wave of 1 KHz.
7. Measure and record the peak to peak amplitude of the signal input and op-Amp output.
Vin(p-p)=……….
Vout(p-p)=……….
8. Calculate differential gain using
Gain(ACM)=Vout/Vin
9. Now calculate the CMRR using the given formula.
CMRR=20log (AD / ACM) db

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Fig 5.4: Circuit diagram to measure the Differential Gain

Fig 5.5: Circuit diagram to measure Common mode Gain

NOTE: - The typical value of CMRR is 90dB as per 741 Datasheet.

5(d). To measure the gain bandwidth product of an op-amp

g. Procedure:
1. Connect the circuit as shown in above figure 5.6
2. Apply DC power supply (±12V), set the function generator to provide an input sine wave of 1
KHz.
3. Connect oscilloscope to measure Vout of op-Amp. Measure and record the amplifier peak-peak
output voltage and calculate the gain of an amplifier.
Vout(1Khz) =………………
Gain at 1KHz =Vout/Vin=……………..
4. Increase the signal generator frequency while monitoring amplifier output. Measure and
record the frequency, where the output is 0.707 of the 1KHz output amplitude. This is the
upper cutoff frequency and should occur at approximately 1MHz

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5. Compute the op-amp gain bandwidth product using below equation.

Gain band width= 1 KHz gain * upper cutoff frequency=_______________.
6. Turn off the dc power supply and modify the circuit as shown in the figure 5.7
7. Reapply DC power supply and repeat the measure of step3 to 4. Record the 1KHz output, the
circuit gain and upper cutoff frequency
Vout(1Khz= __________________

Gain at 1KHz =Vout/Vin=________________

Upper cutoff frequency = __________________

8. Compute the gain band width product again. This value is close with the value find in step5
Gain band width=1 KHz gain * upper cutoff frequency=.........................

Fig 5.6: Voltage follower Fig 5.7: Non-Inverting Amplifier

h. Result: The characteristics parameter of an op- amp has been checked and verified as per the
required specification for 741 IC.

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i. Short questions
1. Draw the pin diagram of op-amp.
2. What is the supply voltage range that an op-amp can with stand?
3. What is the input voltage range that an op-amp can with stand?
4. What are the available package types of IC 741?
5. What is a virtual ground? What are the differences between the physical ground and
the virtual ground?
6. What is the current flowing through the input terminals of an Ideal op-amp?
7. Which gain is larger, closed or open loop?
8. What is the normal value of saturation voltage of an op-amp?
9. Mention some characteristics of op-amp.
10. Define CMRR, input offset voltage, Slew rate and gain-bandwidth product?

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EXPERIMENT NO.6

Inverting and non inverting Op-Amp amplifier

a. Aim: To determine the inverting and non inverting Op- Amp amplifier for different gains using IC
741.
b. Components required: op-amp 741 IC
Resistors (1KΩ, 10KΩ, 33KΩ),
Breadboard
DC power supply (±12V)
DC Voltmeter(0-30)V
Signal generator
CRO
c. Theory: Operational Amplifiers, or Op-amps as they are more commonly called, are one of the
basic building blocks of Analogue Electronic Circuits. Operational amplifiers are linear devices that
have all the properties required for nearly ideal DC amplification and are therefore used extensively
in signal conditioning, filtering or to perform mathematical operations such as add, subtract,
integration and differentiation. An Operational Amplifier is basically a three-terminal device which
consists of two high impedance inputs, one called the Inverting Input, marked with a negative or
“minus” sign, ( - ) and the other one called the Non-inverting Input, marked with a positive or “plus”
sign ( + ). The third terminal represents the Operational Amplifiers output port. In a linear
operational amplifier, the output signal is the amplification factor, known as the amplifiers gain (A)
multiplied by the value of the input signal. An operational amplifier (Op-Amp) is a direct-coupled,
differential-input, high gain voltage amplifier, usually packaged in the form of a small integrated
circuit. Today's op amps are used in a much wider variety of circuits and operate at considerably
lower voltages and powers.
Output of the inverting amplifier is the inverted version/out-of-phase (180o) of input signal.
The inverted version of the output is amplified by a factor of AV (gain). In an non-inverting amplifier
output signal is in-phase with the input signal. Here also the output is amplified by a factor of AV
(gain).

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6(a). Inverting Amplifier:

d. Procedure:
1. Make the connections as shown in fig 6.1
2. Apply +12V and -12V voltage to the op amp as shown in the circuit.
3. Now set the signal generator (i/p voltage) amplitude 1V peak to peak sine wave at 1KHz
frequency.
4. Observe the input and output signal simultaneously on the CRO.
5. The output voltage Vo should be 10(gain may be varied) times amplified as compared to Vin
for the given design and output waveform should be out of phase with respect to input wave
form.
6. Now calculate the theoretical and practical gain using the formula as shown below.

Circuit component values:

Av=Vo/Vin= -Rf/Rin
Select Rin=1KΩ,
Rf=10KΩ
Then Av=10

Fig 6.1: Circuit diagram of inverting amplifier circuit and waveforms

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Table 6.1: Comparisons of Theoretical and Practical Gain

Input voltage Output voltage Gain= -Rf/Rin Gain= -Vo/Vin

Vin (V) Vout(V) (Theoretical) (Practical)

6(b). Non-Inverting Amplifier:

e. Procedure:
1. Make the connections as shown in fig 6.2
2. Apply +12V and -12V voltage to the op amp as shown in the circuit.
3. Now set the signal generator (i/p voltage) amplitude 1V peak to peak sine wave at 1KHz
frequency.
4. Observe the input and output signal simultaneously in the CRO.
5. The output voltage Vo should be 4.3(gain may be varied) times amplified as compared to Vin
and output waveform should be in phase with respect to input wave form.
6. Now calculate the theoretical and practical gain using the formula as shown below.

Circuit component values:

Av= Vo/Vin= 1+Rf/Rin
Select Rin=10KΩ,
Rf=33KΩ
Then Av= 4.3

Fig 6.2 circuit diagram of non inverting amplifier and waveforms

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Table 6.2: Comparisons of Theoretical and Practical Gain

Input voltage Output voltage Gain= 1+Rf/Rin Gain=Vo/Vin

Vin(V) Vout(V) (Theoretical) (Practical)

f. Result: The inverting and non inverting amplifier of a 741 IC has been checked and the practical
and theoretical values are compared.

g. Short Questions

1. What is an Inverting amplifier?

2. What is the expression for Gain in an inverting amplifier?
3. What is a Non-Inverting amplifier?
4. What is the expression for Gain in a Non-Inverting amplifier?
5. Compare the Inverting and Non-Inverting amplifier
6. Design an inverting and non-inverting amplifier for a gain of 24 & 6.

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EXPERIMENT NO.7

OP AMP adder, Subtractor and voltage follower using IC 741

a. Aim: To demonstrate op-amp adder, Subtractor and voltage follower using IC 741 op-amp

b. Components required: Op-amp IC 741

Resistors-1KΩ, 2KΩ
Breadboard
DC Voltmeter (0-30) V
DC supply (±12V)
Connecting wires.

C. Theory: Operational amplifiers are used to perform arithmetic operations like addition,
subtraction, and averaging. Op-amps are used in many practical applications where these
computations are necessary. Op-amps has one inverting and one non inverting terminal, inputs are
applied at these terminals depending on the operation to be performed.
Adder is a circuit which adds the applied input voltages to inverting (acts as inverting adder)
or non-inverting (acts as non-inverting adder) input terminal. The same circuits can be modified to
work as an averaging circuit.
Subtractor is a circuit which subtracts the inputs applied to the non-inverting and inverting
input terminals. Feedback resistor is provided to set proper gain by proper selection of resistor.The
voltage follower is the circuit in which o/p voltage follows i/p, it has unity gain.
7(a). Adder:
d. Procedure for inverting adder:
1. Make the connections as shown in figure 7.1
2. Apply +12V and -12V at pin nos 7 and 4 respectively.
3. Apply DC input voltages at V1 and V2 respectively.
4. Note down output voltage at pin no 6 and verify with theoretical value.
5. To perform Averaging, Design the Rf as shown in the design equation below.

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Fig 7.1: Circuit diagram of inverting summer

For Summer Vo= -(Rf/R1)(V1+V2) [By assuming R1=R2 ]

If Rf = R1=R2 = 1KΩ
Then Vo= -(V1+V2)
For Average
Vo= -(Rf/R1)(V1+V2)
If R1=R2 = 1KΩ=R
Rf=R/2=0.5KΩ
Then Vo= -(V1+V2)/2

e. Procedure for Non-inverting adder:

1. Make the connections as shown in figure 7.2
2. Apply +12V and -12V at pin nos 7 and 4 respectively.
3. Apply DC input voltages at V1 and V2 respectively.
4. Note down output voltage at pin no 6 and verify with theoretical value
5. To perform Averaging, Design the Rf as shown in the design equation below.

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Fig 7.2: Circuit diagram of Non-Inverting summer

For summer Vo= (1+Rf/R3)(V1+V2)/2 [ By assuming R1=R2]

If Rf=R3, Gain=1+Rf/R3=2
Then Vo= (V1+V2)
Take Rf=R1=R2=R3=1KΩ
For average
If Rf = 0(Pin numbers 6 and 2 are shorted), then Gain=1
Then VO = (V1+V2)/2

7(b). Subtractor:
f. Procedure:
1. Make the connections as shown in the figure 7.3.
2. Apply +12V and -12V at pin 7 and 4 respectively.
3. Apply DC input voltages at V1 and V2 respectively.
4. Note down output voltage at pin no 6 and verify with theoretical value

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Fig 7.3: Circuit diagram of Difference Amplifier

Vout=Rf/R1(V2-V1) [ By assuming R2=R1 and R3=Rf]

If Rf = R1 then Vout= (V2-V1)
So take R1=R2=R3=Rf=1KΩ
7(c). Voltage follower:

Fig 7.4: Circuit diagram and Waveform of Voltage Follower

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g. Procedure:
1. Make the connections as shown in the figure 7.4.
2. Observe the input and output waveforms on CRO.

h .Result: The adder, subtractor and voltage follower circuits are constructed and verified using IC
741 Op-amp.

i. Short questions

1. What is an summing amplifier?

2. Write the output expression for 3 input Inverting adder.
3. Write the output expression for 3 input Non- Inverting adder.
4. What is a Subtractor?
5. Write the output expression for 3 inputs Subtractor.
6. What is a Scaling adder?
7. What is the gain of the voltage follower?

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EXPERIMENT NO.8

OP–AMP as Integrator and Differentiator circuit

a. Aim: To study the op-amp applications as Integrator and Differentiator.

b. Components Required: Op-amp IC 741

Resistors,100Ω, 1KΩ, 10KΩ, 100KΩ
Capacitors- 1μF,0.1μF, 0.01μF,
DC Power supply(±12V)
Signal generator
CRO

8(a). Integrator

c. Theory: A circuit in which the output waveform is the integral of the input waveform. Such a
circuit is obtained by using a basic inverting amplifier configuration. If the feedback resistor R f in the
basic inverting amplifier is replaced by a capacitor Cf, then output voltage can be obtained by,
Vo= -(1/R1Cf )∫Vin dt+C
Where C is the integration constant and proportional to the value of the output voltage Vo at
time t=0 sec. Thus, the output voltage is directly proportional to the negative integral of the input
voltage and inversely proportional to the time constant R1Cf. In basic integrator circuit, due to input
offset voltage the capacitor Cf charges due to this input current, cause error output voltage. Hence we
connect Rf across the Cf to limits the low frequency gain and to prevent the variations in the output
voltage. Suppose if we give a sine wave input, the integrator circuit provide cosine wave. Similarly if
we provide Square wave as a input it provide a triangular wave as output.
Integration can be performed by a simple RC circuit. The non- inverting input terminal is
grounded, and this keeps the inverting input at the ground level (a virtual ground). During the positive
half cycle of the input square wave, the input current is a constant quantity (I1 = V1/R1). So as long as
I1>>IB(max), effectively all of I1 flows through capacitor Cf, charging it positive on the left side and

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negative on the right. Because the left side of Cf is at the ground level, and because I1 is constant, the
output voltage is a linear negative-going quantity. During the negative half cycle of the input, the
direction of I1 is reversed, the capacitor is charged with reversed polarity (positive on the right and
negative on the left), and so the output grows linearly in a positive-going direction. It is seen that the
triangular output voltage waveform from the op-amp integrating circuit is an inverted version of the
square wave input.

d. Procedure:
1. Assemble the circuit as shown in figure 8.1.
2. Set the signal generator output to square wave with peak value of 2Vp-p and frequency of 1KHz.
3. Feed both the input and output signals to an oscilloscope.
4. Observe the triangular wave as output on CRO and repeat the procedure with a sine wave as input.

Fig 8.1: Circuit diagram of Integrator.

For proper integration of input signal
Choose RfCf ≥ T,
Where T is the time period of input signal.
Set the input signal frequency to 1KHz so that T=1ms.
Let RfCf=2T,
Assume Cf=1μF, then Rf=2KΩ.
Choose Rf=10R1 so that,
R1 = 200Ω = R2 (To minimize input offset voltage).
Use R2=200Ω to compensate the input offset voltage effect.

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Fig 8.2: Output waveforms of integrator

8(b). Differentiator

e. Theory: Differentiator circuits as its name implies, performs the mathematical operation of
differentiation, that is, the output waveform is the derivative of the input. The differentiator may be
constructed from a basic inverting amplifier when an input resistor R1 and capacitor Cin are in series
so that output voltage is given by
Vo= -(Rf Cin) d (Vin /dt)
Thus, the output Vo is equal to the RfCin times the negative instantaneous rate of change of the
input voltage Vin with time. Capacitor current moves through the feedback resistor, producing a drop
across it, which is the same as the output voltage. A linear, positive rate of input voltage change will
result in a steady negative voltage at the output of the op-amp. Conversely, a linear, negative rate of
input voltage change will result in a steady positive voltage at the output of the op-amp. This polarity
inversion from input to output is due to the fact that the input signal is being sent (essentially) to the
inverting input of the op-amp, so it acts like the inverting amplifier. It is found that the basic
differentiator circuit is subjected to high frequency noise so that output may be corrupted by this high
frequency noise. Hence in order to overcome this high frequency noise and stability problem we use
R1 in series with Cin and Cf across the Rf. Suppose if we give a square wave as an input, the above
circuit provide spikes as output and if we give a triangular wave as input it provide an almost square
wave as output.

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f. Procedure:
1. Assemble the circuit as shown in figure 8.3
2. Set the signal generator output to square wave with peak value of 4Vp-p and frequency of 1KHz.
3. Feed both the input and output signals to an oscilloscope.
4. Observe the spikes as output on CRO and repeat the procedure with a sine wave and triangular
wave as input.

Fig 8.3: Circuit diagram of Differentiator

For proper differentiation of input signal

Choose T ≥ RfCin or RfCin ≤ T
Where T is time period of input signal.
Select input signal of 1 KHz,
RfCin = 0.5T
Choose Cin=1μF and T=1ms(1KHz input signal)
Rf=500Ω. ( use 470 Ω)
Choose Rf=10R1, so that R1=47Ω.
But RfCf=R1Cin,
so that Cf=0.1μF.
Choose R2=47Ω to compensate the input offset voltage effect.

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Fig 8.4: Output waveforms of Differentiator

g. Result: The op-amp Integrator and Differentiator operations are verified

h. Short questions

1. What is an Integrator?
2. Write down the expression for Vo of an Integrator.
3. Draw the output waveform of the Integrator when the input is a Square wave.
5. What is the purpose of connecting Rf in the feedback path of Integrator?
6. What are the applications of Integrator?
7. What is a Differentiator?
8. Write down the expression for Vo for a Differentiator.
9 Draw the output waveform of the Differentiator output when the input is a Sine wave.
10. Why R1 and Cf are connected in the circuit of Differentiator?
14. What are the applications of Differentiator?

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EXPERIMENT NO.9

Half wave and full wave precision rectifier using OP AMP

a. Aim: To conduct half wave and full wave precision rectifier using 741IC

b. Components required: Op-amp IC 741

Diodes
Resistors-10KΩ, 20KΩ
Bread board
DC Power supply (±12V)
Signal generator
CRO

C. Theory:
Precision half wave rectifier:
The op amps can enhance the performance of diode circuits. The use of Op-Amp can improve
the performance of a wide variety of signal processing circuits. In a rectifier circuit, the voltage drop
that occurs with an ordinary semiconductor rectifier can be eliminated to give precision (Accurate)
rectification. The Precision rectifier circuit in fig 9.1 uses a inverting amplifier configuration. Diode
D1 is reverse biased and D2 is forward biased, when the Op-amp output terminal is positive. These
occur when the input signal is negative. While D2 is forward biased, the circuit output is Vo= -
Vi(R2/R1). If R2=R1, Vo= -Vi during the negative half cycle of the input. If R2>R1, the output is an
amplified (inverted and half wave rectified) version of the input. The sole purpose of D1 is to keep the
Op-amp output from going into saturation. During the positive cycle, Op-Amp output terminal goes
negative, causing D2 reverse bias and D1 forward bias, so Vo=0.

Precision full wave rectifier:

The left side of the circuit in fig 9.2 is a precision half wave rectifier as in Fig 9.1, but with the
diodes reversed. The right side is an inverting summing amplifier circuit. The input voltage is applied

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to terminal a of the summing amplifier and to the input of precision rectifier. Note that the resistor R 2
in the precession half-wave rectifier circuit has twice the resistance of R1, so the rectified voltage
applied to terminal b of the summing amplifier is -2Vi as illustrated in figure 9.2.
During the positive half cycle of the input, the voltage at terminal a is +Vi, while at terminal b
is -2Vi. The output from summing circuit with R5=R4 is

Vo= - (R5/R3)(Va+Vb)= - (R5/R3)(Vi-2Vi) = (R5/R3)(Vi).

During negative half cycle of the input, Va=-Vi and Vb=0. Consequently the output is

Vo= - (R5/R3)(Va+Vb) = - (R5/R3)(-Vi+0)= R5/R3(Vi).

It is seen that the output is fullwave rectified version of the input voltage. If resistor R5=R4=
R3 circuit has an overall voltage gain of 1. When R5 is greater than R3 and R4, Amplification and
rectification occurs.

9(a). Precision half wave rectifier circuit:

d. Procedure:
1. Make the connections as shown in figure 9.1
2. Apply +12V and -12V at pin numbers 7 and 4 respectively.
3. Apply sinusoidal signal of required amplitude and frequency say 1 KHz and 2 volts Peak to Peak
voltage at pin no 2.
4. Display the output wave form on CRO and compare it with the expected wave form

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Input

Output

Fig 9.1: Circuit diagram of precision half wave rectifier circuit

9(b). Precision full wave rectifier circuit:

e. Procedure:

1. Make the connections as shown in figure 9.2

2. Apply +12V and -12V at pin numbers 7 and 4 respectively.
3. Apply sinusoidal signal of required amplitude and frequency say 1 KHz and 2 volts Peak to Peak
voltage at pin no 2.
4. Display the output wave form on CRO and compare it with the expected wave form

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Fig 9.2: Circuit diagram of precision full wave rectifier circuit

f. Result: The precision half wave and full wave rectifiers using op amp have been checked with the
expected waveforms.

g. Short questions:
1. Define a Rectifier?
2. What is an Half wave Rectifier?
3. What is a fill wave Rectifier?
4. What is a Precision rectifier?
5. Define Ripple Factor?
6. What is the efficiency of Half wave Rectifier?
7. What is the efficiency of fill wave Rectifier?
8. What is the RMS value of Half wave Rectifier?
9. What is the RMS value of Full wave Rectifier?

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EXPERIMENT NO.10

Schmitt trigger circuit and Zero crossing detector

a. Aim: To demonstrate the working of Schmitt trigger circuit for a given upper trigger point (UTP)
and lower trigger point (LTP) and verify the operation of Zero crossing detector

b. Components required: Op-Amp – 741

Resistors-1KΩ, 15KΩ,
DC Power Supply (±12V)
Signal generator and CRO.

c. Theory: Schmitt Trigger is also known as Regenerative Comparator. This is a square wave
generator which generates a square wave, based on the positive feedback applied. As shown in the
fig10.1, the feedback voltage is Va. The input voltage is applied to the inverting terminal and the
feedback voltage is applied to the non-inverting terminal. In this circuit, the op-amp acts as a
comparator. It compares the potentials at two input terminals. Here the output shifts between + V sat
and –Vsat. When the input voltage is greater than Va, the output shifts to – Vsat and when the input
voltage is less than Va, the output shifts to + Vsat. Such a comparator circuit exhibits a curve known as
Hysterisis curve which is a plot of Vin v/s V0.

The input voltage at which the output changes from + Vsat to – Vsat is called Upper Threshold
Point (UTP) and the input voltage at which the output shifts from – Vsat to + Vsat is called Lower
Threshold Point (LTP). The feedback voltage Va depends on the output voltage as well as the
reference voltage. A Zero Cross Detector is also a comparator where op-amp compares the input
voltage with the ground level. The output is a square wave and inverted form of the input.
10(a). Schmitt Trigger:
d. Procedure:
1. Rig up the connections as shown in the figure 10.1
2. Give a sinusoidal input of 10V peak to peak and 500 Hz from a signal generator.

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3. Check the output at pin no. 6 (square wave).

4. Coincide the point where the output shifts from + Vsat to – Vsat with any point on the input wave.
5. Measure the input voltage ( i.e amplitude from ground line) at this point. This voltage is UTP.
6. Coincide the point where the output shifts from – Vsat to + Vsat with any point on the input wave.
7. Measure the input voltage at this point ( i.e amplitude from ground line). This voltage is LTP.
8. Another method of measuring UTP and LTP is using the Hysterisis Curve.
9. To plot the hysterisis curve give channel 1 of CRO to the output and channel 2 of CRO to the input.
10. Press the XY knob. Adjust the grounds of both the knobs.
11. Measure UTP and LTP as shown in the fig. and check whether it matches with theoretical value.

Note: The same circuit can be designed for different values of UTP and LTP.
For example, if UTP = 4V and LTP = 2V, R1= 10k, R2 = 1k and Vref = 3.3V.
Check whether the circuit works properly for these values.

Fig 10.1: Circuit diagram of inverting Schmitt Trigger

Calculations:
Given UTP = +2.5V and LTP = +1V
But, UTP=[(R1Vref)/(R1+R2)]+[(R2Vsat)/(R1+R2)]
LTP=[(R1Vref)/(R1+R2)] – [(R2Vsat)/(R1+R2)]
UTP + LTP = [(2R1)/(R1+R2)]Vref --------------------------------------------------(1)
UTP - LTP=[(2R2)/(R1+R2)]Vsat-----------------------------------------------------(2)
Using equation (2)
2.5 - 1= [(2R2)/(R1+R2)]12

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On simplification,
R1=15R2
Let R2=1 KΩ then R1=15 KΩ
Using equation (1)
3.5 = 2[15R2/16R2]Vref
On simplification
Vref=1.87V
Therefore we choose Vref=1.9V

Fig 10.2: Waveforms of Schmitt Trigger

Fig 10.3: Hysterisis curve of Schmitt Trigger

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10(b). Zero Cross Detector:

e. Procedure:
1. Rig up the connections as shown in figure 10.4.
2. Give a sinusoidal input of 10V peak to peak and 500 Hz from a signal generator.
3. Check the output at pin no. 6 (square wave).

Fig 10.4: Circuit diagram of Zero Cross Detector

Fig 10.5: Waveforms of Zero Cross Detector

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f. Result: Schmitt trigger circuit for a given UTP and LTP and the operation of Zero crossing
detector is verified

g. Short questions
1. What is the output wave of Schmitt trigger if the input is sine wave?
2. How do you calculate the theoretical values of UTP and LTP in the case of IC741 schmitt
trigger?
3. What is the Hysteresis curve?
4. What is the minimum amplitude of the input sine wave in the case of Schmitt
trigger using IC741?

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EXPERIMENT NO.11

R-2R ladder DAC using Op - amp IC 741

a. Aim: To demonstrate the working of R/2R ladder 4-bit D/A Converter using IC 741

b. Components required: Op-amp IC 741,

Resistors-12KΩ, 24KΩ,
DC power supply (±12V),
Voltmeter (0-30)V,
Breadboard, connecting wires , etc.

c. Theory: Real world signals are analog. Digital systems that interface with the real world do so
using analog-to-digital converters (ADC). Conversion back to analog is accomplished using digital-
to- analog converters (DAC). The R-2R ladder network is commonly used for Digital to Analog
conversions. In basic N bit R-2R resistor ladder network the digital inputs or bits range from the most
significant bit (MSB) to the least significant bit (LSB). The bits are switched between either 0V or VR
(5V) and depending on the state and location of the bits, Vo will vary between 0V and VR (5V). The
MSB causes the greatest change in output voltage and the LSB causes the smallest.

The R-2R ladder is inexpensive and relatively easy to manufacture since only two resistor
values are required. It is fast and has fixed output impedance R. In R-2R ladder type Digital to
Analog converter, only two values of resistor is used (i.e. R and 2R). Hence it is suitable for
integrated circuit fabrication. The typical values of R are from 2.5KΩ to 12KΩ. In this, output
voltage is a weighted sum of digital inputs. Since the resistive ladder is a linear network, the principle
of super position can be used to find the total analog output voltage for a particular digital input by
adding the output voltages caused by the individual digital inputs. The output voltage is linearly
proportional to the digital input and the range can be adjusted by changing the reference voltage VR.

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d.Procedure:
1. Connect the R/2R ladder 4 bit DAC circuit shown in fig 11.1 on the bread board.
2. Select the approximate value of R and 2R.
3. Reference voltage VR is set as 5V ( By the inbuilt switch)
4. Find the output voltage Vo for different combinations of digital binary
inputs from 0000 to 1111.
5. Compare the calculated values with practical values

Circuit Diagram:

Fig 11.1: Circuit Diagram R-2R ladder DAC using Op-amp IC 741
Calculations:
Output Voltage is given by
Vo = - VR * [Rf / 2R] * [d1/2 + d2/4 + d3/8 + d4/16]
where, VR = 5V , Rf = 2R , d1 (MSB bit ) and d4 (LSB bit )
Let R = 12KΩ, then
Resolution = VFS / ( 2n- 1 ) , where n= no of digital inputs
VFS = Value of analog output when digital input is 1111.
Resolution = 0.3125 = Value of LSB bit.

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Table 11.1: Comparison of Theoretical and Practical values of DAC

d1 d2 d3 d4 Vo ( observed) Vo ( Calculated)

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

1 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

e. Result: Conversion of DAC using R-2R ladder is verified.

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f. Short Questions

1. What is an analog signal?

2. What is a Digital signal?
3. Define a DAC?
4. Define an ADC?
5. What is Resolution?
6. What is the Maximum Value of output voltage in R-2R DAC?

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EXPERIMENT NO.12

Voltage regulator using LM317

a. Aim: To demonstrate a LM 317 three pin adjustable o/p voltage regulator

b. Components required: LM317 IC,

Resistors - 5KΩ, 240Ω,
DC Voltmeter (0-30V).

c. Theory: The LM317 IC regulator is a three terminal device which is easy to use. The 317 is a
positive voltage regulator. Input and output terminals are provided for supply and regulated output
voltage and an adjustment terminal (Adjust) is included for output voltage selection. The output
voltage range is 1.2V to 37V, and the maximum load current ranges from 300mA to 2A, depending on
the device package type. The internal reference voltage for 317 is typically 1.25V and Vref appears
across the ADJ and output terminals. The resistor R1 and R2 are used to set the o/p voltage range of
1.2 to 37V. The output voltage Vo is given by equation. Vo=Vref(1+R2/R1)+IadjR2 Typical values which
can be used are Vref=1.25v Iadj=100µA

d. Procedure:
1. Connect the ckt as shown in figure 12.1
2. Vary the i/p voltage Vin from 0 to 37V and note corresponding o/p voltage
3. Note o/p current when o/p voltage is regulated.

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Circuit Diagram:

Fig 12.1: Circuit Diagram of Voltage regulator using LM317

Calculation:
Vref=1.25V = I1R1
I1=1.25/R1
I2=Iadj+I1
Vo=Vref + I2R2
Vo=Vref + (Iadj+I1)R2
Vo=Vref + IadjR2+I1R2
Vo=Vref + IadjR2 + (Vref/R1)R2
As Vref=1.25V
Vo=1.25(1+R2/R1) + Iadj R2

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To obtain o/p voltage at 8V

Vo=8V
WKT, Vo=1.25(1+R2/R1)+Iadj R2
Where Iadj = 100 µA , since it is very small value it is neglected.
There fore, Vo=1.25(1+R2/R1)
(8/1.25) = (1+R2/R1)
R2 = 5.4R1
Let R1 = 1Kohm
Then R2 = 5.4Kohm

Table 12.1: Readings of Output voltage and Load current

Vin volts Vo volts

Fig 12.2: Ideal graph of input v/s Output

Note: Output voltage varies till 8V according to design and after that it remains constant,

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e.Result: The variable regulated power supply is verified using IC LM 317

f.Short Questions

1. Define a Voltage Regulator?

2. What is the value of Reference voltage in LM317?
3. What is the expression for output voltage of Voltage regulator using LM 317?
4. What is the output voltage range in LM 317?
5. Mention other voltage regulator ICs.

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EXPERIMENT NO.12
Clipping and clamping using 741 IC

a. Aim: (i) To verify clipping circuit using 741 IC.

(ii) To verify clamping circuit using 741 IC.

12(a). Clipping circuit using 741 IC

b. Components required: Op-amp 741 IC, diode, 10 KΩ resistor, 10 KΩ pot, signal generator,
DC voltage source and CRO.

c. Theory: Positive Clipper:

A circuit that removes positive parts of the input signal can be formed by using an op-amp with a
rectifier diode. T he clipping level is determined by the reference voltage Vref, which should less than
the i/p range of the op-amp (Vref < Vin). The Output voltage has the portions of the positive half
cycles above Vref clipped off.

The circuit works as follows:

During the positive half cycle of the input, the diode D1 conducts only until Vin = Vref. This happens
because when Vin <Vref, the output volts V0 of the op-amp becomes negative to device D1 into
conduction when D1 conducts it closes feedback loop and op-amp operates as a voltage follower.
(i.e.) Output V0 follows input until Vin = Vref.

When Vin > Vref => the V0 becomes +ve to derive D1 into off. It opens the feedback loop and op- amp
operates open loop. When Vin drops below Vref (Vin<Vref) the o/p of the op-amp V0 again becomes –
ve to device D1 into conduction. It closes the feedback path. (o/p follows the i/p). The op-amp
alternates between open loop (off) and closed loop operation as the D1 is turned off and on
respectively. For this reason the op-amp used must be high speed and preferably compensated for
unity gain.

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Negative Clipper: The positive clipper is converted into a –ve clipper by simply reversing diode D1
and changing the polarity of Vref voltage. The negative clipper clips off the –ve parts of the input
signal below the reference voltage. Diode D1 conducts -> when Vin > -Vref and therefore during this
period o/p volt V0 follows the i/p volt Vin. The –Ve portion of the output volt below –Vref is clipped
off because (D1 is off) Vin<-Vref. If –Vref is changed to –Vref by connecting the potentiometer Rp to the
+Vcc, the V0 below +Vref will be clipped off. The diode D1 must be on for Vin > Vref and off for Vin.

Circuit Diagram

Fig12.1: Positive clipper

Fig 12.2: Input and output wave form for positive clipper

Fig 12.3: Negative clipper

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Fig 12.4: Input and output wave form for negative clipper
d. Procedure:
7. Rig up the circuit as shown in the figure 12.1 and 12.3.
8. Observe the sinusoidal input and output voltage.
9. Measure the clipping level at DC reference level.

12(b). Clamping circuit using 741 IC

e. Components required: Op-amp 741 IC, diode, 10 KΩ resistor, 10 KΩ pot, signal generator,
0.1 µF capactor, DC voltage source and CRO.

f. Theory:
A clamper is an electronic circuit that produces an output, which is similar to the input but with a
shift in the DC level. In other words, the output of a clamper is an exact replica of the input. Hence,
the peak to peak amplitude of the output of a clamper will be always equal to that of the input.

Clampers are used to introduce or restore the DC level of input signal at the output. There are two
types of op-amp based clampers based on the DC shift of the input.

 Positive Clamper
 Negative Clamper

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Positive Clamper

A positive clamper is a clamper circuit that produces an output in such a way that the input signal gets
shifted vertically by a positive DC value. In Fig 12.5, a sinusoidal voltage signal, Vi is applied to the
inverting terminal of op-amp through a network that consists of a capacitor C1 and a resistor R1. That
means, AC voltage signal is applied to the inverting terminal of the op-amp. The DC reference
voltage Vref is applied to the non-inverting terminal of the op-amp. The value of reference voltage
Vref can be chosen by varying the resistor R2. In this case, we will get a reference voltage Vref of a
positive value. The above circuit produces an output, which is the combination (resultant sum) of the
sinusoidal voltage signal Vi and the reference voltage Vref. That means, the clamper circuit produces
an output in such a way that the sinusoidal voltage signal Vi gets shifted vertically upwards by the
value of reference voltage Vref.

Negative Clamper

A negative clamper is a clamper circuit that produces an output in such a way that the input signal
gets shifted vertically by a negative DC value. In fig 12.7, a sinusoidal voltage signal Vi is applied to
the inverting terminal of the op-amp through a network that consists of a capacitor C1 and resistor R1.
That means, AC voltage signal is applied to the inverting terminal of the op-amp. The DC reference
voltage Vref is applied to the non-inverting terminal of the op-amp. The value of reference voltage Vref
can be chosen by varying the resistor R2. In this case, we will get reference voltage Vref of a negative
value. The above circuit produces an output, which is the combination (resultant sum) of sinusoidal
voltage signal Vi and reference voltage Vref. That means, the clamper circuit produces an output in
such a way that the sinusoidal voltage signal Vi gets shifted vertically downwards by the value of
reference voltage Vref.

Circuit Diagram

Fig: 12.5: Positive Clamper

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Fig 12.6: Input and output waveform

Fig 12.7: Negative clamper

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Fig 12.8: Input and output waveform

g. Procedure:
10. Rig up the circuit as shown in the figure 12.5 and 12.6.
11. Observe the sinusoidal input and output voltage.
12. Measure the clamping level as per the reference voltage.

h. Result: (i) The clipper circuit waveforms have been verified for given input signal.
(ii) The clamper circuit waveforms have been verified for given input signal.
i. Short questions:
1. What is the difference between clipping and clamping circuit?
2. What is the difference between diode clamper and precision clamper?
3. Mention the application of clipper and clamper circuit
4. What is the difference between diode clipper and precision clipper?

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Appendix –A
DATASHEET OF LM 741 OP-AMP

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Appendix –B
DATASHEET OF NMOS Transistor.

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