LT6350

Low Noise
Single-Ended to Differential
Converter/ADC Driver
FEATURES DESCRIPTION
n Rail-to-Rail Input and Outputs The LT®6350 is a rail-to-rail input and output low noise
n Fast Settling Time: 240ns, 0.01%, 8VP-P Output Step single-ended to differential converter/ADC driver featuring
n 1.9nV/√Hz Input-Referred Op Amp Noise fast settling time. It converts a high or low impedance,
n High Impedance Input single-ended input signal to a low impedance, balanced,
n –3dB Bandwidth: 33MHz differential output suitable for driving high performance
n 2.7V to 12V Supply Operation differential succesive approximation register (SAR) ADCs.
n No External Gain-Resistors Required The two op amp topology features very low noise op amps,
n 4.8mA Supply Current that can support SNR >110dB in a 1MHz bandwidth.
n Low Power Shutdown
n
The input op amp is trimmed for constant low input-referred
Low Distortion (HD2/HD3): –102dBc/–97dBc at
voltage offset over the input range to prevent VOS steps
100kHz, VOUTDIFF = 4VP-P
n
from degrading distortion.
Low Offset Voltage: ±400μV Max
n High DC Linearity: <±1LSB, 16-Bit, 8VP-P On a single 5V supply, the outputs can drive ADCs from
n Low Input Current Noise: 1.1pA/√Hz 55mV to 4.945V on each input. With the addition of a
n 3mm × 3mm 8-Pin DFN and 8-Lead MSOP Packages negative supply, the LT6350 can drive ADCs from 0V to
4.945V on each input. Output common mode voltage is
APPLICATIONS set by applying a voltage to the +IN2 pin.
n 16-Bit and 18-Bit SAR ADC Drivers The LT6350 draws 4.8mA from a 5V supply and consumes
n Single-Ended to Differential Conversion just 60μA in shutdown mode.
n Differential Line Driver
The LT6350 is available in a compact 3mm × 3mm, 8-pin
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners. leadless DFN package and also in an 8-pin MSOP package
Protected by U.S. Patents including 5610557, 6344773.
and operates over a –40°C to 125°C temperature range.

TYPICAL APPLICATION 20kHz Sine Wave,

ADC Driver: Single-Ended Input to Differential Output –1dBFS 8192-Point FFT
5V 0
–10 V + = 5V, V – = –5V
VOUTDIFF = 7.3VP-P
0.1μF 249Ω –20 V+IN2 = 2.05V
–30 SNR = 94.9dB
VIN + –40 SINAD = 93.8dB
5V
MAGNITUDE (dB)

0V to 4V – +IN1 SHDN V+ OUT2 –50 THD = –100.2dB

–60 SFDR = 102.2dB
+
AIN– –70
– –80
LT6350 – 2200pF LTC2393-16
–90
+ AIN+ –100
–110
– IN1 +IN2 V– OUT1
–120
–130
–140
–5V 249Ω 0 100 200 300 400 500
499Ω FREQUENCY (kHz)
0.1μF 0.1μF 6350 TA01
6350 TA02

2V
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LT6350
ABSOLUTE MAXIMUM RATINGS (Note 1)

Total Supply Voltage Specified Temperature Range

(V+ – V –) ............................................................12.6V (Note 5)..................................................–40°C to 125°C
Input Current (Note 2)..........................................±20mA Maximum Junction Temperature........................... 150°C
Output Short Circuit Current Duration Storage Temperature Range...................–65°C to 150°C
(Note 3)............................................................ Indefinite Lead Temperature
Operating Temperature Range (Soldering, 10 sec, MSOP Package Only) ............. 300°C
(Note 4)..................................................–40°C to 125°C

PIN CONFIGURATION
TOP VIEW

–IN1 1 8 +IN1 TOP VIEW

+IN2 2 7 SHDN –IN1 1 8 +IN1

9 +IN2 2 7 SHDN
V+ 3 6 V– V+ 3 6 V–
OUT1 4 5 OUT2 OUT1 4 5 OUT2
MS8 PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD (3mm s 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 250°C/W
TJMAX = 150°C, θJA = 43°C/W
UNDERSIDE METAL CONNECTED TO V–

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LT6350CDD#PBF LT6350CDD#TRPBF LFJT 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LT6350IDD#PBF LT6350IDD#TRPBF LFJT 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LT6350HDD#PBF LT6350HDD#TRPBF LFJT 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT6350CMS8#PBF LT6350CMS8#TRPBF LTFJV 8-Lead Plastic MSOP 0°C to 70°C
LT6350IMS8#PBF LT6350IMS8#TRPBF LTFJV 8-Lead Plastic MSOP –40°C to 85°C
LT6350HMS8#PBF LT6350HMS8#TRPBF LTFJV 8-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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 LT6350
ELECTRICAL CHARACTERISTICS The l denotes
+
specifications that apply over the full specified temperature range,
– +
otherwise specifications are at TA = 25°C. Unless noted otherwise, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RL = OPEN, RF =
SHORT, RG = OPEN. VS is defined as (V+ – V–). VOUTCM is defined as (VOUT1 + VOUT2)/2. VOUTDIFF is defined as (VOUT1 – VOUT2). See Figure 1.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOSDIFF Differential Input-Referred Offset Voltage VS = 5V
V+IN1 = V2 = Mid-Rail –0.4 0.4 mV
V+IN1 = V2 = V– +1.5V to V+ – 0.1V –0.45 ±0.1 0.45 mV
V+IN1 = V2 = V– +1.5V to V+ – 0.1V l –0.77 1.36 mV
VS = 3V
V+IN1 = V2 = V– +1.5V to V+ – 0.1V –0.45 ±0.1 0.45 mV
V+IN1 = V2 = V– +1.5V to V+ – 0.1V l –0.8 1.36 mV
VS = 10V
V+IN1 = V2 = V– +1.5V to V+ – 0.1V –0.52 ±0.1 0.52 mV
V+IN1 = V2 = V– +1.5V to V+ – 0.1V l –0.78 1.48 mV
VOS1 Input Offset Voltage, Op Amp 1 VS = 5V
V+IN1 = V –+1.5V to V+ l –0.35 ±0.08 0.68 mV
V+IN1 = V – to V+ l –1.5 ±0.28 1.5 mV
VS = 3V
V+IN1 = V –+1.5V to V+ l –0.35 ±0.08 0.68 mV
V+IN1 = V – to V+ l –1.5 ±0.32 1.5 mV
VS = 10V
V+IN1 = V –+1.5V to V+ l –0.68 ±0.07 0.68 mV
V+IN1 = V – to V+ l –1.5 ±0.28 1.5 mV
VOS2 Input Offset Voltage, Op Amp 2 (Note 6) VS = 3V, 5V, 10V
V+IN1 = V2 = V –+1.5V to V+ – 0.1V l –1.0 ±0.1 0.66 mV
ΔVOSDIFF /ΔT Differential Offset Voltage Drift V+IN1 = V2 = V – +1.5V l 5 μV/°C
V+IN1 = V2 = V+ –0.1V l 5.5 μV/°C
IB1 Input Bias Current, Op Amp 1 V+IN1 = Mid-Supply l –6.8 –1.2 μA
(at +IN1, –IN1) V+IN1 = V – l –8.0 –3.0 μA
V+IN1 = V+ l 1.4 2.6 μA
IOS1 Input Offset Current, Op Amp 1 V+IN1 = Mid-Supply l –1 ±0.1 1 μA
(at +IN1, –IN1) V+IN1 = V – l –1 ±0.1 1 μA
V+IN1 = V+ l –1 ±0.1 1 μA
I+IN2 Input Bias Current, Op Amp 2 (at +IN2) V+IN1 = V2 = Mid-Supply l 2.5 4.4 μA
IOS2 Input Offest Current, Op Amp 2 V2 = Mid-Supply ±0.1 μA
en1 Input Voltage Noise Density, Op Amp 1 Op Amp Input Referred 1.9 nV/√Hz
in1 Input Current Noise Density, Op Amp 1 1.1 pA/√Hz
en2 Input Voltage Noise Density, Op Amp 2 Op Amp Input Referred 2.1 nV/√Hz
in2 Input Current Noise Density, Op Amp 2 1 pA/√Hz
en(OUT) Differential Output Noise Voltage Density Total Output Noise Including Both Op Amps 8.2 nV/√Hz
and On-Chip Resistors. Input Shorted. f = 10kHz
Input Noise Voltage 0.1Hz to 10Hz 300 nVP-P
SNR Output Signal to Noise Ratio VOUTDIFF = 8VP-P, 1MHz Noise Bandwidth 110 dB
V+IN1 Input Voltage Range, +IN1 Guaranteed by CMRR1 l V– V+ V
V+IN2 Input Voltage Range, +IN2 Guaranteed by CMRR2 l V – +1.5V V + –0.1V V
RIN Input Resistance Single-Ended Input at +IN1 4 MΩ

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LT6350
ELECTRICAL CHARACTERISTICS The l denotes
+
specifications that apply over the full specified temperature range,
– +
otherwise specifications are at TA = 25°C. Unless noted otherwise, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RL = OPEN, RF =
SHORT, RG = OPEN. VS is defined as (V+ – V–). VOUTCM is defined as (VOUT1 + VOUT2)/2. VOUTDIFF is defined as (VOUT1 – VOUT2). See Figure 1.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN Input Capacitance Single-Ended Input at +IN1 1.8 pF
CMRR1 Common Mode Rejection Ratio, Op Amp 1 VS = 5V, V+IN1 = V–IN1 = V – +1.5V to V + 82 94 dB
VS = 5V, V+IN1 = V–IN1 = V – +1.5V to V + l 77 94 dB
VS = 5V, V+IN1 = V–IN1 = V – to V + l 72 88 dB
VS = 3V, V+IN1 = V–IN1 = V – to V + l 67 82 dB
CMRR2 Common Mode Rejection Ratio, Op Amp 2 VS = 5V, V+IN1 = V2 = V –+1.5V to V+ –0.1V l 93 118 dB
VS = 3V, V+IN1 = V2 = V –+1.5V to V+ –0.1V l 85 110 dB
VS = 10V, V+IN1 = V2 = V –+1.5V to V+ –0.1V l 96 118 dB
PSRR Power Supply Rejection Ratio (ΔVS/ VS = 2.7V to 12V l 80 108 dB
ΔVOSDIFF)
VS Supply Voltage (Note 7) l 2.7 12 V
BAL Output Balance (ΔVOUTDIFF/ΔVOUTCM) (Note VOUTDIFF = 2V l 50 68 dB
8)
GAIN Closed-Loop Gain (ΔVOUTDIFF /Δ(V+IN1 Δ(V+IN1 –V2) = 4V l 2 V/V
–V2))
GAINERR Closed-Loop Gain Error l –0.6 ±0.08 0.6 %
ΔGAINERR/ΔT Closed-Loop Gain Error Drift l 3 ppm/°C
INL DC Linearity (Note 9) V+ = 5V, V – = 0V 230 μV
V+ = 5V, V – = –2V 125 μV
V+ = 5V, V– = –2V, 16-Bit, 8VP-P ±1 LSB
RINT Internal Resistors 1000 Ω
VOH Output Swing to V +, Either Output (Note No load l 55 170 μV
10) Sourcing 12.5mA l 360 750 μV
VOL Output Swing to V –, Either Output (Note No load l 55 170 mV
10) Sourcing 12.5mA l 260 460 mV
ISC Output Short Circuit Current V+IN1 = Mid-Rail ±200mV, V–IN1 = Mid-Rail
VS = 5V ±27 ±45 mA
VS = 5V l ±15 ±45 mA
VS = 3V l ±15 ±40 mA
VIL SHDN Input Logic Low VS = 2.7V to 12V l V – + 0.3 V
VIH SHDN Input Logic High VS = 2.7V to 12V l V – + 2.0 V
ISHDN SHDN Pin Current SHDN = V+ l –1 1 μA
SHDN = V – l –45 –20 μA
IS Supply Current VS = 3V l 4.5 8.1 mA
VS = 5V 5.8 mA
VS = 5V l 4.8 8.3 mA
VS = 10V l 5.4 10.4 mA
IS(SHDN) Supply Current in Shutdown VS = 3V, VSHDN = VIL l 43 220 μA
VS = 5V, VSHDN = VIL l 60 240 μA
VS = 10V, VSHDN = VIL l 70 260 μA
GBW Gain-Bandwidth Product Op Amp 1 (Non-Inverting) 85 MHz
Frequency = 1MHz Op Amp 2 (Inverting) 115 MHz
BW Differential –3dB Small Signal Bandwidth VOUTDIFF = 100mVP-P 23 MHz
VOUTDIFF = 100mVP-P l 19 33 MHz

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 LT6350
ELECTRICAL CHARACTERISTICS The l denotes
+
specifications that apply over the full specified temperature range,
– +
otherwise specifications are at TA = 25°C. Unless noted otherwise, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RL = OPEN, RF =
SHORT, RG = OPEN. VS is defined as (V+ – V–). VOUTCM is defined as (VOUT1 + VOUT2)/2. VOUTDIFF is defined as (VOUT1 – VOUT2). See Figure 1.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
FPBW Full Power Bandwidth (Note 11) VOUTDIFF = 8VP-P 1.6 MHz
CL Capacitive Load Drive, 20% Overshoot No Series Output Resistors 56 pF
SR Differential Slew Rate OUT1 Rising (OUT2 Falling) 48 V/μs
OUT1 Falling (OUT2 Rising) 41 V/μs
10kHz Distortion VS = 5V, VOUTDIFF = 4VP-P, RL = 2kΩ
HD2 2nd Harmonic –115 dBc
HD3 3rd Harmonic –115 dBc
100kHz Distortion VS = 5V, VOUTDIFF = 4VP-P, RL = 2kΩ
HD2 2nd Harmonic –102 dBc
HD3 3rd Harmonic –97 dBc
1MHz Distortion VS = 5V, VOUTDIFF = 4VP-P, RL = 2kΩ
HD2 2nd Harmonic –86 dBc
HD3 3rd Harmonic –75 dBc
tS Settling Time to a 4V Input Step 0.1% 200 ns
0.01% 240 ns
0.0015% (±1LSB, 16-Bit, Falling Edge) 350 ns
tOVDR Overdrive Recovery Time +IN1 to V – and V+ 200 ns
tON Turn-On Time VSHDN = 0V to 5V 400 ns
tOFF Turn-Off Time VSHDN = 5V to 0V 400 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: VOS2 is measured as the total output common mode voltage offset
may cause permanent damage to the device. Exposure to any Absolute (error between output common mode and voltage at V2). VOS2 includes
Maximum Rating condition for extended periods may affect device the combined effects of op amp 2’s voltage offset, IB, IOS and mismatch
reliability and lifetime. between on-chip resistors and the 499Ω external resistor, R1 (See Figure 1).
Note 2: Inputs are protected by back-to-back diodes and diodes to each Note 7: Supply voltage range is guaranteed by the power supply rejection
supply. If the inputs are taken beyond the supplies or the differential input ratio test.
voltage exceeds 0.7V, the input current must be limited to less than 20mA. Note 8: Output balance is calculated from gain error and gain as:
Note 3: A heat sink may be required to keep the junction temperature
GAIN
below the absolute maximum rating when the output is shorted indefinitely. BAL =
GAINERR
Note 4: The LT6350C/LT6350I are guaranteed functional over the
temperature range of –40°C to 85°C. The LT6350H is guaranteed Note 9: DC linearity is measured by measuring the differential output for
functional over the temperature range of –40°C to 125°C. each input in the set V+IN1 = 0.5V, 2.5V, 4.5V, and calculating the maximum
Note 5: The LT6350C is guaranteed to meet specified performance from deviation from the least squares best fit straight line generated from the
0°C to 70°C. The LT6350C is designed, characterized and expected to three data points.
meet specified performance from –40°C to 85°C, but is not tested or Note 10: Output voltage swings are measured between the output and
QA sampled at these temperatures. The LT6350I is guaranteed to meet power supply rails.
specified performance from –40°C to 85°C. The LT6350H is guaranteed to Note 11: Full- power bandwidth is calculated from the slew rate.
meet specified performance from –40°C to 125°C. FPBW = SR/2VP.

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LT6350
TYPICAL
+
PERFORMANCE
–
CHARACTERISTICS
+
TA = 25°C, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RF = SHORT, RG = OPEN, RL = OPEN. See Figure 1.
Offset Voltage vs Input Common Offset Voltage vs Input Common
Differential VOS Delta Distribution Mode Voltage, Op Amp 1 Mode Voltage, Op Amp 1
100 0.2 0.2
434 TYPICAL UNITS VS = 5V V + = 5V, V – = –5V

INPUT REFERRED OFFSET VOLTAGE (mV)

INPUT REFERRED OFFSET VOLTAGE (mV)
90 VS = 5V TYPICAL UNIT TYPICAL UNIT
TA = 25°C
80 V+IN1 = V2 = 0.1 0.1
MID-RAIL TO
70 V + –0.1V
NUMBER OF UNITS

60 0.0 0
50
40 –0.1 –0.1
30
20 –0.2 TA = 125°C –0.2 TA = 125°C
10 TA = 25°C TA = 25°C
TA = –40°C TA = –40°C
0 –0.3 –0.3
–0.3 –0.2 –0.1 0 0.1 0.2 0.3 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5
CHANGE OF INPUT REFERRED VOS (mV) INPUT COMMON MODE VOLTAGE (V) INPUT COMMON MODE VOLTAGE (V)
6350 G02 6350 G10 6350 G11

Differential VOS Distribution DC Linearity DC Linearity

DIFFERENTIAL OUTPUT ERROR FROM LINEAR FIT (mV)

DIFFERENTIAL OUTPUT ERROR FROM LINEAR FIT (mV)

100 0.5 0.5
434 TYPICAL UNITS V – = 0V, V+ = 5V TA = 125°C
90 VS = 5V 0.4 V+IN2 = 2.5V 0.4 TA = 85°C
TA = 25°C NO LOAD TA = 25°C
80 V+IN1 = V2 = 0.3 0.3
TYPICAL UNIT TA = –40°C
MID-RAIL LINEAR FIT FOR 0.25V < VIN < 4.75V
70 0.2 0.2
NUMBER OF UNITS

60 0.1 0.1
50 0 0
40 –0.1 –0.1
V – = –5V, V + = 5V
30 –0.2 –0.2 V+IN2 = 0V
TA = 125°C NO LOAD
20 –0.3 TA = 85°C –0.3 TYPICAL UNIT
10 –0.4 TA = 25°C LINEAR FIT FOR
–0.4
TA = –40°C –4.75V < VIN < 4.75V
0 –0.5 –0.5
–0.3 –0.2 –0.1 0 0.1 0.2 0.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
DIFFERENTIAL INPUT REFFERED VOS (mV) V+IN1 (V) V+IN1 (V)
6350 G01 6350 G21 6350 G22

Common Mode VOS

vs Input (+IN2) Voltage Differential VOS vs Temperature
INPUT REFERRED DIFFERENTIAL OFFSET VOLTAGE (mV)

0.5 0.6
V+IN1 = V+IN2
0.4 VS = 5V VS = 10V
(NOTE 6) TA = –40°C 0.4
0.3
COMMON MODE VOS (mV)

0.2
0.2
0.1
TA = 25°C VS = 5V
0 0
–0.1
–0.2
–0.2
–0.3 TA = 125°C
–0.4
–0.4 V1 = V2 = MID-RAIL
TYPICAL UNIT
–0.5 –0.6
0 1 2 3 4 5 6 –60 –20 20 60 100 140
+IN2 PIN VOLTAGE (V) TEMPERATURE (°C)
6350 G07 6350 G09

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 LT6350
TYPICAL
+
PERFORMANCE
–
CHARACTERISTICS
+
TA = 25°C, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RF = SHORT, RG = OPEN, RL = OPEN. See Figure 1.
Input Bias Current Input Bias Current Input Bias Current
vs Input Voltage, Op Amp 2 vs Input Voltage, Op Amp 1 vs Temperature, Op Amp 1
4 2 3
VS = 5V VS = 5V VS = 5V
V+IN1 = V+IN2
1 2
V+IN1 = V +
INPUT CURRENT +IN2 (μA)

INPUT CURRENT +IN1 (μA)

INPUT CURRENT (μA)

1
3 0
0
–1 V+IN1 = MID-RAIL
–1
2 –2
–2 V+IN1 = V –
TA = 125°C –3 TA = 125°C
TA = 25°C TA = 25°C –3
TA = –40°C TA = –40°C
1 –4 –4
0 1 2 3 4 5 0 1 2 3 4 5 –60 –40 –20 0 20 40 60 80 100 120 140
V+IN2 (V) V+IN1 (V) TEMPERATURE (°C)
3586 G35 6350 G08 6350 G13

Supply Current vs Supply Voltage Supply Current vs Temperature

10 10
VSHDN = V+
9 9
TA = 125°C
8 8
SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

7 7
6 6
TA = 25°C
5 5
4 TA = –40°C 4
3 3
2 2 VS = 10V
1 1 VS = 5V
VS = 3V
0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 –60 –20 20 60 100 140
SUPPLY VOLTAGE (V) TEMPERATURE (°C) 6350 G04

6350 G03

Supply Current in Shutdown Turn-On and Turn-Off

Supply Current vs SHDN Voltage vs Supply Voltage Transient Response
8 120 3
VS = 5V VSHDN = V – V+ = 2.5V
7 V – = –2.5V
TA = –40°C
TA = 125°C 100 2 RL = 2k
6
SUPPLY CURRENT(mA)

SUPPLY CURRENT (μA)

80 1
VOUT, VSHDN (V)

5 TA = 25°C

4 TA = 25°C 60 TA = 125°C 0

3
40 –1 VSHDN
TA = –40°C
2
20 –2
1
VOUTDIFF
0 0 –3
0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10 11 12 5μs/DIV
SHDN PIN VOLTAGE (V) 6350 G05
SUPPLY VOLTAGE (V) 6350 G06
6350 G43

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LT6350
TYPICAL
+
PERFORMANCE
–
CHARACTERISTICS
+
TA = 25°C, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RF = SHORT, RG = OPEN, RL = OPEN. See Figure 1.
Differential Output Voltage Noise 0.1Hz to 10Hz Differential Output Settling Time
vs Frequency Input-Referred Voltage Noise vs Output Step
100 600 300
VS = 5V VS = 5V VS = 5V

INPUT-REFERRED VOLTAGE NOISE (nV)

TA = 25°C
OUTPUT NOISE VOLTAGE(nV/√Hz)

400 250

SETTLING TIME (ns)

200 200

10 0 150 2mV 2mV

–200 100
20mV 20mV

–400 50

1 –600 0
1 1k 1M 100M –8 –6 –4 –2 0 2 4 6 8
FREQUENCY (Hz) TIME (2s/DIV) DIFFERENTIAL OUTPUT STEP (V)
6350 G23 6350 G24 6350 G35

Output Saturation Voltage Output Saturation Voltage

Output Settling Time vs Load Current, Output Low, vs Load Current, Output High,
vs Output Step Either Output Either Output
400 10 10
VS = 10V VS = 5V VS = 5V
350

OUTPUT SATURATION VOLTAGE (V)

OUTPUT SATURATION VOLTAGE (V)

300
SETTLING TIME (ns)

1 1
250 0.01%

200

150 2mV
0.1 0.1
100
TA = 125°C TA = 125°C
50 TA = 25°C TA = 25°C
20mV TA = –40°C TA = –40°C
0 0.01 0.01
–20 –15 –10 –5 0 5 10 15 20 0.0.1 0.1 1 10 100 0.01 0.1 1 10 100
DIFFERENTIAL OUTPUT STEP (V) LOAD CURRENT (mA) LOAD CURRENT (mA)
6350 G36 6350 G14 6350 G15

Output Impedance Output Short Circuit Current

vs Frequency vs Supply Voltage, Either Output Overdrive Recovery
100 100 6 7
VS = 5V VS = 5V
OUTPUT SHORT CIRCUIT CURRENT (mA)

80
5 5
SINKING
60
OUTPUT IMPEDANCE (Ω)

10
40 4 3
VOUTDIFF (V)

20
V+IN1 (V)

TA = 85°C 3 1
1 0 TA = 25°C
OUT2 TA = –40°C 2 –1
–20

OUT1 –40 1 –3
0.1
–60
SOURCING 0 –5
–80 V+IN1 VOUTDIFF

0.01 –100 –1 –7
0.01 0.1 1 10 100 0 2 4 6 8 10 12 0 1 2 3 4
FREQUENCY (MHz) SUPPLY VOLTAGE (V) TIME (μs)
6350 G28 6350 G16 6350 G44

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 LT6350
TYPICAL
+
PERFORMANCE
–
CHARACTERISTICS
+
TA = 25°C, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RF = SHORT, RG = OPEN, RL = OPEN. See Figure 1.
Differential Frequency Response Differential Frequency Response Closed Loop Small Signal
vs Gain vs Temperature Frequency Response, Op Amp 1
40 10 30
VS = 5V VS = 5V VS = 5V
RL = 2k RL = 2k RL = 2k
30 RF + RG = 2k FOR AVDIFF > 2 AV1 = 10 RF + RG = 2k for AV1 > 1
5
DIFFERENTIAL GAIN (dB)

DIFFERENTIAL GAIN (dB)

20

GAIN MAGNITUDE (dB)

20 AV1 = 5
0
10 10
AV1 = 2
–5
0 AV1 = 1
AVDIFF = 20 0
AVDIFF = 10 –10 TA = 85°C
–10
AVDIFF = 4 TA = 25°C
AVDIFF = 2 TA = –40°C
–20 –15 –10
0.1 1 10 100 1000 0.1 1 10 100 1000 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
6350 G37 6350 G38 6350 G19

Closed Loop Small Signal Closed Loop Magnitude and

Frequency Response, Op Amp 2 Group Delay Response, Op Amp 2 Output Balance vs Frequency
OP AMP2 FREQUENCY RESPONSE MAGNITUDE (dB)

OP AMP2 FREQUENCY RESPONSE MAGNITUDE (dB)

5 500 5 8 60
VS = 5V VS = 5V
MAGNITUDE
0 400 MAGNITUDE 50

OP AMP2 GROUP DELAY (ns)

0 7
OP AMP2 PHASE (DEG)

OUTPUT BALANCE (dB)

–5 300 40
GROUP DELAY

–10 PHASE 200 –5 6 30

–15 100 20
–10 5
–20 0 10

–25 –100 –15 4 0

0.1 1 10 100 1000 0.1 1 10 100 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
6350 G20 6350 G40 6350 G41

Differential Slew Rate

Small Signal Step Response Large Signal Step Response vs Temperature
5 80
OUT2, CL = 56pF EACH OUTPUT TO GND VS = 5V
DIFFERENTIAL OUTPUT SLEW RATE (V/μS)

OUT1 TIED TO –IN1

OUT2 70 50Ω SOURCE IMPEDANCE
4 RL = 1k
OUTPUT VOLTAGE (V)

OUT1, NO LOAD 60
3 V+ = 5V, V – = 0V
20mV/DIV

OUT1 RISING
V+IN2 = 2.5V (OUT2 FALLING)
50
NO LOAD
2
40
OUT2, NO LOAD OUT2 RISING
1 (OUT1 FALLING)
OUT1 30

OUT1, CL = 56pF EACH OUTPUT TO GND

0 20
VS = 5V 200ns/DIV 200ns/DIV –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
6350 G33 6350 G34 3586 G35

6350f

9
LT6350
TYPICAL
+
PERFORMANCE
–
CHARACTERISTICS
+
TA = 25°C, V = 5V, V = 0V, V+IN1 = V2 = Mid-Supply, VSHDN = V , RF = SHORT, RG = OPEN, RL = OPEN. See Figure 1.
Harmonic Distortion Harmonic Distortion
Harmonic Distortion vs Frequency vs Output Amplitude vs Output Amplitude
–50 –60 –40.0
V+ = 5V, V – = 0V, VOUTCM = 2.5V fIN = 100kHz fIN = 1MHz
RL = 2k RL = 2k RL = 2k
–60
–50.0
–70
V + = 5V, V – = 0V, VOUTCM = 2.5V
–70 V + = 5V, V – = 0V, VOUTCM = 2.5V
DISTORTION (dBc)

DISTORTION (dBc)

DISTORTION (dBc)
–60.0
–80 VOUTDIFF = 8VP-P –80
–70.0
–90
–90 HD3
HD3 HD3 –80.0
–100 HD2
VOUTDIFF = 4VP-P HD2
–100
–110 HD2 –90.0
V + = 5V, V – = –2V, VOUTCM = 2V
V + = 5V, V – = –2V, VOUTCM = 2V
–120 –110 –100.0
1k 10k 100k 1M 4 5 6 7 8 2 3 4 5 6 7 8
FREQUENCY (Hz) VOUTDIFF (VP-P) VOUTDIFF (VP-P)
6350 G47 6350 G45 6350 G46

PIN FUNCTIONS
–IN1 (Pin 1): Inverting Input. Normally used to take feed- V– (Pin 6): Negative Power Supply. Can be ground.
back from OUT1. SHDN (Pin 7): Shutdown. If tied high or left floating, the
+IN2 (Pin 2): High Impedance Input. Normally used as a part is enabled. If tied low, the part is disabled and draws
reference input. less than 70μA of supply current.
V+ (Pin 3): Positive Power Supply. +IN1 (Pin 8): High Impedance Input. Normally used as
OUT1 (Pin 4): Noninverting Output. In phase with +IN1. the single-ended input.

OUT2 (Pin 5): Inverting Output. Exposed Pad (Pin 9, DD8 Package Only): Tie to V –

6350f

10
 LT6350
BLOCK DIAGRAM
+IN1 SHDN V– OUT2
8 7 6 5

BIAS
+
OP AMP 1
1k 1k
–

_
OP AMP 2

1 2 3 4
6350 BD
– IN1 +IN2 V+ OUT1

DC TEST CIRCUIT
VSHDN
+ V+
–
V+IN1 0.1μF VOUT2

+ V1 V+
– +IN1 SHDN OUT2 –

+ RL
– VOUTDIFF
LT6350 –
+
– IN1 +IN2 V– OUT1 +
RF VOUT1

V– 6350 TC

RG R1
499Ω 0.1μF 0.1μF

V2 +
–

Figure 1. DC Test Circuit.

6350f

11
LT6350
OPERATION
The LT6350 is a low noise single-ended to differential 4.5V
5V
converter /ADC driver. It converts a high or low impedance, VIN

single-ended input signal to a low impedance, balanced 0.5V 0.1μF VOUT2

differential output suitable for driving high performance + VIN 4.5V
differential sucessive approximation register (SAR) ADCs. – 0.5V-4.5V +IN1 SHDN V+ OUT2

The closed loop –3dB bandwidth for the typical gain-of-two +

0.5V
configuration is 33MHz. –
LT6350 –
The LT6350 uses a two op amp topology as shown in +
the Block Diagram: at the input is one fully uncommitted – IN1 +IN2 V– OUT1

op amp with both inputs and output brought out to pins. VOUT1
This is followed by an op amp internally hardwired and 4.5V
optimally compensated as a unity-gain inverter with its 2.5V
0.1μF
input connected to the output of the first op amp. The 0.5V
noninverting input of the inverting op amp is brought out to 6350 F02

a pin and is used to set the output common mode voltage

Figure 2. Basic Connections
level. The outputs of the two op amps are therefore 180°
out-of-phase and provide a low impedance differential
drive for differential-input analog to digital converters. DESIGN EQUATIONS AND ALTERNATIVE CONNECTIONS
The outputs of the LT6350 can swing rail-to-rail and can Because the input op amp presents its output and both
source or sink a transient 45mA of current. The outputs its inputs to LT6350 pins, alternative configurations are
are designed to drive 40pF to ground or 20pF differentially. possible. Consider the general configuration shown in
Load capacitances larger than 40pF should be decoupled Figure 3.
from each output with at least 25Ω of series resistance.
Ordinary op amp analysis gives the equations for VOUT1
The LT6350 features very low noise op amps to support and VOUT2 given the input voltages V1, V2, VIN and VA:
signal-to-noise ratios >110dB.
VOUT1 = VIN • (1+RF /RG) – V1 • (RF/RG)
BASIC CONNECTIONS VOUT1 = VA • (1+RF /RG) + V1
A typical use of the LT6350 is to convert a high impedance, VOUT2 = –VOUT1 + 2 • V2
single-ended input signal into a low impedance differential
output. The configuration for such an application is shown If we define the differential and common mode output
in Figure 2. Here, the input op amp is wired as a non- voltages as:
inverting buffer with a high input impedance at +IN1. At VOUTDIFF ≡ VOUT1 – VOUT2
the outputs, VOUT1 follows the input, and VOUT2 provides
and
an inverted copy of VOUT1 for an overall differential gain
of two. The input op amp has a rail-to-rail input stage, and VOUTCM ≡ (VOUT1 + VOUT2)/2,
both outputs are rail-to-rail, typically swinging to within then combining the expressions for VOUT1 and VOUT2 with
55mV of the rails at each output in this configuration the definitions gives the resulting differential and common
allowing 8VP-P differential outputs from a single 5V rail. mode output voltages:
This provides a simple interface to differential input ADCs
that accept a mid-rail input common mode voltage. VOUTDIFF = 2 • (VIN • (1+RF/RG)–V1 • (RF/RG)–V2) (1)
VOUTDIFF = 2 • (VA • (1+RF /RG) + V1 – V2) (2)
VOUTCM = V2 (3)
6350f

12
 LT6350
OPERATION
Notice that the output common mode voltage is determined sensed signals coming through an op amp running from
simply by the voltage at +IN2. However, since the voltage ±15V rails. The LT6350 can easily interface the high voltage
applied at +IN2 does not affect the voltage at the VOUT1 output, op amp to a 5V ADC by using the inverting gain configuration.
a differential offset voltage will develop for VA = 0 when V1 For a clean interface, three conditions must be met:
does not equal V2. The value of the offset voltage will be
1. VOUTDIFF = 0 when OUTHV is centered at OUTHVNOM.
2 • (V1 – V2), as can be seen in Equation 2. For lowest
differential offset, therefore, the input signal to pin +IN1, 2. VOUT1 = VOUTCM = V2 when OUTHV is centered at
VIN , should be centered around the common mode voltage OUTHVNOM.
applied to pin +IN2. Often this voltage is provided by the 3. Full-scale signals at OUTHV are translated at the
ADC reference output. When the input is so centered and output of the LT6350 into the appropriate full-scale
V1 = V2, Equation 2 reduces to: range for the ADC.
VOUTDIFF = 2 • VA • (1+RF /RG) Applying the above constraints to the design Equations
The simple connection described in the Basic Connections (1) to (3) gives values for the ratio of RF to RG and for
section can be seen as a special case of the general circuit the value of VIN :
in Figure 3 where RF is a short circuit, RG is an open circuit,
and the voltage at VIN is centered around the voltage V2. If RF /RG = (OUTMAX − OUTMIN )/(OUTHVMAX − OUTHVMIN )
differential gain greater than two is needed, the values of RF VIN = V 2 / (1+ (RF / RG )) + (OUTHVNOM )/(1+ (RG /RF ))
and RG can be adjusted in accordance with Equation (2).
Additional information about feedback networks is given +IN1 OP AMP 1 4 OUT1
in the next section and in the Input Amplifier (Op Amp 1) 8 + RINT RINT

Feedback Components section. –IN1 1 –

RF
OP AMP 2
Inverting Gain Connections/Interfacing to High –
RS RG 5 OUT2
Voltage Signals +IN2 2 +
+ VA –
6350 F03

Although the previous examples have assumed the input + VIN + V1 + V2

– – –
signal is applied at +IN1, it is also possible to use the input
op amp in an inverting configuration by fixing the voltage
VIN and applying the input signal at V1 of Figure 3. Using the Figure 3. General Configuration
input op amp in the inverting configuration fixes its input
common mode voltage at the voltage VIN , which allows the OUTMAX

input signal at V1 to traverse a swing beyond the LT6350 V2

supply rails. To avoid unwanted differential offsets in this OUTMIN

+IN1 OP AMP 1 4 OUT1
configuration VIN should be chosen such that: 8 + RINT RINT
+ VIN –
VIN = V2/(1+(RF /RG)) –
+15V OP AMP 2
Then Equation (1) reduces to: –
OUTHV RG RF
5 OUT2
SIGNAL 1 +IN2 2 +
VOUTDIFF = –2 • V1 • (RF/RG)) –IN1 OUTMAX
+ V2
Choosing RF = RG with the input at V1 leads to the gain –15V
OUTHVMAX
– V2
HIGH VOLTAGE OP AMP
of –2 configuration. OUTHVNOM OUTMIN

A practical application for the inverting gain configuration is OUTHVMIN

6350 F04

interfacing a high voltage op amp to a 5V differential SAR

ADC. As seen in Figure 4, an industrial application might have Figure 4. Interfacing to High Voltage Signals

6350f

13
LT6350
APPLICATIONS INFORMATION
INPUT AMPLIFIER (OP AMP 1) CHARACTERISTICS within 1.3V of the positive rail and only Q2/Q3 are active.
Typical total change in input bias current over the entire
Figure 5 shows a simplified schematic of the LT6350’s input
input common mode range is approximately 4μA. These
amplifier. The input stage has NPN and PNP differential
changes in input bias current will generate corresponding
pairs operating in parallel. This topology allows the inputs
changes in voltage across the source and gain-setting
to swing all the way from the negative supply rail to the
resistors. Because the LT6350 input offset current is less
positive supply rail. Both differential pairs are operational
than the input bias current, matching the effective source
when the common mode voltage is at least 1.3V from
and feedback resistances at the input pins will reduce total
either rail. As the common mode voltage swings higher
offset errors generated by changes in input bias current
than V + – 1.3V, current source I1 saturates, and current
in PNP differential pair Q1/Q4 drops to zero. Feedback is and will keep distortion to a minimum.
maintained through the NPN differential pair Q2/Q3, but the
input stage transconductance, gm , is reduced by a factor INPUT AMPLIFIER (OP AMP 1) FEEDBACK
of 2. A similar effect occurs with I2 when the common COMPONENTS
mode voltage swings within 1.3V of the negative rail. A When feedback resistors are used to set gain in op amp 1,
precision, two-point algorithm is used to maintain near care should be taken to ensure that the pole formed by the
constant offset voltage over the entire input range (see feedback resistors and the total capacitance at the inverting
Offset Considerations). input, –IN1, does not degrade stability. For instance, to
Negative input bias current flows into the +IN1 and –IN1 set the LT6350 in a differential gain of +4, RF and RG of
inputs when the input common mode is centered between Figure 3 could be set to 1kΩ. If the total capacitance at
the rails. The magnitude of this current increases when –IN1 (LT6350 plus PC board) were 3pF, a new pole would
the input common mode voltage is within 1.3V of the be formed in the loop response at 106MHz, which could
negative rail and only Q1/Q4 are active. The polarity of the lead to ringing in the step response. A capacitor connected
current reverses when the input common mode voltage is across the feedback resistor and having the same value

V+
+
R1 I1 R2 VBIAS
–
Q11
V– V+
Q5
Q6
DESD1 DESD2 Q1 Q4
V+
+IN1 Q2 Q3 CM
V+
D1 D2 DESD5
DIFFERENTIAL
–IN1 Q9 DRIVE OUT1
GENERATOR
DESD3 DESD4 Q7 DESD6
Q8

V– V+ V–

R3 R4 R5 Q10

I2 D3

V– 6350 F05

Figure 5. Input Amplifier (Op Amp 1) Simplified Schematic

6350f

14
 LT6350
APPLICATIONS INFORMATION
as the total –IN1 parasitic capacitance will eliminate Since the inverting op amp is permanently configured
any ringing or oscillation. Special care should be taken with a noise gain of two, the internal frequency compen-
during layout, including using the shortest possible trace sation has been adjusted such that the GBW product
lengths and stripping the ground plane under the –IN1 of the inverting op amp is higher than that of the input
pin, to minimize the parasitic capacitance introduced at op amp. This allows the closed loop bandwidths of the
that pin. two op amps to match more closely when the LT6350 is
used in the typical differential gain of two configuration
Input bias current induced DC voltage offsets in the input
and increases the closed loop differential bandwidth in
op amp can be minimized by matching the parallel
that application.
impedance of RF and RG to the impedance of the source
that drives +IN1. For example, in the typical gain-of-two The input referred voltage offset of the inverting op amp,
application, when the input op amp is configured as a unity which is equivalent to output common mode voltage
gain buffer, choosing RF = RS will minimize the differential offset, and which could contribute to differential voltage
offset at the output. Since nonzero values of RF will offset in accordance with Equation (2), is trimmed during
contribute to the total output noise, RF may be bypassed manufacture to within ±125μV. To minimize the offset
with a capacitor to reduce the noise bandwidth. contribution of the input bias current into pin +IN2, an
external 499Ω resistor should be installed at pin +IN2
INVERTING AMPLIFIER (OP AMP 2) CHARACTERISTICS for all applications. For more information, see the Setting
The operational amplifier at pins OUT1, +IN2 and OUT2 is The Output Common Mode and Offset Considerations
internally configured as a unity gain inverter and provides sections.
on pin OUT2 an inverted copy of the voltage at pin OUT1.
INPUT PROTECTION
The voltage applied to pin +IN2 sets the output common
mode voltage in accordance with Equation (3). The range There are back-to-back diodes across the + and – inputs
of useful output common mode voltages is limited by the of both LT6350 op amps. The inputs of the LT6350 do not
full-scale input range of A/D converters; values of output have internal resistors in series with the input transistors,
common mode near mid-rail are most useful. The op amp a technique often used to protect the input transistors
used for the inverting buffer therefore differs from the from excessive current flow during a differential overdrive
input op amp primarily in that its input common mode condition. Adding series input resistors would significantly
range is not rail-to-rail: the inverting op amp has an input degrade the low noise performance. Therefore, if the
stage that functions over the input range from V – + 1.5V voltage across the op amp input stages is allowed to
to V + –0.1V. exceed ±0.7V, steady state current conducted though the
protection diodes should be externally limited to ±20mA.
The inverting op amp uses tightly matched, 1k on-chip
The input diodes are rugged enough to handle transient
resistors to set the gain of –1. Note that during output
currents due to amplifier slew rate overdrive or momentary
swings, current flows through these resistors, increasing
clipping without protection resistors.
the total power dissipation of the LT6350. The worst
case increase over quiescent power dissipation can be
found by assuming that the full power supply voltage
appears between OUT1 and OUT2. In this case the extra
power dissipated in the internal feedback network will be
VS2/2kΩ.

6350f

15
LT6350
APPLICATIONS INFORMATION
Driving the input signal sufficiently beyond the power INTERFACING THE LT6350 TO A/D CONVERTERS
supply rails will cause the input transistors to saturate. When driving an ADC, an additional single-pole passive
When saturation occurs, the amplifier loses a stage of RC filter added between the outputs of the LT6350 and
phase inversion and the output tries to invert. Diodes D1 the inputs of the ADC can sometimes improve system
and D2 (Figure 5) forward bias and hold the output within performance. This is because the sampling process of ADCs
a diode drop of the input signal. With very heavy input creates a charge transient at the ADC inputs that is caused
overdrive the output of op amp 1 could invert. To avoid by the switching in of the ADC sampling capacitor. This
this inversion, limit the input overdrive to 0.5V beyond momentarily shorts the output of the amplifier as charge is
the power supply rails. transferred between amplifier and sampling capacitor. For
an accurate representation of the input signal, the amplifier
OUTPUT VOLTAGE RANGE
must recover and settle from this load transient before
The outputs of the LT6350 typically swing to within 55mV the acquisition period has ended. An RC network at the
of the upper and lower supply rails when driving a purely outputs of the driver helps decouple the sampling transient
capacitive load such as at the switched-capacitor input of the ADC from the amplifier reducing the demands on
stage of a SAR ADC. The LT6350 can therefore share a the amplifier’s output stage (see Figure 6). The resistors
single 5V supply with the SAR ADC and drive a full 8VP-P at the inputs to the ADC minimize the sampling transients
differential around an input common mode voltage between that charge the RC filter capacitors.
2.055V and 2.945V. A modest negative supply can be
+5V
added to allow the LT6350 to swing all the way to 0V in VIN +
–
systems where the ADC requires a true 0V-referenced 0.1μF RFILT

signal or when the input common mode range of the ADC

+IN1 SHDN V+ OUT2 CCM
is restricted to be lower than 2.055V. Some SAR ADCs use 5V
+
2V as the input common mode voltage with a full-scale
– RS
input signal range at each input of 0V to 4V. The outputs LT6350 – AIN+
of the LT6350 can swing 7.78VP-P differentially around a + CDIFF ADC

2V common mode voltage, which is a loss of only 0.24dB AIN–

– IN1 +IN2 V– OUT1
RS
of the full-scale range of such ADCs.
RFILT
2V 0.1μF CCM
6350 F06

Figure 6. Driving an ADC

6350f

16
 LT6350
APPLICATIONS INFORMATION
The capacitance serves to provide the bulk of the charge SETTING THE OUTPUT COMMON MODE VOLTAGE
during the sampling process, while the two resistors at the
The output common mode voltage is set by the voltage
outputs of the LT6350 are used to dampen and attenuate
applied to pin +IN2 in accordance with Equation (3). The
any charge injected by the ADC. The RC filter can also be
usable output common mode range is determined by the
used to the additional benefit of band limiting broadband
input common mode range of the inverting op amp and
output noise. See the Noise Considerations section for
is from V – + 1.5V to V +.
more information.
In single supply applications, the optimal common mode
The selection of the RC time constant depends on the ADC; input range to the ADC is often determined by the ADC’s
but generally, longer time constants will improve SNR at reference. If the ADC has an output pin for setting the input
the expense of longer settling time. Excessive settling time common mode voltage, it can be directly tied to the +IN2
can introduce gain errors and can cause distortion if the pin, as long as it is capable of providing the input current
filter components are not perfectly linear. Note also that into +IN2 as listed in the Electrical Characteristics Table.
too small of a resistor will not properly dampen the load Alternatively, +IN2 may be driven by an external precision
transient of the sampling process, prolonging the time reference such as the LT1790.
required for settling. 16-bit applications typically require
a minimum settling time of eleven RC time constants of For lowest offset, the +IN2 pin should see 499Ω of driving
a first order filter. resistance in all applications (see Offset Considerations).
If the driving resistance is nominally less than 499Ω,
Note that the filter’s series resistance also serves to additional resistance can be added to make up the
decouple the LT6350 outputs from load capacitance. The difference. The resistor noise bandwidth can be reduced
outputs of the LT6350 are designed to drive a maximum by bypassing the +IN2 pin to the ground plane with a
of 40pF to ground or 20pF differentially; higher values chip ceramic capacitor of at least 0.1μF (see the Typical
of filter capacitor should always be decoupled with filter Application on the front page). The bypass capacitance
resistors of at least 25Ω. also helps prevent AC signals on this pin from being
High quality resistors and capacitors should be used in inadvertently converted to differential signals.
the RC filter since these components can contribute to
distortion. For lowest distortion, choose capacitors with SHDN
a high quality dielectric, such as a C0G multilayer ceramic If the SHDN pin (Pin 7), is pulled low within 300mV of the
capacitor. Metal film surface mount resistors are more negative supply rail, the LT6350 will power down. The pin
linear than carbon types. is connected through a diode to an internal current source
of 20μA. When pulled below the shutdown threshold, the
20μA current will flow from the pin. If the pin is left open
or pulled high (above V – + 2V), the part will enter normal
active operation, and the current into the pin will be very
small due to the reverse-biased diode.

6350f

17
LT6350
APPLICATIONS INFORMATION
In shutdown, all biasing current sources are shut off, IOS1 OP AMP 1 VOSOUT1
RS +IN1 VOS1 IB1 +
and the output pins, OUT1 and OUT2, each appear as 2
+ RINT RINT

+
–
open collectors with non-linear capacitors in parallel and IB1 –
IOS1
2 –
steering diodes to either supply. Because of the non-linear –IN1 IOS2 OP AMP 2
capacitance, the outputs still have the ability to sink and RF IB2 –
2
–
source small amounts of transient current if driven with IB2 +
IOS2
RG 2 + VOSOUT2
significant voltage transients. The input protection diodes
+ 6350 F07

between +IN1 and +IN2 can still conduct if voltage tran- – VOS2

sients at the input exceed 700mV. All other inputs also +IN2
have ESD protection diodes that can conduct when the R+IN2
applied voltage exceeds 700mV. Using the SHDN feature
to wire-OR outputs together is not recommended.
The turn-on and turn off times between the shutdown and Figure 7. Offset Model
active states are typically 400ns.
The resulting DC offset voltages at pin OUT1 and OUT2
ESD can be calculated:
The LT6350 has ESD protection diodes on all inputs and VOSOUT1 = VOS1•(1+RF/RG) + IB1•(RF-RS•(1+RF/RG))
outputs. The diodes are reverse biased during normal – (IOS1/2)•(RF+RS•(1+RF/RG))
operation. If input pins are driven beyond either supply,
large currents will flow through these diodes. If the current VOSOUT2 = –VOSOUT1 + 2•VOS2 + IB2•(RINT –2•R+IN2)
is transient and limited to 100mA or less, no damage to – (IOS2/2)•(RINT + 2•R+IN2)
the device will occur. Using the above equations and Equations (2) and (3), the
output common mode and output differential mode offsets
OFFSET CONSIDERATIONS can be found. The common mode offset is found to be:
For excellent offset and distortion performance, both the VOSCM = VOS2 + IB2•((RINT/2) – R+IN2) – (IOS2/2)
common mode and differential mode output voltage off- •((RINT/2) + R+IN2)
sets are trimmed during manufacturing.
Figure 7 shows the contributors to DC offset voltage in
the LT6350.

6350f

18
 LT6350
APPLICATIONS INFORMATION
Because the input bias current into op amp 2 is much larger The LT6350 uses very low noise op amps, resulting in a
than the offset current, choosing R+IN2 to be RINT/2 greatly total differential output spot noise at 10kHz of 8.2nV/√Hz
reduces the offset contribution of op amp 2’s input currents when the LT6350 is in the non-inverting gain-of-two
on all units. With R+IN2 = RINT/2, VOSCM reduces to: configuration shown in Figure 2. This is equivalent to the
VOSCM = VOS2 – (IOS2/2) • RINT voltage noise of a 1015Ω resistor at the +IN1 input. For
source resistors larger than about 1k, voltage noise due to
VOSCM is trimmed to within ±125μV with a 499Ω resistor the source resistance will start to dominate output noise.
installed at +IN2. Source resistors larger than about 13k will interact with
The value of VOS1 is trimmed to bring VOSDIFF to ± 125μV. the input current noise and result in output noise that is
Because linear modulation of VOS1 with input common resistor noise and amplifier current noise dominant.
mode could degrade the common mode rejection ratio
in1
specification of op amp 1, and nonlinear modulation of en1 OP AMP 1 eno1
+IN1
VOS1 could cause nonlinear gain error (distortion), VOS1 + RINT
enRINT enRINT
RINT
+
is trimmed to a low constant value over as wide an input –IN1 –
common mode range as possible. A precision, two-point RS in1 in2 eno
trim algorithm is used that results in VOS1 within ±125μV OP AMP 2
enRS
over the input range V – + 1.3V ≤ V+IN1 ≤ V + and VOS1 RF
en2 –
–
+IN2
within ±300μV over the input range V – ≤ V+IN1 ≤ V +. A enRF
+
eno2

negative supply below –1.3V can be used to extend the enRG enR+IN2 in2 6350 F08

input range for which VOS1 is within ±125μV all the way
RG R+IN2
down to ground.
As a result of the trim procedure, the lowest offsets, both
common mode and differential mode, will occur with a Figure 8. Noise Model
499Ω resistor at +IN2. This resistor can be bypassed with
a capacitor to eliminate its noise contribution. The gain- Note that the parallel combination of gain-setting resis-
setting resistor network (RG and RF) impedance should tors RF and RG behaves like the source resistance, RS ,
be matched to that of the source to minimize op amp 1’s from the point of view of noise calculations, and the value
input bias current contributions to the offsets. should be kept below about 1k to avoid increasing the
output noise. Lower-value gain and feedback resistors,
NOISE CONSIDERATIONS
A model showing the sources of output noise in the LT6350
is shown in Figure 8. The total output noise resulting from
all contributors is governed by the equation:
eno = √(4 • [e2n1 + (in1RS)2 + e2nRS](1 + (RF / RG))2 + 4 • (in1RF)2 + 4e2nRF (1 + (RF / RG)) + 4e2n2 + 4e2nR+IN2 +
2e2nRINT + (in2RINT)2 + 4 • (in2R+IN2)2 )

6350f

19
LT6350
APPLICATIONS INFORMATION
RG and RF, will always result in lower output noise at the OUTPUT PHASE BALANCE
expense of increased distortion due to increased loading of
The topology of the LT6350 is that of a noninverting stage
op amp 1. Note that op amp 1 is loaded internally by the 1k
followed by an inverting stage. This topology presents
input resistor to op amp 2, and therefore external loading
a high impedance single-ended input and provides low
should not be much heavier than 1k to avoid degrading
impedance differential outputs. The output of the inverting
distortion performance.
buffer, OUT2, is slightly delayed with respect to the output
When using RF equal to RS (for low offsets) in the gain- of the noninverting buffer, OUT1. In the LT6350, the delay
of-two configuration, wideband noise can be substantially from OUT1 to OUT2 over an input bandwidth from DC to
reduced by bypassing across RF. For lowest output noise the differential f–3dB frequency is a nearly constant 6.8ns,
always bypass at the +IN2 pin with a capacitor of at as shown in the group delay plot in the Typical Performance
least 0.1uF as seen in the Typical Application schematic Characteristics section of this data sheet. The delay is
on the front page. Alternatively, for systems that can equivalent to a small phase offset from the nominal 180°
tolerate output voltage offsets, omitting R+IN2 and RF will phase of the differential outputs. The size of the phase
minimize output noise at the expense of larger output offset grows with frequency. The phase imbalance causes
offset voltage. a small frequency-dependent common mode component
Using a single pole passive RC filter network at the output to appear at the outputs. A practical measure of this effect
of the LT6350, as shown in Figure 6, reduces the output can be found in the balance specification, which is defined
noise bandwidth and thereby increases the signal to noise to be the change in output common mode level caused by
ratio of the system. For example, in a typical system with the presence of an output differential signal:
output signals of 8VP-P, and a signal bandwidth of 100kHz, Balance ≡ ((VOUTDIFF/VIN)/(VOUTCM /VIN))
an RC output filter with RFILT = 100Ω and CDIFF = 6.8nF, The balance of the LT6350 at any frequency, f, can be
slightly increases the output spot noise from 8.2nV√Hz to
approximated from the delay, td, between outputs:
8.4nV√Hz, but will reduce the total integrated noise from
47μV (33MHz noise bandwidth) to 3.6μV (184kHz noise Balance (dB) ≅ 20 • log((4)/(2 • π • f • td))
bandwidth) and improve the SNR from 96dB to 118dB. The approximation is very good from low frequencies up
Keep in mind that long RC time constants in the output to frequencies where the balance approaches 20dB, about
filter can increase the settling time at the inputs of the 10MHz for the LT6350. At DC, the balance is limited by
ADC; incomplete settling can cause gain errors or increase the matching of the internal resistors that set the gain in
apparent crosstalk in multiplexed systems. the inverting buffer. 1% matching of the resistors limits
the balance to 52dB at DC. At frequencies near the f–3dB
point of the differential transfer function, additional phase
lag and gain rolloff also contribute to balance. See the
balance plot in the Typical Performance Characteristics
for a detailed picture of Balance vs Input Frequency.

6350f

20
 LT6350
APPLICATIONS INFORMATION
BOARD LAYOUT AND BYPASS CAPACITORS/DC1538A Stray parasitic capacitance at the –IN1 pin should be kept
DEMOBOARD to a minimum to prevent degraded stability resulting in
For single-supply applications it is recommended that excessive ringing or oscillations. Traces at –IN1 should be
a high quality X5R or X7R, 0.1μF bypass capacitor be kept as short as possible, and any ground plane should
placed directly between the V + and the V – pin; the V – pin be stripped from under the pin and pin traces.
(including the Exposed Pad on the DD8 package) should be Because the outputs operate differentially, load imped-
tied directly to a low impedance ground plane with minimal ances seen by both outputs (stray or intended) should
routing. For split power supplies, it is recommended that be as balanced and symmetric as possible. This will help
additional high quality X5R or X7R, 0.1μF capacitors preserve the balanced operation that minimizes the gen-
be used to bypass pin V + to ground and V – to ground, eration of even-order harmonic distortion in the output
again with minimal routing. Small geometry (e.g., 0603) stage and maximizes the rejection of common mode
surface mount ceramic capacitors have a much higher signals and noise.
self-resonant frequency than do leaded capacitors, and
The DC1538A demoboard has been designed for the
perform best with the LT6350.
evaluation of the LT6350 following the above layout prac-
The +IN2 pin should be bypassed to ground with a high tices. Its schematic and component placement are shown
quality ceramic capacitor of at least 0.1μF, both to reduce in Figures 9 and 10.
the noise bandwidth of the recommended DC offset balance
resistor and to prevent changes in the common mode
reference voltage from being converted into a differential
output signal.

6350f

21
LT6350
APPLICATIONS INFORMATION
+IN2
E1
V+

R8
30.1k

R1 JP5 3
10k +IN2 R15
+IN1 2 EXT
20k
E3 C10 GND SHDN
1μF E2
JP2 V+ JP1
+COUPLING JP3
1 1 SHDN
+IN1CM 3
AC DC +IN2
1 3 2 OUT2
2 ENABLE OUT2FILT
E2
C2
R2 2 C1 C5 E5
J1 1μF SHDN J2
0Ω 1 NC OPT R4 OPT
3 R3 BNC
+IN1 NPO 0Ω NPO
C3 V– 10Ω
BNC V–
R5 C4 OPT
8 7 6 5
OPT OPT
+IN1 SHDN V+ OUT2

LT6350CMS8 GND
+ E7
– C6
R6
GND OPT
– OPT
E6 NPO
+
OUT1FILT

R7 –IN1 +IN2 V– OUT1 E10

J4
JP4 499Ω 1 2 3 4 R9 R10 BNC
–COUPLING 10Ω 0Ω
AC DC C8 C11
–IN1 C9 C7
1 3 0.1μF OPT
E8 OPT OPT
V+ NPO
C12 NPO NPO
J3 R11 2 R14
OPT 1μF OUT1
0Ω OPT
E9
–IN1
R12
BNC R13 C16 0Ω
OPT OPT

GND
E11 V– V+
V– C13 V+
1 1μF
JP6 E12 E13
SINGLE SUPPLY 2

SPLIT SUPPLY 3 C14

V– 0.1μF V+

C23 C21 C15 C17 C18 C19 C20 C22

10μF 10μF 0.1μF 1μF 1μF 0.1μF 10μF 10μF

6350 F09

LT6350 BYPASS

Figure 9. DC1538A Demoboard Schematic

6350f

22
 LT6350
APPLICATIONS INFORMATION

Figure 10. DC1538A Demoboard Layout

6350f

23
LT6350
APPLICATIONS INFORMATION

Figure 11. DC1539A Demoboard Layout

DRIVING THE LTC239X-16 / DC1539A DEMOBOARD 0

f = 20kHz
–10
V + = 5V, V – = –5V
–20
The DC1539A demoboard, shown in Figure 11, has been –30
VOUTDIFF = 7.3VP-P
V+IN2 = 2.05V
developed to demonstrate the interfacing of the LT6350 –40 SNR = 94.9dB
MAGNITUDE (dB)

SINAD = 93.8dB
to the LTC239x-16 family of 16-bit SAR ADCs. –50
–60 THD = 100.2dB
–70 SFDR = 102.2dB
Spurious-free dynamic range of 102.2dB is achievable on –80
the DC1539A as seen in the FFT in Figure 12. –90
–100
–110
–120
–130
–140
0 100 200 300 400 500
FREQUENCY (kHz)
6350 F12

Figure 12. 8192-point FFT LT6350 Driving the

LTC2393-16 on the DC1539A Demoboard

6350f

24
 LT6350
APPLICATIONS INFORMATION
100kHz, 3RD-ORDER BUTTERWORTH FILTER 20

The LT6350 can be configured as a single-ended to 0

differential filter incorporating feedback from the inverting
–20
output. Figure 13 shows the schematic of the configuration

GAIN (dB)
with values giving a 3rd Order Butterworth characteristic –40
having a 100kHz –3dB point with a differential gain of four.
Figure 14 shows the filter output response to 10MHz. As –60

an option, to match the source impedance and preserve

–80
the low DC errors of the LT6350, connect a 2.10k series
resistor at +IN1. To reduce the resistor noise, the +IN1 –100
1K 10K 100K 1M 10M
pin can be bypassed with a 0.1μF capacitor. For similar FREQUENCY (Hz)
topologies please consult the LT1567 data sheet and 6350 F14

design guide. Figure 14. 100KHz, 3rd Order Butterworth Filter Response

5V
Low Noise, Low Power 1MΩ Single Supply Photo-
2.5V 0.1μF VOUT2 diode Differential Output Transimpedance Amplifier
8 7 3 5
+IN1 SHDN V+ OUT2 The Typical Application on the back page shows the LT6350
+ applied as a differential output transimpedance amplifier.
– The LT6350 forces the BF862 ultralow noise JFET source
LT6350 –
to 3V, with R2 ensuring that the JFET has an IDRAIN of 1mA.
+
The JFET acts as a source follower, buffering the input of
– IN1 +IN2 V– OUT1
the LT6350 and making it suitable for the high impedance
1 2 6 4
VOUT1 feedback element R1. The BF862 has a minimum IDSS of
1000pF
10mA and a pinchoff voltage between –0.3V and –1.2V.
499Ω 0.1μF
The JFET gate and OUT1 therefore sit at a point slightly
2.5V C5 higher than one pinchoff voltage below 3V, about mid-
R3 1000pF
174Ω 2210Ω 523Ω supply at 2.5V.
+ VIN 0.01μF 4750Ω When the photodiode is illuminated, the current must come
–
6350 F13 from OUT1 through R1 as in a normal transimpedance
amplifier. Amplifier output noise density is dominated at
Figure 13. 100KHz, 3rd Order Butterworth Filter low frequency by the 130nV/√Hz of the feedback resistor,
rising to 210nV/√Hz at 1MHz. Note that because the JFET
has a high gm, approximately 1/30Ω, its attenuation looking
into R2 is only about 1%. The closed-loop bandwidth
using a 3pF photodiode was measured at approximately
1.35MHz. With the output taken differentially, the gain and
the noise are both doubled.

6350f

25
LT6350
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)

0.675 ±0.05

3.5 ±0.05 1.65 ±0.05

2.15 ±0.05 (2 SIDES)

PACKAGE
OUTLINE

0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115 0.38 ± 0.10
TYP
5 8

3.00 ±0.10 1.65 ± 0.10

(4 SIDES) (2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD) DFN 1203

4 1
0.200 REF 0.75 ±0.05 0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE

6350f

26
 LT6350
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)

0.889 ± 0.127
(.035 ± .005)

5.23
(.206) 3.20 – 3.45
MIN (.126 – .136)

3.00 ± 0.102
0.42 ± 0.038 0.65 (.118 ± .004) 0.52
(.0165 ± .0015) (.0256) (NOTE 3) 8 7 6 5 (.0205)
TYP BSC REF
RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102
4.90 ± 0.152
DETAIL “A” (.118 ± .004)
0.254 (.193 ± .006)
(NOTE 4)
(.010)
0° – 6° TYP
GAUGE PLANE
1 2 3 4
0.53 ± 0.152
(.021 ± .006) 1.10 0.86
(.043) (.034)
DETAIL “A” MAX REF
0.18
(.007)
SEATING
PLANE 0.22 – 0.38 0.1016 ± 0.0508
(.009 – .015) (.004 ± .002)
0.65 TYP MSOP (MS8) 0307 REV F
(.0256)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6350f

27
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT6350
TYPICAL APPLICATION
Low Noise, Low Power 1MΩ Single Supply Photodiode Transimpedance Amplifier
5V

20k
3V 5V

0.1μF 0.1μF VOUT2

4.99k
VOUT1
2.5V +IN1 SHDN V+ OUT2 500mV/DIV
24.9k + VOUT2
500mV/DIV
–
LT6350 –
LIGHT
+ ASSERT
IPD PHILIPS/NXP
OSRAM BF862
– IN1 +IN2 V– OUT1
SFH213
6350 TA04

2.5V 0.1μF
R1
VOUTDIFF = ~ ±200mV + IPD • 2MΩ
1M VOUT1 BW = 1.35MHz
6350 TA03
R2
3.01k

0.1pF

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6350f

LT 0110 • PRINTED IN USA

28 Linear Technology Corporation

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