Veek-Mt2s User Manual
Veek-Mt2s User Manual
Introduction
The VEEK-MT2S (Video and Embedded Evaluation Kit - Multi-touch, Second Edition for SoC
FPGA) is a comprehensive design environment with everything embedded developers need to
create processing-based systems. The VEEK-MT2S delivers an integrated platform including
hardware, design tools, and reference designs for developing embedded software and hardware
platforms in a wide range of applications. The fully integrated kit allows developers to rapidly
customize their processor and IP to best suit their specific application. The VEEK-MT2S is
assembled by the DE10-Standard FPGA main board and MTLC2 module. The DE10-Stanard FPGA
board uses Cyclone® V SoC FPGA. The MTLC2 module is an 800x480 color LCD with touch
panel which natively supports five point multi-touch and gestures. An 8-megapixel digital image
sensor, ambient light sensor, and 3-axis accelerometer are also included in the module.
The all-in-one embedded solution offered on the VEEK-MT2S, in combination of a LCD touch
panel and digital image module, provides embedded developers the ideal platform for multimedia
applications with unparalleled processing performance. Developers can benefit from the use of an
FPGA-based embedded processing system such as mitigating design risk and obsolescence, design
reuse, lowering bill of material (BOM) costs by integrating powerful graphics engines within the
FPGA.
For SoC reference design in Linux for touch-screen display, please refer to the “Programming
Guide for Touch-Screen Display” document in the System CD of VEEK-MT2S.
Cyclone V SE SoC—5CSXFC6D6F31C6N
o Dual-core ARM Cortex-A9 (HPS)
o 110K programmable logic elements
o 5,140 Kbits embedded memory
o 6 fractional PLLs
o 2 hard memory controllers
Configuration Sources
o Quad serial configuration device – EPCS128 for the FPGA
o On-board USB Blaster II (normal type B USB connector)
Memory Devices
o 64MB (32Mx16) SDRAM for the FPGA
o 1GB (2x256MBx16) DDR3 SDRAM for the HPS
o microSD card socket for the HPS
Peripherals
o Two USB 2.0 Host porsts (ULPI interface with USB type A connector)
o UART to USB (USB Mini B connector)
o 10/100/1000 Ethernet
o PS/2 mouse/keyboard
o IR emitter/receiver
o I2C multiplexer
Connectors
o One HSMC expansion header
o One 40-pin expansion header
o One 10-pin ADC input header
One LTC connector (one Serial Peripheral Interface (SPI) master ,one I2C bus, and one
GPIO interface)Display
o 24-bit VGA DAC
o 128x64 dot Mono Graphic LCD with backlight for HPS
Audio
o 24-bit CODEC, line-in, line-out, and microphone-in jacks
Video Input
o TV decoder (NTSC/PAL/SECAM) and Video-in connector
ADC
o Fast throughput rate: 1 MSPS
o Channel number: 8
o Resolution: 12-bit
VEEK-MT2S User Manual 4 www.terasic.com
April 7, 2017
o Analog input range : 0 ~ 2.5 V or 0 ~ 5V by selecting the RANGE bit in the
control register
Sensor
o G-sensor for the HPS
Power
o 12V DC input
1. Please make sure the microSD card is inserted to the microSD card socket (J11) onboard.
2. Set MSEL[4:0] = 01010, as shown in Figure 1-3.
3. Plug in a USB keyboard to the USB host on the DE10-Standard board. (Optional)
4. Plug in the 12V DC power supply to the DE10-Standard board.
5. Power on the DE10-Standard board.
6. The LXDE Desktop will appear on the LCD display.
7. Use the touch-screen to select the system menu, as shown in Figure 1-4.
Terasic Inc.
Tel: +886-3-575-0880
Email: [email protected]
VEEK-MT2S User Manual 7 www.terasic.com
April 7, 2017
VEEK-MT2S User Manual 8 www.terasic.com
April 7, 2017
Chapter 2
Architecture
This chapter provides information regarding the features and architecture of VEEK-MT2S. The kit
is composed of DE10-Standard mainboard and MTLC2 (Multi-Touch LCD with Camera, second
edition) module. The MTLC2 module is connected to a HSMC expansion header on DE10-Standard
board through an HSMC Flex Cable. For more information about the DE10-Standard mainboard,
please refer to the user manual in DE10-Standard System CD, which can be downloaded from the
link:
http://de10-standard.terasic.com/cd
Using VEEK-MT2S
This chapter provides information on how to control the Multi-touch LCD with Camera Module
Second Edition (MTLC2) hardware, which includes the definition of HSMC interface, LCD control,
and multi-touch control signals, 8-mega pixel camera, ambient light sensor and 9-axis sensor.
http://de10-standard.terasic.com/cd
The 5-point touch chip used in the VEEK_MT2S is I2C interface. Developers can use generic I2C
master controller to communicate with the touch chip. For details information about the touch chip,
please refer to the control panel datasheet located in the folder Datasheet/lcd in the VEEK-MT2S
System CD. For a Nios II project, a c-code library is provided in the multi_touch2.c files.
To display images on the LCD panel correctly, the RGB color data along with the data enable and
clock signals must act according to the timing specification of the LCD touch panel as shown in
Table 3-1 and
Table 3-2.
Table 3-3 gives the pin assignment information of the LCD touch panel.
named VM149C VCM Driver IC.pdf also can be found in the System CD.
FPGA also can read/write MIPI Decoder through a I2C bus (MIPI_I2C_SDA / MIPI_I2C_SCL ;
I2C device address is 0x1C), which is different from the camera module I2C bus. On the
VEEK-MT2S board, MIPI Decoder can output clocks to the MIPI camera and FPGA board. So in
the demonstrations, most of them show how to control IC PLL parameters as well as others.
Detailed clock functions are described as below.
Clock Tree
Figure 3-3 is the VEEK-MT2S board’s camera clock tree block diagram. MIPI Decoder PLL
receives FPGA Reference Clock (MIPI_REFCLK) and outputs Clock to Camera sensor (MCLK), at
the same time, MIPI Decoder PLL will also output a parallel port clock (MIPI_PIXEL_CLK) and
feedback to the FPGA to deal with parallel data.
In the provided demonstrations, MIPI_REFCLK is set to 20MHz. The FPGA transmits this clock to
the VEEK-MT2S’s MIPI Decoder PLL through the HSMC connector. No matter how much the
camera resolution is, the MCLK fixed output is 25MHz. According to the output resolution,
MIPI_PIXEL_CLK can be set as 25MHz for 640x480@60fps and 50MHz for 1920x1080@15fps.
For more MIPI Decoder PLL setting details, please refer to TC358746AXBG_748XBG_rev09.pdf
"Chapter 5: Clock and System" or refer to Terasic camera or vip_camera demonstrations.
Gyroscope
The MPU-9250 consists of three independent vibratory MEMS rate gyroscopes, which detect
rotation about the X-, Y-, and Z- Axes. When the gyros are rotated about any of the sense axes, the
Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is
amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate.
This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to
sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±250,
±500, ±1000, or ±2000 degrees per second (dps). The ADC sample rate is programmable from
8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters
enable a wide range of cut-off frequencies.
Accelerometer
The MPU-9250’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration
along a particular axis induces displacement on the corresponding proof mass, and capacitive
sensors detect the displacement differentially. The MPU-9250’s architecture reduces the
accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device
is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The
accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply
voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs. The full scale
range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.
Magnetometer
The 3-axis magnetometer uses highly sensitive Hall sensor technology. The magnetometer portion
of the IC incorporates magnetic sensors for detecting terrestrial magnetism in the X-, Y-, and Z-
Axes, a sensor driving circuit, a signal amplifier chain, and an arithmetic circuit for processing the
signal from each sensor. Each ADC has a 16-bit resolution and a full scale range of ±4800 μT.
Communication with all registers of the device is performed using either I2C at 400kHz or SPI at
1MHz. For applications requiring faster communications, the sensor and interrupt registers may be
read using SPI at 20MHz. For more detailed information of better using this chip, please refer to its
datasheet which is available on manufacturer’s website or under the /datasheet folder of the system
CD. Table 3-5 gives the pin assignment information of the LCD touch panel. For more detailed
information of better using this chip, please refer to its datasheet which is available on
manufacturer’s website or under the /datasheet folder of the system CD.
Table 3-5 contains the pin names and descriptions of the MPU-9250.
Signal Name FPGA Pin No. Description I/O Standard
I2C Slave Address LSB (AD0);
MPU_AD0_SDO K27 2.5V
SPI serial data output (SDO)
MPU_CS_n F28 Chip select (SPI mode only) 2.5V
Table 3-6 contains the pin names and descriptions of the ambient light sensor module.
Signal Name FPGA Pin No. Description I/O Standard
LSENSOR_ADDR_SEL J25 Chip select 2.5V
LSENSOR_INT L28 Interrupt output 2.5V
LSENSOR_SCL J26 Serial Communications Clock 2.5V
LSENSOR_SDA L27 Serial Data 2.5V
Linux BSP
This chapter describes how to use the Linux BSP (Board Support Package) provided by Terasic.
Users can develop touch-screen GUI program easily with the BPS including QT 5.3.1 library.
The Linux image files are implemented on HPS/ARM and the Quartus project is implemented on
FPGA/Qsys. The Linux image files include the pre-built Linux system. Users can create a Linux
bootable microSD card with the image files. The Quartus project includes the controller for VGA
display and the touch-screen controller for touch-screen panel.
The BSP includes not only precompiled QT library and touch-screen library in the Linux image
files, but also the document that show how to cross-compile these libraries, as well as to develop
touch-screen GUI program based on these libraries.
Figure 4-2 shows a screenshot of LXDE desktop after booting. The LXDE desktop is displayed on
the LCD touch panel. This image file also includes the QT library and touch-screen library. To
perform these demos, users need to double click the icons of the demos on desktop.
VGA display
Touch-screen
HPS component
The VGA display part is designed to display the Linux console or desktop on the LCD touch panel.
Altera Video and Image Processing (VIP) suite is used to implement this function. The Linux frame
buffer driver fills up the DDR3 with data to be displayed, and the VIP frame-reader component
reads the data from the DDR3 in a DMA manner. The video data is streamed into the VIP Clocked
Video Output component. Finally, the VIP Clocked Video Output component drives the VGA DAC
chip to display the video data.
An I2C master controller in Qsys is used to communicate with the touch-screen panel. The
component interfaces with the touch-screen panel through I2C protocol.
The HPS communicate with the FPGA through AXI bridge. The components in FPGA are mapped
into user memory of the linux system through memory-mapped interface. Then the user software
can access the IPs in FPGA portion. The Quartus project is located under the folder
“Demonstration/SoC_FPGA/ControlPanel/Quartus” in the VEEK-MT2S system CD.
VEEK-MT2S User Manual 20 www.terasic.com
April 7, 2017
4.4 QT Libraries
Users can develop touch-screen GUI program based on the QT library. For more information,
please refer to the document “VEEK-MT2S_Control_Panel.pdf” included in the VEEK-MT2S
system CD. The precompiled QT libraries can be found from
“Demonstration/SoC_FPGA/ControlPanel/lib/qt5.5.1_for_intel_soc.tar.gz”
FPGA Demonstration
This chapter gives detailed description of the provided bundles of exclusive demonstrations
implemented on VEEK-MT2S. These demonstrations are particularly designed (or ported) for
VEEK-MT2S, with the goal of showing the potential capabilities of the kit and showcase the unique
benefits of FPGA-based systems such as reducing BOM costs by integrating powerful graphics and
video processing circuits within the FPGA. The camera demonstration is a RTL only code, and the
other demonstrations are incorporated with VIP (Video and Image and Nios II processor).
5.1 Painter
This section shows how to implement a painter demo on the Multi-touch LCD module based on
Altera Qsys tool and the Video and Image Processing (VIP) suite. It demonstrates how to use
multi-touch gestures and resolution. The GUI of this demonstration is controlled by the Nios II
processor.
Operation Description
Figure 5-1 shows the Graphical User Interface (GUI) of Painter demo. The GUI is classified into
four separate areas: Painting Area, Gesture Indicator, Clear Button, and Color Palette. Users can
select a color from the color palette and start painting in the paint area. If a gesture is detected, the
associated gesture symbol will be shown in the gesture area. To clear the painting area, click the
“Clear” button.
For multi-touch processing, when touch activity occurs, an I2C Controller IP is used to retrieve
serial data from the I2C interface, the associated touch information including multi-touch gestures
and 5 Point touch coordinates can be calculated through the data in NIOS II. Note: the license for
this IP must be installed before compiling the Quartus II project including this encrypted
component.
Figure 5-5 shows the system generic block diagram of painter demonstration.
Demonstration Setup
The first function is using I2C bus to write D8M Voice Coil Motor (VCM) driver IC register,
and control the camera lens’ movements to perform image focusing. VCM driver IC
register (I2C Slave Address =0x18) shares I2C bus with camera module. The other
function is doing the current image high frequency component statistic. When the VCM
drives the camera lens’ movement, a real-time statistics of image high-frequency sum will
be done in every step of the moving. Finally, the lens will move to a position which has
the largest number of high frequency to complete the automatic focus operation. Focus
area can be selected by SW3. There are two options:
Once you set SW3 to a value (0 or 1) and press KEY3 one time, the automatic focus operation
will be performed in the selected area.
Resolution: 800x480
VEEK-MT2S User Manual 27 www.terasic.com
April 7, 2017
Pixel Data: RAW10
Frame Rate: 60 fps
Bin Mode: 1 (no bin mode: x2, x4 will out of full-size)
Project Information
Item Description
Tool Quarts II Prime 16.1.1 Standard Edition
Quartus Project directory Demonstration\FPGA\Camera
FPG bit stream file Camera.sof
Demo batch folder Camera\demo_batch
Demonstration Setup
Connect the DE10-Stanrad board (J13) to the host PC with a USB cable and install the
USB-Blaster II driver if necessary
Plug the 12V adapter to VEEK-MT2S Board.
Power on the VEEK-MT2S board.
Load the bit stream into FPGA by executing the batch file ‘test.bat’ under
Camera\demo_batch\ folder
The system enters the FREE RUN mode automatically (See Figure 5-7).
LED0~1 light up, stand the settings of MIPI-BRIDGE I2C and Camera I2C are completed.
LED7~9 blink in 1Hz, stand MIPI-PIXEL-CLOCK, MIPI-REF-CLOCK and
MT2-PIXEL-CLOCK are generated correctly.
HEX1~0 decimal number “60” stands Camera capturing frame rate is 60Hz
Camera capturing image displays on LCD, if the LCD image is fuzzy, please press Key3
one time again (will perform the focus operation again). Users can switch SW3 to “1”
(there will be a yellow box on image, see Figure 5-8), then, press SW3 one time again, the
middle area focus operation will be performed.
Table 5-1 summarizes the functional keys and details of each LED status.
Figure 5-8 Area Focus Mode of the VEEK-MT2S RTL camera demonstration
These functions allow you to fully integrate common video functions with video interfaces,
processors, and external memory controllers. The example design uses an Altera Cyclone® V SE
SoC 5CSXFC6D6F31C6N featured on the VEEK-MT2S.
A video source is input through the CMOS sensor on VEEK-MT2S which generates a digital output
in RGB format. A number of common video functions are performed on this input stream in the
FPGA. These functions include clipping, chroma resampling, motion adaptive deinterlacing, color
space conversion, picture-in-picture mixing, and polyphase scaling.
The input and output video interfaces on the VEEK-MT2S are configured and initialized by
software running on a Nios® II processor. Nios II software demonstrates how to control the clocked
video input, clocked video output, and mixer functions at run-time is also provided. The video
system is implemented using the QSYS system level design tool. This abstracted design tool
provides an easy path to system integration of the video processing data path with a NTSC or PAL
video input, VGA output, Nios II processor for configuration and control. The Video and Image
Processing Suite MegaCore functions have common open Avalon-ST data interfaces and Avalon
Memory-Mapped (Avalon-MM) control interfaces to facilitate connection of a chain of video
functions and video system modeling. In addition, video data is transmitted between the Video and
Image Processing Suite functions using the Avalon-ST Video protocol, which facilitates building
run-time controllable systems and error recovery.
For the objective of a better visual effect, the CMOS sensor is configured with autofocus function.
The autofocus function works at first when the demonstration starting up.
Note: The focus driver IC (VCM149C) in the camera module is also configured by the Terasic
auto-focus IP through its own I2C master controller. Users must make sure there is only one I2C
master used one at a time.
In this demonstration, the OV9965 Image sensor is configured to generate a serial 800x480 pixel
Bayer pattern. The MIPI-decoder translates the serial Bayer pattern data into parallel Bayer pattern
data. The Terasic CAMERA IP is used to convert the 800x480 Bayer Pattern into an 800x480 RGB
Altera VIP video stream. The Terasic Autofocus is used to automatically find the proper focus
position for the camera lens. The VIP Frame Buffer is used to store the complete video frame for
display later. The VIP Frame Buffer uses the external SDRAM as video memory. The Clock Video
Output IP will translate the video stream to an 800x480 VGA format so the video can be displayed
on the VGA monitor.
Quartus Project
Item Desciption
Tool Quarts II Prime 16.1.1 Standard Edition
Quartus Project directory Demonstration\FPGA\vip_camera
FPG bit stream file DE10_Standard.sof
Nios II Workspace vip_camera\software
Nios binary file vip_camera.elf
Demo batch folder vip_camera\demo_batch
Demonstration Setup
Nios II Processor SDRAM VIP: Frame Reader VIP: Clocked Video Output LCD
Panel..
In the NIOS II program, the GUI (graphic user interface) is implemented in the gui_gsensor.cpp.
The MPU9250 class, implemented in the MPU9250.cpp/.h is used to retrieve accelerometer
information from the MPU9250. The member function initialize of the MPU9250 class should be
called first before calling any other member function. In this demonstration, the member function
getMotion9 is called to get the gravity value of X/Y/Z. The light_sensor.cpp/h includes the library
which allows it to communicate with the APDS-9300 Miniature Ambient Light Photo Sensor.
Before reading the light level information, call function Light_Init first to initialize the sensor
APDS-9300. The function Light_GetID is designed to get the chip ID of APDS-9300. Function
Light_Get_ADCData0 and Light_Get_ADCData1 are designed to get the two ADC values in
APDS-9300
Project Information
VEEK-MT2S User Manual 34 www.terasic.com
April 7, 2017
Item Description
Tool Quarts II Prime 16.1.1 Standard Edition
Quartus Project directory Demonstration\FPGA\G_Sensor
FPGA bit stream file G_Sensor
Nios II Workspace G_Sensor\software
Nios binary GUI_APP.elf
Demo batch folder G_Sensor\demo_batch
Demonstration Setup
1. Execute the test.bat under the demo_batch folder to configure FPGA and launch the Nios
II program (Note*).
2. Tilt the VEEK-MT2S to all directions, and you will find that the angle of the g-sensor and
value of light sensor will change. When turning the board from -80º to -10º and from 10º
to 80º in Y-axis, or from 10ºto 80º and from -80º to -10º in Y-axis, the image will invert.
Figure 5-13 shows the demonstration in action. The values measured from the ambient
light sensor is displayed on the top left of the GUI.
Operation Description
Figure 5-14 shows the graphic interface of the e-compass demonstration. The left area show the
gravity information measured by accelerometer in the MPU9250. Also, a bubble level is shown on
the LCD. The center of LCD panel shows the e-compass. The north direction and magnetic field
information are shown on the LCD panel. The Calibration button is used to start the calibration
process for the e-compass.
Nios II Processor SDRAM VIP: Frame Reader VIP: Clocked Video Output LCD Panel.
In the NIOS II program, the graphic interface is implemented in the gui_gsensor.cpp. The
MPU9250 class (implemented in MPU9250.cpp.h) is used to retrieve accelerometer information
from the MPU9250. The member function initialize should be called before calling any other
member functions. In this demonstration, the member function getMotion9 is called to get the
gravity value of X/Y/Z. The function Light_Init is designed to initialize the sensor APDS-9300. The
function Light_GetID is designed to get the chip ID of APDS-9300. The Function
Light_Get_ADCData0 and Light_Get_ADCData1 are designed to get the two ADC values in
APDS-9300.
The section introduces the method to calculate the heading angle based on the values measured by
accelerometer and magnetometer in this demonstration. If the compass is on a flat surface, then
heading angle can be calculated with the following formula:
arctan(Xh/Yh)
where Xh and Yh are the magnetic field in X and Y directions. If the compass is not on a flat surface,
the Xh and Yh can be calculated with the following formula:
Yh = my*soc(roll) + mz*size(roll)
Where mx/my/mz are the measured valued by the magnetometer in the MPU9250. The pitch and
VEEK-MT2S User Manual 37 www.terasic.com
April 7, 2017
roll can be calculated by the gravity valued measured by the accelerometer in the MPU9250.
The measurement of magnetic field will be subjected to distortion. There are two categories of these
distortions: the hard iron distortions and the soft iron distortions. The hard iron errors refer to the
presence of magnetic fields around the sensor (magnets, power supply wires) and are related to the
measurement offset errors, while the soft iron errors refer to the presence of ferromagnetic materials
around the sensor, which skew the density of the Earth's magnetic field locally and are related to
scaling offset errors. In other words, to get the correct magnetometer data you should calibrate it
first. In this demonstration, we corrected the magnetic field with the following formula:
Xcalibrated = X – Xoffset
Ycalibrated = Y – Yoffset
Zcalibrated = Z – Zoffset
Where Xoffset, Yoffset and Zoffset are the average value of X/Y/Z magnetic field, defined as:
Where Xmax/Xmin/Ymax/Ymin/Zmax/Zmin are the maximal and minimal value of X/Y/Z values reported
by magnetometer in the MPU9250 while the VEEK-MT2S is rotated in its X/Y/Z axes as shown in
Figure 5-16.
Demonstration Setup
1. Execute the test.bat under the demo_batch folder to configure FPGA and launch the NIOS
II program (Note*).
2. The E-Compass will be displayed on the LCD panel.
3. Touch the Calibration button to start the calibration process. When the button is touched,
the LCD content will be changed as shown in Figure 5-17.
4. Rotate VEEK-MT2S in X/Y/Z axis individually. Touch the Finished button when rotation
is done.
5. When the Finished button is touched, the LCD content is changed as shown in Figure
5-18. The minimal, maximal, and average values are displayed in the LCD. If the value is
valid, please touch Yes button to apply the calibration result.
6. Keep the VEEK-MT2S on as flat a surface as possible by watching the bubble level on
the LCD. The e-compass will show the accuracy North direction on the LCD.
Note:
HFP-FPGA Demonstration
Although HPS and FPGA can operate independently, they are tightly coupled via a high-bandwidth
system interconnect built from high-performance ARM AMBA® AXITM bus bridges. Both FPGA
fabric and HPS can access to each other via these interconnect bridges. This chapter provides
demonstrations on how to achieve superior performance and lower latency through these
interconnect bridges when comparing to solutions containing a separate FPGA and discrete
processor.
The ADC9300 demo shows how to use the Linux application and to use the I2C driver to
communicate with the ADC9300 chip on the FPGA sit. The MPU9250 demo shows how the Linux
application is used via the SPI driver to communicate with the MPU9250 chip on FPGA sit. The
System CD also controls a more complex demo, called “Control Panel”. The Control Panel is a QT
based GUI application. It is a collection for controlling various hardware on VEEK-MT2S. For
details about the demo, please refer to the document VEEK-MT2S_Contrl_Panel.pdf.
6.1 HPS_FPGA_ADC9300
This section shows how to implement a Linux console application to access the ADC9300 light
sensor on the FPGA side. In the Linus/HPS site, I2C driver is used. In the FPGA side, the I2C
opencore controller is used.
System Description
Figure 6-1 shows the system block diagram of hps_fpga_adc9300 demonstration. In the FPGA side,
the Qsys component i2c_opencore is used to control the ADC9300 sensor through the I2C interface.
The I2C driver drives the i2c_opencore controller through the Lightweight HPS-to-FPGA bridge.
The hps_fpga_adc9300 uses I2C driver to access the registers in the ADC9300 to get measured
lighting values.
The hps_fpga_adc9300 software application is implemented by C++ code. Figure 6-2 shows the
software stack of the software application. The main program is implemented in the main.cpp file.
ADC9300 class is designed to provide relative functions for ADC9300 chip and it is implemented
in adc9300.cpp.
Figure 6-3 shows the declaration of the ADC9300 class. In the constructor, a file name “/dev/i2c-5”
should be given. In the VEEK-MT2S Desktop Linux Image, the I2C driver file “/dev/i2c-5” is
mapped to the i2c_opencore controller for ADC9300 chip. Before reading the measured value,
developers should call Set_PowerSwitch function to turn the power of ADC9300. Then, call
Get_ADCData0 and Get_ADCData1 function to get measured lighting value for Visible+IR and
IR, in respectively.
In the ADC9300 class, the ADC9300 register accessing functions are implemented as protected
member functions REG_READ and REG_WRITE. Figure 6-3Figure 6-4 shows the code body of
these two function. The standard file read and write are used to implement these two functions.
Demonstration Setup
Project Information
Quartus project:
Item Description
Compile Tool Quartus Prime 16.1.2 Standard Edition
Project directory Demonstration\SoC_FPGA\ContorlPanel\Quartus
Bin file soc_system.rbf
System Description
Figure 6-1 shows the system block diagram of hps_fpga_mpu9250 demonstration. In the FPGA
side, the Qsys component i2c_opencore is used to control the MPU9250 sensor through the I2C
interface. The I2C driver drives the i2c_opencore controller through the Lightweight HPS-to-FPGA
bridge. The hps_fpga_mpu9250 uses I2C driver to access the registers in theMPU9250 chip.
The hps_fpga_mpu9250 software application is implemented by C++ code. Figure 6-8 shows the
software stack of the software application. The main program is implemented in the
hps_fpga_mpu.cpp file. MPU9250 class is designed to provide relative functions for MPU9250
chip and it is implemented in MPU9250.cpp.
Figure 6-3 shows the member function declaration of the MPU9250 class. Before reading the
measured value, developers should call initialize function to initialize the MPU9250 chip. Then,
call GetMotion9 function to get measured 9-asix value.
In the MPU9250 class, the MPU9250 register accessing functions are implemented as public
member functions WriteReg and ReadReg. Figure 6-10 shows the code body of these two
functions. In the code body of these two functions, a SPI driver file name “/dev/spidev32766.0” is
used. In the VEEK-MT2S Desktop Linux Image, the file name is mapped to the SPI controller for
MPU9250 chip. The SPIdev class is used to implement low-level translation. The SPIdev class is
Demonstration Setup
Project Information
Item Description
Compile Tool SoC Embedded Design Suite (ESD) 16.1.0.196
Project directory Demonstration\SoC_FPGA\hps_fpga_mpu9250
Bin file hps_fpga_mpu9250
Main file hps_fpga_mpu9250.cpp
Appendix