CAO Assignment-I

Module-1
1. Consider having a program that runs in 50 s on computer A, which has a 500 MHz clock. We
would like to run the same program on another machine, B, in 20 s. If machine B requires 2.5
times as many clock cycles as machine A for the same program, determine the clock rate (in
MHz) which machine B must has.

2. Suppose that we have two implementations of the same instruction set architecture. Machine
A has a clock cycle time of 50 ns and a CPI of 4.0 for some program, and machine B has a
clock cycle of 65 ns and a CPI of 2.5 for the same program. Which machine is faster and by
how much?

3. A benchmark program is run on a 40 MHz processor. The executed program consists of

100,000 instruction executions, with the following instruction mix and clock cycle count:

Determine the effective CPI, MIPS rate, and execution time for this program.

4. A compiler designer is trying to decide between two code sequences for a particular machine.
The hardware designers have supplied the following facts:

For a particular high-level language, the compiler writer is considering twosequences that
require the following instruction counts:

What is the CPI for each sequence? Which code sequence is faster? By howmuch?

5. Consider a machine with three instruction classes and CPI measurements as follows:
Suppose that we measured the code for a given program in two differentcompilers and
obtained the following data:

Assume that the machine’s clock rate is 500 MHz. Which code sequence willexecute faster
according to MIPS? And according to execution time?

6. Early examples of CISC and RISC design are the VAX 11/780 and the IBM RS/6000,
respectively. Using a typical benchmark program, the following machine characteristics
result:

The final column shows that the VAX required 12 times longer than the IBM measuredin CPU
time.
a. What is the relative size of the instruction count of the machine code for thisbenchmark
program running on the two machines?
b. What are the CPI values for the two machines?

7. Consider a machine for which a speedup of 30 is possible after applying an enhancement. If

under certain conditions the enhancement was only possible for 30% of the time, what is the
speedup due to this partial application of the enhancement?

8. The hypothetical machine of Figure 1.9 also has two I/O instructions: (Refer Unit-I word
file)
0011 = Load AC from I/O
0111 = Store AC to I/O
In these cases, the 12-bit address identifies a particular I/O device. Show the programexecution
(using the format of Figure 1.10) for the following program:
1. Load AC from device 5.
2. Add contents of memory location 940.
3. Store AC to device 6.
Assume that the next value retrieved from device 5 is 3 and that location 940 containsa value of
2.

9. In a 16-bit instruction the size of address field is 7 bits. The computer uses expanding opcode
technique. It has 2, two address instructions and 250 one address instruction. How many Zero
address instructions can be formulated?

10. An instruction is stored at location 300 with its address field at location 301. The address
field has the value 400. A processor register R1 contains the number 200. Evaluate the
effective address if the addressing mode of the instruction is (i) Direct (ii) Immediate (iii)
Relative (iv) Register indirect (v) Index with R1 as the index register

11. Consider the following program segment for a hypothetical CPU having three user registers
R1, R2 and R3.
Instruction Operation Instruction Size
(in Words)
MOV R1,5000 R1 ← 2
Memory[5000]
MOV R2, (R1) R2 ← Memory[(R1)] 1
ADD R2, R3 R2 ← R2 + R3 1
MOV 6000, R2 Memory[6000] ← 2
R2
HALT Machine halts 1
Let the clock cycles required for various operations be as follows: Register to/ from memory
transfer: 3 clock cycles; ADD with both operands in register: 1 clock cycle; Instruction fetch and
decode : 2 clock cycles per word. Compute the total number of clock cycles required to execute
the program.
12. Consider the byte addressable memory unit of a computer has 256 K words of 32 bits each.
The computer has an instruction format with 4 fields:
1. An opcode field.
2. A mode filed to specify 1 of 7 addressing modes.
3. A register address field to specify 1 of 60 registers.
4. A memory address field.
If instruction size is 32 bits long then determine the number of possible operations that can be
represented with above instruction format.
13. A computer has 170 different operations. The word size is 4 bytes and each instruction
requires one word and are two address instructions. One address for register and one address
for memory. If there are 37 registers then the memory size would be?
 14. The memory locations 1000, 1001 and 1020 have data values 15, 1 and 18 respectively
before the following program is executed.

MOVI Rs, 1 Move immediate

LOAD Rd, 1000(Rs) Load from memory

ADDI Rd, 1000 Add immediate

STOREI 0(Rd), 20 Store immediate

Illustrate the execution of the instructions given in above table and discuss the changes in
data values stored in memory as a consequence of the execution of these instructions.

Module-2
15. Compute the decimal value of the binary number 1011 1101 0101 0110 if the given number
represents unsigned integer. Repeat if the number represents2’s complement. Repeat if the
number represents sign-magnitude integer.

16. Describe the floating point representation of the number 45.125 if 8 bits are used to
represent exponent and 23 bits for mantissa.

17. Illustrate the step-by-step process to obtain the floating point representation of 32.125 using
single precision and double precision.

18. Use the Booth’s Algorithm to compute the multiplication of a multiplicand X = 5 = (0101) and
a multiplierM = -3 = (1101).

19. Use the restoring division algorithm to compute the division of a dividend X = 14 = (1110) and
a divisor D = 6 = (0110).

20. Use the non-restoring division algorithm to compute the division of a dividend X = 14 = (1110)
and a divisor D = 6 = (0110).

21. Compute the decimal value of the binary number 1011 1101 0101 0110 if the given number
represents 2’s complement.

22. Consider the following floating point numbers which are represented in a 9-bit format
using a base b = 2, a 4-bit exponent e with a bias = 8, and 4-bit normalized mantissa m.
S Exponent (e) Mantissa (m)
 1 1100 1100
1 1010 1000

Describe how to perform addition, subtraction, multiplication and division of the above
floating point numbers