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Chapter 2

The document discusses different types of combinational logic circuits including static CMOS design, ratioed circuits design, dynamic CMOS design, and clocked CMOS design. It provides an example of a dynamic logic circuit and discusses its advantages of lower transistor count and power dissipation compared to static CMOS, as well as disadvantages related to needing a clock and potential timing issues. The document also discusses other logic circuit styles including pseudo-nMOS, transmission gates, CMOS domino logic, and cascode voltage switch logic.

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Hussein Hasen
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91 views47 pages

Chapter 2

The document discusses different types of combinational logic circuits including static CMOS design, ratioed circuits design, dynamic CMOS design, and clocked CMOS design. It provides an example of a dynamic logic circuit and discusses its advantages of lower transistor count and power dissipation compared to static CMOS, as well as disadvantages related to needing a clock and potential timing issues. The document also discusses other logic circuit styles including pseudo-nMOS, transmission gates, CMOS domino logic, and cascode voltage switch logic.

Uploaded by

Hussein Hasen
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 2

Designing Combinational Logic Circuits

• Static CMOS Design

• Ratioed Circuits Design

• Dynamic CMOS Design

• Clocked CMOS Design

• Power Dissipation
Combinational Logic Circuits
F = AB + BC + AC
Dynamic Logic example

Advantages of dynamic logic circuits:

1) The number of transistors required here are less (N+2) as compared to 2N in the Static CMOS
circuits.

2) This circuit is still a ratio less circuit as in case of Static.

3) The static power loss is very less in a dynamic logic circuit.

4) Faster switching speed because of lower load capacitance (CL) and Cint.

Disadvantages of dynamic logic circuits:

1) It needs a clock for the correct working of the circuit.


2) The output node of the circuit is Vdd till the end of precharge. Now if the CLK in the circuit
that follows arrives earlier compared to the CLK in this, or the PDN network in this block takes a
longer time to evaluate its output, then the next block will start to evaluate using this incorrect
value. To solve this, we need to follow this circuit with an inverter (dominos) so that the next
block is not evaluated till this output has been evaluated. Therefore the output has to be inverted
i.e. the logic must be changed to accommodate this.

3) Some excess power is consumed because the circuit has to be precharged after every
evaluation, i.e. the evaluation transition takes place only once for one precharge cycle.
• CMOS logic: Best option for most cases. Safe, fast
• Pseudo-nMOS: Large fan-in NOR gates, i.e. PLAs, ROMs
• Transmission gate:
Speed advantage, good for complex Boolean functions.
• CMOS domino logic: Low-power, high speed.
Cascode Voltage Switch Logic

Cascode Voltage Switch Logic (CVSL ) seeks the performance of ratioed


circuits without the static power consumption. It uses both true and
complementary input signals and computes both true and complementary
outputs using a pair of nMOS pull-down networks, as shown in Figure (a).

The pull-down network F Implements the logic function as in a static CMOS


gate, while F uses inverted inputs feeding transistors arranged in the
conduction complement. For any given input pattern, one of the pull-down
networks will be ON and the other OFF. The pull-down network that is ON will
pull that output low.

This low output turns ON the pMOS transistor to pull the opposite output
high. When the opposite output rises, the other pMOS transistor turns OFF so
no static power dissipation occurs. Figure (b) shows a CVSL AND/NAND gate.
Observe how the pull-down networks are complementary, with parallel
transistors in one and series in the other. CVSL has a potential speed
advantage because all of the logic is performed with nMOS transistors, thus
reducing the input capacitance.

As in pseudo-nMOS, the size of the pMOS transistor is important. It fights the


pull-down network, so a large pMOS transistor will slow the falling transition.
Unlike pseudo-nMOS, the feedback tends to turn off the pMOS, so the outputs
will eventually settle to a legal logic level.

A small pMOS transistor is slow at pulling the complementary output high. In


addition, the CVSL gate requires both the low- and high-going transitions,
adding more delay. Contention current during the switching period also
increases power consumption.

Pseudo-nMOS worked well for wide NOR structures. Unfortunately, CVSL also
requires the complement, a slow tall NAND structure. Therefore, CVSL is
poorly suited to general NAND and NOR logic. Even for symmetric structures
like XORs, it tends to be slower than static CMOS, as well as more power-
hungry
What is called threshold voltage?

The threshold voltage, commonly abbreviated as Vth, of a field-effect


transistor (FET) is the minimum gate-to-source voltage VGS (th) that is
needed to create a conducting path between the source and drain terminals
`

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