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Totrl No of Pages : I

Roll No' 3 'q""t""""tQ""'

cs&utr202

2fi16

COMPUTER
M
SY@RCIIITECTURE

ftfraqqq zt/zill tffio,ttrdo:30

fUaxtnnuo Marf,s : 30
fim altowed zt/zfrovrl

ab: fu) tfrnw'ffitwmb'swt'dr.wt t

I iru*
Notc : and each
Alt Qtpstiow are compulsory Erestion is of

(a)eh}flg.rqr#.irf,f[}++}ftryfrddddairrrtt.et<*t
Only &tglish version is wlid in case of differerce in both tlu l4ttgwges'

1. ffie1mqutffiiffit 1: Von Neumann archit€otur€ is

(a) sIsD (a) sIsD

(h) SIMD o) SIMD

(c) ldMD (c) lvffMD

(d) MISD
(d) tvflSD

In register addpssing mode operands

rffis{GkTds{ dqt€fism&t are looked u
(a) +{ri (a) Incache
(b)' ferdtq{ (b) InsecondarYstorage
(c) trq+ (c) IDCPU
(d) srssrtt+sd (d) Inpcinarymemory

EElCgqgIglTETEffitrTE The e,xmple of inplied addressug is

(a) dffiqqtur (a) Stack addressing

ol dtuqgqqtur O) Immediateaddressing
(c) Ergrdt€qifrrr
(c) Indircct addressing
(d) None of these
(d) Et{+dtqfi
(1)
P.T.o.
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4. Vmil: frFnm uqar qu,fur tit f 4. . Noroauy digtal computers are based
rt

(a) Al.tD ellcOn gare on

(a) AhID and OR gate
(c) NOT gate (b) NAI,.ID and NOR gare
(d) Frd++t{fi (c) NOT gaie
(d) None of these
5, EqR$r ALU tfresqkil qar t 5. ALU unit of a computerperforms
(a) fr, qersftFqrq' (a) edditio.tr, subtraction operations
O) qrft sififi,rfrqkr(, O) all ryircs of oith.rti.
(c) efuXqqffi
.AIYD, OR
operations.
(c) AIID, OR and multiplication
(d) v$sisrrfufuEil{drfuffi. operations.
(d) all arithmetic and logical
operations.
6. w'cpu*.ws rofue*qmcrsrs{t r
A CPU has 16 bit pnogram
vmr q{ gwr fu. cnu qis Hr vffir t counter.
This means that the CpU can aAOress
(a) 161{$Se}fus (a) 16 k memory locations
O) 321td{fr}nr O) 32 k memory locations
(c) 6a 1{Stfr}nr (c) 64 kmemory locations
(d) 2s6ktd+d*nq (d) 256knemorylocatioos
7. cpuqr*ert 7. CPU consists of
(a) ALU, CU dTIfud (a) ALU, CUandregisters
(b) ALU st{cu O) ALU and CU
(c) ALU, CU sku$kw. (c) ALU, CU and Ilsrd Disk
(d) ALU, CU drdter (d) ALU, CU and Monitor
qwr+ilftfos*.qqfuirtit
r Cache memory resides in between
(a) cPU st(nail{ (a) CPU aEdRAI!,I
O) net{ sil{nolu O) MIr,tandROM
(c) cPU sfr{Er$fug. (c) CPtI and Hard Disk
(d) Ed+qiltqf (d) None of these

9. r fu sra r*{ u,rl qmr sfu wililr t 9. The circuit usod to stote one
(a) Ht of
rqq+w data is known as
O) ORgato (a) Encodcr
(c) fqaq-wtq (b) ORgate
(d) furts{ (c) FlteFtop
(d) Decoder
 (r) 2fi29
csmutrlfrz
10. FFr { qere at Stsrt'qmem: H 10. In,,:computer, subtraction is gcnerally
carried out bY
qTft t j (a) 9s comPliments
(a) !55ffifqg
(b) 10's comPliments
O) lsrsd+qt1 (c) I's comPliments
(c) I'sdtq61"' (d) ?s comPliments
(d) 2'gffiqr
Floating point repesentation is used
u. ffirr qiefifiur rqli" q,rcr t 11.
to.stot€
(a) Boolean values

O) qryt{qr .: O) Wlole numbers

(c) qrfiHo+q (c) Rcal values
(d) ffi (d) Integers

12. tfrfr i[ nr$ gls r&e tilHn tm' 12. The average tine requircd to reach
a
t oarticular storage location in memo'ry
ddffirss+dtttlweori{aqr *a oUt"io its contens is called the
uin.fiqcqqqwflilrt
(a)
I

seektimo
(a) *+'qqq
O) et-q{rsusqqq O) turnarqrndtime
(c) access time
(e) q{d({qq
(d) uansfer time

Ll. ThE adthes mode usd itr an

13. ADD A)L [sll s{q r<ftEr + kq insruction of the form ADD A)q [SU
q.iqrist rs
(a) w+W (a) Abrolurc
(b) gstqt€ O) Itrdtu€ct
(c) dN (c) Index
(d) F{+6tqfi (d) None of these

14. thrrqqRr i[,r r+qrc qrm' ECi E t4. The,idoa of cache Inomory is bascd

(a) d*ffiemu,ftrsteq{ (a) mlocalitYofreference

(b) 90-10Frw O) on 9G10 ntle
(c) wrg{rR (c) m cluster
(a; uqtffiqqfr (d) Alloffteabove
F T'O'
\
 cs2IWn2,Oz (4)
_ 2,,/29
ls. idttsvofuRq{wrqfi ftrt r 15. In .a men_ory map,ped VO syste,m,
(a) LDA which of ffie following will not be
(b) suB
there ?
(a) LDA
(c) ADD
O) sLrB
(d) CMP (c) ADD
(d) cMP
16. E{+ + +h r<f-efuqrvs q# t r 16. Which of the following is not an
(a) rllir€ input device ?

O) ftt-qtt (a) .Mouse

(c) erratq, O) Keyboqr.d

(c) Lightppn
(d) +ftr
(d) Monitor

t r-. E{d+amr<garwrwir t7. Which of the following is an input

(a, FD;R device ?

t-ol Hffi.{ (a) Scanner

(c) cD O) Speaker
(d) fie{ (c) cD
(d) Printer
tB. 1qc{ e} ffi Er{ fr,m 6} Htftil
q,-fr. q-iFil ie Of qrF
18. A group of bits that tell the compu@r
Wfl Hf i to perfoiln a specific operation is
(a, {*iffi{ i[rg known as

(O,, ITr{fiT ETqt{E (a) Instruction code

(c, \rflrgrdt O) Micro operation

(d) {Pw{
(c) Accumulatm
(d) Regisler
:

19. qsffirc fuqT + *r vrqi6* iraenflr

t 19.
Ihe.time inrcrval between
bits is calted
adjacent

(a) +6-s{q (a) Word-tine

tbt rcesqq O) Bit-time
(c, ai.gtrswgqq (c) Tttnarortndtime
(d) Rn$rwm (d} Slice time
 cs2h2/mw2
zo. Kfoeiwrfrdo{int
(s)
*te
2A. K bit field specry any one of
(a) ltfrs (a) 3kregister
O) 2krPqg (b) 2kregister
' (c) k2rtqs{ (c)' k2register
(d) rcrlqw (d) k3 register

zl. MrMDwennt r. 21. ' MIMD stands for

(a) mdrof<gq{Hretrosrsr (a) llulfipte instruction multiple
data.
\o, ;ffi'EWlTIFIffigI4 (b) Multiple instnrction memory
(c) tdtr<qEuqqo*,muar data.
(c) Memory instnrction multiple
(d) qdquEqh+flr*frrtsrzr data.
(d) Multiple information memory
data.
22. E{ge *r wrqav,p*.ur eilfurrta 22. Iog1c gates with a set of input
*amqr+twhf andJ

1a) oq!,vrreufu (a) computationalcircuit

O) dtuq6o (b) Iogic circuit
(c) kqrtrqfr (c) design circuit
(d) {Fqs{ (d) register

23. qttfli srcr Hr tfuTd + Fqidftfr q,{+

The circuit convening binary data
into decimal is
ta) wsrst (a) Encoder
(o, f€Iqf,t{ O) Multiplexer
(c) Hs{ (c) Decoder
(d) +so.q& (d) Code convster

u. w'*{ {agaqril NoR tq, arftmyq

qleggmrr$.rort w 1 F * input NOR gate gives logic
high output only when
(a) w.lrgauat (a) one input is high
(b) qq,s<gaftad (b) one input is low
(c) tr<gefrqd (c) two inputs are low
(d) uftrtgatsqd (d) all inputs are h,igh
P.T.O..
IIr
 (o ?,u29
csnaffi2fr2
qqrdtstq*+{{ftrt 25. Pipelining Process is
25,
(a) instnrctionexecution
(a) ffi4qffitq (b)' instnrctionPrrefach
o) {ffiHfit q
(c) {<wlrffiB'r (c) instnrctiondecoding
(d) instnrctionmaniPtrhtion
(d) rglqffife{tr
"Delayed-1oad" is used for
26;.'ffi6+g' 51 3ffi fuqr iillil t (a) pnocessor-printcrcommunication
(a) fi+st'frIr46qfii'vl4
O) memory-mtnitorcommwrication
O) ++t'dFtt('5fivrlr (c) piPelining
(c) qtEqf,I#rtl
(d) @oofthse
(d) r+i+Erifti
n. hrallel P'rocessing may occur
27, $ffi*4fi{"qtc?ttdrt (a) in the instnrction stream
(a) Fg*rqdq{ (b) in the datasream
O) qadq{ (c) inthe(a) and(b)
(c) (a) aer O) { (d) I.trone of these
(d) r+f +qttqfi
28. The Gost of parallel processing is
28. tfl-fr m{fu or
qtrc tqrlIrtd lsqi qmi t determined bY
(a) zr{q6,qdM (a) time comPlexitY
O) tsf+'r68dM (b) swirchingcomPbxitY
(c) qFraffidffi (c) circuit comPlexitY
(d) l'trone of these

29, Rrscqr qft{ffiurt n. Characteristic of RISC is

(a) *{Eqewsfrqffi" (a) three insttuctions Per cYcle

(b) {$qffsfrqr (b) nnro instnrctions Per cYcle
(c) qtF{ffir{uhqm' (c) one instnrction Per cYcle
(d) r++*ftttqfi (d) Itone of these

30. Charact€ristic of CISC is

30. clsc Er qftmqq t (a) Fixed format instrtrction
(a) fiFffisr+et<fiq (b)' Vuiable format instnrcdou
o) qctnfufqwtt (c) ltrardrfare executedinstnrction
(c) il€*q{tErtrFlqfrnr<ffi{
(d) I*one of these
(d) r+S * fr1tqfi
cs202fiT202 Roll No. ! ................r......

2016
COMPT]TER SYSTEM ARCHITECTURE

ftqlftavm *rrit1 .;"

fine allowed' : Ihrce Hours] 1oftmmft.3 76
MadmumMar*sl Z0
qlr : (i) tattrp qW tph++ffi rfr#r*cq?Fd t
Nate: gttcstion ua i x conirursory, answer anyfwe questionsfum the remaining,
(ii) sdzry#pqt v,i al m+qv<rrwlqraqfFrq t
Solve all pans of a question consecr$ively togahcr.

fiiil ydamrdrd ys#rrer t deq.

Stan each question on afreshpage.
(iv) Ei*qrvr,irr#emrati #fgfdt dnE?,ryw6l.,aj. r
onty Engtish versioa is vatid in case of difference ln both ttw languages.

l. frq*'wrftrq:
Write the answer of following :

(i) I{Bn Ef uan rPqs qqr t r

What is MBR and IvIAR registor ?

(ii)
,

ga qdw u,qH+{H d sflr<ur Ekn wrri r

Explah full duplex communication ryith example.

(iii) qFr$fffnrt ?

Whatis virtualme,mory ?

(iv) ffi ftq EFqo.qr6) eiqtsrl *.qrqqffradfiqq r

Enlist any five logic micro operations.

(v) IllqlfrEfrrr*rd*t ?

Wbat is pipelining ?
(2x9
(7)
P.n o.
 2fr29 d
6?.0wr2p2 (u,

2. (1) ERte( *.qlwqfi s{.ia q{ttt Eq 3q|q =T{H snffirr -ry* dfrq r rdo
EqTi€qtqrrifrmm t

showing its qsseatial

Draw the 'Von Neumann Arctitecture' of conparEr
components. Give firpction of each comPonsnt'
(ii) ftrgqlqfti silqfutdqq|q+ t
(6+6)
Exptqln shift micro oPerations'

3. (r) 6q{ ffi$q * lffitrlq {nFFer ni qffSr$ t

Explaininstnrctioncycleofcompnrterorganization.
(iD ftfirq qlffir dq 6| qf,{rt+ 1

(6{6)
Explain various addressing schemes'

(i) wfift56qu({rgffi ffi qq Ecr+ +frFs \rn'ilfuqdy.arut.,

_
in Arithnetic Processor'
Explain any addition and subrasti-on algorithmused
(ii) ftfi{qdBT+fa silqtfl"atqwil{n I (6'tf)
Explain different floating point oporations'
5. (D fu,ffiflqqrtrqqflE+ t

Wrat is stack onganization ? fi*ptalo'

(ii) rrd*+rtffi{tdnt"ftf qqflE} I
(6.15)
Explain Multiproceeso. r organizafion

(r) kr ++t Hr +ft t r wt qqffi+ r'

What isCacte memory ? ExPlain it"

(ii) **fi qq {rraq d qqsrd t
(G+6)
Explain pracessotr bus organization'

7. (r) sfirfr sqrf,rur dtRTq.ff * qqrflff iil+qt#q'rffi

aIMIrt, t
Exptain the working of paralht Processor with suitable example'
(ii) ffi sgnfiIfu qrql d swrd t
(6{6)
Explqin various computcr instnrctiol

frrrqT{{Hqffiffig:
Write short notes on following :

(r) uqa+ttFrd
Crsnerations of ComPutcr
(ii) s.qqs.
DMA
(in) wrrqqrfir{ur
Flynn's classification
(4#)