Lab Session # 2

Synthesis Using Logic Gates in SOP & POS Forms

1. Introduction
In this experiment, you will get to know what is meant by a Minterm, Maxterm, Sum of Products (SOP)
and Product of Sums (POS). In addition, you will learn how to design the expressions of the SOP and POS
using Quartus II 13.1 software.

2. Objectives
By the end of this lab experiment, students will be:
• Familiar with the Minterms, Maxterms, Sum of Products (SOP) and Product of Sums (POS).
• Able to design the expressions of the SOP and POS using Quartus II Software.
• Able to test the correct behavior of the expressions generated using SOP and POS.

3. Synthesis Using AND, OR, and NOT Gates

Suppose that we wish to design a logic circuit with two inputs, x and y. Assume that x and y represent the
state of two switches, either of which maybe open (0) or closed (1). The function of the circuit is to
continuously monitor the state of the switches and to produce an output logic value 1 whenever the
switches (x, y) are in states (0, 0), (0, 1) or (1, 1). If the state of the switches is (1, 0), the output should be
0. Another way of stating the required functional behavior of this circuit is that the output must be equal
to 0 if the switch x is closed and y is open; otherwise, the output must be 1. We can express the required
behavior using a truth table, as shown in Table 1.
Table 1: A Function to Be Synthesized
x y f (x, y)
0 0 1
0 1 1
1 0 0
1 1 1

A possible procedure for designing a logic circuit that implements the truth table is to create a product
term that has a value of 1 for each valuation for which the output function f has to be 1. Then we can take
a logical sum of these product terms to realize f. Let us begin with the fourth row of the truth table, which
corresponds to x = y = 1. The product term that is equal to 1 for this valuation is x . y, which is just the AND
of x and y. Next, consider the first row of the table, for which x = y = 0. For this valuation, the value 1 is
produced by the product term x' . y'. Similarly, the second row leads to the term x' . y. Thus, f may be
realized as
f ( x, y ) = x y + x' y' + x' y
The logic network that corresponds to this expression is shown in Figure 1.
 Figure 1: The Implementation of the Function in Table 1

Although this network implements f correctly, it is not the simplest such network. To find a simpler
network, we can manipulate the obtained expression using the theorems and properties in Figure 2.

Figure 2: Boolean Algebraic Theorems

According to theorem 7b, we can replicate any term in a logical sum expression. Replicating the third
product term, the above expression becomes
f ( x, y ) = x y + x' y' + x' y + x' y
Using the commutative property 10b to interchange the second and third product terms gives
f ( x, y ) = x y + x' y + x' y' + x' y
Now, the distributive property allows us to write
f ( x, y ) = ( x + x' ) y + x' ( y' + y)
By applying theorem 8b, we get
f ( x, y ) = 1 . y + x' . 1
Finally, theorem 6a leads to
f ( x, y ) = y + x'
The network described by the last expression is given in Figure 3. Obviously, the cost of this network is
much less than the cost of the network in Figure 1.

Figure 3: Minimal Cost Realization of Figure 1

This simple example illustrates two things. First, a straightforward implementation of a function can be
obtained by using a product term (AND gate) for each row of the truth table for which the function is
equal to 1. Each product term contains all input variables, and it is formed such that if the input variable x
i

is equal to 1 in the given row, then x is entered in the term; if x = 0, then x ' is entered. The sum of these
i i i

product terms realizes the desired function. Second, there are many different networks that can realize a
given function. Some of these networks may be simpler than others. Algebraic manipulation can be used
to derive simplified logic expressions and thus lower-cost networks.

If a function f is specified in the form of a truth table, then an expression that realizes f can be obtained by
considering the rows in the table for which f = 1, as has been explained earlier, or by considering the rows
for which f = 0, as will be explained later.

3.1 Minterm
A binary variable may appear either in normal form (x) or in its complement form (x'). Now, consider two
binary variables, x and y, combined with an AND operation. Since each variable may appear in either
form, there are four possible combinations: x' y', x' y, x y' and x y. Each of these four AND terms is called a
minterm, or a standard product. A minterm is defined as a product term in which each of the function
variables appears once in either complemented or uncomplemented form. In a similar manner, n
n n
variables can be combined to form 2 minterms. The different 2 minterms may be determined by a
n
method similar to the one shown in Table 2 for three variables. The binary numbers from 0 to 2 – 1 are
listed under the n variables. Each minterm is obtained from an AND term of the n variables, with each
variable being primed (x') if the corresponding bit of the binary number is a 0 and unprimed (x) if it is a 1.
A symbol for each minterm is also shown in Table 1 and is of the form m , where j denotes the decimal
j

equivalent of the binary number of the minterm designated.

3.2 Maxterm
Given a logic expression, its dual is obtained by replacing all "+" operators with "." operators, and vice
versa, and by replacing all 0s with 1s, and vice versa. This principle suggests that if it is possible to
synthesize a function f by considering the rows in the truth table for which f = 1, then it should also be
possible to synthesize f by considering the rows for which f = 0. This alternative approach uses the
complement of minterms, which are called maxterms. In other words, the n variables forming an OR term,
n
with each variable being primed or unprimed, provide 2 possible combinations, are called maxterms, or
standard sums. The eight maxterms for three variables, together with their symbolic designation, are
n
listed in Table 2. Any 2 maxterms for n variables may be determined similarly. Each maxterm is obtained
from an OR term of the n variables, with each variable being unprimed if the corresponding bit is a 0 and
primed if it is a 1. Note that each maxterm is the complement of its corresponding minterm, and vice
versa.
Table 2: Minterms and Maxterms for Three Binary Variables
Minterms Maxterms
x y z Term Designation Term Designation
0 0 0 x' y' z' m x+y+z M
0 0
0 0 1 x' y' z m x + y + z' M
1 1
0 1 0 x' y z' m x + y' + z M
2 2
0 1 1 x' y z m x + y' + z' M
3 3
1 0 0 x y' z' m x' + y + z M
4 4
1 0 1 x y' z m x' + y + z' M
5 5
1 1 0 x y z' m x' + y' + z M
6 6
1 1 1 xyz m x' + y' + z' M
7 7

3.3 The Significance Between Minterms and Maxterms

In short, minterms and maxterms may be used to define the two standard forms for logic expressions,
namely the sum of products (SOP), or sum of minterms, and the product of sums (POS), or product of
maxterms. These standard forms of expression aid the logic circuit designer by simplifying the derivation
of the function to be implemented.

3.4 Sum of Products (SOP)

A function f can be represented by an expression that is sum of minterms, where each minterm is ANDed
with the value of f for the corresponding valuation of input variables. Back to our example represented by
Table 1, the two-variable minterms are m = x' y', m = x' y, m = x y', and m = x y. The function in Figure 1
0 1 2 3

can be represented as
f ( x, y ) = m . 1 + m . 1 + m . 0 + m . 1
0 1 2 3

f ( x, y ) = m + m + m
0 1 3

f ( x, y ) = x y + x' y' + x' y

which is the form that was derived in the previous section using perceptive approach. Only the minterms
that correspond to the rows for which f = 1 appear in the resulting expression.

Any function f can be represented by a sum of minterms that correspond to the rows in the truth table for
which f = 1. The resulting implementation is functionally correct and unique, but it is not necessarily the
lowest-cost implementation of f. A logic expression consisting of product (AND) terms that are summed
(ORed) is said to be of the sum-of-products (SOP) form. If each product term is a minterm, then the
expression is called canonical sum-of-products for the function f. As we have seen in the example of Table
1, the first step in the synthesis process is to derive a canonical sum-of-products expression for the given
function. Then we can manipulate the expression, using the Boolean Algebraic theorems, with the goal of
finding a functionally equivalent sum-of-products expression that has a lower cost.

Minterms, with their row-number subscripts, can also be used to specify a given function in a more
concise form. Again, for the example of Table 1, the function can be specified as

f ( x, y ) = Ʃ ( m , m , m )
0 1 3

or even more simply as

f ( x, y ) = Ʃ ( 0, 1, 3 )

where the sign Ʃ denotes the logical sum operation. This shorthand notation is often used in practice.

3.5 Products of Sums (POS)

If a given function f is specified by a truth table, then its complement f ' can be represented by a sum of
minterms for which f ' = 1, which are the rows where f = 0. Back to our example of Figure 1
f ' ( x, y ) = m = x y'
2

If we implement this expression using DeMorgan's theorem, the result is

( f ' ) ' = f = ( x y') '
f = x' + y
Note that we obtained this expression previously by algebraic manipulation of the canonical sum-of-
products form for the function f. The key point here us that
f = m ' =M
2 2

where M is the maxterm for row 2 in the truth table. Using shorthand notation, an alternative way of
2

specifying the function is

f ( x, y ) = Π ( M2 )
or more simply
f ( x, y ) = ΠM (2)

3.6 Important Note

• Boolean functions expressed as a sum of products or a product of sums are said to be in canonical form.
• Note the POS is not the complement of the SOP expression.
4. Design Procedure
The design of combinational circuit starts with problem definition, which is solved by designing
appropriate logic circuit. The procedure involves the following steps;

1. From the specification of the circuit, determine the required number of inputs and outputs
and assign a symbol to each one of them, if they were not given in the problem statement.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions using Boolean algebra for the output as a function of
input variables.
4. Draw the logic diagram (graphical design) or write a Verilog code representing your design.
5. Simulate and check the functionality of the designed circuit.

Problem Statement: Designing simplest SOP & POS circuits for a given function

Design the combinational circuit for the given function:

f ( x, y ) = Ʃ ( 0, 1, 3 )

1. Using graphical/schematic design for the simplest SOP expression.

2. Using Verilog code design for the simplest POS expression.
3. Simulate each design using the waveform editor to verify its functionality.

Step 1: Identifying Number of Inputs and Outputs

From the specification of the circuit, we can find out that:
1. The given function has two inputs and one output.
2. The three inputs are designated as x and y.
3. The output is specified as f.

Step 2: Truth Table Preparation

The rows in the truth table are obtained from the 2n combinations of the n input variables. The 2-bit
binary numbers range from 0 in decimal (00 in binary) up to 3 in decimal (11 in binary). From the given
function, conclude the Truth Table shown as Table 3.
 Table 3: Minterms and Maxterms for the Given Equation

F Minterms Maxterms
x y Output
Term Designation Term Designation

0 0 1 x' y' m x+y M

0 0

0 1 1 x' y m x + y' M
1 1

1 0 0 x y' m x' + y M
2 2

1 1 1 xy m x' + y' M
3 3

Step 3: Deriving Simplified Boolean Expressions

1. From Table 3, take the output column (f), to which you will develop the logic expression for.
2. To derive the SOP, find the minterms from the output column (rows having value 1). For
example, output f in table 3 has three 1's; therefore, the logic expression for f has three minterms
(if the is to be represented in sum of product form).
3. Use Boolean Algebra to simplify the logic expression for the simplest SOP. You may alternatively
use any other method to simply this expression such as k-map or computer based simplification
program.
4. To derive the POS, find the maxterms from the output column (rows having value 0). For
example, output f in table 3 has one 0; therefore, the logic expression for f has one maxterm (if
the is to be represented in sum of product form).
5. Use Boolean Algebra to simplify the logic expression for the simplest POS. You may alternatively
use any other method to simply this expression such as k-map or computer based simplification
program.

Step 4: Design Entry

1. You can either implement the design entry as Block Diagram/Schematic or Verilog.
2. Follow whatever is specified for you in the problem statement.
3. Implement your design using the Quartus II Software.

Step 5: Simulation
1. Synthesize your design for the implemented circuit (refer to Section 3.2.5 in Lab Session#1).
2. Perform Functional Simulation (refer to Section 3.4 in Lab Session#1).
Student Name: Date:
Student ID:

Lab Exercise # 2

Problem Statement:
Use the expression of the logic circuit given to you by your instructor to derive the SOP and POS forms,
then design them using Quartus II Software. Synthesize your designs and test their functionality
correctness (Functional Simulation) for the correct behavior of the expressions generated using SOP and
POS.

Procedure:
1. Design the combinational circuit for the given function:
The given Equation is: …………………………………………………………………………………………………………………
2. Fill in the truth table for the given equation, in Table 4 shown below.
Table 4: Minterms and Maxterms for the Given Equation

F Minterms Maxterms
x y z Output
Term Designation Term Designation

3. Use the Boolean Algebraic simplification rules given in Figure 2 to design the simplest Sum-Of-
Products (SOP) circuit equation that implements F.
 4. Use graphical/schematic to design the simplest SOP expression.
5. Create a Block Diagram/Schematic design file for the designed circuit (refer to Section 3.2 in Lab
Session#1).
6. Synthesize it (refer to Section 3.2.5 in Lab Session#1).
7. Perform a Functional Simulation (refer to Section 3.4 in Lab Session#1) to test your design for all
the possible test cases (Table 4).
8. Use the Boolean Algebraic simplification rules given in Figure 2 to design the simplest Product-Of-
Sums (POS) circuit equation that implements F.

9. Use Verilog code to design the simplest POS expression.

10. Create a Verilog code design file for the designed circuit (refer to Section 3.2 in Lab Session#1).
11. Synthesize it (refer to Section 3.2.5 in Lab Session#1).
12. Perform a Functional Simulation (refer to Section 3.4 in Lab Session#1) to test your design for all
the possible test cases (Table 4).
13. Print your design files and simulation waveforms.

Ask your engineer to check your results, write his/her comments and sign below:

………………………………………………………………………………………………………………………...…………………………...……….
……………………………………………………………………………………………………………………...………………………...…………….
…………………………………………………………………………………………………………………...…………………………………………

Engineer Signature
……..……………..

Attachments:
Please attach with the lab exercise sheet printouts of the files indicated below. Don't forget to
write your Name and ID Number as comments in every file before printing.

1. Verilog code (*.v file).

2. Waveform file (*.sim.vwf file)
3. Graphical design file (*.bdf file)
4. Waveform file (*.sim.vwf file)