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Alternately, You Can Run Your Design On A 50M Clock, and Sample The Ila On 100Mhz Clock. You Will Then See 50M Clock On Ila

The document discusses how to use an Integrated Logic Analyzer (ILA) and Virtual Input/Output (VIO) for debugging a design in Vivado. It explains that the ILA samples signals at the clock frequency and requires a trigger. It also describes how to: 1. Add a VIO to generate inputs and probe outputs of a module. 2. Add an ILA template to probe internal signals and mark the probes in the synthesized design. 3. Program the bitstream and use the VIO and ILA windows to observe waveforms.

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Gaurav Sharma
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45 views7 pages

Alternately, You Can Run Your Design On A 50M Clock, and Sample The Ila On 100Mhz Clock. You Will Then See 50M Clock On Ila

The document discusses how to use an Integrated Logic Analyzer (ILA) and Virtual Input/Output (VIO) for debugging a design in Vivado. It explains that the ILA samples signals at the clock frequency and requires a trigger. It also describes how to: 1. Add a VIO to generate inputs and probe outputs of a module. 2. Add an ILA template to probe internal signals and mark the probes in the synthesized design. 3. Program the bitstream and use the VIO and ILA windows to observe waveforms.

Uploaded by

Gaurav Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ILA

●
ILA Runs on the main clock.
●
It samples the signals to be probed at the clk frequency
●
So you will not be able to see the clock on ILA (sampling
the clock on itself will result in a constant)
– Alternately, you can run your design on a 50M clock, and sample
the ILA on 100MHz clock. You will then see 50M clock on ILA
●
When you hit “Play” on the ILA, it serves as a trigger and
ILA starts displaying the probed data. (The design has
started running even before we hit “Play”). So, sample 0
on the ILA is NOT time=0 of the design
●
ILA works only with trigger
●
Probe values are captured/displayed after Trigger.
Otherwise ILA will say “Wait for trigger”
ILA
●
You can alternately trigger the ILA on a signal such as
reset going from low to high.
– You can give reset externally through a switch, so that you
have control over the reset
– If you generate reset in the design, then you have to make
sure it is low for a large number of clk cycles, so that by the
time you hit Play, the reset has not disappeared already
●
Alternately, “Trigger at Startup” can be done following
the procedure in the documentation: “Vivado Design
Suite User Guide: Programming and Debugging”
●
ILA Uses block RAM to store the captured values.
Depth of Block RAM is equal to the ILA Sample depth
1. Add VIO
Inputs of the adder will be generated by the VIO. Hence they are
VIO outputs

Outputs of the adder will be probed by VIO. Hence, they are VIO inputs
1 input probe 2 output
To VIO probe from
VIO
VIO (virtual input/ b
Design ILA
Output)
adder
Has a clk already a
c

2. Add ILA to probe any internal wire or reg you want to see the waveform
for
1. Add VIO
Inputs of the adder will be generated by the VIO. Hence they are
VIO outputs

Outputs of the adder will be probed by VIO. Hence, they are VIO inputs
1 input probe 2 output
To VIO probe from
VIO
VIO (virtual input/ reset reset
Output) Memory address ILA
Has a clk already clk
address
data

2. Add ILA to probe any internal wire or reg you want to see the waveform
for
Steps
●
Modify the verilog code according to the steps followed for VIO
– Your module ports should be modified to make all inputs as wires and outputs as
reg, except clock
●
Create VIO as explained earlier. In addition to VIO, now add an ILA as
explained below
●
Create an ILA template using IP catalog
– Add probes – input
– Change the probe width accordingly
●
Once the template is generated, now, click on IP sources --
>Instantiation template (ILA)--> veo (for verilog)
●
Copy paste the template inside your code
– Now, change the module probe names of the ILA template you just copied
– Probe names should be assigned according to the comments mentioned there
●
Now, the design is ready to simulate
..cont
●
After elaboration --> assign pin names.
– We have only clk. So, assign clk pin to W5 for Basys FPGA --> save constraints
●
Synthesise--> after synthesis, open synthesised design
– Now, go to the left side panel under Synthesis--> Open schematic
– Zoom in to the ILA which is towards the output (RHS of the schematic)
– Right click on each probe --> If it is already shown as Mark debug--> Unmark it
and then Mark it again (you can see the bug symbol next to the probe) --> Save
constraints
●
Run implementation --> generate bit stream--> program bitstream-->
– VIO and ILA windows will now appear
– Set the inputs a and b on VIO
– observe ILA outputs - waveforms
References
●
Integrated Logic Analyzer v6.2 LogiCORE IP
Product Guide
●
Vivado Design Suite User Guide: Programming
and Debugging

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