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    This document contains a Verilog module that defines a PLL (Phase Locked Loop) circuit. The PLL module takes an input clock signal CLK and generates an output clock signal CLKOP at 8 times the frequency of the input clock. It also generates a LOCK signal indicating when the PLL has locked. The PLL instance PLLInst_0 is defined using an EPLLD1 primitive and its parameters like bypass modes and frequency divisions are set through attributes.

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    'Timescale: Input Wire Output Wire Output Wire Wire Wire

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    fghdfgh
    29 views2 pages
    This document contains a Verilog module that defines a PLL (Phase Locked Loop) circuit. The PLL module takes an input clock signal CLK and generates an output clock signal CLKOP at 8 times the frequency of the input clock. It also generates a LOCK signal indicating when the PLL has locked. The PLL instance PLLInst_0 is defined using an EPLLD1 primitive and its parameters like bypass modes and frequency divisions are set through attributes.

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    This document contains a Verilog module that defines a PLL (Phase Locked Loop) circuit. The PLL module takes an input clock signal CLK and generates an output clock signal CLKOP at 8 times the frequency of the input clock. It also generates a LOCK signal indicating when the PLL has locked. The PLL instance PLLInst_0 is defined using an EPLLD1 primitive and its parameters like bypass modes and frequency divisions are set through attributes.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    29 views2 pages

    'Timescale: Input Wire Output Wire Output Wire Wire Wire

    Uploaded by

    fghdfgh
    This document contains a Verilog module that defines a PLL (Phase Locked Loop) circuit. The PLL module takes an input clock signal CLK and generates an output clock signal CLKOP at 8 times the frequency of the input clock. It also generates a LOCK signal indicating when the PLL has locked. The PLL instance PLLInst_0 is defined using an EPLLD1 primitive and its parameters like bypass modes and frequency divisions are set through attributes.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    D:\DATA\Produits\Resolver\_FPGA\PLL.

    v mardi 21 décembre 2021 16:05

    /* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */


    /* Module Version: 5.7 */
    /* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n PLL -lang verilog -synth lse -arch
    mg5a00 -type pll -fin 100 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -fb_mode CLOCKTREE
    -noclkos -noclkok -norst -noclkok2 */
    /* Mon Dec 20 15:48:31 2021 */

    `timescale 1 ns / 1 ps
    module PLL (CLK, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */;
    input wire CLK;
    output wire CLKOP;
    output wire LOCK;

    wire CLKOP_t;
    wire scuba_vlo;

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    // synopsys translate_off
    defparam PLLInst_0.CLKOK_BYPASS = "DISABLED" ;
    defparam PLLInst_0.CLKOS_BYPASS = "DISABLED" ;
    defparam PLLInst_0.CLKOP_BYPASS = "DISABLED" ;
    defparam PLLInst_0.PHASE_CNTL = "STATIC" ;
    defparam PLLInst_0.DUTY = 8 ;
    defparam PLLInst_0.PHASEADJ = "0.0" ;
    defparam PLLInst_0.CLKOK_DIV = 2 ;
    defparam PLLInst_0.CLKOP_DIV = 8 ;
    defparam PLLInst_0.CLKFB_DIV = 1 ;
    defparam PLLInst_0.CLKI_DIV = 1 ;
    // synopsys translate_on
    EPLLD1 PLLInst_0 (.CLKI(CLK), .CLKFB(CLKOP_t), .RST(scuba_vlo), .RSTK(scuba_vlo),
    .DPAMODE(scuba_vlo), .DRPAI3(scuba_vlo), .DRPAI2(scuba_vlo), .DRPAI1(scuba_vlo),
    .DRPAI0(scuba_vlo), .DFPAI3(scuba_vlo), .DFPAI2(scuba_vlo), .DFPAI1(scuba_vlo),
    .DFPAI0(scuba_vlo), .PWD(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(),
    .CLKOK(), .LOCK(LOCK), .CLKINTFB())
    /* synthesis CLKOK_BYPASS="DISABLED" */
    /* synthesis CLKOS_BYPASS="DISABLED" */
    /* synthesis FREQUENCY_PIN_CLKOP="100.000000" */
    /* synthesis CLKOP_BYPASS="DISABLED" */
    /* synthesis PHASE_CNTL="STATIC" */
    /* synthesis DUTY="8" */
    /* synthesis PHASEADJ="0.0" */
    /* synthesis FREQUENCY_PIN_CLKI="100.000000" */
    /* synthesis CLKOK_DIV="2" */
    /* synthesis CLKOP_DIV="8" */
    /* synthesis CLKFB_DIV="1" */
    /* synthesis CLKI_DIV="1" */
    /* synthesis FIN="100.000000" */;

    assign CLKOP = CLKOP_t;

    // exemplar begin
    // exemplar attribute PLLInst_0 CLKOK_BYPASS DISABLED
    // exemplar attribute PLLInst_0 CLKOS_BYPASS DISABLED
    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 100.000000

    -1-
    D:\DATA\Produits\Resolver\_FPGA\PLL.v mardi 21 décembre 2021 16:05

    // exemplar attribute PLLInst_0 CLKOP_BYPASS DISABLED


    // exemplar attribute PLLInst_0 PHASE_CNTL STATIC
    // exemplar attribute PLLInst_0 DUTY 8
    // exemplar attribute PLLInst_0 PHASEADJ 0.0
    // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 100.000000
    // exemplar attribute PLLInst_0 CLKOK_DIV 2
    // exemplar attribute PLLInst_0 CLKOP_DIV 8
    // exemplar attribute PLLInst_0 CLKFB_DIV 1
    // exemplar attribute PLLInst_0 CLKI_DIV 1
    // exemplar attribute PLLInst_0 FIN 100.000000
    // exemplar end

    endmodule

    -2-

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