t and output resistance of 50Ω. Determine the
t and output resistance of 50Ω. Determine the
t and output resistance of 50Ω. Determine the
5.1. An antenna modeled as a Thevenin equivalent having a voltage 15cos2π×103t and output resistance of 50Ω. Determine the
average power delivered to a load resistance of 15Ω.
Sol:
𝑉0 15 𝑉𝑟𝑚𝑠 10.61𝑉
𝑉𝑟𝑚𝑠 = = ≅ 10.61𝑉, 𝐼𝑟𝑚𝑠 = = ≅ 163.23𝑚𝐴
√2 √2 𝑅𝑂 + 𝑅𝐿 50Ω + 15Ω
2
𝑃𝐴𝑉 = 𝐼𝑟𝑚𝑠 𝑅𝐿 = (163.23𝑚𝐴)2 × 15Ω = 399.66mW
5.2. Determine the small-signal input resistance of the circuits shown in Fig. 5.96. Assume all diodes are forward-biased. (Recall
from Chapter 3 that each diode behaves as a linear resistance if the voltage and current changes are small.)
Sol:
(a)
𝑅𝑖𝑛 = 𝑟𝐷1 + 𝑅1
(b)
𝑅𝑖𝑛 = 𝑟𝐷1 + 𝑟𝐷2 ∥ 𝑅1
(c)
𝑅𝑖𝑛 = 2𝑟𝐷1 + 𝑟𝐷2 ∥ 𝑅1
5.3. Compute the input resistance of the circuits depicted in Fig. 5.97. Assume VA=∞.
Sol:
(a)
𝑉𝑋 = 𝑉𝜋
𝑉𝜋 𝑉𝜋
𝐼𝑋 = +
𝑟𝜋 𝑅1 ∥ 𝑅2
𝑉𝑋 𝑉𝑋
𝑅𝑖𝑛 = = = 𝑅1 ∥ 𝑅2 ∥ 𝑟𝜋
𝐼𝑋 𝑉𝜋 + 𝑉𝜋
𝑟𝜋 𝑅1 ∥ 𝑅2
(b)
𝑣𝜋 1
𝑣𝜋 + 𝑅𝐵 × 1 + 𝑅𝐵 × 𝑟𝜋 + 𝑅𝐵 𝑟𝜋 + 𝑅𝐵 1 𝑅𝐵
𝑟𝜋 𝑟𝜋
𝑅𝑖𝑛,𝐸 = 𝑣𝜋 = = = ≈ +
𝑔𝑚 𝑣𝜋 + 1 𝑔𝑚 𝑟𝜋 + 1 𝛽+1 𝑔𝑚 𝛽 + 1
𝑟𝜋 𝑔𝑚 +
𝑟𝜋
1 𝑅𝐵
𝑅𝑖𝑛 = 𝑅1 ∥ 𝑅𝑖𝑛,𝐸 = 𝑅1 ∥ ( + )
𝑔𝑚 1 + 𝛽
(c)
1 1
𝑅𝑖𝑛,𝑄2 = (𝑟𝜋2 ∥ ) + 𝑅1 , 𝑅𝑖𝑛,𝑄1 = 𝑟𝜋1 + (1 + 𝛽1 ) [(𝑟𝜋2 ∥ ) + 𝑅1 ]
𝑔𝑚2 𝑔𝑚2
(d)
𝑅𝑖𝑛 = 𝑅1 + 𝑅2 ∥ [𝑟𝜋1 + (1 + 𝛽)𝑟𝜋2 ]
1
高雄科技大學電子系 兼任副教授李謨中
5.4. Compute the output resistance of the circuits depicted in Fig. 5.98.
Sol:
(a)
𝑔𝑚 𝑟𝜋 𝑅𝐸 𝑅𝐸 ∥ (𝑟𝜋 + 𝑅𝐵 ) 𝑣𝑥
𝑖𝑥 [1 + + ]=
𝑅𝐸 + 𝑟𝜋 + 𝑅𝐵 𝑟𝑂 𝑟𝑂
𝑣𝑥 𝑔𝑚 𝑟𝜋 𝑅𝐸 𝑅𝐸 ∥ (𝑟𝜋 + 𝑅𝐵 )
𝑅𝑜𝑢𝑡 = = 𝑟𝑂 [1 + + ]
𝑖𝑥 𝑅𝐸 + 𝑟𝜋 + 𝑅𝐵 𝑟𝑂
(c)
1
𝑅𝑜𝑢𝑡,𝑄2 = (𝑟𝜋2 ∥ 𝑟𝑂2 ∥ ) + 𝑅𝐸
𝑔𝑚2
1
𝑅𝑜𝑢𝑡 = 𝑟𝑂1 + (𝑔𝑚1 𝑟𝑂1 + 1) {𝑟𝜋1 ∥ [(𝑟𝜋2 ∥ 𝑟𝑂2 ∥ ) + 𝑅𝐸 ]}
𝑔𝑚2
5.5. Determine the input impedance of the circuits depicted in Fig. 5.99. Assume VA =∞.
Sol:
(a)
𝑅𝑖𝑛 = 𝑅1 ∥ 𝑟𝜋
(b)
𝑣𝜋 𝑣𝑋 1 1
v𝜋 = −𝑣𝑋 , 𝑖𝑋 = − (𝑔𝑚 𝑣𝜋 + ) , 𝑅𝑖𝑛 = = = ∥𝑟
𝑟𝜋 𝑖𝑋 𝑔 + 1 𝑔𝑚 𝜋
𝑚 𝑟𝜋
2
高雄科技大學電子系 兼任副教授李謨中
(c)
1 1
𝑅𝑖𝑛,𝑄2 = ∥ 𝑟𝜋2 , 𝑅𝑖𝑛,𝑄1 = 𝑟𝜋1 + (1 + 𝛽1 ) ( ∥𝑟 )
𝑔𝑚2 𝑔𝑚2 𝜋2
(d)
1 1
𝑅𝑖𝑛,𝑄2 = ∥ 𝑟𝜋2 , 𝑅𝑖𝑛,𝑄1 = 𝑟𝜋1 + (1 + 𝛽1 ) ( ∥𝑟 )
𝑔𝑚2 𝑔𝑚2 𝜋2
(e)
𝑅𝑖𝑛 = 𝑟𝜋2
5.6. Compute the output impedance of the circuits shown in Fig. 5.100.
Sol:
(a)
𝑅𝑜𝑢𝑡 = 𝑅𝐶 ∥ 𝑟𝑂
(b)
𝑣𝑋 1
= 𝑟𝜋2 ∥ ∥𝑟
𝑖𝑋 𝑔𝑚2 𝑂2
𝑣𝑋
= [1 + 𝑔𝑚1 (𝑟𝜋1 ∥ 𝑅𝐸 )]𝑟𝑂1 + (𝑟𝜋1 ∥ 𝑅𝐸 ) = 𝑟𝑂1 + (𝑔𝑚1 𝑟𝑂1 + 1)(𝑟𝜋1 ∥ 𝑅𝐸 )
𝑖𝑋
1
𝑅𝑜𝑢𝑡 = 𝑟𝑂1 + (𝑔𝑚1 𝑟𝑂1 + 1) (𝑟𝜋1 ∥ 𝑟𝜋2 ∥ ∥𝑟 )
𝑔𝑚2 𝑂2
5.7. Compute the bias point of the circuits depicted in Fig. 5.101. Assume β = 100, IS = 6 × 10−16 A, and VA =∞.
Sol:
(a)
Assume Q1 is at active region.
𝑉𝐶𝐶 − 𝑉𝐵𝐸 𝐼𝐶
𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐵 𝐼𝑆
3
高雄科技大學電子系 兼任副教授李謨中
(b)
Q2 is at the edge of active region, assume Q1 is at active region.
𝑉𝐶𝐶 − 𝑉𝐵𝐸1 − 𝑉𝐵𝐸2 𝐼𝐶1
𝐼𝐶1 = × 𝛽 , 𝑉𝐵𝐸1 = 𝑉𝑇 ln = 𝑉𝐵𝐸2
𝑅𝐵 𝐼𝑆
𝛽 100
𝑟𝜋 = = ≅ 1.49𝐾Ω
𝑔𝑚 67.31𝑚𝑆
(b)
𝐼𝐶1 1.03𝑚𝐴
𝑔𝑚1 = = ≅ 39.62𝑚𝑆 = 𝑔𝑚2
𝑉𝑇 26𝑚𝑉
𝛽 100
𝑟𝜋1 = = ≅ 2.52𝐾Ω = 𝑟𝜋2
𝑔𝑚1 39.62𝑚𝑆
(c)
𝐼𝐶 1.26𝑚𝐴
𝑔𝑚 = = ≅ 48.46𝑚𝑆
𝑉𝑇 26𝑚𝑉
𝛽 100
𝑟𝜋 = = ≅ 2.06𝐾Ω
𝑔𝑚 63.71𝑚𝑆
4
高雄科技大學電子系 兼任副教授李謨中
*5.9. Calculate the bias point of the circuits shown in Fig. 5.102. Assume β = 100, IS = 5 × 10−16 A, and VA =∞.
Sol:
(a)
16𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 0.8𝑉
34𝐾Ω + 16𝐾Ω
𝑅𝑡ℎ = 34𝐾Ω ∥ 16𝐾Ω = 10.88𝐾Ω
Assume Q1 is at active region.
𝑉𝑡ℎ − 𝑉𝐵𝐸 𝐼𝐶
𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝑡ℎ 𝐼𝑆
16𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 1.6𝑉 , 𝑅𝑡ℎ = 9𝐾Ω ∥ 16𝐾Ω = 5.76𝐾Ω
9𝐾Ω + 16𝐾Ω
Q2 is at the edge of active region, assume Q1 is at active region.
𝑉𝑡ℎ − 𝑉𝐵𝐸1 − 𝑉𝐵𝐸2 𝐼𝐶1 𝐼𝐶2
𝐼𝐶1 = × 𝛽 , 𝑉𝐵𝐸1 = 𝑉𝑇 ln , 𝐼𝐶2 = 𝐼𝐸1 , 𝑉𝐵𝐸2 = 𝑉𝑇 ln
𝑅𝑡ℎ 𝐼𝑆 𝐼𝑆
13𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 1.3𝑉 , 𝑅𝑡ℎ = 12𝐾Ω ∥ 13𝐾Ω = 6.24𝐾Ω
12𝐾Ω + 13𝐾Ω
Assume Q1 is at active region.
𝑉𝑡ℎ − 𝑉𝐵𝐸 − 0.5𝑉 𝐼𝐶
𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝑡ℎ 𝐼𝑆
5
高雄科技大學電子系 兼任副教授李謨中
5.10. In the circuit of Fig. 5.103, β = 100, VA =∞. (a) If the collector current of Q1 is equal to 1 mA, calculate the value of IS. (b) If
Q1 is biased at the edge of saturation, calculate the value of IS.
Sol:
(a)
30𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × ≅ 1.07𝑉 , 𝑅𝑡ℎ = 40𝐾Ω ∥ 30𝐾Ω ≅ 17.14𝐾Ω
40𝐾Ω + 30𝐾Ω
Assume Q1 is at active region.
𝑉𝑡ℎ = 𝐼𝐵 𝑅𝑡ℎ + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸 , 1.07𝑉 = 10𝜇𝐴 × 17.14𝐾Ω + 𝑉𝐵𝐸 + 1.01𝑚𝐴 × 500Ω
𝐼𝐶
𝑉𝐵𝐸 = 393.6𝑚𝑉 , 𝐼𝑆 = 𝑉𝐵𝐸 ≅ 2.66 × 10−10 𝐴
𝑒 𝑉𝑇
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝐼𝐸 𝑅𝐸 = 995𝑚𝑉 > 𝑉𝐵𝐸 , Q1 is at active region.
(b)
Q1 is biased at the edge of saturation, 𝑉𝐵 = 𝑉𝐶 .
𝑉𝑡ℎ − 𝐼𝐵 𝑅𝑡ℎ = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 , 𝐼𝐶 = 1.726𝑚𝐴 , 𝑉𝐵𝐸 = 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝐼𝐸 𝑅𝐸 = −97.63𝑚𝑉 , impossible!
Q1 can not biased at the edge of saturation. To avoid entering the deep saturation region, 𝑉𝐶𝐸 > 200𝑚𝑉
𝑉𝐶𝐶 −𝑉𝐶𝐸 2.5𝑉−200𝑚𝑉
By KVL: 𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 + 𝐼𝐸 𝑅𝐸 , 𝐼𝐶 = 1+𝛽 , 𝐼𝐶 < 101 , 𝐼𝐶 < 1.53𝑚𝐴
𝑅𝐶 + 𝑅 1𝐾Ω+ ×500Ω
𝛽 𝐸 100
𝑅𝑡ℎ
𝑉𝐶𝐶 − 𝑉𝑡ℎ 𝑉𝐶𝐶 − 𝑉𝐶𝐶 × 𝑅1
𝑉𝑡ℎ − 𝐼𝐵 𝑅𝑡ℎ = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 , 𝐼𝑐 = = , 𝑅𝑡ℎ > 20.55𝐾Ω , 𝑅2 > 42.26𝐾Ω
𝑅 𝑅
𝑅𝐶 − 𝑡ℎ 𝑅𝐶 − 𝑡ℎ
𝛽 𝛽
R2 must be changed to 42.26𝐾Ω in order for Q1 to be biased at the edge of the saturation region.
We choose R2=43 𝐾Ω
43𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × ≅ 1.3𝑉 , 𝑅𝑡ℎ = 40𝐾Ω ∥ 43𝐾Ω ≅ 20.72𝐾Ω
40𝐾Ω + 43𝐾Ω
Q1 is biased at the edge of saturation, 𝑉𝐵 = 𝑉𝐶 .
𝑉𝑡ℎ − 𝐼𝐵 𝑅𝑡ℎ = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 , 𝐼𝐶 ≅ 1.51𝑚𝐴 , 𝑉𝐵𝐸 = 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝐼𝐸 𝑅𝐸 = 227.45𝑚𝑉
𝐼𝐶
𝐼𝑆 = 𝑉𝐵𝐸 ≅ 2.4 × 10−7 𝐴
𝑒 𝑉𝑇
5.11. Consider the circuit of Fig. 5.104, where β = 100, IS = 5 × 10−15 A and VA =∞. Calculate the value of IC and VCE.
Sol:
18𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 0.75𝑉 , 𝑅𝑡ℎ = 42𝐾Ω ∥ 18𝐾Ω = 12.6𝐾Ω
42𝐾Ω + 18𝐾Ω
Assume Q1 is at active region.
𝑉𝑡ℎ − 𝑉𝐵𝐸 𝐼𝐶
𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝑡ℎ + (1 + 𝛽)𝑅𝐸 𝐼𝑆
6
高雄科技大學電子系 兼任副教授李謨中
5.12. For the circuit of Fig. 5.105 where β = 100, IS = 5 × 10−15 A and VA =∞, what is the minimum value of RB that guarantees the
operation of Q1 in the active mode?
Sol:
Guarantees the operation of Q1 in the active mode, 𝑉𝐶𝐸 > 𝑉𝐵𝐸 .
At the edge of active region, 𝑉𝐶 = 𝑉𝐵 :
𝑉𝐶𝐶 − 𝑉𝐶𝐸 𝐼𝐶
𝐼𝐶 = , 𝑉𝐶𝐸 = 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐶 𝐼𝑆
5.13. For the CE stage depicted in Fig. 5.106, where β = 100, IS = 5 × 10−16 A and VA =∞, determine the gain, input, and output
impedance.
Sol:
16𝐾Ω
𝑉𝑡ℎ = 2𝑉 × = 0.8𝑉 , 𝑅𝑡ℎ = 24𝐾Ω ∥ 16𝐾Ω = 9.6𝐾Ω
24𝐾Ω + 16𝐾Ω
Assume Q1 is at active region.
𝑉𝑡ℎ − 𝑉𝐵𝐸 𝐼𝐶
𝑉𝑡ℎ = 𝐼𝐵 𝑅𝑡ℎ + 𝑉𝐵𝐸 , 𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝑡ℎ 𝐼𝑆
10𝐾Ω
𝑉𝑡ℎ = 3𝑉 × = 1𝑉 , 𝑅𝑡ℎ = 20𝐾Ω ∥ 10𝐾Ω = 6.67𝐾Ω
20𝐾Ω + 10𝐾Ω
Assume Q1 is at active region.
𝑉𝑡ℎ = 𝐼𝐵 𝑅𝑡ℎ + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸 , 1𝑉 = 5𝜇𝐴 × 6.67𝐾Ω + 658.54𝑚𝑉 + 505𝜇𝐴 × 𝑅𝐸
311.13𝑚𝑉
𝑅𝐸 = = 616.01Ω
505𝜇𝐴
7
高雄科技大學電子系 兼任副教授李謨中
5.15. In the circuit of Fig. 5.108, determine the value of R1 that guarantees operation of Q1 in the active mode. Assume β = 100, IS
= 10−16 A and VA =∞.
Sol:
Guarantees the operation of Q1 in the active mode, 𝑉𝐶𝐸 > 𝑉𝐵𝐸 .
At the edge of active region, 𝑉𝐶 = 𝑉𝐵 :
𝑉𝐶𝐶 − 𝑉𝐶𝐸 𝐼𝐶
𝐼𝐶 = , 𝑉𝐶𝐸 = 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐶 𝐼𝑆
15𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 1.5𝑉 , 𝑅𝑡ℎ = 10𝐾Ω ∥ 15𝐾Ω = 6𝐾Ω
10𝐾Ω + 15𝐾Ω
Q2 is at the edge of active region, assume Q1 is at active region.
𝑉𝑡ℎ − 𝑉𝐵𝐸1 − 𝑉𝐵𝐸2 𝐼𝐶1 𝛽 𝛽 𝐼𝐶2
𝐼𝐶1 = × 𝛽 , 𝑉𝐵𝐸1 = 𝑉𝑇 ln , 𝐼𝐶2 = × 𝐼𝐸2 = × 𝐼𝐸1 , 𝑉𝐵𝐸2 = 𝑉𝑇 ln
𝑅𝑡ℎ 𝐼𝑆 𝛽+1 𝛽+1 𝐼𝑆
𝛽 100 𝛽 100
𝑟𝜋1 = = ≅ 1.48𝐾Ω , 𝑟𝜋2 = = ≅ 1.46𝐾Ω
𝑔𝑚1 67.69𝑚𝑆 𝑔𝑚2 68.46𝑚𝑆
1
Q2 is a resistance with a value of ∥ 𝑟𝜋2 .
𝑔𝑚2
𝑣𝜋1 1
𝑣𝑖𝑛 = 𝑣𝜋1 + 𝑣𝑟𝜋2 = 𝑣𝜋1 + ( + 𝑔𝑚1 𝑣𝜋1 ) ( ∥ 𝑟 ) , 𝑣𝑜𝑢𝑡 = −𝑔𝑚1 𝑣𝜋1 𝑅𝐶
𝑟𝜋1 𝑔𝑚2 𝜋2
𝑣𝑜𝑢𝑡 −𝑔𝑚1 𝑣𝜋1 𝑅𝐶 −𝑔𝑚1 𝑅𝐶 −𝑅𝐶
𝐴𝑣 = = = = ≅ −3.4
𝑣𝑖𝑛 𝑣 1 1 1 1 1
𝑣𝜋1 + ( 𝜋1 + 𝑔𝑚1 𝑣𝜋1 ) ( ∥ 𝑟𝜋2 ) 1 + ( + 𝑔𝑚1 ) ( ∥ 𝑟𝜋2 ) 𝑔 + 𝑔
𝑟𝜋1 𝑔𝑚2 𝑟𝜋1 𝑔𝑚2 𝑚1 𝑚2
8
高雄科技大學電子系 兼任副教授李謨中
5.17. Consider the circuit of Fig. 5.110, where IS1 = 2IS2 = 3IS3 = 5 × 10−15A, β1 = β2 = β3 = 100, and VA =∞. Determine collector
currents ofQ1, Q2 and Q3.
Sol:
12𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 1.2𝑉 , 𝑅𝑡ℎ = 13𝐾Ω ∥ 12𝐾Ω = 6.24𝐾Ω
13𝐾Ω + 12𝐾Ω
Q3 is at the edge of active region, assume Q1 and Q2 is at active region.
3 3.03 𝐼𝐸3
𝐼𝑆1 = 2𝐼𝑆2 ⟹ 𝐼𝐶1 = 2𝐼𝐶2 , 𝐼𝐸3 = 𝐼𝐸1 + 𝐼𝐸2 = 𝐼𝐸1 = 𝐼𝐶1 , 𝐼𝐶3 = = 1.5𝐼𝐶1
2 2 1.01
𝑉𝐶𝐶 −𝑉𝐵𝐸 𝐼𝐶 X
By KVL: 𝑉𝐶𝐶 = 𝐼𝐸 𝑅𝐶 + 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 , 𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐵 +(1+𝛽)𝑅𝐶 𝐼𝑆
9
高雄科技大學電子系 兼任副教授李謨中
5.20. Due to a manufacturing error, a parasitic resistor, RP, has appeared in series with the collector of Q1 in Fig. 5.113. What is
the minimum allowable value of RB if the base-collector forward bias must not exceed 200 mV? Assume IS = 3 × 10−16 A, β
= 100, and VA =∞.
Sol:
Base-collector forward bias must not exceed 200 mV, Q1 is at soft saturation region.
𝑉𝐶𝐶 −𝑉𝐵𝐸 +200𝑚𝑉 𝐼𝐶
By KVL: 𝑉𝐶𝐶 = 𝐼𝐸 𝑅𝐶 + 𝐼𝐶 𝑅𝑃 − 200𝑚𝑉 + 𝑉𝐵𝐸 , 𝐼𝐶 = 𝛽+1 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝑃 + 𝑅 𝐼𝑆
𝛽 𝐶
𝑉𝐶𝐶 −𝑉𝐵𝐸 𝐼𝐶
By KVL: 𝑉𝐶𝐶 = 𝐼𝐸 (𝑅𝐶 + 𝑅𝐸 ) + 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 , 𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐵 +(1+𝛽)(𝑅𝐶 +𝑅𝐸 ) 𝐼𝑆
𝑉𝐶𝐶 −𝑉𝐵𝐸 𝐼𝐶
By KVL: 𝑉𝐶𝐶 = 𝐼𝐸 (𝑅𝐶 + 𝑅𝐸 ) + 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 , 𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐵 +(1+𝛽)(𝑅𝐶 +𝑅𝐸 ) 𝐼𝑆
10
高雄科技大學電子系 兼任副教授李謨中
5.24. Determine the bias point of circuit shown in Fig. 5.117 given IS = 9 × 10−16A, β = 100 and VA =∞.
Sol:
Assume Q1 is at active region.
𝑉𝐶𝐶 −𝑉𝐸𝐵 𝐼𝐶
By KVL: 𝑉𝐶𝐶 = 𝐼𝐸 𝑅𝐸 + 𝐼𝐵 𝑅𝐵 + 𝑉𝐸𝐵 , 𝐼𝐶 = × 𝛽 , 𝑉𝐸𝐵 = 𝑉𝑇 ln
𝑅𝐵 +(1+𝛽)𝑅𝐸 𝐼𝑆
18𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 900𝑚𝑉 , 𝑅𝑡ℎ = 32𝐾Ω ∥ 18𝐾Ω = 11.52𝐾Ω
32𝐾Ω + 18𝐾Ω
Assume Q1 is at active region.
18𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 900𝑚𝑉 , 𝑅𝑡ℎ = 32𝐾Ω ∥ 18𝐾Ω = 11.52𝐾Ω
32𝐾Ω + 18𝐾Ω
Q1 is at the edge of active region, assume Q2 is at active region.
𝐼𝐶2 𝐼𝐶1
𝑉𝐸𝐵2 = 𝑉𝑇 ln , 𝑉𝐵𝐸1 = 𝑉𝑇 ln
𝐼𝑆 𝐼𝑆
11
高雄科技大學電子系 兼任副教授李謨中
5.26. Calculate the value of RE in Fig. 5.119 such that Q1 sustains a reverse bias of 300 mV across its base-collector junction.
Assume β = 50, IS = 8 × 10−16 A, and VA =∞. What happens if the value of RE is halved?
Sol:
10𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 1.25𝑉 , 𝑅𝑡ℎ = 10𝐾Ω ∥ 10𝐾Ω = 5𝐾Ω
10𝐾Ω + 10𝐾Ω
A reverse bias of 300 mV across its base-collector junction, Q1 is at active region.
1.25𝑉 − 0.3𝑉
𝑉𝐵𝐶 = 𝑉𝑡ℎ + 𝐼𝐵 𝑅𝑡ℎ − 𝐼𝐶 𝑅𝐶 , 𝐼𝐶 = ≅ 193.88𝜇𝐴
5𝐾Ω
5𝐾Ω −
50
𝐼𝐶 193.88𝜇𝐴
𝑉𝐸𝐵 = 𝑉𝑇 ln = 26𝑚𝑉 × ln ≅ 681.55𝑚𝑉
𝐼𝑆 8 × 10−16 𝐴
𝑉𝐶𝐶 −𝑉𝐸𝐵 𝐼𝐶
By KVL: 𝑉𝐶𝐶 = 𝑉𝐸𝐵 + 𝐼𝐶 𝑅𝐶 , 𝐼𝐶 = , 𝑉𝐸𝐵 = 𝑉𝑇 ln
𝑅𝐶 𝐼𝑆
𝑅𝑡ℎ 1.76𝑚𝐴
𝑉𝑡ℎ + 𝐼𝐵 𝑅𝑡ℎ = 𝑉𝐵 , 2.5𝑉 × + × 𝑅𝑡ℎ = 1.76𝑉 , 𝑅𝑡ℎ ≅ 3.29𝐾Ω
5𝐾Ω 50
𝑅1 × 𝑅2 5𝐾Ω × 𝑅𝐵
𝑅𝑡ℎ = 𝑅1 ∥ 𝑅2 = = , 𝑅 ≅ 9.62𝐾Ω
𝑅1 + 𝑅2 5𝐾Ω + 𝑅𝐵 𝐵
𝑅𝐵 𝑐ℎ𝑎𝑛𝑔𝑒 + 5% , 𝑅𝐵 ≅ 10.1𝐾Ω
10.1𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × ≅ 1.67𝑉 , 𝑅𝑡ℎ = 5𝐾Ω ∥ 10.1𝐾Ω ≅ 3.34𝐾Ω
5𝐾Ω + 10.1𝐾Ω
12
高雄科技大學電子系 兼任副教授李謨中
9.14𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × ≅ 1.62𝑉 , 𝑅𝑡ℎ = 5𝐾Ω ∥ 9.14𝐾Ω ≅ 3.23𝐾Ω
5𝐾Ω + 9.14𝐾Ω
5.30. We wish to design the CE stage of Fig. 5.123 for a voltage gain of 20. What is the minimum allowable supply voltage if Q1
must remain in the active mode? Assume VA =∞ and VBE = 0.8V.
Sol:
𝐼𝐶 20
𝐴𝑣 = 20 , 𝑔𝑚 = = , 𝐼 = 10.4𝜇𝐴
𝑉𝑇 𝑅𝐶 𝐶
At the edge of active region, 𝑉𝐵 = 𝑉𝐶 , 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 = 𝑉𝐵𝐸 , 𝑉𝐶𝐶 = 10.4𝜇𝐴 × 50𝐾Ω + 0.8𝑉 = 1.32𝑉
𝑉𝐶𝐶 ≥ 1.32𝑉
5.31. The circuit of Fig. 5.124 must be designed for maximum gain while maintaining Q1 in the active mode. If VA = 10 V and VBE
= 0.8 V, calculate the required bias current.
Sol:
Be designed for maximum gain, Q1 is in the edge of active mode. We don’t have β, assume IC=IE.
3𝑉−0.8𝑉 𝐼𝐶
By KVL: 𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸 , 𝐼𝐶 = ≅ 1.47𝑚𝐴 , 𝐼𝐵 =
1.5𝐾Ω 𝛽
𝑣𝜋
𝑣𝑖𝑛 = 𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 , 𝑣𝑜𝑢𝑡 = −𝑔𝑚 𝑣𝜋 × {𝑅𝐶 ∥ [𝑟𝑂 + (𝑅𝐸 ∥ 𝑟𝜋 ) + 𝑔𝑚 𝑟𝑂 (𝑅𝐸 ∥ 𝑟𝜋 )]}
𝑟𝜋
13
高雄科技大學電子系 兼任副教授李謨中
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑣𝜋 × {𝑅𝐶 ∥ [𝑟𝑂 + (𝑅𝐸 ∥ 𝑟𝜋 ) + 𝑔𝑚 𝑟𝑂 (𝑅𝐸 ∥ 𝑟𝜋 )]} −𝑔𝑚 × {𝑅𝐶 ∥ [𝑔𝑚 𝑟𝑂 (𝑅𝐸 ∥ 𝑟𝜋 )]}
𝐴𝑣 = = 𝑣 ≈
𝑣𝑖𝑛 𝜋
𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 1 + 𝑔𝑚 𝑅𝐸
𝑟𝜋
𝐼𝐶 1.47𝑚𝐴 𝑉𝐴 10𝑉 𝑉𝑇
𝑔𝑚 = = ≅ 56.54𝑚𝑆 , 𝑟𝑂 = = ≅ 6.8𝐾Ω , 𝑟𝜋 = × 𝛽 ≅ 1.77𝐾Ω
𝑉𝑇 26𝑚𝑉 𝐼𝐶 1.47𝑚𝐴 𝐼𝐶
𝑉𝐵𝐸
5.32. Suppose the bipolar transistor in Fig. 5.125 exhibits the following hypothetical characteristic: 𝐼𝐶 = 𝐼𝑆 𝑒𝑥𝑝( ), and no
2𝑉𝑇
Early effect. Compute the voltage gain for a bias current of 1 mA.
Sol:
𝐼𝐶 1𝑚𝐴
𝐴𝑣 = −𝑔𝑚 𝑅𝐶 = − × 𝑅𝐶 = − × 1𝐾Ω ≅ −19.23
2𝑉𝑇 2 × 26𝑚𝑉
5.33. The CE stage of Fig. 5.126 employs an ideal current source as the load. If the voltage gain is equal to 50 and the output
impedance equal to 10 kΩ, determine the bias current of the transistor.
Sol:
𝐼𝐶
𝑅𝑜𝑢𝑡 = 10𝐾Ω , 𝐴𝑣 = −𝑔𝑚 𝑅𝑜𝑢𝑡 = − 𝑅 = −50 , 𝐼𝐶 = 130𝜇𝐴
𝑉𝑇 𝑜𝑢𝑡
**5.34. Determine the voltage gain and I/O impedances of the circuits shown in Fig. 5.127. Assume VA =∞. Transistor Q2 in Figs.
5.127(d) and (e) operates in soft saturation.
Sol:
(a)
1 1
𝑅𝑖𝑛 = 𝑟𝜋1 , 𝑅𝑜𝑢𝑡 = ∥ 𝑟𝜋2 , 𝐴𝑣 = −𝑔𝑚1 𝑅𝑜𝑢𝑡 = −𝑔𝑚1 ( ∥𝑟 )
𝑔𝑚2 𝑔𝑚2 𝜋2
(b)
1 1
𝑅𝑖𝑛 = 𝑟𝜋1 , 𝑅𝑜𝑢𝑡 = 𝑅1 + ∥ 𝑟𝜋2 , 𝐴𝑣 = −𝑔𝑚1 𝑅𝑜𝑢𝑡 = −𝑔𝑚1 (𝑅1 + ∥𝑟 )
𝑔𝑚2 𝑔𝑚2 𝜋2
(c)
1 1
𝑅𝑖𝑛 = 𝑟𝜋1 , 𝑅𝑜𝑢𝑡 = 𝑅𝐶 + ( ∥ 𝑟𝜋2 ) , 𝐴𝑣 = −𝑔𝑚1 𝑅𝑜𝑢𝑡 = −𝑔𝑚1 (𝑅𝐶 + ( ∥ 𝑟 ))
𝑔𝑚2 𝑔𝑚2 𝜋2
14
高雄科技大學電子系 兼任副教授李謨中
(d)
1 1
𝑅𝑖𝑛 = 𝑟𝜋1 , 𝑅𝑜𝑢𝑡 = ∥ 𝑟𝜋2 , 𝐴𝑣 = −𝑔𝑚1 𝑅𝑜𝑢𝑡 = −𝑔𝑚1 ( ∥𝑟 )
𝑔𝑚2 𝑔𝑚2 𝜋2
(e)
𝑣𝜋2
𝑣𝜋2 𝑣𝜋2 𝑣𝑋 𝑟𝜋2 (𝑅𝐶 + 𝑟𝜋2 ) 𝑅𝐶 + 𝑟𝜋2
𝑣𝑋 = (𝑅𝐶 + 𝑟𝜋2 ) , 𝑖𝑋 = + 𝑔𝑚2 𝑣𝜋2 , 𝑅𝑜𝑢𝑡 = = 𝑣 =
𝑟𝜋2 𝑟𝜋2 𝑖𝑋 𝜋2
+ 𝑔𝑚2 𝑣𝜋2 1 + 𝑔𝑚2 𝑟𝜋2
𝑟𝜋2
𝑅𝐶 + 𝑟𝜋2 𝑅𝐶 + 𝑟𝜋2
𝑅𝑖𝑛 = 𝑟𝜋1 , 𝑅𝑜𝑢𝑡 = , 𝐴𝑣 = −𝑔𝑚1 𝑅𝑜𝑢𝑡 = −𝑔𝑚1 ×
1 + 𝑔𝑚2 𝑟𝜋2 1 + 𝑔𝑚2 𝑟𝜋2
5.35. Calculate the voltage gain of the stage shown in Fig. 5.128, if the voltage drop across RC is 1 V, β = 100 and VA =∞.
Sol:
𝐼𝐶 𝛽 𝛽𝑉𝑇
𝑉𝑅𝐶 = 1𝑉 , 𝐼𝐶 = 1𝑚𝐴 , 𝑔𝑚 = , 𝑟𝜋 = = = 2.6𝐾Ω
𝑉𝑇 𝑔𝑚 𝐼𝐶
𝑣𝜋
𝑣𝑖𝑛 = 𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 , 𝑣𝑜𝑢𝑡 = −𝑔𝑚 𝑣𝜋 𝑅𝐶
𝑟𝜋
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑣𝜋 𝑅𝐶 −𝑔𝑚 𝑅𝐶 −𝛽𝑅𝐶
𝐴𝑣 = = 𝑣 = = ≅ −1.36
𝑣𝑖𝑛 𝑣𝜋 + ( 𝜋 + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 1 + ( 1 + 𝑔𝑚 ) 𝑅𝐸 𝑟𝜋 + (1 + 𝛽)𝑅𝐸
𝑟𝜋 𝑟𝜋
5.36. Design the degenerated stage of Fig. 5.129 for a voltage gain of 5. Calculate the bias currents and value of RE, if β = 100, IS
= 5 × 10−16 A and VA =∞. Calculate the input impedance of the circuit.
Sol:
𝛽 𝛽𝑉𝑇 −𝛽𝑅𝐶 −𝛽𝑅𝐶 −𝐼𝐶 𝑅𝐶 𝐼𝐶 𝑅𝐶
𝑟𝜋 = = , 𝐴𝑣 = = = = −5 , 𝐼𝐸 𝑅𝐸 = − 𝑉𝑇
𝑔𝑚 𝐼𝐶 𝑟𝜋 + (1 + 𝛽)𝑅𝐸 𝛽𝑉𝑇 (1 𝑉𝑇 + 𝐼𝐸 𝑅𝐸 5
+ + 𝛽)𝑅𝐸
𝐼𝐶
Assume Q1 is at the edge of active region. VB=VC
𝑉𝐶𝐶 −𝑉𝐵𝐸 +𝑉𝑇 𝐼𝐶
By KVL: 𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 + 𝐼𝐸 𝑅𝐸 , 𝐼𝐶 = 6 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅 𝐼𝑆
5 𝐶
15
高雄科技大學電子系 兼任副教授李謨中
5.37. Construct the small-signal model of the CE stage shown in Fig. 5.43(a) and calculate the voltage gain. Assume VA =∞.
Sol:
𝑣𝜋 𝑣𝜋
𝑣𝑖𝑛 = × (𝑅𝐵 + 𝑟𝜋 ) + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 , 𝑣𝑜𝑢𝑡 = −𝑔𝑚 𝑣𝜋 𝑅𝐶
𝑟𝜋 𝑟𝜋
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑣𝜋 𝑅𝐶 −𝑔𝑚 𝑅𝐶
𝐴𝑣 = =𝑣 𝑣𝜋 =
𝑣𝑖𝑛 𝜋
× (𝑅𝐵 + 𝑟𝜋 ) + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 1 1
𝑟𝜋 𝑟𝜋 × (𝑅𝐵 + 𝑟𝜋 ) + ( + 𝑔𝑚 ) 𝑅𝐸
𝑟𝜋 𝑟𝜋
−𝑅𝐶 −𝑅𝐶
= ≈
1 1 𝑅𝐵 1
× (𝑅𝐵 + 𝑟𝜋 ) + ( + 1) 𝑅𝐸 1 + 𝛽 + 𝑔 + 𝑅𝐸
𝛽 𝛽 𝑚
**5.38. Determine the voltage gain and I/O impedances of the circuits shown in Fig. 5.130. Assume VA =∞.
Sol:
(a)
𝑣𝜋1 𝑣𝜋1
𝑣𝑖𝑛 = 𝑣𝜋1 + ( + 𝑔𝑚1 𝑣𝜋1 ) 𝑅𝐸 , 𝑖𝑖𝑛 =
𝑟𝜋1 𝑟𝜋1
𝑣𝜋1
𝑣𝑖𝑛 𝑣𝜋1 + ( 𝑟𝜋1 + 𝑔𝑚1 𝑣𝜋1 ) 𝑅𝐸
𝑅𝑖𝑛 = = 𝑣𝜋1 = 𝑟𝜋1 + (1 + 𝛽)𝑅𝐸
𝑖𝑖𝑛
𝑟𝜋1
1 1
𝑅𝑜𝑢𝑡 = 𝑅1 + (𝑟𝜋2 ∥ ) , 𝑣𝑜𝑢𝑡 = −𝑔𝑚1 𝑣𝜋1 × [𝑅1 + (𝑟𝜋2 ∥ )]
𝑔𝑚2 𝑔𝑚2
1 1
𝑣𝑜𝑢𝑡 −𝑔𝑚1 𝑣𝜋1 × [𝑅1 + (𝑟𝜋2 ∥ 𝑔𝑚2 )] −𝑔𝑚1 × [𝑅1 + (𝑟𝜋2 ∥ 𝑔𝑚2 )]
𝐴𝑣 = = 𝑣 =
𝑣𝑖𝑛 𝑣𝜋1 + ( 𝜋1 + 𝑔𝑚1 𝑣𝜋1 ) 𝑅𝐸 1
𝑟𝜋1 1+( + 𝑔𝑚1 ) 𝑅𝐸
𝑟𝜋1
(b)
1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽) (𝑟𝜋2 ∥ ) , 𝑅𝑜𝑢𝑡 = 𝑅𝐶
𝑔𝑚2
−𝑔𝑚1 𝑅𝐶
𝐴𝑣 =
1 1
1 + ( + 𝑔𝑚1 ) (𝑟𝜋2 ∥ )
𝑟𝜋1 𝑔𝑚2
(c)
1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽) (𝑟𝜋2 ∥ ) , 𝑅𝑜𝑢𝑡 = 𝑅𝐶
𝑔𝑚2
−𝑔𝑚1 𝑅𝐶
𝐴𝑣 =
1 1
1+( + 𝑔𝑚1 ) (𝑟𝜋2 ∥ )
𝑟𝜋1 𝑔𝑚2
(d)
1
𝑅𝑖𝑛 = 𝑅𝐵 + 𝑟𝜋1 + (1 + 𝛽) (𝑟𝜋2 ∥ ) , 𝑅𝑜𝑢𝑡 = 𝑅𝐶
𝑔𝑚2
−𝑔𝑚1 𝑅𝐶
𝐴𝑣 =
𝑅𝐵 1 1
+1+( + 𝑔𝑚1 ) (𝑟𝜋2 ∥ )
𝑟𝜋1 𝑟𝜋1 𝑔𝑚2
(e)
1
𝑅𝑖𝑛 = 𝑅𝐵 + 𝑟𝜋1 + (1 + 𝛽) (𝑟𝜋2 ∥ ) , 𝑅𝑜𝑢𝑡 = 𝑅𝐶
𝑔𝑚2
16
高雄科技大學電子系 兼任副教授李謨中
−𝑔𝑚1 𝑅𝐶
𝐴𝑣 =
𝑅𝐵 1 1
+1+( + 𝑔𝑚1 ) (𝑟𝜋2 ∥ )
𝑟𝜋1 𝑟𝜋1 𝑔𝑚2
**5.39. Compute the voltage gain the I/O impedances of the circuits depicted in Fig. 5.131. Assume VA =∞.
Sol:
(a)
1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽)𝑅𝐸 , 𝑅𝑜𝑢𝑡 = 𝑅1 + (𝑟𝜋2 ∥ )
𝑔𝑚2
1
−𝑔𝑚1 × [𝑅1 + (𝑟𝜋2 ∥ )]
𝑔𝑚2
𝐴𝑣 =
1
1+( + 𝑔𝑚1 ) 𝑅𝐸
𝑟𝜋1
(b)
1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽)𝑅𝐸 , 𝑅𝑜𝑢𝑡 = 𝑟𝜋2 ∥ , 𝑣𝑖𝑛 𝑔𝑟𝑜𝑢𝑛𝑒𝑑, 𝑣𝜋1 = 0
𝑔𝑚2
1
−𝑔𝑚1 × (𝑟𝜋2 ∥ )
𝑔𝑚2
𝐴𝑣 =
1
1+( + 𝑔𝑚1 ) 𝑅𝐸
𝑟𝜋1
(c)
1 1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽) (𝑟𝜋3 ∥ ) , 𝑅𝑜𝑢𝑡 = 𝑅𝐶 + (𝑟𝜋2 ∥ )
𝑔𝑚3 𝑔𝑚2
1
−𝑔𝑚1 × [𝑅𝐶 + (𝑟𝜋2 ∥ )]
𝑔𝑚2
𝐴𝑣 =
1 1
1+( + 𝑔𝑚1 ) (𝑟𝜋3 ∥ )
𝑟𝜋1 𝑔𝑚3
(d)
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽)𝑅𝐸 , 𝑅𝑜𝑢𝑡 = 𝑅𝐶 ∥ 𝑟𝜋2
−𝑔𝑚1 × (𝑅𝐶 ∥ 𝑟𝜋2 )
𝐴𝑣 =
1
1 + ( + 𝑔𝑚1 ) 𝑅𝐸
𝑟𝜋1
*5.40. Compare the output impedances of the circuits illustrated in Fig. 5.132. Assume 𝛽 ≫ 1.
Sol:
(a)
𝑣𝜋 = −𝑖𝑋 (𝑅𝐸 ∥ 𝑟𝜋 )
𝑣𝑋 = (𝑖𝑋 − 𝑔𝑚 𝑣𝜋 )𝑟𝑂 − 𝑣𝜋 = [𝑖𝑋 + 𝑔𝑚 𝑖𝑋 (𝑅𝐸 ∥ 𝑟𝜋 )]𝑟𝑂 + 𝑖𝑋 (𝑅𝐸 ∥ 𝑟𝜋 )
𝑣𝑋
𝑅𝑜𝑢𝑡 = = [1 + 𝑔𝑚 (𝑅𝐸 ∥ 𝑟𝜋 )]𝑟𝑂 + (𝑅𝐸 ∥ 𝑟𝜋 ) = 𝑟𝑂 + (𝑔𝑚 𝑟𝑂 + 1)(𝑅𝐸 ∥ 𝑟𝜋 )
𝑖𝑋
1 1
𝑅𝐸 = 𝑟𝜋1 ∥ ∥ 𝑟𝑂1 , 𝑅𝑜𝑢𝑡 = 𝑟𝑂2 + (𝑔𝑚2 𝑟𝑂2 + 1) [(𝑟𝜋1 ∥ ∥ 𝑟 ) ∥ 𝑟𝜋2 ]
𝑔𝑚1 𝑔𝑚1 𝑂1
(b)
𝑅𝐸 = 𝑟𝑂1
𝑅𝑜𝑢𝑡 = 𝑟𝑂2 + (𝑔𝑚2 𝑟𝑂2 + 1)(𝑟𝑂1 ∥ 𝑟𝜋2 )
17
高雄科技大學電子系 兼任副教授李謨中
*5.41. Calculate the output impedance of the circuits shown in Fig. 5.133. Assume 𝛽 ≫ 1.
Sol:
(a)
1
𝑅𝑜𝑢𝑡 = 𝑟𝑂1 + (𝑔𝑚1 𝑟𝑂1 + 1) [(𝑟𝜋2 ∥ ∥ 𝑟 ) ∥ 𝑟𝜋1 ]
𝑔𝑚2 𝑂2
(b)
1 𝑅𝐵
𝑅𝑜𝑢𝑡 = 𝑟𝑂1 + (𝑔𝑚1 𝑟𝑂1 + 1) [( + ) ∥ 𝑟𝜋1 ]
𝑔𝑚2 1 + 𝛽
(c)
𝑅𝐸 = 𝑅1 ∥ 𝑟𝜋2
𝑅𝑜𝑢𝑡 = 𝑟𝑂1 + (𝑔𝑚1 𝑟𝑂1 + 1)(𝑅1 ∥ 𝑟𝜋2 ∥ 𝑟𝜋1 )
5.42. Calculate vout/vin for each of the circuits depicted in Fig. 5.134. Assume IS = 8 × 10−16 A, β = 100, and VA =∞. Also, assume
the capacitors are very large.
Sol:
(a)
By KVL: 𝑉𝐶𝐶 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸
Assume Q1 is at the active region.
𝑉𝐶𝐶 − 𝑉𝐵𝐸 𝐼𝐶
𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐵 + (1 + 𝛽)𝑅𝐸 𝐼𝑆
18
高雄科技大學電子系 兼任副教授李謨中
11𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × = 1.1𝑉 , 𝑅𝑡ℎ = 14𝐾Ω ∥ 11𝐾Ω = 6.16𝐾Ω
14𝐾Ω + 11𝐾Ω
By KVL: 𝑉𝑡ℎ = 𝐼𝐵 𝑅𝑡ℎ + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸
Assume Q1 is at the active region.
𝑉𝑡ℎ − 𝑉𝐵𝐸 𝐼𝐶
𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝑡ℎ + (1 + 𝛽)𝑅𝐸 𝐼𝑆
5.44. Determine the voltage gain of the circuits shown in Fig. 5.136. Assume VA =∞, IC = 2 mA and βnpn = 2βpnp = 100.
Sol:
(a)
19
高雄科技大學電子系 兼任副教授李謨中
𝛽𝑛𝑝𝑛 100
𝑟𝜋2 = = ≅ 1.3𝐾Ω = 𝑟𝜋1
𝑔𝑚2 76.92𝑚𝑆
1 1
𝐴𝑣 = 𝑔𝑚1 × (𝑅𝐶 + ∥ 𝑟𝜋2 ) = 76.92𝑚𝑆 × (1𝐾Ω + ∥ 1.3𝐾Ω) ≅ 77.91
𝑔𝑚2 76.92𝑚𝑆
(b)
Assume Q1 and Q2 is at active region.
𝑣𝜋2 = 0 → 𝑔𝑚2 𝑣𝜋2 = 0 , 𝑚𝑢𝑠𝑡 𝑏𝑒 𝑐𝑜𝑛𝑠𝑖𝑑𝑒𝑟 𝑟𝑂 .
𝐴𝑣 = 𝑔𝑚1 × 𝑟𝑂2 = ∞
(c)
Assume Q1 and Q2 is at active region.
𝐼𝐶1 𝛽𝑝𝑛𝑝 50
𝐼𝐶1 = 2𝑚𝐴 , 𝑔𝑚1 = ≅ 76.92𝑚𝑆 = 𝑔𝑚2 , 𝑟𝜋2 = = ≅ 650.03Ω
𝑉𝑇 𝑔𝑚2 76.92𝑚𝑆
1 1
𝐴𝑣 = 𝑔𝑚1 × (𝑅𝐶 + ∥ 𝑟𝜋2 ) = 76.92𝑚𝑆 × (1𝐾Ω + ∥ 650.03Ω) ≅ 77.9
𝑔𝑚2 76.92𝑚𝑆
5.45. Compute the input impedance of the stages shown in Fig. 5.137. Assume VA =∞, IC = 2 mA and β = 100.
Sol:
(a)
Assume Q1 and Q2 is at active region.
𝐼𝐶1 𝛽
𝐼𝐶1 = 2𝑚𝐴 , 𝑔𝑚1 = ≅ 76.92𝑚𝑆 , 𝐼𝐵1 = 𝐼𝐸2 , 𝐼𝐶2 = 𝐼 ≅ 19.8𝜇𝐴
𝑉𝑇 1 + 𝛽 𝐸2
𝑅2 𝑣𝜋 1
𝑣𝑖𝑛 = −(𝑣𝜋 + 𝑣𝑅2 ) = −𝑣𝜋 (1 + ) , 𝑖𝑖𝑛 = − ( + 𝑔𝑚 𝑣𝜋 ) = −𝑣𝜋 ( + 𝑔𝑚 )
𝑟𝜋 𝑟𝜋 𝑟𝜋
(c)
Assume Q1 and Q2 is at active region. 𝐴𝑠𝑠𝑢𝑚𝑒 𝐼𝐶1 = 𝐼𝐶2
20
高雄科技大學電子系 兼任副教授李謨中
𝑣𝜋 1 𝑣𝜋
𝑣𝑖𝑛 = − {𝑣𝜋 + [𝑅2 ∥ (𝑟𝜋2 ∥ )]} , 𝑖𝑖𝑛 = − ( + 𝑔𝑚 𝑣𝜋 )
𝑟𝜋 𝑔𝑚2 𝑟𝜋
1 1
𝑣𝑖𝑛 𝑟𝜋 + [𝑅2 ∥ (𝑟𝜋2 ∥ 𝑔𝑚2 )] 1.3𝐾Ω + [10𝐾Ω ∥ (1.3𝐾Ω ∥ 76.92𝑚𝑆)]
𝑅𝑖𝑛 = = = ≅ 12.999Ω
𝑖𝑖𝑛 1 + 𝑔𝑚 𝑟𝜋 101
𝑖𝑓 𝐼𝐶1 ≈ 10𝐼𝐶2 , 𝑔𝑚2 ≅ 7.69𝑚𝑆 , 𝑟𝜋2 ≅ 13𝐾Ω
1 1
𝑣𝑖𝑛 𝑟𝜋 + [𝑅2 ∥ (𝑟𝜋2 ∥ 𝑔𝑚2 )] 1.3𝐾Ω + [10𝐾Ω ∥ (13𝐾Ω ∥ 7.69𝑚𝑆)]
𝑅𝑖𝑛 = = = ≅ 14.13Ω
𝑖𝑖𝑛 1 + 𝑔𝑚 𝑟𝜋 101
5.46. Compute the input/output impedance and voltage gain of the stages shown in Fig. 5.138. Assume VA =∞.
Sol:
𝑣𝜋
𝑣𝑖𝑛 = −(𝑣𝑅𝑆 + 𝑣𝜋 ) , 𝑖𝑖𝑛 = − ( + 𝑔𝑚 𝑣𝜋 ) , 𝑣𝑜𝑢𝑡 = −𝑔𝑚 𝑣𝜋 𝑅𝐶
𝑟𝜋
𝑣𝜋 1
𝑣𝑖𝑛 [( 𝑟𝜋 + 𝑔𝑚 𝑣𝜋 ) 𝑅𝑆 + 𝑣𝜋 ] [(𝑟𝜋 + 𝑔𝑚 ) 𝑅𝑆 + 1]
𝑅𝑖𝑛 = = 𝑣 = , 𝑅𝑜𝑢𝑡 = 𝑅𝐶
𝑖𝑖𝑛 ( 𝜋 + 𝑔𝑚 𝑣𝜋 ) 1
𝑟𝜋 ( + 𝑔𝑚 )
𝑟𝜋
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑣𝜋 𝑅𝐶 𝑔𝑚 𝑅𝐶
𝐴𝑣 = = 𝑣𝜋 =
𝑣𝑖𝑛 1
− [( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝑆 + 𝑣𝜋 ] [( + 𝑔𝑚 ) 𝑅𝑆 + 1]
𝑟𝜋 𝑟𝜋
5.47. Consider CB stage depicted in Fig. 5.139, where β = 100, IS = 8 × 10−16 A, VA =∞ and CB is very large. (a) Calculate the
operating point of Q and (b) calculate the voltage gain.
Sol:
12𝐾Ω
𝑉𝑡ℎ = 2.5𝑉 × ≅ 1.1𝑉 , 𝑅𝑡ℎ = 15𝐾Ω ∥ 12𝐾Ω ≅ 6.67𝐾Ω
15𝐾Ω + 12𝐾Ω
By KVL: 𝑉𝑡ℎ = 𝐼𝐵 𝑅𝑡ℎ + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸
Assume Q1 is at the active region.
𝑉𝑡ℎ − 𝑉𝐵𝐸 𝐼𝐶
𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝑡ℎ + (1 + 𝛽)𝑅𝐸 𝐼𝑆
𝑣𝑜𝑢𝑡
𝑣𝑖𝑛 = −𝑣𝜋 , 𝑣𝑜𝑢𝑡 = −𝑔𝑚 𝑣𝜋 𝑅𝐶 , 𝐴𝑣 = = 𝑔𝑚 𝑅𝐶 = 36.28𝑚𝑆 × 1𝐾Ω = 36.28
𝑣𝑖𝑛
*5.48. Calculate the voltage gain and the I/O impedances of the stage depicted in Fig. 5.140 if VA =∞ and CB is very large.
Sol:
1
𝑅𝑖𝑛 = 𝑟𝜋 ∥ ,𝑅 = 𝑅1
𝑔𝑚 𝑜𝑢𝑡
𝐴𝑣 = 𝑔𝑚 𝑅1
21
高雄科技大學電子系 兼任副教授李謨中
5.49. Compute the voltage gain and I/O impedances of the stage shown in Fig. 5.141 if VA =∞ and CB is very large.
Sol:
1 1
𝑅𝑖𝑛 = 𝑟𝜋 ∥ , 𝑅𝑜𝑢𝑡 = 𝑅1 ∥ (𝑟𝜋2 ∥ )
𝑔𝑚 𝑔𝑚2
1
𝐴𝑣 = 𝑔𝑚 [𝑅1 ∥ (𝑟𝜋2 ∥ )]
𝑔𝑚2
5.50. Calculate the voltage gain of the circuit shown in Fig. 5.142. Assume VA<∞, β = 100 and gm = (26Ω)−1.
Sol:
𝑟𝜋
𝑣𝐴 = 𝑣𝜋 + 𝑣𝑅𝐸 , 𝑣𝑅𝐸 = 𝑣𝐴 − 𝑣𝜋 , 𝑣𝜋 = 𝑣𝐴 ×
𝑟𝜋 + (1 + 𝛽)𝑅𝐸
𝑣𝑜𝑢𝑡 − 𝑣𝑅𝐸 𝑅𝐶 𝑅𝐶
𝑣𝑜𝑢𝑡 = − (𝑔𝑚 𝑣𝜋 + ) 𝑅𝐶 = −𝑔𝑚 𝑣𝜋 𝑅𝐶 − 𝑣𝑜𝑢𝑡 + (𝑣 − 𝑣𝜋 )
𝑟𝑂 𝑟𝑂 𝑟𝑂 𝐴
𝑅𝐶 𝑣𝐴 𝑟𝜋 𝑅𝐶 𝑟𝜋
𝑣𝑜𝑢𝑡 (1 + ) = −𝑔𝑚 𝑅𝐶 × + 𝑣𝐴 (1 − )
𝑟𝑂 (1
𝑟𝜋 + + 𝛽)𝑅𝐸 𝑟𝑂 (1
𝑟𝜋 + + 𝛽)𝑅𝐸
𝑟𝜋 𝑅𝐶 𝑟𝜋 −𝑔𝑚 𝑅𝐶 𝑟𝜋 𝑟𝑂 − 𝑅𝐶 𝑟𝜋
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑅𝐶 × 𝑟𝜋 + (1 + 𝛽)𝑅𝐸 + 𝑟𝑂 (1 − 𝑟𝜋 + (1 + 𝛽)𝑅𝐸 ) 𝑟 + (1 + 𝛽)𝑅𝐸
+ 𝑅𝐶
= = 𝜋
𝑣𝐴 𝑅 𝑟𝑂 + 𝑅𝐶
1+ 𝐶
𝑟𝑂
−(𝑔𝑚 𝑟𝑂 + 1)𝑅𝐶 𝑟𝜋
𝑣𝑜𝑢𝑡 𝑣𝐴 𝑣𝑜𝑢𝑡 𝑟𝜋 + (1 + 𝛽)𝑅𝐸 + 𝑅𝐶
𝑟 + (1 + 𝛽)𝑅𝐸
𝐴𝑣 = = = × 𝜋
𝑣𝑖𝑛 𝑣𝑖𝑛 𝑣𝐴 𝑅𝐵 + 𝑟𝜋 + (1 + 𝛽)𝑅𝐸 𝑟𝑂 + 𝑅𝐶
5.51. The circuit of Fig. 5.143 provides two outputs. If IS1 = 3IS2, determine the relation between Vout1/Vin and Vout2/Vin. Assume VA
=∞.
Sol:
𝐼𝑆1 = 3𝐼𝑆2 , 𝐼𝐶1 = 3𝐼𝐶2 , 𝑔𝑚1 = 3𝑔𝑚2
𝑣𝑜𝑢𝑡1 𝑔𝑚1 𝑅𝐶 𝑣𝑜𝑢𝑡2 𝑔𝑚2 𝑅𝐶 𝑣𝑜𝑢𝑡1 𝑣𝑜𝑢𝑡2
= , = , ≈3
𝑣𝑖𝑛 1 + 𝑔𝑚1 𝑅𝑆 𝑣𝑖𝑛 1 + 𝑔𝑚2 𝑅𝑆 𝑣𝑖𝑛 𝑣𝑖𝑛
**5.52. Using a small-signal model, determine the voltage gain of a CB stage with emitter degeneration, a base resistance, and VA
< ∞. Assume β ≫1.
Sol:
𝑣𝑜𝑢𝑡 − 𝑣𝐸 𝑣𝜋
𝑣𝑜𝑢𝑡 = −(𝑖1 + 𝑔𝑚 𝑣𝜋 )𝑅𝐶 , 𝑖1 = , 𝑣𝐸 = − (𝑟𝜋 + 𝑅𝐵 )
𝑟𝑂 𝑟𝜋
𝑅 𝑣
𝑣𝑜𝑢𝑡 𝑣𝐸 − [𝑔𝑚 𝑣𝜋 𝑅𝐶 + 𝐶 𝜋 (𝑟𝜋 + 𝑅𝐵 )] 𝑣
𝑟𝑂 𝑟𝜋 𝜋
𝑣𝑜𝑢𝑡 = −( − + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐶 = = , 𝑣𝜋 = 𝐴𝑣𝑜𝑢𝑡
𝑟𝑂 𝑟𝑂 𝑅𝐶 𝐴
1+
𝑟𝑂
𝑣𝜋 𝑣𝜋 𝑣𝜋 𝑣𝑜𝑢𝑡 𝑣𝐸 𝑣𝜋
𝑣𝑖𝑛 = 𝑣𝐸 − 𝑣𝑅𝐸 = − (𝑟𝜋 + 𝑅𝐵 ) − (𝑖1 + 𝑔𝑚 𝑣𝜋 + ) 𝑅𝐸 = − (𝑟𝜋 + 𝑅𝐵 ) − ( − + 𝑔𝑚 𝑣𝜋 + ) 𝑅𝐸
𝑟𝜋 𝑟𝜋 𝑟𝜋 𝑟𝑂 𝑟𝑂 𝑟𝜋
𝑅
𝑣𝑜𝑢𝑡 𝐴 1 𝐴 𝐴 −1 1+ 𝐶
𝑟𝑂
= {− (𝑟𝜋 + 𝑅𝐵 ) − [ + (𝑟 + 𝑅𝐵 ) + 𝑔𝑚 𝐴 + ] 𝑅𝐸 } , A =
𝑣𝑖𝑛 𝑟𝜋 𝑟𝑂 𝑟𝑂 × 𝑟𝜋 𝜋 𝑟𝜋 − [𝑔𝑚 𝑅𝐶 +
𝑅𝐶
(𝑟 + 𝑅𝐵 )]
𝑟𝑂 × 𝑟𝜋 𝜋
22
高雄科技大學電子系 兼任副教授李謨中
5.53. For RE = 600Ω in Fig. 5.144, determine the bias current of Q1 such that the gain is equal to 0.9. Assume VA =∞.
Sol:
𝑣𝜋 𝑣𝜋
𝑣𝑖𝑛 = 𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 , 𝑣𝑜𝑢𝑡 = ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸
𝑟𝜋 𝑟𝜋
𝑣
𝑣𝑜𝑢𝑡 ( 𝜋 + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 𝑅𝐸 𝑅𝐸
𝑟𝜋
𝐴𝑣 = = 𝑣 = 𝑟 ≈ = 0.9 , 𝑔𝑚 ≅ 15𝑚𝑆
𝑣𝑖𝑛 𝜋 𝜋
𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐸 1 + 𝛽 + 𝑅𝐸 1
𝑟𝜋 + 𝑅𝐸
𝑔𝑚
𝐼𝐶
𝑔𝑚 = , 𝐼 = 𝑔𝑚 × 𝑉𝑇 = 15𝑚𝑆 × 26𝑚𝑉 = 390𝜇𝐴
𝑉𝑇 𝐶
5.54. The circuit of Fig. 5.144 must provide an input impedance of greater than 10 KΩ with a minimum gain of 0.9. Calculate the
required bias current and RE. Assume β = 100 and VA =∞.
Sol:
𝑅𝐸 𝑅𝐸 𝐼𝐶 𝑅𝐸
𝐴𝑣 ≈ = = > 0.9 , 𝐼𝐶 𝑅𝐸 > 9𝑉𝑇 = 234𝑚𝑉
1 𝑉𝑇 𝑉𝑇 + 𝐼𝐶 𝑅𝐸
+ 𝑅𝐸 𝐼 + 𝑅𝐸
𝑔𝑚 𝐶
𝑉𝑇
𝑅𝑖𝑛 = 𝑟𝜋 + (1 + 𝛽)𝑅𝐸 = 𝛽 × + (1 + 𝛽)𝑅𝐸 > 10𝐾Ω , 100𝑉𝑇 + 101𝐼𝐶 𝑅𝐸 > 10𝐾Ω × 𝐼𝐶
𝐼𝐶
𝑉𝑇 𝑅𝑆 26𝑚𝑉 200Ω
⟹ + ≤ 10Ω , + ≤ 10Ω , 𝐼𝐶 ≥ 3.24𝑚𝐴
𝐼𝐶 1 + 𝛽 𝐼𝐶 101
5.56. Compute the voltage gain and I/O impedances of the circuits shown in Fig. 5.146. Assume VA =∞.
Sol:
(a)
𝑉𝐴 = ∞ , 𝑟𝑂 = ∞ , 𝑅𝑖𝑛 = 𝑟𝜋1 + 𝑟𝑂2 = ∞
1 1
𝑅𝑜𝑢𝑡 = 𝑟𝜋1 ∥ ∥ 𝑟𝑂2 = 𝑟𝜋1 ∥
𝑔𝑚1 𝑔𝑚1
𝑟𝑂2
𝐴𝑣 = =1
1
𝑟𝑂2 +
𝑔𝑚1
(b)
1 1 1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽) (𝑟𝜋2 ∥ ) , 𝑅𝑜𝑢𝑡 = 𝑟𝜋1 ∥ ∥ 𝑟𝜋2 ∥
𝑔𝑚2 𝑔𝑚1 𝑔𝑚2
1
𝑟𝜋2 ∥
𝑔𝑚2
𝐴𝑣 =
1 1
(𝑟𝜋2 ∥ )+
𝑔𝑚2 𝑔𝑚1
(c)
1 𝑅𝑆 1 1 𝑅𝑆
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽) [(𝑟𝜋2 ∥ )+ ] , 𝑅𝑜𝑢𝑡 = 𝑟𝜋1 ∥ ∥ [(𝑟𝜋2 ∥ )+ ]
𝑔𝑚2 1+𝛽 𝑔𝑚1 𝑔𝑚2 1+𝛽
23
高雄科技大學電子系 兼任副教授李謨中
1 𝑅𝑆
[(𝑟𝜋2 ∥ )+ ]
𝑔𝑚2 1+𝛽
𝐴𝑣 =
1 𝑅𝑆 1
[(𝑟𝜋2 ∥ )+ ]+
𝑔𝑚2 1+𝛽 𝑔𝑚1
(d)
1 1 1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽) [𝑅𝐸 + (𝑟𝜋2 ∥ )] , 𝑅𝑜𝑢𝑡 = 𝑟𝜋1 ∥ ∥ [𝑅𝐸 + (𝑟𝜋2 ∥ )]
𝑔𝑚2 𝑔𝑚1 𝑔𝑚2
1
[𝑅𝐸 + (𝑟𝜋2 ∥ )]
𝑔𝑚2
𝐴𝑣 =
1 1
[𝑅𝐸 + (𝑟𝜋2 ∥ )] +
𝑔𝑚2 𝑔𝑚1
(e)
1 1 1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽) [𝑅𝐸 + (𝑟𝜋2 ∥ )] , 𝑅𝑜𝑢𝑡 = [(𝑟𝜋1 ∥ ) + 𝑅𝐸 ] ∥ (𝑟𝜋2 ∥ )
𝑔𝑚2 𝑔𝑚1 𝑔𝑚2
1
(𝑟𝜋2 ∥ )
𝑔𝑚2
𝐴𝑣 =
1 1
𝑅𝐸 + (𝑟𝜋2 ∥ )+
𝑔𝑚2 𝑔𝑚1
*5.57. Figure 5.147 depicts a “Darlington pair,” where Q1 plays a role somewhat similar to an emitter follower driving Q2.
Assume VA =∞ and the collectors of Q1 and Q2 are tied to VCC. Note that IE1(≈IC1) = IB2 = IC2/β. (a) If the emitter of Q2 is
grounded, determine the impedance seen at the base of Q1. (b) If the base of Q1 is grounded, calculate the impedance seen
at the emitter of Q2. (c) Compute the current gain of the pair, defined as (IC1 + IC2)/IB1.
Sol:
(a)
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽)𝑟𝜋2
(b)
1 1 1
𝑅𝑜𝑢𝑡 = (𝑟𝜋2 ∥ )+ (𝑟𝜋1 ∥ )
𝑔𝑚2 1+𝛽 𝑔𝑚1
(c)
𝐼𝐶1 + 𝐼𝐶2 𝐼𝐶1 𝐼𝐶2 𝛽𝐼𝐵2 𝐼𝐶1 + 𝐼𝐶2 𝛽 × 𝛽𝐼𝐵1
= + =𝛽+ , 𝐼𝐵2 = 𝐼𝐸1 ≈ 𝐼𝐶1 = 𝛽𝐼𝐵1 , =𝛽+ = 𝛽(1 + 𝛽)
𝐼𝐵1 𝐼𝐵1 𝐼𝐵1 𝐼𝐵1 𝐼𝐵1 𝐼𝐵1
5.58. Determine the voltage gain of the follower depicted in Fig. 5.148. Assume IS = 7 × 10−16 A, β = 100, and VA = 5 V. (But for
bias calculations, assume VA =∞.) Also, assume the capacitors are very large.
Sol:
Assume Q1 is at active region. By KVL:
𝑉𝐶𝐶 − 𝑉𝐵𝐸 𝐼𝐶
𝑉𝑐𝑐 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸 , 𝐼𝐶 = × 𝛽 , 𝑉𝐵𝐸 = 𝑉𝑇 ln
(1
𝑅𝐵 + + 𝛽)𝑅𝐸 𝐼𝑆
24
高雄科技大學電子系 兼任副教授李謨中
5.59. Assuming VA =∞ determine the voltage gain of the circuit shown in Fig. 5.149.
Sol:
𝑟𝜋 𝑟𝜋 + (1 + 𝛽)(𝑅𝐸 ∥ 𝑅2 )
𝑣𝜋 = 𝑉𝑋 × , 𝑉𝑋 = 𝑣𝜋 ×
𝑟𝜋 + (1 + 𝛽)(𝑅𝐸 ∥ 𝑅2 ) 𝑟𝜋
𝑅𝑋
𝑅𝑋 = 𝑟𝜋 + (1 + 𝛽)(𝑅𝐸 ∥ 𝑅2 ) , 𝑉𝑋 = 𝑣𝜋 ×
𝑟𝜋
𝑅1 ∥ 𝑅𝑋 𝑅𝑆 + 𝑅1 ∥ 𝑅𝑋 𝑅𝑆 (𝑅1 +𝑅𝑋 ) + 𝑅1 𝑅𝑋
𝑉𝑋 = 𝑣𝑖𝑛 × , 𝑣𝑖𝑛 = 𝑉𝑋 × = 𝑉𝑋 ×
𝑅𝑆 + (𝑅1 ∥ 𝑅𝑋 ) (𝑅1 ∥ 𝑅𝑋 ) 𝑅1 𝑅𝑋
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑣𝜋 𝑅𝐶 −𝑔𝑚 𝑅𝐶 −𝑔𝑚 𝑅𝐶 𝑟𝜋 𝑅1
𝑣𝑜𝑢𝑡 = −𝑔𝑚 𝑣𝜋 𝑅𝐶 , 𝐴𝑣 = = = =
𝑣𝑖𝑛 𝑅𝑋 𝑅𝑆 (𝑅1 +𝑅𝑋 ) + 𝑅1 𝑅𝑋 𝑅𝑆 (𝑅1 +𝑅𝑋 ) + 𝑅1 𝑅𝑋 𝑅𝑆 (𝑅1 +𝑅𝑋 ) + 𝑅1 𝑅𝑋
𝑣𝜋 × ×
𝑟𝜋 𝑅1 𝑅𝑋 𝑟𝜋 𝑅1
−𝑔𝑚 𝑅𝐶 𝑟𝜋 𝑅1
𝐴𝑣 =
𝑅𝑆 1 + 𝜋 + + 𝛽)(𝑅𝐸 ∥ 𝑅2 )]) + 𝑅1 [𝑟𝜋 + (1 + 𝛽)(𝑅𝐸 ∥ 𝑅2 )]
(𝑅 [𝑟 (1
5.60. Calculate the input and output impedances of the circuit depicted in Fig. 5.150. Determine the voltage gain.
Sol:
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽)(𝑅𝐸 ∥ 𝑟𝜋2 ∥ 𝑟𝑂1 )
𝑅𝑜𝑢𝑡 = 𝑅𝐶 ∥ 𝑟𝑂2
𝑅𝐸 ∥ 𝑟𝑂1
𝐴𝑣 = − × 𝑔𝑚2 (𝑅𝐶 ∥ 𝑟𝑂2 )
1
𝑅𝐸 ∥ 𝑟𝑂1 +
𝑔𝑚1
5.61. Figure 5.151 shows a cascade of an emitter follower and common base stage. Calculate the input/output impedances of the
circuit. Assume VA =∞, gm1 = gm2 = (26Ω)−1 and β = 100.
Sol:
1
𝑅𝑖𝑛 = 𝑟𝜋1 + (1 + 𝛽1 ) (𝑅𝐸 ∥ 𝑟𝜋2 ∥ ) , 𝑟𝜋1 = 𝑟𝜋2 = 2.6𝐾Ω
𝑔𝑚2
𝐼𝐶 0.26𝑚𝐴
𝑉𝐵𝐸 = 𝑉𝑇 ln = 26𝑚𝑉 × ln ≅ 696.66𝑚𝑉 , 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 = 2.24𝑉 > 𝑉𝐵𝐸 , Q1 is at active region.
𝐼𝑆 6×10−16 𝐴
2.5𝑉−696.66𝑚𝑉 𝑉𝑇 26𝑚𝐴
By KVL: 𝑉𝐶𝐶 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 , 𝐼𝐵 = = 2.6𝜇𝐴 , 𝑅𝐵 ≅ 693.59𝐾Ω , 𝑟𝜋 = 𝛽 × = 100 × = 10𝐾Ω
𝑅𝐵 𝐼𝐶 0.26𝑚𝐴
25
高雄科技大學電子系 兼任副教授李謨中
5.63. We wish to design the CE stage of Fig. 5.153 for maximum voltage gain but with an output impedance no greater than 500
Ω. Allowing the transistor to experience at most 400mVof base-collector forward bias, design the stage.
Sol:
𝑅𝑜𝑢𝑡 = 𝑅𝐶 ≤ 500Ω , 𝑅𝐶 = 500Ω
𝑉𝐶𝐶 − 𝑉𝐵𝐸 + 400𝑚𝑉 𝐼𝐶
𝑉𝐵𝐸 − (𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 ) ≤ 400𝑚𝑉 , 𝐼𝐶 ≥ , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐶 𝐼𝑆
𝐼𝐶 4.26𝑚𝐴
𝐴𝑣 = −𝑔𝑚 𝑅𝐶 = − × 𝑅𝐶 = − × 500Ω ≅ −81.92
𝑉𝑇 26𝑚𝑉
5.64. The CE stage of Fig. 5.153 must be designed for minimum supply voltage but with a voltage gain of 15 and an output
impedance of 2KΩ. If the transistor is allowed to sustain a base-collector forward bias of 400mV, design the stage and
calculate the required supply voltage.
Sol:
𝐼𝐶 15 × 𝑉𝑇 15 × 26𝑚𝑉
𝑅𝑜𝑢𝑡 = 𝑅𝐶 = 2𝐾Ω , 𝐴𝑣 = −𝑔𝑚 𝑅𝐶 = − × 𝑅𝐶 = −15 , 𝐼𝐶 = = = 195𝜇𝐴
𝑉𝑇 𝑅𝐶 2𝐾Ω
𝐼𝐶 195𝜇𝐴
𝑉𝐵𝐸 = 𝑉𝑇 ln = 26𝑚𝑉 × ln ≅ 689.18𝑚𝑉
𝐼𝑆 6 × 10−16 𝐴
𝑉𝐵𝐸 − (𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 ) ≤ 400𝑚𝑉 , 𝑉𝐶𝐶 ≥ 689.18𝑚𝑉 − 400𝑚𝑉 + 195𝜇𝐴 × 2𝐾Ω , 𝑉𝐶𝐶 ≥ 679.18𝑚𝑉 , 𝑤𝑒 𝑠𝑒𝑡 𝑉𝐶𝐶 = 690𝑚𝑉
690𝑚𝑉 − 689.18𝑚𝑉
𝑉𝐶𝐶 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 , 𝑅𝐵 = ≅ 420.51Ω
1.95𝜇𝐴
5.65. Design the degenerated CE stage of Fig. 5.154 for a voltage gain of 5 and an output impedance of 500Ω. Assume RE sustains
a voltage drop of 300 mV and the current flowing through R1 is approximately 10 times the base current.
Sol:
Assume Q1 is at active region.
𝑟𝜋 + (1 + 𝛽)𝑅𝐸
𝑅𝑜𝑢𝑡 = 𝑅𝐶 = 500Ω , 𝑣𝑖𝑛 = 𝑣𝜋 × , 𝑣𝑜𝑢𝑡 = −𝑔𝑚 𝑣𝜋 𝑅𝐶
𝑟𝜋
𝑣𝑜𝑢𝑡 −𝑔𝑚 𝑣𝜋 𝑅𝐶 −𝑔𝑚 𝑅𝐶 𝑟𝜋 𝛽𝑉𝑇
𝐴𝑣 = = = ,𝑟 =
𝑣𝑖𝑛 𝑟𝜋 + (1 + 𝛽)𝑅𝐸 𝑟𝜋 + (1 + 𝛽)𝑅𝐸 𝜋 𝐼𝐶
𝑣𝜋 ×
𝑟𝜋
𝛽𝑉𝑇
−𝑔𝑚 𝑅𝐶 −𝑔𝑚 𝑅𝐶 𝛽𝑉𝑇 −𝐼𝐶 𝑅𝐶 26𝑚𝑉 + 300𝑚𝑉
𝐼𝐶
𝐴𝑣 = = = = −5 , 𝐼𝐶 = 5 × = 3.26𝑚𝐴
𝛽𝑉𝑇 𝛽𝑉𝑇 + (1 + 𝛽)𝐼𝐶 𝑅𝐸 𝑉𝑇 + 𝐼𝐸 𝑅𝐸 500Ω
+ (1 + 𝛽)𝑅𝐸
𝐼𝐶
300𝑚𝑉 𝐼𝐶 3.26𝑚𝐴
𝐼𝐸 𝑅𝐸 = 300𝑚𝑉 , 𝑅𝐸 = ≅ 91.11Ω , 𝑉𝐵𝐸 = 𝑉𝑇 ln = 26𝑚𝑉 × ln ≅ 762.41𝑚𝑉
1.01 × 3.26𝑚𝐴 𝐼𝑆 6 × 10−16 𝐴
𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − 𝐼𝐸 𝑅𝐸 = 2.5𝑉 − 3.26𝑚𝐴 × 500Ω − 3.29𝑚𝐴 × 91.11Ω ≅ 570.25𝑚𝑉 , 𝑉𝐵𝐸 − 𝑉𝐶𝐸 = 192.16𝑚𝑉
Q1 is at soft saturation region, active region characteristics still apply.
𝑉𝐶𝐶 − 𝑉𝐵 𝑉𝐶𝐶 − 𝑉𝐵 2.5𝑉 − (762.41𝑚𝑉 + 300𝑚𝑉)
= 10𝐼𝐵 , 𝑅1 = = ≅ 4.41𝐾Ω
𝑅1 10𝐼𝐵 3.26𝑚𝐴
10 ×
100
26
高雄科技大學電子系 兼任副教授李謨中
𝑉𝐵𝐸 + 𝑉𝑅𝐸 762.41𝑚𝑉 + 300𝑚𝑉
𝑅2 = = ≅ 3.62𝐾Ω
9𝐼𝐵 3.26𝑚𝐴
9×
100
5.66. The stage of Fig. 5.154 must be designed for maximum voltage gain but an output impedance of no greater than 1KΩ.
Design the circuit, assuming that RE sustains 200 mV, the current flowing through R1 is approximately 10 times the base
current, and Q1 experiences a maximum base collector forward bias of 400 mV.
Sol:
𝑅𝑜𝑢𝑡 = 𝑅𝐶 = 1𝐾Ω
𝑉𝐶𝐶 + 400𝑚𝑉 − 𝑉𝐵𝐸 − 𝑉𝑅𝐸 𝐼𝐶
𝑉𝐵𝐶 = 𝑉𝐵 − 𝑉𝐶 = 𝑉𝐵𝐸 + 𝑉𝑅𝐸 − (𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 ) = 400𝑚𝑉 , 𝐼𝐶 = , 𝑉𝐵𝐸 = 𝑉𝑇 ln
𝑅𝐶 𝐼𝑆
5.67. Design the common-base stage shown in Fig. 5.155 for a voltage gain of 20 and an input impedance of 50Ω. Assume a
voltage drop of 10VT = 260mV across RE so that this resistor does not affect the input impedance significantly. Also, assume the
current flowing through R1 is approximately 10 times the base current, and the lowest frequency of interest is 200 Hz.
Sol:
Assume Q1 is at active region.
1 1 1
Assume 𝑟𝜋 and 𝑅𝐸 ≫ , 𝑅𝑖𝑛 = 𝑅𝐸 ∥ 𝑟𝜋 ∥ ≈ = 50Ω
𝑔𝑚 𝑔𝑚 𝑔𝑚
𝑉𝑇 26𝑚𝑉 260𝑚𝑉
= 50𝛺 , 𝐼𝐶 = = 520𝜇𝐴 , 𝐼𝐸 𝑅𝐸 = 260𝑚𝑉 , 𝑅𝐸 = ≅ 495.05Ω
𝐼𝐶 50𝛺 1.01 × 520𝜇𝐴
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高雄科技大學電子系 兼任副教授李謨中
5.68. The CB amplifier of Fig. 5.155 must achieve a voltage gain of 8 with an output impedance of 500Ω. Design the circuit with
the same assumptions as those in Problem 5.67.
Sol:
𝐼𝐶 8 × 26𝑚𝑉
𝑅𝑜𝑢𝑡 = 𝑅𝐶 = 500Ω , 𝐴𝑣 = −𝑔𝑚 𝑅𝐶 = × 𝑅𝐶 = −8 , 𝐼𝐶 = = 416𝜇𝐴
𝑉𝑇 500Ω
5.69. Design the emitter follower shown in Fig. 5.156 for a voltage gain of 0.85 and an input impedance of greater than 10 KΩ.
Assume RL = 200Ω.
Sol:
Assume Q1 is at active region.
𝑣𝜋 𝑣𝜋
𝑣𝑖𝑛 = 𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐿 , 𝑣𝑜𝑢𝑡 = ( + 𝑔𝑚 𝑣𝜋 )
𝑣𝜋 𝑣𝜋
𝑣
𝑣𝑜𝑢𝑡 ( 𝜋 + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐿 𝑅𝐿 𝑅𝐿
𝑟𝜋
𝐴𝑣 = = 𝑣 = 𝑟 = = 0.85 , 𝐼𝐶 ≅ 729.46𝜇𝐴
𝑣𝑖𝑛 𝜋 𝜋
𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐿 1 + 𝛽 + 𝑅𝐿 𝛽 𝑉𝑇
𝑟𝜋 × + 𝑅𝐿
1 + 𝛽 𝐼𝐶
𝐼𝐶 729.46𝜇𝐴
𝑉𝐵𝐸 = 𝑉𝑇 ln = 26𝑚𝑉 × ln ≅ 723.49𝑚𝑉
𝐼𝑆 6 × 10−16 𝐴
5.70. The follower shown in Fig. 5.157 must drive a load resistance, RL = 50Ω, with a voltage gain of 0.8. Design the circuit
assuming that the lowest frequency of interest is 100 MHz. (Hint: Select the voltage drop across RE to be much greater than
VT so that this resistor does not affect the voltage gain significantly.)
Sol:
Assume Q1 is at active region.
𝑣𝜋 𝑣𝜋
𝑣𝑖𝑛 = 𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) (𝑅𝐿 ∥ 𝑅𝐸 ) , 𝑣𝑜𝑢𝑡 = ( + 𝑔𝑚 𝑣𝜋 ) , 𝑅𝐿 ∥ 𝑅𝐸 ≈ 𝑅𝐿
𝑟𝜋 𝑟𝜋
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高雄科技大學電子系 兼任副教授李謨中
𝑣
𝑣𝑜𝑢𝑡 ( 𝜋 + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐿 𝑅𝐿 𝑅𝐿
𝑟𝜋
𝐴𝑣 = = 𝑣 = 𝑟 = = 0.8 , 𝐼𝐶 ≅ 2.06𝑚𝐴
𝑣𝑖𝑛 𝜋 𝜋
𝑣𝜋 + ( + 𝑔𝑚 𝑣𝜋 ) 𝑅𝐿 1 + 𝛽 + 𝑅𝐿 𝛽 𝑉𝑇
𝑟𝜋 × + 𝑅𝐿
1 + 𝛽 𝐼𝐶
𝐼𝐶 2.06𝑚𝐴
𝑉𝐵𝐸 = 𝑉𝑇 ln = 26𝑚𝑉 × ln ≅ 750.48𝑚𝑉 , 𝑅𝐸 ≫ 𝑅𝐿 , 𝐶ℎ𝑜𝑜𝑠𝑒 𝑅𝐸 = 500Ω
𝐼𝑆 6 × 10−16 𝐴
The lowest signal frequency of interest is 100 MHz, fcl =10 MHz.
𝑉𝑇
𝑟𝜋 = 𝛽 × ≅ 1.26𝐾Ω , 𝑅𝑖𝑛 = 𝑅1 ∥ [𝑟𝜋 + (1 + 𝛽)(𝑅𝐿 ∥ 𝑅𝐸 )] ≅ 5𝐾Ω
𝐼𝐶
1 1 1
𝑓𝑐𝑙 = , 𝐶1 = = ≅ 3.183 × 10−12 𝑓 = 3.183𝑝𝑓
2𝜋𝑅𝑖𝑛 𝐶1 2𝜋𝑓𝑐𝑙 𝑅𝑖𝑛 2𝜋 × 10 𝑀𝐻𝑧 × 5𝐾Ω
1
𝑅𝑜𝑢𝑡 = 𝑅𝐸 ∥ ∥ 𝑟 = 500Ω ∥ 12.6Ω ∥ 1.26𝐾Ω ≅ 11.66Ω
𝑔𝑚 𝜋
1 1 1
𝑓𝑐𝑙 = , 𝐶2 = = ≅ 2.581 × 10−10 𝑓 = 25.81𝑛𝑓
2𝜋(𝑅𝑜𝑢𝑡 + 𝑅𝐿 )𝐶2 2𝜋(𝑅𝑜𝑢𝑡 + 𝑅𝐿 )𝑓𝑐𝑙 2𝜋 × 10 𝑀𝐻𝑧 × 61.66Ω
29