GOVERNMENT ENGINEERING COLLEGE

GANDHINAGAR

LAB MANUAL
FOR

VLSI Technology&
Design (3151105)

(ELECTRONICSANDCOMMUNICATIONDEPARTMENT)

GOVERNMENT ENGINEERING COLLEGE ,

GANDHINAGAR

GovernmentEngineeringCollege,Gandhinagar -1-
 Government Engineering College
Sector28,Gandhinagar

Certificate
This is to certify that the Lab/term work carried out in the subject of

VLSI Technology & Design (3151105) and recorded in this

journal is the bonafide work of Mr. Sahani krishna A.

EnrollNo.200130111537. of B.E.semester 5Thin the branch of

Electronics& Communication during the academic year2020-2021

FacultyinCharge HeadoftheDepartment
Date: Date:
 INDEX
Sr.No. Title DATE SIGN
1 (A) TostudyVHDLBasics
(B) TostudyXilinxISEtool
2 ToimplementalllogicgatesusingThreeselectline.

3 Toimplementhalfadder&FullAdder
usingdataflow,behaviorandstructuralmodelingusingVHDL.

4 1.Toimplement4x1multiplexerusingVHDL.
2. Toimplement1x4de-multiplexerusingVHDL.

5 1.Toimplement3to8decoderusingVHDL.
2. Toimplement8to3encoderusingVHDL.

6 Toimplement4bitcomparatorusing
behavioral&structuralmodeling.
7 Toimplement4-bitGraytobinarycode
converterusingbehavioral&structuralmodeling.

8 TodesignD,RS,T,JKflipflopusingVHDL.

9 To implementbinaryasynchronousup
counterusingthebehavioralmethodusingVHDL.

10 To design 4-bit shift register with parallelload,serial-

in,shiftleft/shiftrightcontrol.
11 Toimplementsequencedetector(mealymodel) usingVHDL.

12 UsingµwinddrawlayoutofCMOSinverter.

13 UsingµwinddrawlayoutofCMOSNANDgate.

14 Usingµwinddrawlayout ofCMOS NORgate.

 EXPERIMENTNO.-1

Aim: a)To study VHDL

Basicsb)TostudyXilinxIS
Etool

VHDLBasics:

VHDL stands for very high-speed integrated circuit hardware description

language.Which is one of the programming language used to model a digital
system bydataflow,behavioralandstructuralstyleofmodeling.

Describing adesign:
InVHDLanentityisusedto describeahardwaremodule.
Anentitycanbedescribedusing,
b) Entitydeclaration.
c) Architecture.
d) Configuration
e) Packagedeclaration.
f) Packagebody.

Entitydeclaration:
Itdefinesthenames, inputoutputsignalsandmodesofahardwaremodule.
Syntax:
entityentity_nameis
Portdeclaration;
endentity_name;

Anentitydeclarationshould startswith‘entity’andendswith‘end’keywords.
Ports are interfaces through which an entity can communicate with
itsenvironment.Eachportmusthaveaname,directionandatype.Anentitymayhavenoportd
eclarationalso.Thedirectionwillbeinput,outputorinout.

In Portcanberead
Out Portcanbe written
Inout Port canbereadandwritten
Buffer Portcanberead and written,itcanhave onlyonesource.

Architecture:
It describes the internal description of design or it tells what is there
insidedesign.Eachentityhasatleastonearchitectureandanentitycanhavemanyarchitecture.
Architecture can be described using structural, dataflow, behavioral ormixed
style.Architecture can be used to describe a design at differentlevels ofabstraction like
gatelevel,registertransferlevel(RTL)orbehaviorlevel.
Syntax:
architecturearchitecture_nameofentity_namearchitecture_declarative_part;
begin
 Statements;
endarchitecture_name;

Hereweshouldspecifytheentitynameforwhichwearewritingthearchitecturebody.The
architecture statements should be inside the begin and end keyword.
Architecturedeclarativepartmaycontainvariables,constants,orcomponentdeclaration.

Configuration:
If an entity contains many architectures and any one of the possible
architecturebinding with its entity is done using configuration. It is used to bind the
architecturebodytoits entityandacomponentwithanentity.
Syntax:
configurationconfiguration_nameofentity_nameisblock_conf
iguration;
endconfiguration_name.

Block_configurationdefinesthebindingofcomponentsinablock.Thiscanbewrittenas

for
block_namecompon
ent_binding;
endfor;

block_nameisthenameofthearchitecturebody.Componentbindingbindsthecomponents
oftheblocktoentities.This canbewrittenas,

forcomponent_labels:component_nameblock_configuration;
endfor;

Packagedeclaration:
Packagedeclarationisusedto declarecomponents,types,constants, functionsandsoon.
Syntax:
packagepackage_nameis
Declarations;
endpackage_name;

Packagebody:
Apackagebodyisusedtodeclarethedefinitionsandproceduresthataredeclared
incorresponding package. Values can be assigned to constants declared in package
inpackage body.
Syntax:
package body package_name
isFunction_proceduredefinition
s;
endpackage_name;
 L i b r ar y IE E E ;
Theinternalworku i sen g o f an en t it ycanbedefinedusingdifferentmodelingstylesinside
architcturebody .T hIeEyEarEe.STD_LOGIC_1164.all;
1. Dataflowmodeling.
e nt it y h a _ en is
2. Behaviora lm o d e l in g .
3. Structuralmodelin p o rt(A,B:inbit;S,C:outbit);e
ndha_en;g .

a r c h it ectureha_arofha_enisbe
Structureofanegin
n t i ty :
S<=AxorB;

Let’stryto understandwiththehelpofoneexample.
Dataflowmodeling:
Inthisstyle
ofmodeling,theinternalworkingofanentitycanbeimplementedusingconcurrentsignal
assignment.
Let’stakehalfadderexample which ishavingoneXORgate andaANDgate.
 C<=AandB;e ndha_ar;

Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value

logictype, called STD_ULOGIC. use is a keyword, which imports all the declarations
fromthis package. The architecture body consists of concurrent signal assignments,
whichdescribes the functionality of the design. Whenever there is a change in RHS,
theexpressionisevaluatedandthevalueisassignedtoLHS.

Behavioralmodeling:
Inthisstyle
ofmodeling,theinternalworkingofanentitycanbeimplementedusingsetofstatements.
Itcontains:
· Processstatements
· Sequentialstatements
· Signalassignmentstatements
· Waitstatements
Process statementis the primary mechanism usedto model the behavior of an
entity.Itcontainssequentialstatements,variableassignment(:=)statementsorsignalassign
ment(<=) statements etc. Itmay or may notcontain sensitivity list. If thereisan event
occurs on any of the signals in the sensitivity list, the statements within theprocessis
executed.
Inside the process the execution of statements will be sequential and if one entity
ishavingtwoprocessestheexecutionoftheseprocesseswillbeconcurrent.Attheenditwaitsf
or anothereventtooccur.
 libraryIEEE;
useIEEE.STD_LOGIC_1164.all;

entityfa_enis
port(A,B,Cin:inbit;SUM,CARRY:outbit);en
dfa_en;

architecturefa_aroffa_enisco
mponentha_en
port(A,B:inbit;S,C:outbit);
Herewhenever thereisachangeinthevalueofaor btheprocessstatementsareexecuted.

Structuralmodeling:
Theimplementationofanentityisdonethroughsetofinterconnected
components.Itcontains:
· Signaldeclaration.
· Componentinstances
· Portmaps.
· Waitstatements.
Componentdeclaration:

Syntax:

component component_name

[is]List_of_interfaceports;

endcomponentcomponent_name;

Beforeinstantiatingthecomponentitshouldbedeclaredusingcomponentdeclarationas
shown above. Component declaration declares the name of the entity and
interfaceofacomponent.
Let’stryto understandthisbytakingtheexampleoffulladder using2
halfadderand1OR gate.

-8 -
 libraryIEEE;
useIEEE.STD_LOGIC_1164.all;

entityfa_enis
port(A,B,Cin:inbit;SUM,CARRY:outbit);en
dfa_en;

architecturefa_aroffa_enisco
mponentha_en
port(A,B:inbit;S,C:outbit);

GovernmentEngineeringCollege,Gandhinagar -9-
libraryIEEE;
useIEEE.STD_LOGIC_1164.all;
entitytb_enise
nd tb_en;
architecturetb_aroftb_enis
signala_i,b_i,c_i,sum_i,carry_i:bit;begin
eut:entitywork.fa_en(fa_ar)
portmap(A=>a_i,B=>b_i,Cin=>c_i,SUM=>sum_i,CARRY=>carry_i);stimulu
s:process
begin
a_i<='1';b_i<='1';c_i<='1';wai
tfor10ns;a_i<='0';b_i<='1';c_i
<='1';waitfor10ns;a_i<='1';b_
i<='0';c_i<='0';

endcomponent;

signal

C1,C2,S1:bit;begin
HA1:ha_enportmap(A,B,S1,C1);HA2:h
a_enportmap(S1,Cin,SUM,C2);CARR
Y<=C1orC2;
endfa_ar;
The program we have written for half adder in dataflow modeling is instantiated
asshown above. ha_en is the name of the entity in dataflow modeling. C1, C2, S1 are
thesignals used for internal connections of the component which are declared using
thekeyword signal. Port map is used to connect different components as well as
connectcomponentstoportsoftheentity.

Component instantiationisdoneasfollows.

Component_label:component_nameportmap(signal_list);

Signal_lististhearchitecturesignalswhichweareconnectingtocomponentports.This
can be done in different ways. What we declared above is positional
binding.Onemoretypeisthe namedbinding.The abovecanbe writtenas,

HA1:ha_en port map(A => A,B => B, S => S1 ,C => C1

);HA2:ha_enportmap(A=>S1,B=>Cin,S=>SUM,C=>C2);

Test bench:
The correctness of the above program can be checked by writing the test
bench.Thetestbench isusedfor generatingstimulusfortheentityunder
test.Let’swriteasimpletestbenchforfulladder.
 waitfor10ns;
ifnow=30nsthen
wait;
endif;end

processstimulus;

endtb_ar;
1. TostudyXilinxISEtool

STEPSTOIMPLEMENTTHEXILINXSOFTWARE

Step1:Startthe XilinxProjectNavigatorbyusingthe desktopshortcutor byusingStart-

>programs-> XilinxISE->ProjectNavigator.
Step 2: In the project Navigator window go to FILE->New project->Select
Device.Step3:ClickonthesymbolofFPGAdeviceandthenrightclick-
>clickonnewsource-
>VHDLmoduleandgivethenamebasicgates->Defineports->finish.

FORCPLDDEVICESETTING:

Step3:Selectthefollowing
ProductCategory: All
Family: xc9500CPLDs
Device: xc9572
Package: PC84
Speed: -15
FORFPGADEVICESETTING:-

Step3:Selectthefollowing
ProductCategory: All
Family: Spartan3E
Device: XC3S250E
Package: PQ208
Speed: -4

Step4:GeneratethebehavioralVHDLCodeforthebasicgates.
Step5:Check syntax,andremove errorsifpresent.
Checksyntaxwindowshownbelow.

Step6:SimulatethedesignusingModelsim.
Highlight basicgates.vhd file in the sources in project window. To run
theFunctional Simulation, Click on the symbol of FPGA device and then
rightclick->Clickonnewsource->clickontestbenchwaveform->givefilename-
>Select

Themodelsimwindow setting shownnextpage.

 entity->Finish->Give inputs-> Click on simulate behavioral model->see
theoutput.

Step7:SynthesisthedesignusingXST.
Highlightbasicgates.vhdfileintheSourcesinProjectwindow.Torunsynthesis,
right-click on synthesis, and choose the run option, double-click
onSynthesize in the processes for Current Source window. Synthesis will
run,andagreen
checkwillappearnexttosynthesiswhenitissuccessfullycompleted. A yellow
exclamation mark indicates an error was generated.WarningsareOK.
If there are any errors, you can view the error through the console
windowotherwisecontinueontothenextstep.

Step8: Write User Constraint file wherein the FPGA or CPLD pins are locked as
perthe
Manual.UCFwindow shownonnextpage.
 UCFwindow

Step9: MakethesettingofJTAGclock.GotoGenerateProgrammingfilerightclick
Onthatandthenselectproperties.

ThengotostartupoptionandselectJTAGclock.
Step10:RuntheXilinximplementationTools.
Once synthesis is complete, you can place and route your design to fit into
aXilinxdevice,andyoucanalsogetsomepostplace-and-routetiminginformation
about the design. This procedure runs you through the basic
flowforimplementation.
Right-click on Implement Design, and choose the Run option, or double left-
clickonImplementationDesign.
Right-click on Generate Programming File, and choose the Run option,
ordoubleleft-clickonGenerateProgrammingFile.
• A .jed file will be created in case of CPLD and .bit file is created in case
ofFPGA(spartan3).
IMPACTwindow

AnIMPACTwindowwillappear onscreen.

PROGRAMMINGTHROUGHUSB
a) ProgrammingXC9572CPLD

CreatinganSVFFile
Consider you finished off the CPLD/FPGA design and finally want to get
itonto the programmable logic IC by means of a download cable which
canexecuteSVFfiles(likejtagusb).So,
hereishowtocreateanSVFfileinXilinxISEWebPACKe.g.foranXC9572CPLD:

• Select Configure Device (iMPACT) which is visible when expanding the

levelGenerate Programming File invoked before and double-click or use again
Runfromthecontext menu.ThiswillbringupiMPACTaftersometime.
• SelectPrepareaBoundary-ScanFileandformatSVF:
 PressFinish.

• Now,afileselectionboxwillpopup whereyou should

enterthefilenameoftheSVFfiletobegenerated.Entertest.svfandpress
thereturnkey.
• iMPACTwillinformyouthatalloperationsarenowdirected toafile,sopress
OKafter havingreadthebox.
• Now,afileselectiondialogwillshowupallowingyoutoselectthedesignfiletobeloa
dedontotheprogrammablelogicchip; inourcasethisismain.jed.

The SVF file created in the following steps will contain all the actions
weperform now in the order we do them. So, select the context menu of the
ICsymboltogetalistofavailablecommands;thisshouldlook asshownbelow:
 Inthisorder, selectthefollowingcommands:

a) Erase...toerasetheCPLD (orbetter:towritethe erasecommandstothe

SVFfile).(SayOKtothenextbox,ofcourse.)
Note that may not even be necessary since you can activate erasing
whenprogrammingaswell.Butlet'sbesurethistime...YoucanalsofirstcallGetDevi
ce ID but this is always done as first step when programming so it
isactuallynotneeded.
b) Program...toactuallyprogramthepreviouslyselected
JEDECfileontotheXC9572XL CPLD. Make sure Verify is activated so
that errors atprogrammingtimecanbedetected.PressOK.

That'sall. ExitiMPACTnow. WehavetheSVFfileready.

Now,it'smerelyaboutdownloadingit(e.g.viatheDIGILENTadeptsoftware).
 EXPERIMENTNO.-2

AIM:ToimplementalllogicgatesusingThreeselectline.

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;

entitylogic_gatesis
Port(a:inSTD_LOGIC;b:i
nSTD_LOGIC;
clk:inSTD_LOGIC;
s:inSTD_LOGIC_VECTOR(2downto0);y:o
utSTD_LOGIC);
endlogic_gates;

architectureBehavioraloflogic_gatesisbeg

in
process(clk)
begin

ifrising_edge(clk)thenc
asesis
when "000"=>y<=a and
b;when "001"=>y<=a or
b;when "010"=>y<=a nor
b;when"011"=>y<=anandb
;when"100"=>y<=axorb;
when"101"=>y<=((not(a))andb)or(aand(not(b)));when
"110"=>y<=(nota)andb;
when"111"=>y<=(notb)andb;w
henothers=>null;
endcase;
endif;
end
process;endBeh
avioral;
Testbench:
LIBRARYieee;
USEieee.std_logic_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--USEieee.numeric_std.ALL;

ENTITYlogic_gates_tbIS
ENDlogic_gates_tb;

ARCHITECTUREbehaviorOFlogic_gates_tbIS

--ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENT

logic_gates
PORT(
a : IN
std_logic;b:INst
d_logic;
clk :INstd_logic;
s:INstd_logic_vector(2downto0);y:
OUTstd_logic
);
ENDCOMPONENT;

--Inputs
signal a : std_logic :=
'0';signal b : std_logic :=
'0';signalclk:std_logic:='0';
signals:std_logic_vector(2downto0):=(others=>'0');
--Outputs
signaly:std_logic;B

EGIN

--
InstantiatetheUnitUnderTest(UUT)uut:
logic_gatesPORTMAP(
a =>
a,b=>b
,
clk=>clk,s
=>s,
y=>y
 );

-- Stimulus
processstim_proc1:
processbegin
waitfor50ns;a
<=nota;
endprocess;

stim_proc2:process
begin
waitfor100ns;b
<=not b;
endprocess;

stim_proc3:process
begin
waitfor25ns;cl
k<=notclk;
endprocess;

stim_proc4:process
begin
waitfor200ns;s(
0)<=nots(0);
endprocess;

stim_proc5:process
begin
waitfor400ns;s(
1)<= not
s(1);endprocess;

stim_proc6:process
begin
waitfor800ns;s(
2)<=nots(2);
end
process;END;
Output:
 EXPERIMENTNO.-3

AIM:Toimplementhalfadder&FullAdderusingdataflow,behaviorand
structuralmodelingusingVHDL.

a) HALFADDER
--dataflowmodeling
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityHAis
Port(a:inSTD_LOGIC;b:i
nSTD_LOGIC;
sum :out
STD_LOGIC;carry:outS
TD_LOGIC);
end HA;

architectureBehavioralofHAisbe

gin

sum<=a xor
b;carry<=aandb;
endBehavioral;
--HALFADDERUSINGBEHAVIORALMETHOD
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
entityhadd_behis
port(a,b:inbit;sum,carry:outbit);e
ndhadd_beh;
architectureBehavioralofhadd_behisbe
gin
process(a,b)
begin
ifa=bthensum<='0';
elsesum<='1';
end if;

ifa='1'andb='1'thencarry<='1';else
carry<='0';
end if;
end
process;endBeh
avioral;
--StructuralModeling
libraryieee;
useieee.std_logic_1164.all;
entityhad_stris
port(a,b:inbit;sum,carry:outbit);e
ndhad_str;

architectureBehavioralofhad_striscompon
entxor_2
port(x,y:inbit;z:outbit);e
nd component;

component
and_2port(x1,y1:inbit;z1:o
utbit);end component;

begin
p: xor_2 port
map(a,b,sum);q:and_2portm
ap(a,b,carry);endBehavioral;
--
nowentityandarchitectureofxorgateentityx
or_2is
port(x,y:inbit;z:outbit);e
ndxor_2;
architecture
Aofxor_2isbegin
z<=x xor
y;endA;

--nowentityandarchitectureofand
gateentityand_2is
port(x1,y1:inbit;z1:outbit);e
nd and_2;
architecture Bofand_2
isbegin
z1<=x1andy1;e
ndB;
Testbench:
LIBRARYieee;
USEieee.std_logic_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--USEieee.numeric_std.ALL;
ENTITYHA_tbIS
ENDHA_tb;
ARCHITECTUREbehaviorOFHA_tbIS

--ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENT

HA
PORT(
a : IN
std_logic;b:INst
d_logic;
sum : OUT
std_logic;carry:OUTst
d_logic
);
ENDCOMPONENT;

--Inputs
signala:std_logic:='0';sig
nalb:std_logic:='0';
--Outputs
signal sum :
std_logic;signalcarry:st
d_logic;

BEGIN
--
InstantiatetheUnitUnderTest(UUT)uut:HAP
ORT MAP(
a =>
a,b=>b
,
sum =>
sum,carry=>c
 arry
);
 -- Stimulus
processstim_proc:
processbegin
wait for 100
ns;a<=nota;
endprocess;

stim_proc1:process
begin
waitfor200ns;b
<=not b;
end
process;END;
Output:
b) FULLADDER

---fulladderusingdataflowmodelling
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityFAis
Port ( a : in
STD_LOGIC;b:inST
D_LOGIC;c:inSTD_
LOGIC;
sum : out
STD_LOGIC;carry:outST
D_LOGIC);
end FA;

architectureBehavioralofFAisbe

gin

sum<=(axorb)xorc;
carry<=(aandb)or(aandc)or(bandc);endBe

havioral;
--fulladderstructuralmodeling
libraryieee;
useieee.std_logic_1164.all;
entityfull_stris
port(a,b,c:inbit;sum,carry:outbit);e
ndfull_str;

architecturestructoffull_strisc
omponentxor_2port(x1,y1:in
bit;z1:out bit);end component;
component
and_2port(x2,y2:inbit;z2:o
utbit);end component;

component
or_2port(x3,y3:inbit;z3:out
bit);end component;

signals1,t1,t2,t3,v:bit;be

gin
p1:xor_2 port
map(a,b,s1);p2:xor_2portma
p(s1,c,sum);p3:and_2portma
p(a,b,t1);p4:and_2portmap(b,
c,t2);p5:and_2portmap(a,c,t3
);p6:or_2portmap(t1,t2,v);p7:
or_2 port
map(t3,v,carry);end struct;

--entityandarchitecture

ofxorcomponententityxor_2is
port(x1,y1:inbit;z1:outbit);e
ndxor_2;

architecturehh1ofxor_2isbe
gin
z1<=x1xory1;e
ndhh1;
--entityandarchitectureofandcomponent
entityand_2isport(x2,y2:inb
it;z2:outbit);end and_2;

architecture
hh2ofand_2isbegin
z2<=x2andy2;e
ndhh2;

--

entityandarchitectureoforcomponententity

or_2is
port(x3,y3:inbit;z3:outbit);e
ndor_2;
architecturehh3ofor_2isbe
gin
z3<=x3xory3;e
ndhh3;
Testbench:
LIBRARYieee;
USEieee.std_logic_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--USEieee.numeric_std.ALL;

ENTITYFA_tbIS
ENDFA_tb;

ARCHITECTUREbehaviorOFFA_tbIS

--

ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTFA
PORT(
a : IN
std_logic;b : IN
std_logic;c:INst
d_logic;
sum : OUT
std_logic;carry:OUTst
d_logic
);
ENDCOMPONENT;

--Inputs
signal a : std_logic :=
'0';signalb:std_logic:='0';
signalc:std_logic:='0';
--Outputs
signal sum :
std_logic;signalcarry:st
d_logic;

BEGIN

--
InstantiatetheUnitUnderTest(UUT)uut:
FAPORT MAP(
a =>
a,b =>
b,c=>c
,
 sum =>
sum,carry=>c
arry
);

-- Stimulus
processstim_proc:
processbegin
wait for 100
ns;a<=not a;
endprocess;

stim_proc1:process
begin
waitfor200ns;b
<=not b;
endprocess;

stim_proc2:process
begin
waitfor400ns;c
<=notc;
end
process;END;

Output:
 EXPERIMENTNO.-4

AIM:a)Toimplement4x1multiplexer usingVHDL.
b)Toimplement1x4demultiplexerusingVHDL.a)Toim

plement 4x1multiplexerusing VHDL.

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitymultiplexeris
Port(I0:inSTD_LOGIC;I1
: inSTD_LOGIC;I2 :
inSTD_LOGIC;I3:inS
TD_LOGIC;
S:inSTD_LOGIC_VECTOR(1downto0);Y:o
utSTD_LOGIC);
endmultiplexer;

architectureBehavioralofmultiplexerisbeg
in

process(S,I0,I1,I2,I3)b
egin
caseSis
when
"00"=>Y<=I0;when
"01"=>Y<=I1;when
"10"=>Y<=I2;when
"11"=>Y<=I3;
when
others=>Y<='0';end
case;
end

process;endBeh
avioral;
Testbench:

LIBRARYieee;
USEieee.std_logic_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--USEieee.numeric_std.ALL;
ENTITYMUX_TBIS
ENDMUX_TB;

ARCHITECTUREbehaviorOFMUX_TBIS

--

ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTmul

tiplexer
PORT(
I0 : IN
std_logic;I1 : IN
std_logic;I2 : IN
std_logic;I3:INst
d_logic;
S:INstd_logic_vector(1downto0);Y:
OUTstd_logic
);
ENDCOMPONENT;

--Inputs
signalI0
:std_logic:='0';signalI1
:std_logic:='0';signalI2
:std_logic:='0';signalI3:st
d_logic:='0';
signalS:std_logic_vector(1downto0):=(others=>'0');

--
OutputssignalY:std
_logic;

BEGIN
 --
InstantiatetheUnitUnderTest(UUT)uut:
multiplexerPORTMAP(
I0=> I0,
 I1 =>
I1,I2 =>
I2,I3 =>
I3,S =>
S,Y=>Y
);
--
Stimulusprocessstim
_proc: processbegin
waitfor100ns;I
0<=NOTI0;
endprocess;

stim_proc1:process
begin
waitfor200ns;I
1<=NOTI1;
endprocess;

stim_proc2:process
begin
waitfor400ns;I
2<=NOTI2;
endprocess;

stim_proc3:process
begin
waitfor800ns;I
3<= NOTI3;
endprocess;

stim_proc4:process
begin
waitfor1600ns;S(
0)<=NOTS(0);
endprocess;

stim_proc5:process
begin
waitfor3200ns;S(
1)<=NOTS(1);
end
process;END;
Output:
b)Toimplement1x4demultiplexerusingVHDL.

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmetic functionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;

--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;

entityDemuxis
Port(I:inSTD_LOGIC;
S : in STD_LOGIC_VECTOR (1 downto
0);Y0:outSTD_LOGIC;
Y1 : out
STD_LOGIC;Y2 : out
STD_LOGIC;Y3:outST
D_LOGIC);
endDemux;

architectureBehavioralofDemuxisbe

gin
Process(S,I)
begin

caseSis
when "00" => Y0<=I;Y1<='0';Y2<='0';
Y3<='0';when "01" => Y0<='0';Y1<=I;Y2<='0';
Y3<='0';when "10" => Y0<='0';Y1<='0';Y2<=I;
Y3<='0';when "11" => Y0<='0';Y1<='0';Y2<='0';
Y3<=I;whenothers=>Y0<='0';Y1<='0';Y2<='0';Y3<=
'0';
end
case;endpro
cess;

endBehavioral;
Testbench:
LIBRARYieee;
USEieee.std_logic_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--USEieee.numeric_std.ALL;

ENTITYDemux_tbIS
ENDDemux_tb;

ARCHITECTUREbehaviorOFDemux_tbIS

--ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENT

Demux
PORT(
I:INstd_logic;
S : IN std_logic_vector(1 downto
0);Y0:OUTstd_logic;
Y1 : OUT
std_logic;Y2 : OUT
std_logic;Y3:OUTst
d_logic
);
ENDCOMPONENT;

--Inputs
signalI:std_logic:='0';
signalS:std_logic_vector(1downto0):=(others=>'0');

--Outputs
signal Y0 :
std_logic;signal Y1 :
std_logic;signal Y2 :
std_logic;signalY3:st
d_logic;

BEGIN

--
InstantiatetheUnitUnderTest(UUT)uut:Dem
uxPORT MAP(
I =>
I,S=>S
,
Y0 =>Y0,
 Y1 =>
Y1,Y2 =>
Y2,Y3
=>Y3
);

-- Stimulus
processstim_proc:
processbegin

waitfor100ns;I
<= notI;
endprocess;

stim_proc1:process
begin

wait for 200

ns;S(0)<=notS(
0);
endprocess;

stim_proc2:process
begin

wait for 400

ns;S(1)<=notS(
1);
end

process;END;
Output:
 EXPERIMENTNO.-5

AIM:a)Toimplement3to8linedecoder usingVHDL.

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
entitydec3to8is
Port ( I : in STD_LOGIC_VECTOR (2 downto
0);Y : out STD_LOGIC_VECTOR (7 downto
0);en :inSTD_LOGIC);
enddec3to8;

architectureBehavioralofdec3to8isb

egin
process(en,I)
begin
if
en='0'thenY<=(othe
rs=>'0');else
caseIis
when
"000"=>y<="00000001";when
"001"=>y<="00000010";when
"010"=>y<="00000100";when
"011"=>y<="00001000";when
"100"=>y<="00010000";when
"101"=>y<="00100000";when
"110"=>y<="01000000";when
"111"=>y<="10000000";
when
others=>y<="00000000";end
case;
end if;
end

process;endBeh
avioral;
Testbench:
LIBRARYieee;
USEieee.std_logic_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--USEieee.numeric_std.ALL;

ENTITYdec3to8_tbIS
ENDdec3to8_tb;
ARCHITECTUREbehaviorOFdec3to8_tbIS

--ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENT

dec3to8
PORT(
I:INstd_logic_vector(2 downto0);
Y:OUTstd_logic_vector(7downto0);en
:IN std_logic
);
ENDCOMPONENT;

--Inputs
signalI
:std_logic_vector(2downto0):=(others=>'0');signalen:std_logi
c:='0';

--Outputs
signalY:std_logic_vector(7downto0);B

EGIN

--
InstantiatetheUnitUnderTest(UUT)uut:dec3t
o8PORTMAP (
I=>I,Y
=>Y,
en=>en
);
-- Stimulus
processstim_proc:
processbegin
 waitfor100ns;I(
0)<=notI(0);
endprocess;

stim_proc1:process
begin
waitfor200ns;I(
1)<=notI(1);
endprocess;

stim_proc2:process
begin
waitfor400ns;I(
2)<=notI(2);
end
process;stim_proc3
:processbegin
waitfor50ns;e
n<=noten;
endprocess;

END;

Output:
b)Toimplement8to3lineencoderusingVHDL.
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;

entityenco8to3is
Port(D:inSTD_LOGIC_VECTOR(7downto0);E:in
STD_LOGIC;
Dout:outSTD_LOGIC_VECTOR(2downto0));end
enco8to3;

architectureBehavioralofenco8to3isbegin
process(D,E)
begin
if (E = '0')
thenDout<="ZZZ";
else
caseDis
when"00000001"=>Dout<="000";
when"00000010"=>Dout<="001";
when"00000100"=>Dout<="010";
when"00001000"=>Dout<="011";
when"00010000"=>Dout<="100";
when"00100000"=>Dout<="101";
when"01000000"=>Dout<="110";
whenothers=>Dout<="111";e
nd case;
end if;
endprocess;

endBehavioral;
Output:
 EXPERIMENTNO.-6

AIM:Toimplement4bitcomparatorusingbehavioral&structuralmode
ling.

----BehavioralModeling….
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;

entitycomparatoris
Port(A:inSTD_LOGIC_VECTOR(3downto0);B :
in STD_LOGIC_VECTOR (3 downto
0);Equal :outSTD_LOGIC;
AGreaterB:outSTD_LOGIC;A
lessB:outSTD_LOGIC);
endcomparator;

architectureBehavioralofcomparatorisbeg

in
Equal<='1' when A = B else
'0';AGreaterB<='1'whenA>Belse'0';
AlessB<='1'when A<Belse'0';

endBehavioral;
----STRUCTURALMODELING

--MAINPROGRAM
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;

entitycomparatoris
port(A,B:inSTD_LOGIC_VECTOR(3downto0);E
qual :outSTD_LOGIC;
AGreaterB:outSTD_LOGIC;A
lessB : out STD_LOGIC);end
comparator;

architecturestrucofcomparatorisco
mponent equality
port(a,b:instd_logic_vector(3downto0);e
q:outstd_logic);
endcomponent;

componentlesser
port(a,b:instd_logic_vector(3downto0);g
ret:outstd_logic);
endcomponent;

componentgreater
port(a,b:instd_logic_vector(3downto0);g
ret:outstd_logic);
endcomponent;
begin
t1:equality port map
(A,B,Equal);t2:greaterportmap(A,B,
AGreaterB);t3:lesserportmap(A,B,A
lessB);
endstruc;
----PROGRAMFOREQUALITY
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;

entityequalityis
port(a,b:instd_logic_vector(3downto0);e
q:outstd_logic);
endequality;
architecturestrucofequalityissi
gnalc,d,e,f:std_logic;
begin
c<=not(a(3)xorb(3));
d<=not(a(2)xorb(2));
e<=not(a(1)xorb(1));
f<=not(a(0) xor

b(0));eq<=canddandean

df;end struc;

----PROGRAMFORGREATER
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitygreateris
port(a,b:instd_logic_vector(3downto0);g
ret:outstd_logic);
endgreater;

architecturestrucofgreaterissi
gnalp,q,r,s:std_logic;
begin
p<=(notb(3)anda(3));
q<=(not(b(3)xora(3)))and(notb(2))anda(2);
r<=(not(b(3)xora(3)))and(not(b(2)xora(2)))and(notb(1))anda(1);
s<=(not (b(3) xor a(3))) and (not (b(2) xor a(2))) and (not (b(1) xor
a(1)))and (notb(0)) anda(0);
gret<=p or q or r or

s;end struc;

---PROGRAMFORLESSER
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;

entitylesseris
port(a,b:instd_logic_vector(3downto0);g
ret:outstd_logic);
endlesser;

architecturestrucoflesserissi
gnalp,q,r,s:std_logic;
begin
p<=(notb(3)anda(3));
q<=(not(b(3)xora(3)))andb(2)and(nota(2));
r<=(not(b(3)xora(3)))and(not(b(2)xora(2)))and(nota(1))andb(1);
s<=(not(b(3) xora(3)))and(not(b(2)xora(2)))and(not(b(1)xora(1)))and
(nota(0)) andb(0);

gret<=p or q or r or

s;end struc;
OUTPUT:
 EXPERIMENTNO.-7
AIM:Toimplement4-bitGraytobinarycodeconverterusingbehavioral
&structuralmodeling.

----BEHAVIOURALMODELING

libraryIEEE;
use
IEEE.STD_LOGIC_1164.ALL;useIE
EE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
----Uncommentthefollowinglibrarydeclarationifinstantiating
----anyXilinxprimitivesinthis code.
--libraryUNISIM;
--
useUNISIM.VComponents.all;e
ntityg2b1is
Port(
g0,g1,g2,g3:inSTD_LOGIC;b0,
b3 :outSTD_LOGIC;
b1,b2:inout
STD_LOGIC);endg2b1;
architectureBehavioralofg2b1isbe
gin
b3<=g3;
b2<=g3 xor
g2;b1<= b2 xor
g1;b0<= b1 xor
g0;endBehavior
al;
----STRUCTURALMODELING
libraryIEEE;
use
IEEE.STD_LOGIC_1164.ALL;useIE
EE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
----Uncommentthefollowinglibrarydeclarationifinstantiating
--libraryUNISIM;
--
useUNISIM.VComponents.all;e
ntityg2bs1is
Port(
g0,g1,g2,g3:inSTD_LOGIC;b0,
b3 :outSTD_LOGIC;
b1,b2:inout
STD_LOGIC);endg2bs1;
architectureBehavioralofg2bs1iscompone
nt exor2in11
port(p,q:instd_logic;r:
outstd_logic);
endcomponent;
begin
x1: exor2in11 port map
(g0,b1,b0);x2: exor2in11 port map
(g1,b2,b1);x3: exor2in11 port map
(g2,g3,b2);b3<=g3;
endBehavioral;
OUTPUT:
 EXPERIMENTNO.-8

AIM:TodesignD,RS,JK,TflipflopusingVHDL.

--implementDflipflop

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;

--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;

entitydffis
Port (d:
inSTD_LOGIC;clk,clear,preset:i
nSTD_LOGIC;q
:outSTD_LOGIC;
qbar:outSTD_LOGIC);e
nddff;

architecture

Behavioralofdffisbegin
process(clear,clk,preset)beg
in

if(clear='1')
thenq<='0';
qbar<='1';elsif(prese
t='1') thenq<='1';
qbar<='0';elsif(rising_edge
(clk))thenif(d='0')then
q<='0';
qbar<='1';elsif(
d='1')then
q<='1';
qbar<='0';
endif;endi
f;
end

process;endBeh

avioral;

Output:
--implementrsflipflop

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;

entitysrffis
Port(s:inSTD_LOGIC;r:i
nSTD_LOGIC;
clk : in
STD_LOGIC;q:outS
TD_LOGIC;
qbar:outSTD_LOGIC);e
nd srff;

architecture

Behavioralofsrffisbegin

process(r,s,clk)
begin
if(clk='1'andclk'event)thenif
(r='0' and s='1') thenq<='1';
qbar<='0';
elsif(r='1'ands='0')thenq
<='0';
qbar<='1';
elsif(r='1'ands='1')thenq
<='0';
qbar<='0';
endif;endi
f;
end

process;endBeh

avioral;
Output:
--toimplementjkflipflop
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;

--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;

entityjkffis
Port(jk:inSTD_LOGIC_VECTOR(1downto0);q
:outSTD_LOGIC;
q1 : out
STD_LOGIC;clk:inST
D_LOGIC);
endjkff;

architectureBehavioralofjkffissi
gnals:std_logic;
beginproces
s(clk)begin
if(clk='1'andclk'event)thenc
asejkis
when"01"=>s<='0';
when"10"=>s<='1';
when"11"=>s<=nots;
when
others=>null;end
case;
end if;
end
process;q<=
s;q1<=nots;

endBehavioral;
Output:
--toimplementtflipflop
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;

entitytffis
Port ( t : in
STD_LOGIC;q:outS
TD_LOGIC;
qbar:outSTD_LOGIC;cl
k:inSTD_LOGIC);
endtff;

architecture

Behavioraloftffisbegin

process(t,clk)variab
les:std_logic;begin
--s:='0';
if(clk='1'andclk'event)thenif
(t='1')then
s:=nots;
elses:='
0';
endif;q<=s;
qbar<=nots;
endif;
end

process;endBeh

avioral;
Output:
 EXPERIMENTNO.-9

AIM:Toimplementbinaryasynchronousupcounterusingthebehaviora
l methodusingVHDL.

libraryIEEE;
use
IEEE.STD_LOGIC_1164.ALL;useIE
EE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;

--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;

--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;

entity binarycounter
isport(C,CLR:instd_logic;
Q:outstd_logic_vector(3downto0));en
d binarycounter;

architectureBehavioralofbinarycounterisbegin
process(C, CLR)
variables:std_logic_vector(3downto0);b
egin
if(CLR='1') then
s :="0000";
elsif(C'eventandC='1')thens:
=s+1;
end if;
Q<=s;
end

process;endBeh
avioral;
Output:
 EXPERIMENTNO.-10

AIM:Todesign4-bitshiftregisterwithparallelload, serial-
in,shiftleft/shift right control.

--

4bitshiftregisterlibr

aryieee;
useieee.std_logic_1164.all;
entityshift_4is
port(input:in std_logic_vector(3 downto
0);clk,clr,load,shift_en,left_right,w:in
std_logic;output:buffer std_logic_vector(3
downto 0));end shift_4;
architecturebehavofshift_4
isbegin
process(clr,load,clk)b
egin
if(clr='1')
thenoutput<="0000";elsif(r
ising_edge(clk))thenif(loa
d='1')
thenoutput<=input;elsif(sh
ift_en='1')
thenif(left_right='1')
thenoutput(3)<=w;output(
2)<=output(3);output(1)<=
output(2);output(0)<=outp
ut(1);
elseoutput(0)<=
w;
output(1)<=output(0);
output(2)<=output(1);
output(3)<=output(2);
endif;
endif;
endif;
end
process;end
behav;
Output:
 EXPERIMENTNO.-11

AIM:ToimplementsequencedetectorusingVHDL.

libraryieee;
useieee.std_logic_1164.all;

entityseq_detis
port(data,clk,rst:instd_logic;y:outstd_logic);end
seq_det;

architectureh3ofseq_detis
typestate_typeis
array(2downto0)ofbit;constantA:state_typ
e:="000";
constant
B:state_type:="001";constant
C:state_type:="010";constant
D:state_type:="011";constant
E:state_type:="100";signalsta
te:state_type;
beginprocess(c
lk,rst)begin
ifrst='1'thens
tate<=A;y<=
'0';
elsifclk'eventandclk='1'thenca
sestateis
whenA=>ifdata='1'then
state<=B;
y<='0';
elsestate<
=A;y<='0
';
endif;when
B=>ifdata='1'then
state
<=C;y<='
0';
elsestate<
=A;y<='0
';
endif;
whenC=>ifdata='1'then
state
<=C;y<='
0';
elsestate<
=D;y<='0
';
endif;
whenD=>ifdata='1'then
state
<=E;y<='
1';
elsestate<
=A;y<='0
';
endif;when
E=>ifdata='1'then
state
<=C;y<='
0';
elsestate<
=A;y<='0
';
endif;
whenothers=>state<=A;
y<='0';

end
case;endi
f;
end
process;end
h3;
Output:
 EXPERIMENTNO.-12

AIM:Usingµwinddrawlayoutof CMOSinverter.
.
 EXPERIMENTNO.-13

AIM:Usingµwinddrawlayoutof CMOSNANDgate
 EXPERIMENTNO.-14

AIM:UsingµwinddrawlayoutofCMOSNORgate