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Contact Hours: L: 3 T: - P: - 3. Semester: III

This document provides details about a Logic Design course offered in the Computer Science and Engineering department. The course is offered in the third semester and has prerequisites in mathematics, computer programming, and computer systems. The course syllabus is divided into 5 units that cover topics like number systems, Boolean algebra, combinational logic circuits, sequential logic circuits, counters, and the design of synchronous and asynchronous sequential circuits. The total contact hours for the course is 46.

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Vishal Joshi
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44 views1 page

Contact Hours: L: 3 T: - P: - 3. Semester: III

This document provides details about a Logic Design course offered in the Computer Science and Engineering department. The course is offered in the third semester and has prerequisites in mathematics, computer programming, and computer systems. The course syllabus is divided into 5 units that cover topics like number systems, Boolean algebra, combinational logic circuits, sequential logic circuits, counters, and the design of synchronous and asynchronous sequential circuits. The total contact hours for the course is 46.

Uploaded by

Vishal Joshi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Name of Department:- Computer Science and Engineering

1. Subject Code: Course Title: Logic Design


2. Contact Hours: L: 3 T: - P: -
3. Semester: III

4. Pre-requisite: Basics of Mathematics, Basic knowledge of computer programming and


components of computer system

5. Details of Syllabus

Contact
Hrs
UNIT CONTENTS

Review of Number System: Digital Signals and Waveforms, Binary, Octal,


Hexadecimal; Complements, Signed Binary Numbers, Arithmetic Operation,
Binary Codes, Error Detection and Correction.
Unit - I 10
Boolean Algebra and Gate Level Minimization: Basic Definition, Boolean Logic,
postulates, Theorems and Properties. Digital Logic Gates, K-Map Method for
Minimization upto 6-Variables, Quine-Mc Clusky Method for Minimization, NAND
and NOR Gate Implementation.
Combinational Logic Circuit: Combinational circuits, Analysis Procedure,
Design Procedure, Binary Adder & Subtractor, Decimal Adder, Binary Multiplier,
Unit - II Magnitude Comparator, Multiplexer, Demultiplexer, Decoder, Encoder, Parity 9
Generator & Checker, Programmable Array Logic, Programmable Logic Array,
Code Convertors (BCD, Gray and Seven Segment Code etc.).
Sequential Logic Circuits: Triggering, Latches, Flip Flops: RS, JK, D and T
Unit – III (Characteristics Table, Equation and Excitation Table), Flip Flop Conversion, 9
Race Around Condition, JK Master Slave Flip Flop.
Register: Types of Register, Serial In-Serial Out, Serial In-Parallel Out, Parallel
In- Parallel Out, Parallel In- Serial Out, Universal Shift Register, Application of
Shift Registers.
Unit – IV 10
Counter: Asynchronous Counter, Decoding Gates, Synchronous Counters,
Changing the Counter Modulus, Decade Counter, Presettable Counter, Designing
of Asynchronous and Synchronous Counters
Design of Synchronous and Asynchronous Sequential Circuit:

Design of Synchronous Sequential circuit: Model Selection, State Transition


Diagram, State Synthesis Table, Design Equations and Circuit Diagram,
Unit – V Implementation using Read Only Memory, State Reduction Table and ASM Chart. 8

Design of Asynchronous Sequential Circuit: Analysis of Asynchronous


Sequential Circuit, Problems with Asynchronous Sequential Circuit, Circuit
Designing, Case study - ORCAD
Total 46

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