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    Answer:: 3.figure 5-3 (B) Shows One Way of Having Memory-Mapped I/O Even in The Presence of Separate

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    Mamunur Rashid
    The proposed change to allow more than four partitions on a hard disk would cause operating systems to fail, as they are designed to only recognize four partitions. All operating systems would need to be updated simultaneously to work with the new partition table format. Trying to access the memory and I/O buses in parallel for memory-mapped I/O would reduce performance to that of the slower I/O bus. The bus bandwidth needed to avoid bottlenecking for a DMA controller that can request data every 40 nanoseconds across five channels is 40 megabytes per second, regardless of how requests are distributed across channels. The maximum interrupts per second for a computer that can read/write a word in 5 nanoseconds and requires pushing/popping 34 words

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    Answer:: 3.figure 5-3 (B) Shows One Way of Having Memory-Mapped I/O Even in The Presence of Separate

    Uploaded by

    Mamunur Rashid
    23 views2 pages
    The proposed change to allow more than four partitions on a hard disk would cause operating systems to fail, as they are designed to only recognize four partitions. All operating systems would need to be updated simultaneously to work with the new partition table format. Trying to access the memory and I/O buses in parallel for memory-mapped I/O would reduce performance to that of the slower I/O bus. The bus bandwidth needed to avoid bottlenecking for a DMA controller that can request data every 40 nanoseconds across five channels is 40 megabytes per second, regardless of how requests are distributed across channels. The maximum interrupts per second for a computer that can read/write a word in 5 nanoseconds and requires pushing/popping 34 words

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    A Computer Manufacturer Decides

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    The proposed change to allow more than four partitions on a hard disk would cause operating systems to fail, as they are designed to only recognize four partitions. All operating systems would need to be updated simultaneously to work with the new partition table format. Trying to access the memory and I/O buses in parallel for memory-mapped I/O would reduce performance to that of the slower I/O bus. The bus bandwidth needed to avoid bottlenecking for a DMA controller that can request data every 40 nanoseconds across five channels is 40 megabytes per second, regardless of how requests are distributed across channels. The maximum interrupts per second for a computer that can read/write a word in 5 nanoseconds and requires pushing/popping 34 words

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    23 views2 pages

    Answer:: 3.figure 5-3 (B) Shows One Way of Having Memory-Mapped I/O Even in The Presence of Separate

    Uploaded by

    Mamunur Rashid
    The proposed change to allow more than four partitions on a hard disk would cause operating systems to fail, as they are designed to only recognize four partitions. All operating systems would need to be updated simultaneously to work with the new partition table format. Trying to access the memory and I/O buses in parallel for memory-mapped I/O would reduce performance to that of the slower I/O bus. The bus bandwidth needed to avoid bottlenecking for a DMA controller that can request data every 40 nanoseconds across five channels is 40 megabytes per second, regardless of how requests are distributed across channels. The maximum interrupts per second for a computer that can read/write a word in 5 nanoseconds and requires pushing/popping 34 words

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    30.

    A computer manufacturer decides to redesign the partition table of a Pentium hard disk to
    provide more than four partitions. What are some consequences of this change?
    Answer:
    One fairly obvious consequence is that no existing operating system will work because they all
    look there to see where the disk partitions are. Changing the format of the partition table will
    cause all the operating systems to fail. The only way to change the partition table is to
    simultaneously change all the operating systems to use the new format.

    3.Figure 5-3(b) shows one way of having memory-mapped I/O even in the presence of separate
    buses for memory and I/O devices, namely, to first try the memory bus and if that fails try the
    I/O bus. A clever computer science student has thought of an improvement on this idea: try
    both in parallel, to speed up the process of accessing I/O devices. What do you think of this
    idea?
    Answer:
    It is not a good idea. The memory bus is surely faster than the I/O bus, otherwise why bother
    with it? Consider what happens with a normal memory request. The memory bus finishes first,
    but the I/O bus is still busy. If the CPU waits until the I/O bus finishes, it has reduced memory
    performance to that of the I/O bus. If it just tries the memory bus for the second reference, it
    will fail if this one is an I/O device reference. If there were some way to instantaneously abort
    the previous I/O bus reference to try the second one, the improvement might work, but there is
    never such an option. All in all, it is a bad idea.

    5. A DMA controller has five channels. The controller is capable of requesting a 32-bit word
    every 40 nsec. A response takes equally long. How fast does the bus have to be to avoid being a
    bottleneck?
    Answer:
    Each bus transaction has a request and a response, each taking 50 nsec, or 100 nsec per bus
    transaction. This gives 10 million bus transactions/sec. If each one is good for 4 bytes, the bus
    has to handle 40 MB/sec. The fact that these transactions may be sprayed over five I/O devices
    in round-robin fashion is irrelevant. A bus transaction takes 100 nsec, regardless of whether
    consecutive requests are to the same device or different devices, so the number of channels
    the DMA controller has does not matter. The bus does not know or care.

    8. Suppose that a computer can read or write a memory word in 5 nsec. Also suppose that
    when an interrupt occurs, all 32 CPU registers, plus the program counter and PSW are pushed
    onto the stack. What is the maximum number of interrupts per second this machine can
    process?
    Answer:
    An interrupt requires pushing 34 words onto the stack. Returning from the interrupt requires
    fetching 34 words from the stack. This overhead alone is 340 nsec. Thus the maximum number
    of interrupts per second is no more than about 2.94 million, assuming no work for each
    interrupt.

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