17BCB0091 DLD Da 6
17BCB0091 DLD Da 6
17BCB0091 DLD Da 6
f b
e g c
d
by above diagram we made a truth table
Truth table:
Decimal Input Output Display
Digit A B C D a b c d e f g pattern
0 0 0 0 0 1 1 1 1 1 1 0 0
1 0 0 0 1 0 1 1 0 0 0 0 1
2 0 0 1 0 1 1 0 1 1 0 1 2
3 0 0 1 1 1 1 1 1 0 0 1 3
4 0 1 0 0 0 1 1 0 0 1 1 4
5 0 1 0 1 1 0 1 1 0 1 1 5
6 0 1 1 0 1 0 1 1 1 1 1 6
7 0 1 1 1 1 1 1 0 0 0 0 7
8 1 0 0 0 1 1 1 1 1 1 1 8
9 1 0 0 1 1 1 1 1 0 1 1 9
We have some expressions for abcdefg interms of ABCD from above table
Expressions:
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a = A’C’+B+CA+D
b = C’+B’A’+BA
c = B’+A+C
d = A’C’+C’B+BA’+CB’A+D
e = A’C’+A’B
f = A’B’+B’C+A’C+D
g = BC’+A’B+B’C+D
By using IC we can solve this
Input :
Pin planner :
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Outputs on IC :
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Q.2) Design a Combination Circuit which converts 2421 code to 8 4 -2-1 code.
Ans.) Given two types of codes 2421 and 84-2-1
Weights of 2421 code are 2,4,2,1
Weights if 84-2-1 code are 8,4,-2,-1
For both codes we use 4 bit binary numbers
Let us assume 2421 as ABCD and 84-2-1 as WXYZ
By drawing table we can get expressions for WXYZ in terms of ABCD
Truth table :
Decimal 2 4 2 1 8 4 -2 -1
number A B C D W X Y Z
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 1 1 1
From above table we can get expressions for
2 0 0 1 0 0 1 1 0
WXYZ in terms of ABCD using k –
3 0 0 1 1 0 1 0 1
maps 4 0 1 0 0 0 1 0 0
Expressions : 5 1 0 1 1 1 0 1 1
6 1 1 0 0 1 0 1 0
W=A 7 1 1 0 1 1 0 0 1
X = A’(B+C+D) + 8 1 1 1 0 1 0 0 0 BCD
9 1 1 1 1 1 1 1 1
Y = AC’D’ + ACD + A’C’D + A’CD’
Z=D
Using above expressions we simulate and get output.
Input :
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Output :
Q.3) A circuit has four inputs RSTU and four outputs VWYZ. RSTU represents a binary
coded-decimal digit. VW represents the quotient and YZ the remainder when RSTU is
divided by 3 (VW and YZ represent 2-bit binary numbers). Assume that invalid inputs
do not occur. Design a code converter which converts RSTU to VWYZ.
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Ans.) given a circuit has four inputs RSTU and four outputs VWYZ.
Also given some conditions.
From those conditions we can construct a table to find expressions for VWYZ in terms of
RSTU using k – map.
Table:
R S T U VW YZ V W Y Z
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 1
0 0 1 0 0 2 0 0 1 0
0 0 1 1 1 0 0 1 0 0
0 1 0 0 1 1 0 1 0 1
0 1 0 1 1 2 0 1 1 0
0 1 1 0 2 0 1 0 0 0
0 1 1 1 2 1 1 0 0 1
1 0 0 0 2 2 1 0 1 0
1 0 0 1 3 0 1 1 0 0
1 0 1 0 3 1 1 1 0 1
1 0 1 1 3 2 1 1 1 0
1 1 0 0 4 0 ****
1 1 0 1 4 1 ****
1 1 1 0 4 2 ****
1 1 1 1 5 0 ****
K – map for V :
RS TU
1 1
* * * *
1 1 1 1
RS TU
1
1 1
* * * *
1 1 1
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from above K – map we get
W = RU + ST’ + RTU’ + S’TU
K – map for Y :
RS TU
1
1
* * * *
1 1
RS TU
1
1 1
* * * *
1
From above K – map we get
Z = S(T XNOR U) + RTU’ + R’S’T’U
So expressions for all is
Expressions :
V = R + ST
W = RU + ST’ + RTU’ + S’TU
Y = R(T XNOR U) + ST’U + R’S’TU’
Z = S(T XNOR U) + RTU’ + R’S’T’U
Using above expressions we construct a logical circuit and we obtain VWYZ from RSTU
Input :
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Output :
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