Jerome S.

Del Castillo: BS ECE: 17-21514

Week 4: Assignment 01
Flag registers is one of the special purpose registers existing on the Intel 8086. Its main function is to
provide and signify the status and ongoing processes on the processor (B. Pandey et.al, 2013). The flag register
is a 16-bit wide register but only nine (9) out of the 16 bits are usable, the remaining 7 bits sits idly on the
processor.

Fig. 1. 16bit Flag Register for Intel 8086 microprocessor.

Out of the nine (9) flag bit register, the student used four (4) flag bits to perform a simple operation.
The following flag bits are: (a). Interrupt Flag (IF), this flag interrupts the control of operation, and disables the
external interrupt when the value is zero (0) and enable interrupts when set to 1 (Brey, 2009); (b). Sign Flag (SF)
indicates the sign of the result of an operation (Dandamudi, 2005); (c). Carry Flag (CF), indicates the absence
or presence of carry out from the sign position after an addition or borrow of a subtraction, enabling it to detect
possible overflow (Carter, 2019); (d). Parity Flag (PF) indicates the number of ones in the group.

Fig. 2. Crafted program.

The program has 8 lines mainly consisted of opcodes, operands and comments showing the short
description of the instructions. The 8-line code was able to draw out the functions of the four mentioned flag
registers.
 Fig. 3. Line 09 instruction.
Figure 3 presents the instruction executed in line 09 of the program. (MOV AX, 40H) loaded 40 on
the accumulator register. At the left side of the figure, the AX register has now a value of 40, then the IP register
incremented by 3 (0103), since its main function is to increments every time, an instruction is implemented.
The IF flag has the value of 1, it recognizes the request from the peripherals, which enables us to proceed to
the next step.

Fig. 4. Line 11 instruction.

Figure 4 presents the instruction executed in line 11 of the program. (MOV BX, 45H) loaded 45 on
the accumulator register. At the left side of the figure, the BX register has now a value of 45, while AX register
still keeps a value of 40. The IP register incremented by 3 (0106), since its main function is to increments every
time, an instruction is implemented. The IF flag has the value of 1, it recognizes the request from the
peripherals, which enables us to proceed to the next step.
 Fig. 5. Line 13 instruction.
Figure 4 presents the instruction executed in line 13 of the program. (ADD AX, 50H) added a value
of 50 on the accumulator register. The AX register has now a value of 90, while BX register still keeps a value
of 45. The IP register incremented by 3 (0109), since its main function is to increments every time, an instruction
is implemented. The parity flag has the value of 1, means that sum (10010000) of 40H (1000000) and 50H
(1010000) has an even number of 1 bit equal to 2. The IF flag has the value of 1, it recognizes the request from
the peripherals, which enables us to proceed to the next step.

Fig. 6. Line 15 instruction.

Figure 6 presents the instruction executed in line 15 of the program. (ADD BX, 50H) added a value
of 50 on the base register. The BX register has now a value of 95, while AX register still keeps a value of 90.
The IP register incremented by 3 (010C), since its main function is to increments every time, an instruction is
implemented. The parity flag has the value of 1, means that sum (10010101) of 45H (1000101) and 50H
(1010000) has even number of 1 bit equal to 4. The IF flag has the value of 1, it recognizes the request from
the peripherals, which enables us to proceed to the next step.

Fig. 7. Line 17 instruction.

Figure 7 presents the instruction executed in line 17 of the program. (SUB BX, AX) diminishes the
value of the Base register of 95 to the value of Accumulator register of 90, which results to the remaining value
of 5 on the base register. The IP register incremented by 3 (010E), since its main function is to increments
every time, an instruction is implemented. The parity flag still has the value of 1, means that sum (101) of 95H
(10010101) and 90H (10010000) has an even number of 1 bit equal to 2. The IF flag has the value of 1, it
recognizes the request from the peripherals, which enables us to proceed to the next step.

Fig. 8. Line 19 instruction.

Figure 8 presents the instruction executed in line 19 of the program. (ADD BX, 20H) added a value
of 20 on the base register. The BX register has now a value of 25, while AX register still keeps a value of 90.
The IP register incremented by 3 (0111), since its main function is to increments every time, an instruction is
implemented. The parity flag has the value of 0, means that sum (100010101) of 90H (10010000) and 25H
(100101) has odd number of bits equal to 9. The IF flag has the value of 1, it recognizes the request from the
peripherals, which enables us to proceed to the next step.

Fig. 9. Line 21 instruction.

Figure 9 presents the instruction executed in line 19 of the program. (SUB AX, 60H) subtracted a
value of 60 on the accumulator register. The AX register has now a value of 30, while BX register still keeps a
value of 25. The IP register incremented by 3 (0114), since its main function is to increments every time, an
instruction is implemented. The parity flag has the value of 0, means that (110000) of 90H (110000) and 60H
(100101) has even number of 1 bit equal to 2. The IF flag has the value of 1, it recognizes the request from the
peripherals, which enables us to proceed to the next step.

Fig. 10. Line 23 instruction.

 Figure 10 presents the instruction executed in line 23 of the program. (SUB BX, AX) diminishes the
value of the Base register of 25 to the value of Accumulator register of 30, which results to the remaining value
of -5 or F5 on the base register. The IP register incremented by 3 (0116), since its main function is to increments
every time, an instruction is implemented. The Carry flag has the value of 1, since the subtraction between the
values of 25H-30H requires borrowing. The Sign Flag also has the value of 1, since the resulting value of the
BX is negative. The parity flag still has the value of 1, means that sum (-101) of 25H (100101) and 30H (110000)
has an even number of 1 bit equal to 2. The IF flag has the value of 1, still recognizes the request from the
peripherals, which enables us to proceed to the next step.

Fig. 11. Line 27 instruction

The value of the CR, SF and PF flag bit registers remain the same, since there are no other succeeding
peripheral request or instruction. And then the IF now has the value of 0, means that the processor will not
recognize any requests, since the operand ret was present.

Fig. 12. Termination

Figure 12 shows the termination of the program due to the value of the IF flag bit of 0. The program
was returned to the control of the operating system.
 The expected flag bits on the crafted program are four flags namely the: (a.) the IF, since during the
process of running the program, IF always work to cater the peripheral request of the processor; (b.) PF, since
the program involves addition and subtraction, the number of 1 bits will always change depending on the
resulting sum and difference; (c.) CF, since during the progress of the program, a lower number was subtracted
to higher number, enforcing the program to use borrowing to gain the difference; and (d.) SF, since the program
involved the subtraction between lower and higher number, the sign of the difference will be negative. A
different result could enforce if different number was inputted and different series of operations was used aside
from the two (2) employed on the program. Also, if the program did not acquire a smaller number on the base
register at the later part of the process, the resulting difference might be positive, which results to not using the
function of the Sign Flag to show the existence of negative difference in the program. The subroutine existing
inside the crafted program was the series of addition and subtraction on the registered data on the accumulator
index and base index.

References:
1. B. Pandey, S. Jain and M. Kumar, "Flag and Register Array Based High Performance Instruction Set
Architecture of Embedded Processor," 2013 International Conference on Communication Systems
and Network Technologies, 2013, pp. 716-720, doi: 10.1109/CSNT.2013.153.
2. Brey, B. B. (2009). The Intel Microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486,
Pentium, Pentium (8th ed.). New Jersey, United States of America: Pearson Prentice Hall.
3. Dandamudi, S. P. (2005). Introduction to Assembly Language Programming For Pentium and RISC
Processors. Springer Science & Business Media.