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LA-9332P - VAS10 - rX02 - 201119 Dell Alienware 18

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A B C D E

MODEL NAME : Viking 18


1
PCB NO : LA-9332P 1

BOM P/N : 4619KU31L01

Compal Confidential
2 2

Viking 18
Schematic Document
Rev: X02

3
2012-11-19 3

@ : Nopop Component

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
\\tperdfs1\CIS\SPEC\BAS40-04_SOT23-3.pdf
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 1 of 56
A B C D E
A B C D E

FFS Fan Control CPU XDP


LNG3DMTR P.49 ADM1032 P.54 Conn. P.6
LVDS Mux LVDS Mux eDP to LVDS 2-lane eDP
LVDS Conn. PI3LVD1012 P.42 PI3LVD1012 RTD2136 P.40 Intel
P.33 P.41
1 HDMI Haswell 1

DP1.1 Processor
DP/HDMI
HDMI to LVDS SW 4C 47W/57W Memory Bus DDRIII
Dual Channel 204pin DDRIII SO-DIMM x4
STDP6038 P.37 Scoket G3 BANK 0, 1, 2, 3 P.12, 13, 14,
PEGx 8 15
Gen 3 rPGA-947 1.35V DDRIII 1600 MHz
LVDS
MXM III
HDMI Redriver HDMI Conn.
P.5, 6, 7, 8, 9, 10,
PS121 P.37 11
DP1.2
DMI x4
PEGx 8 100MHz
DP/HDMI
HDMI Redriver HDMI MUX P.16 Gen 3 5GT/s
PS121 P.36 PS8271 P.36 USB3.0 Rediver
USB3.0
PS8713 P.52 USB 3.0/USB 2.0 Conn.
USB 2.0 ( USB Charger Port ) P.52
HDMI 1.3 Input
HDMI 1.4a Output
HDMI SW MXM III USB3.0 Rediver
USB3.0
2 Conn. TS3DV621 P.35 Conn. PS8713 P.52 USB 3.0/USB 2.0 Conn. 2
P.35 USB 2.0 P.52
P.17
USB3.0
USB 2.0
USB 3.0/USB 2.0 Conn.
miniDP Conn. DP Redriver mDP MUX P.52

PS8330 P.31 MAX14998


P.30 P.31
Intel USB3.0
USB 3.0/USB 2.0 Conn.
USB 2.0 P.53
Mini Card #1(Half) USB2.0
WLAN/WiMax PCI-E 2.0
Lynx Point
USB2.0 P.57
BT4.0+LE/WiGig Digital Camera
P.51
HDMI Redriver HDMI MUX PCH
USB2.0 AlienFX/ELC
PS121 P.39 PS8271 P.39 P.48,49
DMC HM87
USB2.0
Display MiniCard
PCI-E 2.0 BGA 695 Balls
P.51

SATA 3.0 SATA Rediver HDD Conn. 1


P.49
3
LAN(GbE) PCI-E 2.0 PS8520BT P.49 3

RJ45 Conn. E2201 Killer


P.46 P.46 SATA 3.0 SATA Rediver HDD Conn. 2
P.49
PS8520BT P.49
Card Reader PCI-E 2.0 HDD Conn. 3
In ODD Bay (In place of ODD)
9 in 1 Conn. RTS5209 P.50
SATA 3.0 SATA Rediver ODD Conn.
Card Reader Board P.50
PS8520BT P.50
SATA 3.0
Mini Card #3(Full)
P.17, 18, 19, 20, 21, 22, 23, 24, mSATA P.50
25

SPI ROM SPI


LPC Bus Front L/R + HP1 +MIC
8MB P.20 HD Audio P.47
RTC conn.
Center/Subwoofer + HP2
P.47
ENE KC3810 ENE KB9012 Audio Codec
Power On/Off CKT. P.43 P.43 ALC3661
P.55
Rear L/R P.47 Audio Daughter Board
4 4
DC/DC Interface CKT. P.47 Array Mics
P.56 P.57

VPK MCU Int.KBD Touch Pad


P.49
Power Circuit DC/DC Subwoofer TI Int. Speaker (2.5W*2)
P.37 VPK Daughter Board TI TPA3111D P.48 TPA3113D2 P.48 P.48

Security Classification Compal Secret Data


Issued Date 2012/02/28 Deciphered Date 2013/02/27 Title
Block Diagram

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 2 of 56
A B C D E
A B C D E

Compal Confidential
Project Code : VAS10
File Name : LA-9332P
1 1
Camera

44 pin LCD Panel


LA-9332P M/B
Coaxial/Wire Combo
FFC B To B conn.
LS-9335P LS-933GP LS-933FP 20 pin HDD3/ODD
Coaxial
POWER BUTTON/B Audio /B
HDD in ODD Bay Cable
on/off SW
Hall Sensor /B 4 pin 22pin

Led x 1
LS-933HP
6pin
Wire Right Tron Light

FFC
2 LS-933IP 2
6 pin 6pin
Wire Left Tron Light
LS-9336P
LS-9337P
INDICATOR/B
CardReader /B LS-933JP
Led-HDD
6pin
Wire Front Right Tron Light
Led-Wireless
Led-CapsLock FFC FFC HDD conn.
20 pin 30 pin LS-933KP
6pin
Card Slot
20pin Wire Front Left Tron Light

FFC FPC
60 pin Wire 20 pin
12pin
KSI/KSO
LS-9338P
30 pin PWM HDD1/HDD2
3 VPK Daughter/B Hot Key LS-XXXXP 3
6 pin
VPK Keyboard
VPK MCU MAX7313
10 pin LOGO /B
40 pin Key Pad
Led x 2

Backlight / 8 Pressure-sense Analog Signals FFC


16 pin Wire Wire Wire
6pin 6pin 6pin

LS-9333P LS-9331P LS-9332P


Touch Pad
Alien Slits-R Light/B Alien head badge/B Alien Slits-L Light/B

Led x 2 Led x 2 Led x 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram

www.vinafix.vn
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 3 of 56
A B C D E
A

USB 3.0 PORT Connetion


Board ID Table for AD channel
Vcc 3.3V +/- 5% 1 JUSB1 (Right side)
BOARD ID Table
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 2 JUSB2 (Right side)
USB PORT# DESTINATION
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1 (SSI)
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2 (PT) 3 NA 0 JUSB1(USB3.0 P1)
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3 (ST)
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.4 (QT) 4 NA
1 JUSB2(USB3.0 P2)
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 1.0 (MP)
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 5 JUSB3 (Left side)
2 JUSB3(USB3.0 P5)
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 6 JUSB4 (Left side) 3 JUSB4(USB3.0 P6)

POWER STATES PM TABLE 4 JMINI1 (WLAN)


Signal SLP SLP SLP S4 SLP ALWAYS SUS RUN CLOCKS +5VS
S3# S4# S5# STATE# M# PLANE PLANE PLANE
5 JMINI2 (DMC)
State +5VALW +3VS

power
+3VALW +1.35V +1.5VS USB2.0 6 AlienFX/ELC
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON plane +3VLP +1.05V +1.05VS
+3V_PCH +0.675VS
7 None
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON ON OFF OFF +3VMXM
+5VMXM
8 None
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF +VCC_CORE
State
+1.35V_CPU_VDDQ
9 None
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF

10 None
S0 ON ON ON
Symbol Note : 11 None
S3 ON ON OFF
: means Digital Ground 12 LVDS CAMERA
S5 S4/AC ON OFF OFF
13 VPK K/B

1
: means Analog Ground S5 S4/AC don't exist OFF OFF OFF
1

DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION


PCI EXPRESS DESTINATION
CLKOUT_PCIE0 MINI CARD-1 WLAN CLKOUTFLEX0 None
Lane 1/USB3.0 Port 3 None
CLKOUT_PCIE1 MINI CARD-2 DMC CLKOUTFLEX1 None
SATAIII DESTINATION
CLKOUT_PCIE2 10/100/1G LAN CLKOUTFLEX2 None Lane 2/USB3.0 Port 4 None
SATA0 HDD1 Lane 3 10/100/1G LAN
CLK CLKOUT_PCIE3 CARD READER CLKOUTFLEX3 None
SATA1 HDD2
CLKOUT_PCIE4 None Lane 4 CARD READER
CLKOUT DESTINATION SATA2 ODD
Lane 5 None
CLKOUT_PCIE5 None
PCI0 PCH_LOOPBACK SATA3 mSATA Lane 6 None
CLKOUT_PCIE6 None
PCI1 EC SATA4/PCIE LANE1 MINI CARD-1 WLAN
CLKOUT_PCIE7 None Lane 7 None
PCI2 80port debug card SATA5/PCIE LANE2 MINI CARD-2 DMC Lane 8 None
CLKOUT_PEG_A MXM
PCI3 None
PCI4 None

SMBUS Control Table

Thermal
SOURCE WLAN DMC BATT DIMM 6038 4028 Sensor FFS 2136 VPK MCU MXM XDP Charger TP mSATA

EC_SMB_CK1
EC_SMB_DA1
KB9012
V V V
EC_SMB_CK2
EC_SMB_DA2
KB9012
V V V V V
PCH_SML0CLK PCH Link
PCH_SML0DATA

PCH_SML1CLK PCH
PCH_SML1DATA Security Classification Compal Secret Data Compal Electronics, Inc.
2012/05/28 2013/05/27 Title
MEM_SMBCLK PCH
V V V V V V Issued Date Deciphered Date
Notes List

www.vinafix.vn
MEM_SMBDATA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 4 of 56
A
5 4 3 2 1

D +VCOMP_OUT D

PEG_COMP 2 1
24.9_0402_1%~D RC2

CAD Note: PEG_GTX_HRX_P[0..15] 29,30


PEG_GTX_HRX_N[0..15] 29,30
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils. PEG_HTX_C_GRX_P[0..15] 29,30
PEG_HTX_C_GRX_N[0..15] 29,30

Haswell rPGA EDS


JCPU1A

E23 PEG_COMP
PEG_RCOMP M29 PEG_GTX_C_HRX_N0 CC1 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N0
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28 PEG_GTX_C_HRX_N1 CC2 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N1
17 DMI_CRX_PTX_N0 C21 DMI_RXN_0 PEG_RXN_1 M31 1 2
DMI_CRX_PTX_N1 PEG_GTX_C_HRX_N2 CC3 0.22U_0402_16V7K~D PEG_GTX_HRX_N2
17 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 B21 DMI_RXN_1 PEG_RXN_2 L30 PEG_GTX_C_HRX_N3 1 2 PEG_GTX_HRX_N3
CC4 0.22U_0402_16V7K~D
17 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 A21 DMI_RXN_2 PEG_RXN_3 M33 PEG_GTX_C_HRX_N4 1 2 PEG_GTX_HRX_N4
CC5 0.22U_0402_16V7K~D
17 DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PEG_GTX_C_HRX_N5 1 2 PEG_GTX_HRX_N5
CC13 0.22U_0402_16V7K~D
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35 PEG_GTX_C_HRX_N6 CC6 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N6

PEG
17 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34 PEG_GTX_C_HRX_N7 1 2 PEG_GTX_HRX_N7
CC7 0.22U_0402_16V7K~D
17 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 B20 DMI_RXP_1 PEG_RXN_7 E29 PEG_GTX_C_HRX_N8 1 2 PEG_GTX_HRX_N8
CC8 0.22U_0402_16V7K~D
17 DMI_CRX_PTX_P2 A20 DMI_RXP_2 PEG_RXN_8 D28 1 2
DMI_CRX_PTX_P3 PEG_GTX_C_HRX_N9 CC9 0.22U_0402_16V7K~D PEG_GTX_HRX_N9
17 DMI_CRX_PTX_P3

DMI
DMI_RXP_3 PEG_RXN_9 E31 PEG_GTX_C_HRX_N10 CC10 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N10
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30 PEG_GTX_C_HRX_N11 CC11 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N11
17 DMI_CTX_PRX_N0 DMI_TXN_0 PEG_RXN_11
17 DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 C17 E35 PEG_GTX_C_HRX_N12 CC12 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N12
DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34 PEG_GTX_C_HRX_N13 CC14 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N13
17 DMI_CTX_PRX_N2 DMI_TXN_2 PEG_RXN_13
17 DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 A17 E33 PEG_GTX_C_HRX_N14 CC15 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N14
DMI_TXN_3 PEG_RXN_14 E32 PEG_GTX_C_HRX_N15 CC16 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_N15
C DMI_CTX_PRX_P0 D17 PEG_RXN_15 L29 PEG_GTX_C_HRX_P0 CC17 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P0 C
17 DMI_CTX_PRX_P0 DMI_TXP_0 PEG_RXP_0
17 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 C18 L28 PEG_GTX_C_HRX_P1 CC18 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P1
DMI_CTX_PRX_P2 B18 DMI_TXP_1 PEG_RXP_1 L31 PEG_GTX_C_HRX_P2 CC19 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P2
17 DMI_CTX_PRX_P2 DMI_TXP_2 PEG_RXP_2
17 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 A18 K30 PEG_GTX_C_HRX_P3 CC20 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P3
DMI_TXP_3 PEG_RXP_3 L33 PEG_GTX_C_HRX_P4 CC21 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P4
PEG_RXP_4 K32 PEG_GTX_C_HRX_P5 CC22 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P5
PEG_RXP_5 L35 PEG_GTX_C_HRX_P6 CC23 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P6
PEG_RXP_6 K34 PEG_GTX_C_HRX_P7 CC24 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P7
@ PEG_RXP_7 F29 PEG_GTX_C_HRX_P8 CC25 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P8
RC3 2 1 0_0402_1% FDI_CSYNC_R H29 PEG_RXP_8 E28 PEG_GTX_C_HRX_P9 CC26 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P9
17 FDI_CSYNC

FDI
RC87 2 1 0_0402_1% FDI_INT_R J29 FDI_CSYNC PEG_RXP_9 F31 PEG_GTX_C_HRX_P10 CC27 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P10
17 FDI_INT FDI_INT PEG_RXP_10 E30 1 2
@ PEG_GTX_C_HRX_P11 CC28 0.22U_0402_16V7K~D PEG_GTX_HRX_P11
PEG_RXP_11 F35 PEG_GTX_C_HRX_P12 CC29 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P12
PEG_RXP_12 E34 PEG_GTX_C_HRX_P13 CC30 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P13
PEG_RXP_13 F33 PEG_GTX_C_HRX_P14 CC31 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P14
PEG_RXP_14 D32 PEG_GTX_C_HRX_P15 CC32 1 2 0.22U_0402_16V7K~D PEG_GTX_HRX_P15
PEG_RXP_15 H35 PEG_HTX_GRX_N0 CC33 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N0
PEG_TXN_0 H34 PEG_HTX_GRX_N1 CC34 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N1
PEG_TXN_1 J33 PEG_HTX_GRX_N2 CC35 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N2
PEG_TXN_2 H32 PEG_HTX_GRX_N3 CC36 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N3
PEG_TXN_3 J31 PEG_HTX_GRX_N4 CC37 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N4
PEG_TXN_4 G30 PEG_HTX_GRX_N5 CC38 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N5
PEG_TXN_5 C33 PEG_HTX_GRX_N6 CC39 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N6
PEG_TXN_6 B32 PEG_HTX_GRX_N7 CC40 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N7
PEG_TXN_7 B31 PEG_HTX_GRX_N8 CC41 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N8
PEG_TXN_8 A30 PEG_HTX_GRX_N9 CC42 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N9
PEG_TXN_9 B29 PEG_HTX_GRX_N10 CC43 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N10
PEG_TXN_10 A28 PEG_HTX_GRX_N11 CC44 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N11
PEG_TXN_11 B27 PEG_HTX_GRX_N12 CC45 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N12
PEG_TXN_12 A26 PEG_HTX_GRX_N13 CC46 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N13
PEG_TXN_13 B25 PEG_HTX_GRX_N14 CC47 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N14
PEG_TXN_14 A24 PEG_HTX_GRX_N15 CC48 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_N15
B PEG_TXN_15 J35 PEG_HTX_GRX_P0 CC49 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P0 B
PEG_TXP_0 G34 PEG_HTX_GRX_P1 CC50 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P1
PEG_TXP_1 H33 PEG_HTX_GRX_P2 CC51 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P2
PEG_TXP_2 G32 PEG_HTX_GRX_P3 CC52 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P3
PEG_TXP_3 H31 PEG_HTX_GRX_P4 CC53 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P4
PEG_TXP_4 H30 PEG_HTX_GRX_P5 CC54 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P5
PEG_TXP_5 B33 PEG_HTX_GRX_P6 CC55 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P6
PEG_TXP_6 A32 PEG_HTX_GRX_P7 CC56 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P7
PEG_TXP_7 C31 PEG_HTX_GRX_P8 CC57 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P8
PEG_TXP_8 B30 PEG_HTX_GRX_P9 CC58 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P9
PEG_TXP_9 C29 PEG_HTX_GRX_P10 CC59 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P10
PEG_TXP_10 B28 PEG_HTX_GRX_P11 CC60 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P11
PEG_TXP_11 C27 PEG_HTX_GRX_P12 CC61 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P12
PEG_TXP_12 B26 PEG_HTX_GRX_P13 CC62 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P13
PEG_TXP_13 C25 PEG_HTX_GRX_P14 CC63 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P14
PEG_TXP_14 B24 PEG_HTX_GRX_P15 CC64 1 2 0.22U_0402_16V7K~D PEG_HTX_C_GRX_P15
PEG_TXP_15
Near MXM Connector
1 OF 9
INTEL_HASWELL_HASWELL

CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (1/7) DMI,PEG

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 5 of 56
5 4 3 2 1
5 4 3 2 1

+VCCIO_OUT

SM_DRAMPWROK with DDR Power Gating Topology

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D
1 1
+3VALW @ +VCCIO_OUT +VCCIO_OUT

CC65

CC66
@
+1.35V_CPU_VDDQ
2 2

100K_0402_5%~D
+3VALW JXDP1

1
D D

@
1 2
GND0 GND1

1
RC89

1.8K_0402_1%
Deep S3 @ CC156 XDP_PREQ#_R 3 4 CFG17 CFG17 9
1 2 XDP_PRDY#_R 5 OBSFN_A0 OBSFN_C0 6 CFG16
OBSFN_A1 OBSFN_C1 CFG16 9

RC16
7 8
@ 0.1U_0402_25V6K~D CFG0 9 GND2 GND3 10 CFG8
Place near JXDP1 9 CFG0 CFG8 9

2
2 1 +3V_PCH CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9
9 CFG1 CFG9 9

2
59 1.35V_SUS_PWRGD OBSDATA_A1 OBSDATA_C1

5
RC97 0_0402_5%~D 13 14
2 1 1 CFG2 15 GND4 GND5 16 CFG10

P
17 SYS_PWROK B 9 CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 9
RC88 0_0402_5%~D 4 RUNPWROK_AND 2 1 PM_DRAM_PWRGD_CPU 1 2 SYS_PWROK_XDP 9 CFG3 RC56 2 1 CFG3_R 17 18 CFG11 CFG11 9
2 O RC28 0_0402_5%~D @ RC125 1K_0402_1%~D @ 1K_0402_1%~D 19 OBSDATA_A3 OBSDATA_C3 20
17 PM_DRAM_PWRGD A GND6 GND7

G
UC2 XDP_OBS0 21 22 CFG19 CFG19 9
OBSFN_B0 OBSFN_D0

3.3K_0402_1%~D
1 @ 2 @ 74AHC1G09GW_TSSOP5~D XDP_OBS1 23 24 CFG18 CFG18 9
+3V_PCH

3
OBSFN_B1 OBSFN_D1

1
39_0402_5%~D
RC18 200_0402_1%~D 25 26
GND8 GND9

2
@RC64
@

RC14
9 CFG4 CFG4 27 28 CFG12 CFG12 9
OBSDATA_B0 OBSDATA_D0

RC64
9 CFG5 CFG5 29 30 CFG13 CFG13 9
31 OBSDATA_B1 OBSDATA_D1 32
2 1 CFG6 33 GND10 GND11 34 CFG14
9 CFG6 CFG14 9

2
RC94 0_0402_5%~D CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15
RC5 need to close to JCPU1 9 CFG7 CFG15 9

1
OBSDATA_B3 OBSDATA_D3

SSM3K7002FU_SC70-3~D
37 38
H_CPUPWRGD RC5 1 @ 2 1K_0402_1%~D H_CPUPWRGD_XDP 39 GND12 GND13 40 CLK_XDP RC144 1 @ 2 0_0402_5%~D
PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP 18

1
D RC6 1 @ 2 0_0402_5%~D CFD_PWRBTN#_XDP 41 42 CLK_XDP# RC145 1 2 0_0402_5%~D
17,43 PBTN_OUT# HOOK1 ITPCLK#/HOOK5 CLK_CPU_ITP# 18

@ QC1
2 43 44 @
10,56 RUN_ON_CPU1.5VS3# VCC_OBS_AB VCC_OBS_CD
G RC8 1 @ 2 0_0402_5%~D CPU_PWR_DEBUG_R 45 46 XDP_RST#_R 2 1 CPU_PLTRST#_R
10 CPU_PWR_DEBUG HOOK2 RESET#/HOOK6
S RC12 1 @ 2 0_0402_5%~D SYS_PWROK_XDP 47 48 XDP_DBRESET# RC9 @ 1K_0402_1%~D

3
17,43,62 IMVP_PWRGD 49 HOOK3 DBR#/HOOK7 50
RC126 1 @ 2 0_0402_5%~D DDR_XDP_SMBDAT_R1 51 GND14 GND15 52 XDP_TDO
12,13,14,15,19,49,50,51,53 PCH_SMBDATA 1 2 0_0402_5%~D 53 SDA TD0 54
RC127 @ DDR_XDP_SMBCLK_R1 XDP_TRST#_R
12,13,14,15,19,49,50,51,53 PCH_SMBCLK 55 SCL TRST# 56 XDP_TDI
XDP_TCLK_R 57 TCK1 TDI 58 XDP_TMS_R
59 TCK0 TMS 60 CFG3_R
GND16 GND17
SAMTE_BSH-030-01-L-D-A CONN@

+VCCIO_OUT

1 2 H_THERMTRIP#
@RC136
@ RC136 56_0402_5%~D
1 2 H_CATERR# Haswell rPGA EDS
C @RC128
@ RC128 49.9_0402_1%~D JCPU1B C
1 2 H_PROCHOT#
RC44 62_0402_5%~D AP32 MISC AP3 SM_RCOMP0
SKTOCC SM_RCOMP_0 AR3 SM_RCOMP1
SM_RCOMP_1

DDR3
AN32 AP2

THERMAL
H_CATERR# SM_RCOMP2
H_PECI AR27 CATERR SM_RCOMP_2 AN3 DDR3_DRAMRST#_CPU
21,43 H_PECI AK31 PECI SM_DRAMRST DDR3_DRAMRST#_CPU 12
PAD~D T66 @
RC57 1 2 56_0402_5%~D H_PROCHOT#_R AM30 RSVD AR29 XDP_PRDY# RC50 1 @ 2 0_0402_1% XDP_PRDY#_R
43,57 H_PROCHOT# 1 2 0_0402_1% AM35 PROCHOT PRDY AT29 1 2
RC134 @ H_THERMTRIP#_R XDP_PREQ# RC36 @ 0_0402_1% XDP_PREQ#_R
21 H_THERMTRIP# THERMTRIP PREQ AM34 XDP_TCLK 1 2 XDP_TCLK_R
place RC134 near CPU RC46 @ 0_0402_1%
TCK AN33 XDP_TMS RC47 1 @ 2 0_0402_1% XDP_TMS_R
TMS AM33 XDP_TRST# RC48 1 @ 2 0_0402_1% XDP_TRST#_R

JTAG
H_PM_SYNC AT28 TRST AM31 XDP_TDI_R RC23 1 @ 2 0_0402_1% XDP_TDI
17 H_PM_SYNC

PWR
1 @ 2 VCCPWRGOOD_0_R AL34 PM_SYNC TDI AL33 XDP_TDO_R RC24 1 @ 2 0_0402_1% XDP_TDO
21 H_CPUPWRGD PM_DRAM_PWRGD_CPU AC10 PWRGOOD TDO AP33 XDP_DBRESET#_R 1 2 XDP_DBRESET#
RC25 0_0402_1% RC26 @ 0_0402_1% XDP_DBRESET# 17
CPU_PLTRST#_R AT26 SM_DRAMPWROK DBR
PLTRSTIN AR30 XDP_OBS0_R RC30 1 @ 2 0_0402_1% XDP_OBS0
BPM_N_0 AN31 XDP_OBS1_R RC31 1 @ 2 0_0402_1% XDP_OBS1
RC51 2 @ 1 0_0402_1% CPU_DPLL# G28 BPM_N_1 AN29 XDP_OBS2_R @T68
@ T68 PAD~D
18 CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2

CLOCK
RC52 2 @ 1 0_0402_1% CPU_DPLL H28 AP31 XDP_OBS3_R @T69
@ T69 PAD~D
18 CLK_CPU_DPLL 2 1 F27 DPLL_REF_CLKP BPM_N_3 AP30
RC43 @ 0_0402_1% CPU_SSC_DPLL# XDP_OBS4_R @T70
@ T70 PAD~D
18 CLK_CPU_SSC_DPLL# 2 1 E27 SSC_DPLL_REF_CLKN BPM_N_4 AN28
RC22 @ 0_0402_1% CPU_SSC_DPLL XDP_OBS5_R @T71
@ T71 PAD~D
18 CLK_CPU_SSC_DPLL 2 1 D26 SSC_DPLL_REF_CLKP BPM_N_5 AP29
RC15 @ 0_0402_1% CPU_DMI# XDP_OBS6_R @T72
@ T72 PAD~D
18 CLK_CPU_DMI# 2 1 E26 BCLKN BPM_N_6 AP28
RC13 @ 0_0402_1% CPU_DMI XDP_OBS7_R @T73
@ T73 PAD~D
18 CLK_CPU_DMI BCLKP BPM_N_7

INTEL_HASWELL_HASWELL 2 OF 9
For ESD concern, please put near CPU
+VCCIO_OUT CONN@

CPU_SSC_DPLL 1 2
10K_0402_5%~D RC20 @
CPU_SSC_DPLL# 1 2
10K_0402_5%~D RC21 @
PU/PD for JTAG signals
+3VS

B SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21 XDP_DBRESET# RC19 2 1 1K_0402_1%~D B

+1.05VS
VCCPWRGOOD_0_R
XDP_TMS RC27 2 @ 1 51_0402_1%~D
10K_0402_5%~D

Buffered reset to CPU


1

+3VS XDP_TDI RC29 2 @ 1 51_0402_1%~D


+1.05VS CRB Rev 0.7 no pull up
RC135

XDP_PREQ# RC32 2 @ 1 51_0402_1%~D


0.1U_0402_25V6K~D

XDP_TDO RC35 2 @ 1 51_0402_1%~D


1
DDR3 COMPENSATION SIGNALS
2
1
1K_0402_1%~D

@
CC140

CRB Rev 0.7 is depop


RC17

@
@ 2 SM_RCOMP0 RC45 1 2 100_0402_1%~D XDP_TCLK RC42 2 @ 1 51_0402_1%~D
UC1 CAD Note:
2

1 5 SM_RCOMP1 RC55 1 2 75_0402_1%~D XDP_TRST# RC41 2 1 51_0402_1%~D


2 NC VCC Avoid stub in the PWRGD path
17,43,44,51,53 PLT_RST# 3 A 4 1 2
PCH_PLTRST#_BUF @ RC54 2 @ 1 0_0402_5%~D CPU_PLTRST#_R
while placing resistors RC25 & RC130 SM_RCOMP2 RC49 1 2 100_0402_1%~D
GND Y RC10 43_0402_5%~D
SN74LVC1G07DCKR_SC70-5~D CAD Note:
RC53 2 @ 1 0_0402_1%
21 CPU_PLTRST# Trace width=12~15 mil, Spcing=20 mils
20K_0402_5%~D
1

Max trace length= 500 mil


RC11

@
2

CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
CPU (2/7) PM,XDP,CLK

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 6 of 56
5 4 3 2 1
5 4 3 2 1

Haswell rPGA EDS


JCPU1C Haswell rPGA EDS
D JCPU1D D
12,14 DDR_A_D[0..63] DDR_A_D0 AR15 AC7 13,15 DDR_B_D[0..63]
@T67
@ T67 PAD~D
DDR_A_D1 AT14 SA_DQ_0 RSVD_AC7 U4 M_CLK_DDR#0 DDR_B_D0 AR18 AG8 @ T76 PAD~D
AM14 SA_DQ_1 SA_CK_N_0 V4 M_CLK_DDR#0 14 AT18 SB_DQ_0 RSVD Y4
DDR_A_D2 M_CLK_DDR0 DDR_B_D1 M_CLK_DDR#2
DDR_A_D3 AN14 SA_DQ_2 SA_CK_P_0 AD9 DDR_CKE0_DIMMA M_CLK_DDR0 14 DDR_B_D2 AM17 SB_DQ_1 SB_CKN0 AA4 M_CLK_DDR2 M_CLK_DDR#2 15
AT15 SA_DQ_3 SA_CKE_0 U3 DDR_CKE0_DIMMA 14 AM18 SB_DQ_2 SB_CK0 AF10 DDR_CKE2_DIMMB M_CLK_DDR2 15
DDR_A_D4 M_CLK_DDR#1 DDR_B_D3
DDR_A_D5 AR14 SA_DQ_4 SA_CK_N_1 V3 M_CLK_DDR1 M_CLK_DDR#1 14 DDR_B_D4 AR17 SB_DQ_3 SB_CKE_0 Y3 M_CLK_DDR#3 DDR_CKE2_DIMMB 15
DDR_A_D6 AN15 SA_DQ_5 SA_CK_P_1 AC9 DDR_CKE1_DIMMA M_CLK_DDR1 14 DDR_B_D5 AT17 SB_DQ_4 SB_CKN1 AA3 M_CLK_DDR3 M_CLK_DDR#3 15
DDR_A_D7 AM15 SA_DQ_6 SA_CKE_1 U2 M_CLK_DDR#4 DDR_CKE1_DIMMA 14 DDR_B_D6 AN17 SB_DQ_5 SB_CK1 AG10 DDR_CKE3_DIMMB M_CLK_DDR3 15
AM9 SA_DQ_7 SA_CK_N_2 V2 M_CLK_DDR#4 12 AN18 SB_DQ_6 SB_CKE_1 Y2 DDR_CKE3_DIMMB 15
DDR_A_D8 M_CLK_DDR4 DDR_B_D7 M_CLK_DDR#6
DDR_A_D9 AN9 SA_DQ_8 SA_CK_P_2 AD8 DDR_CKE4_DIMMC M_CLK_DDR4 12 DDR_B_D8 AT12 SB_DQ_7 SB_CKN2 AA2 M_CLK_DDR6 M_CLK_DDR#6 13
DDR_A_D10 AM8 SA_DQ_9 SA_CKE_2 U1 M_CLK_DDR#5 DDR_CKE4_DIMMC 12 DDR_B_D9 AR12 SB_DQ_8 SB_CK2 AG9 DDR_CKE6_DIMMD M_CLK_DDR6 13
DDR_A_D11 AN8 SA_DQ_10 SA_CK_N_3 V1 M_CLK_DDR5 M_CLK_DDR#5 12 DDR_B_D10 AN12 SB_DQ_9 SB_CKE_2 Y1 M_CLK_DDR#7 DDR_CKE6_DIMMD 13
DDR_A_D12 AR9 SA_DQ_11 SA_CK_P_3 AC8 DDR_CKE5_DIMMC M_CLK_DDR5 12 DDR_B_D11 AM11 SB_DQ_10 SB_CKN3 AA1 M_CLK_DDR7 M_CLK_DDR#7 13
DDR_A_D13 AT9 SA_DQ_12 SA_CKE_3 DDR_CKE5_DIMMC 12 DDR_B_D12 AT11 SB_DQ_11 SB_CK3 AF9 DDR_CKE7_DIMMD M_CLK_DDR7 13
DDR_A_D14 AR8 SA_DQ_13 M7 DDR_CS0_DIMMA# DDR_B_D13 AR11 SB_DQ_12 SB_CKE_3 DDR_CKE7_DIMMD 13
DDR_A_D15 AT8 SA_DQ_14 SA_CS_N_0 L9 DDR_CS1_DIMMA# DDR_CS0_DIMMA# 14 DDR_B_D14 AM12 SB_DQ_13 P4 DDR_CS2_DIMMB#
DDR_A_D16 AJ9 SA_DQ_15 SA_CS_N_1 M9 DDR_CS4_DIMMC# DDR_CS1_DIMMA# 14 DDR_B_D15 AN11 SB_DQ_14 SB_CS_N_0 R2 DDR_CS3_DIMMB# DDR_CS2_DIMMB# 15
AK9 SA_DQ_16 SA_CS_N_2 M10 DDR_CS4_DIMMC# 12 AR5 SB_DQ_15 SB_CS_N_1 P3 DDR_CS3_DIMMB# 15
DDR_A_D17 DDR_CS5_DIMMC# DDR_B_D16 DDR_CS6_DIMMD#
DDR_A_D18 AJ6 SA_DQ_17 SA_CS_N_3 M8 M_ODT0 DDR_CS5_DIMMC# 12 DDR_B_D17 AR6 SB_DQ_16 SB_CS_N_2 P1 DDR_CS7_DIMMD# DDR_CS6_DIMMD# 13
DDR_A_D19 AK6 SA_DQ_18 SA_ODT_0 L7 M_ODT1 M_ODT0 14 DDR_B_D18 AM5 SB_DQ_17 SB_CS_N_3 DDR_CS7_DIMMD# 13
DDR_A_D20 AJ10 SA_DQ_19 SA_ODT_1 L8 M_ODT4 M_ODT1 14 DDR_B_D19 AM6 SB_DQ_18 R4 M_ODT2
DDR_A_D21 AK10 SA_DQ_20 SA_ODT_2 L10 M_ODT5 M_ODT4 12 DDR_B_D20 AT5 SB_DQ_19 SB_ODT_0 R3 M_ODT3 M_ODT2 15
DDR_A_D22 AJ7 SA_DQ_21 SA_ODT_3 V5 DDR_A_BS0 M_ODT5 12 DDR_B_D21 AT6 SB_DQ_20 SB_ODT_1 R1 M_ODT6 M_ODT3 15
DDR_A_D23 AK7 SA_DQ_22 SA_BS_0 U5 DDR_A_BS1 DDR_A_BS0 12,14 DDR_B_D22 AN5 SB_DQ_21 SB_ODT_2 P2 M_ODT7 M_ODT6 13
AF4 SA_DQ_23 SA_BS_1 AD1 DDR_A_BS1 12,14 AN6 SB_DQ_22 SB_ODT_3 R7 M_ODT7 13
DDR_A_D24 DDR_A_BS2 DDR_B_D23 DDR_B_BS0
DDR_A_D25 AF5 SA_DQ_24 SA_BS_2 DDR_A_BS2 12,14 DDR_B_D24 AJ4 SB_DQ_23 SB_BS_0 P8 DDR_B_BS1 DDR_B_BS0 13,15
DDR_A_D26 AF1 SA_DQ_25 V10 DDR_B_D25 AK4 SB_DQ_24 SB_BS_1 AA9 DDR_B_BS2 DDR_B_BS1 13,15
DDR_A_D27 AF2 SA_DQ_26 RSVD_V10 U6 DDR_A_RAS# DDR_B_D26 AJ1 SB_DQ_25 SB_BS_2 DDR_B_BS2 13,15
DDR_A_D28 AG4 SA_DQ_27 SA_RAS U7 DDR_A_WE# DDR_A_RAS# 12,14 DDR_B_D27 AJ2 SB_DQ_26 R10
AG5 SA_DQ_28 SA_WE U8 DDR_A_WE# 12,14 AM1 SB_DQ_27 RSVD R6
DDR_A_D29 DDR_A_CAS# DDR_B_D28 DDR_B_RAS#
DDR_A_D30 AG1 SA_DQ_29 SA_CAS DDR_A_CAS# 12,14 DDR_B_D29 AN1 SB_DQ_28 SB_RAS P6 DDR_B_WE# DDR_B_RAS# 13,15
C DDR_A_D31 AG2 SA_DQ_30 V8 DDR_A_MA0 DDR_A_MA[0..15] 12,14 DDR_B_D30 AK2 SB_DQ_29 SB_WE P7 DDR_B_CAS# DDR_B_WE# 13,15 C
DDR_A_D32 J1 SA_DQ_31 SA_MA_0 AC6 DDR_A_MA1 DDR_B_D31 AK1 SB_DQ_30 SB_CAS DDR_B_CAS# 13,15
J2 SA_DQ_32 SA_MA_1 V9 L2 SB_DQ_31 R8 DDR_B_MA[0..15] 13,15
DDR_A_D33 DDR_A_MA2 DDR_B_D32 DDR_B_MA0
DDR_A_D34 J5 SA_DQ_33 SA_MA_2 U9 DDR_A_MA3 DDR_B_D33 M2 SB_DQ_32 SB_MA_0 Y5 DDR_B_MA1
DDR_A_D35 H5 SA_DQ_34 SA_MA_3 AC5 DDR_A_MA4 DDR_B_D34 L4 SB_DQ_33 SB_MA_1 Y10 DDR_B_MA2
DDR_A_D36 H2 SA_DQ_35 SA_MA_4 AC4 DDR_A_MA5 DDR_B_D35 M4 SB_DQ_34 SB_MA_2 AA5 DDR_B_MA3
DDR_A_D37 H1 SA_DQ_36 SA_MA_5 AD6 DDR_A_MA6 DDR_B_D36 L1 SB_DQ_35 SB_MA_3 Y7 DDR_B_MA4
DDR_A_D38 J4 SA_DQ_37 SA_MA_6 AC3 DDR_A_MA7 DDR_B_D37 M1 SB_DQ_36 SB_MA_4 AA6 DDR_B_MA5
DDR_A_D39 H4 SA_DQ_38 SA_MA_7 AD5 DDR_A_MA8 DDR_B_D38 L5 SB_DQ_37 SB_MA_5 Y6 DDR_B_MA6
DDR_A_D40 F2 SA_DQ_39 SA_MA_8 AC2 DDR_A_MA9 DDR_B_D39 M5 SB_DQ_38 SB_MA_6 AA7 DDR_B_MA7
DDR_A_D41 F1 SA_DQ_40 SA_MA_9 V6 DDR_A_MA10 DDR_B_D40 G7 SB_DQ_39 SB_MA_7 Y8 DDR_B_MA8
DDR_A_D42 D2 SA_DQ_41 SA_MA_10 AC1 DDR_A_MA11 DDR_B_D41 J8 SB_DQ_40 SB_MA_8 AA10 DDR_B_MA9
DDR_A_D43 D3 SA_DQ_42 SA_MA_11 AD4 DDR_A_MA12 DDR_B_D42 G8 SB_DQ_41 SB_MA_9 R9 DDR_B_MA10
DDR_A_D44 D1 SA_DQ_43 SA_MA_12 V7 DDR_A_MA13 DDR_B_D43 G9 SB_DQ_42 SB_MA_10 Y9 DDR_B_MA11
DDR_A_D45 F3 SA_DQ_44 SA_MA_13 AD3 DDR_A_MA14 DDR_B_D44 J7 SB_DQ_43 SB_MA_11 AF7 DDR_B_MA12
DDR_A_D46 C3 SA_DQ_45 SA_MA_14 AD2 DDR_A_MA15 DDR_B_D45 J9 SB_DQ_44 SB_MA_12 P9 DDR_B_MA13
DDR_A_D47 B3 SA_DQ_46 SA_MA_15 DDR_B_D46 G10 SB_DQ_45 SB_MA_13 AA8 DDR_B_MA14
DDR_A_D48 B5 SA_DQ_47 DDR_B_D47 J10 SB_DQ_46 SB_MA_14 AG7 DDR_B_MA15
E6 SA_DQ_48 AP15 DDR_A_DQS#[0..7] 12,14 A8 SB_DQ_47 SB_MA_15
DDR_A_D49 DDR_A_DQS#0 DDR_B_D48
DDR_A_D50 A5 SA_DQ_49 SA_DQS_N_0 AP8 DDR_A_DQS#1 DDR_B_D49 B8 SB_DQ_48
DDR_A_D51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 DDR_A_DQS#2 DDR_B_D50 A9 SB_DQ_49 AP18 DDR_B_DQS#0 DDR_B_DQS#[0..7] 13,15
DDR_A_D52 D5 SA_DQ_51 SA_DQS_N_2 AF3 DDR_A_DQS#3 DDR_B_D51 B9 SB_DQ_50 SB_DQS_N_0 AP11 DDR_B_DQS#1
DDR_A_D53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDR_A_DQS#4 DDR_B_D52 D8 SB_DQ_51 SB_DQS_N_1 AP5 DDR_B_DQS#2
DDR_A_D54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDR_A_DQS#5 DDR_B_D53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 DDR_B_DQS#3
DDR_A_D55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDR_A_DQS#6 DDR_B_D54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDR_B_DQS#4
DDR_A_D56 E12 SA_DQ_55 SA_DQS_N_6 C11 DDR_A_DQS#7 DDR_B_D55 E9 SB_DQ_54 SB_DQS_N_4 H9 DDR_B_DQS#5
DDR_A_D57 D12 SA_DQ_56 SA_DQS_N_7 AP14 DDR_A_DQS0 DDR_A_DQS[0..7] 12,14 DDR_B_D56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDR_B_DQS#6
DDR_A_D58 B11 SA_DQ_57 SA_DQS_P_0 AP9 DDR_A_DQS1 DDR_B_D57 D15 SB_DQ_56 SB_DQS_N_6 C14 DDR_B_DQS#7
DDR_A_D59 A11 SA_DQ_58 SA_DQS_P_1 AK8 DDR_A_DQS2 DDR_B_D58 A15 SB_DQ_57 SB_DQS_N_7 AP17 DDR_B_DQS0 DDR_B_DQS[0..7] 13,15
DDR_A_D60 E11 SA_DQ_59 SA_DQS_P_2 AG3 DDR_A_DQS3 DDR_B_D59 B15 SB_DQ_58 SB_DQS_P_0 AP12 DDR_B_DQS1
DDR_A_D61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDR_A_DQS4 DDR_B_D60 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDR_B_DQS2
DDR_A_D62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDR_A_DQS5 DDR_B_D61 D14 SB_DQ_60 SB_DQS_P_2 AK3 DDR_B_DQS3
B DDR_A_D63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDR_A_DQS6 DDR_B_D62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDR_B_DQS4 B
AM3 SA_DQ_63 SA_DQS_P_6 C12 DDR_A_DQS7 DDR_B_D63 B14 SB_DQ_62 SB_DQS_P_4 H8 DDR_B_DQS5
+V_SM_VREF SM_VREF SA_DQS_P_7 SB_DQ_63 SB_DQS_P_5
F16 C9 DDR_B_DQS6
+DIMM0_1_VREF SA_DIMM_VREFDQ SB_DQS_P_6
F13 C15 DDR_B_DQS7
+DIMM0_1_CA SB_DIMM_VREFDQ SB_DQS_P_7

4 OF 9 INTEL_HASWELL_HASWELL
3 OF 9 INTEL_HASWELL_HASWELL +1.35V
+1.35V +1.35V
CONN@
CONN@
1

1
1K_0402_1%~D

1K_0402_1%~D

1
1K_0402_1%~D
RC96

RC95

+DIMM0_1_CA +DIMM0_1_VREF

RC86
+DIMM0_1_CA_CPU +DIMM0_1_VREF_CPU +V_SM_VREF
2

RC147 RC148 +V_SM_VREF_CNT

2
RC146
1 2 1 2
1 2
1 1
1K_0402_1%~D

1K_0402_1%~D

2_0402_1%~D 2_0402_1%~D 1
1

1K_0402_1%~D
CC137 CC138 2_0402_1%~D 1
RC82

RC81

0.022U_0402_25V7K~D 0.022U_0402_25V7K~D CC139


2 2 0.022U_0402_25V7K~D
RC78
2
2

2
1

2
1

RC150 RC151
24.9_0402_1% 24.9_0402_1% RC149
24.9_0402_1%
A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (3/7) DDRIII

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 7 of 56
5 4 3 2 1
5 4 3 2 1

COMPENSATION PU FOR eDP


+VCOMP_OUT

EDP_COMP 2 1
24.9_0402_1%~D RC1
D D
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

Haswell rPGA EDS


JCPU1H

CPU_HDMI_N2 T28 M27 CPU_EDP_AUX#


36 CPU_HDMI_N2 CPU_HDMI_P2 U28 DDIB_TXBN_0 EDP_AUXN N27 CPU_EDP_AUX CPU_EDP_AUX# 40
36 CPU_HDMI_P2 CPU_HDMI_N1 T30 DDIB_TXBP_0 EDP_AUXP P27 EDP_HPD CPU_EDP_AUX 40
36 CPU_HDMI_N1 CPU_HDMI_P1 U30 DDIB_TXBN_1 eDP
EDP_HPD E24 EDP_COMP
HDMI 36
36
36
CPU_HDMI_P1
CPU_HDMI_N0
CPU_HDMI_P0
CPU_HDMI_N0
CPU_HDMI_P0
CPU_HDMI_N3
U29
V29
U31
DDIB_TXBP_1
DDIB_TXBN_2
DDIB_TXBP_2
EDP_RCOMP
RSVD
R27
PAD~D T77 @
36 CPU_HDMI_N3 CPU_HDMI_P3 V31 DDIB_TXBN_3
36 CPU_HDMI_P3 DDIB_TXBP_3 P35 CPU_EDP_N0
CPU_mDP_N0 T34 EDP_TXN_0 R35 CPU_EDP_P0 CPU_EDP_N0 40
31 CPU_mDP_N0 DDIC_TXCN_0 EDP_TXP_0 CPU_EDP_P0 40
31 CPU_mDP_P0 CPU_mDP_P0 U34 N34 CPU_EDP_N1
CPU_mDP_N1 U35 DDIC_TXCP_0 EDP_TXN_1 P34 CPU_EDP_P1 CPU_EDP_N1 40
31 CPU_mDP_N1 DDIC_TXCN_1 EDP_TXP_1 CPU_EDP_P1 40
CPU_mDP_P1 V35 P33

mDP 31
31
31
31
CPU_mDP_P1
CPU_mDP_N2
CPU_mDP_P2
CPU_mDP_N3
CPU_mDP_N2
CPU_mDP_P2
CPU_mDP_N3
U32
T32
U33
DDIC_TXCP_1
DDIC_TXCN_2
DDIC_TXCP_2
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
R33
N32
P32
CPU_mDP_P3 V33 DDIC_TXCN_3 FDI_TXP_1
31 CPU_mDP_P3 DDIC_TXCP_3
C CPU_DPD_DMC_N0 P29 C
39 CPU_DPD_DMC_N0 DDID_TXDN_0
39 CPU_DPD_DMC_P0 CPU_DPD_DMC_P0 R29
CPU_DPD_DMC_N1 N28 DDID_TXDP_0
39 CPU_DPD_DMC_N1 DDID_TXDN_1 DDI
CPU_DPD_DMC_P1 P28
DMC 39
39
39
CPU_DPD_DMC_P1
CPU_DPD_DMC_N2
CPU_DPD_DMC_P2
CPU_DPD_DMC_N2
CPU_DPD_DMC_P2
CPU_DPD_DMC_N3
P31
R31
N30
DDID_TXDP_1
DDID_TXDN_2
DDID_TXDP_2
39 CPU_DPD_DMC_N3 DDID_TXDN_3
39 CPU_DPD_DMC_P3 CPU_DPD_DMC_P3 P30
DDID_TXDP_3

INTEL_HASWELL_HASWELL 8 OF 9

CONN@

+VCCIO_OUT

1
B
HPD INVERSION FOR EDP 10K_0402_5%~D
RC65 B

2
EDP_HPD

BSS138_SOT23~D
1
D

QC10
2
40 CPU_EDP_HPD#
G
S

3
100K_0402_5%~D
1
RC75
2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (4/7) FDI,eDP,DDI

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 8 of 56
5 4 3 2 1
5 4 3 2 1

CFG STRAPS for CPU


CFG2

1K_0402_1%~D
1
D D

@RC76
@ RC76
2
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2 definition matches socket pin map definition
0:Lane Reversed
Haswell rPGA EDS

JCPU1I

CFG4
@T103PAD~D
@ T103PAD~D AT1
RSVD_TP

1K_0402_1%~D
@T80
@ T80 PAD~D AT2 C23 PAD~D T99 @
RSVD_TP RSVD_TP

1
@T78
@ T78 PAD~D AD10 B23 PAD~D T90 @
RSVD RSVD_TP

RC77
D24 PAD~D T87 @
@T110PAD~D
@ T110PAD~D A34 RSVD_TP D23 PAD~D T88 @
@T81
@ T81 PAD~D A35 RSVD_TP RSVD_TP
RSVD_TP

2
@ T79 PAD~D
@T79 W29
@ T101PAD~D
@T101PAD~D W28 RSVD AT31 CFG_RCOMP
C H_CPU_RSVD G26 RSVD CFG_RCOMP AR21 CFG16 C
W33 RSVD CFG_16 AR23 CFG18 CFG16 6
AL30 RSVD CFG_18 AP21 CFG18 6
@ T83 PAD~D
@T83 CFG17
AL29 RSVD CFG_17 AP23 CFG19 CFG17 6
@ T108PAD~D
@T108PAD~D
+VCC_CORE
F25 RSVD CFG_19 CFG19 6 Display Port Presence Strap
VCC
@ T82 PAD~D
@T82 C35 AR33 PAD~D T91 @
@T94
@ T94 PAD~D B35 RSVD_TP RSVD G6 PAD~D T104@ 1 : Disabled; No Physical Display Port
RSVD_TP RSVD AM27 PAD~D T92 @
@T85
@ T85 PAD~D AL25 RSVD AM26 PAD~D T89 @ CFG4 attached to Embedded Display Port
RSVD_TP RSVD F5 PAD~D T93 @
@ T84 PAD~D
@T84 W30 RSVD AM2 PAD~D T95 @ 0 : Enabled; An external Display Port device is
@T86
@ T86 PAD~D W31 RSVD RSVD K6 PAD~D T111@
H_CPU_TESTLO W34 RSVD RSVD connected to the Embedded Display Port
TESTLO E18 PAD~D T96 @
CFG0 AT20 RSVD
6 CFG0 CFG1 AR20 CFG_0 U10 CFG6
PAD~D T98 @
6 CFG1 CFG2 AP20 CFG_1 RSVD P10 PAD~D T97 @
6 CFG2 AP22 CFG_2 RSVD
CFG3 CFG5
6 CFG3 CFG_3

1K_0402_1%~D
CFG4 AT22 B1
6 CFG4 CFG_4 NC

1
1K_0402_1%~D
CFG5 AN22 A2 PAD~D T100 @
6 CFG5 CFG_5 RSVD

@ RC92
CFG6 AT25 AR1 PAD~D T109 @
6 CFG6 CFG_6 RSVD_TP

RC90
CFG7 AN23
6 CFG7 CFG8 AR24 CFG_7 E21 PAD~D T102 @
6 CFG8 CFG9 AT23 CFG_8 RSVD_TP E20 PAD~D T107 @
6 CFG9

2
CFG10 AN20 CFG_9 RSVD_TP
6 CFG10 CFG11 AP24 CFG_10 AP27
6 CFG11 AP26 CFG_11 RSVD AR26
CFG12
6 CFG12 CFG13 AN25 CFG_12 RSVD
6 CFG13 CFG14 AN26 CFG_13 AL31 PAD~D T105 @
6 CFG14 CFG15 AP25 CFG_14 RSVD AL32 PAD~D T106 @
6 CFG15 CFG_15 RSVD
B PCIE Port Bifurcation Straps B

2 1 H_CPU_TESTLO INTEL_HASWELL_HASWELL 9 OF 9 11: (Default) x16 - Device 1 functions 1 and 2 disabled


RC60 49.9_0402_1%~D
2 1 CFG_RCOMP
CONN@
10: x8, x8 - Device 1 function 1 enabled ; function 2
RC58 49.9_0402_1%~D
2 1 H_CPU_RSVD CFG[6:5] disabled
RC59 49.9_0402_1%~D 01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1
1K_0402_1%~D
@RC91
@ RC91
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately
A CFG7 following xxRESETB de assertion A

0: PEG Wait for BIOS for training

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (5/7) RSVD,CFG

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 9 of 56
5 4 3 2 1
5 4 3 2 1

+1.35V +1.35V_CPU_VDDQ
@
JP4
1 2

PAD-OPEN 4x4m

@
JP5
1 2

PAD-OPEN 4x4m
D +1.35V_CPU_VDDQ Source @
Haswell rPGA EDS
JCPU1E
+VCC_CORE
D

+1.35V QC3 +1.35V_CPU_VDDQ


+3VALW B+_BIAS AO4304L_SO8 AA26
8 1 VCC AA28
VCC

330K_0402_5%~D

10U_0603_6.3V6M~D
7 2 @ T113
@T113 PAD~D K27 AA34
RSVD VCC

1
20K_0402_5%~D
6 3 1 @T114
@ T114 PAD~D L27 AA30
RSVD VCC

100K_0402_5%~D

RC72

CC135
5 @T112
@ T112 PAD~D T27 AA32
RSVD VCC

@ RC73
@ @T116
@ T116 PAD~D V27 AB26
RSVD VCC

RC74
@ AB29

4
@ 2 +1.35V_CPU_VDDQ VCC AB25

2
RUN_ON_CPU1.5VS3 +1.35V VCC AB27
@ VCC AB28

2
VCC

0.022U_0402_25V7K~D
CC151 2 1 0.1U_0402_10V7K~D AB11 AB30
VDDQ VCC

DMN66D0LDW-7_SOT363-6~D
@ AB2 AB31
VDDQ VCC

1
QC4B

1M_0402_5%~D
1 CC152 2 1 0.1U_0402_10V7K~D AB5 AB33
VDDQ VCC

RC143
RUN_ON_CPU1.5VS3# 5 @ @ AB8 AB34
VDDQ VCC

CC136
@ AE11 AB32
VDDQ VCC

DMN66D0LDW-7_SOT363-6~D
AE2 AC26

4
2 AE5 VDDQ VCC AB35

2
VDDQ VCC

6
AE8 AC28
1 @ 2 AH11 VDDQ VCC AD25
43,56,59,60,61 SUSP# VDDQ VCC

QC4A
RC93 0_0402_5%~D @ K11 AC30
1 @ 2 2 N11 VDDQ VCC AD28
43 CPU1.5V_S3_GATE N8 VDDQ VCC AC32
RC79 0_0402_5%~D
T11 VDDQ VCC AD31

1
T2 VDDQ VCC AC34
T5 VDDQ VCC AD34
T8 VDDQ VCC AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
RUN_ON_CPU1.5VS3# 56,6 W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
@T115
@ T115 PAD~D N26 VCC AD35
K26 RSVD VCC AE26
+VCC_CORE VCC VCC
AL27 AE32
@ T151
@T151 PAD~D AK27 RSVD VCC AE28
@T152
@ T152 PAD~D RSVD VCC AE30
VCC AG28
C
VCC AG34 C
VCC AE34
+1.05VS +VCCIO_OUT VCC AF25
+VCCIO_OUT VCC AF26
SVID ALERT @ RC4
2 1
0_0603_5%~D @T153
@ T153 PAD~D
VCCSENSE_R AL35
E17 VCC_SENSE
RSVD
VCC
VCC
VCC
AF27
AF28
75_0402_1%~D

AN35 AF29
+VCCIO_OUT VCCIO_OUT VCC
1

A23 AF30
@ T156 PAD~D VCCIO2PCH VCC
RC61

CAD Note: Place the PU resistors close to CPU +VCOMP_OUT


F22 AF31
W32 VCCIOA_OUT VCC AF32
RESISTOR STUFFING OPTIONS ARE RSVD VCC
RC60 close to CPU 300 - 1500mils PROVIDED FOR TESTING PURPOSES @T160
@ T160 PAD~D AL16 AF33
@ T159
@T159 PAD~D J27 RSVD VCC AF34
2

@T177
@ T177 PAD~D AL13 VSS VCC AF35
2 1 H_CPU_SVIDALRT# +1.05VS @T154
@ T154 PAD~D RSVD VCC AG26
62 VIDALERT_N VCC AH26
43_0402_5%~D RC69
H_CPU_SVIDALRT# AM28 VCC AH29
VIDSCLK AM29 VIDALERT VCC AG30
+VCCIO_OUT 62 VIDSCLK VIDSCLK VCC

150_0402_5%~D
VIDSOUT AL28 AG32
VIDSOUT VCC

1
AH32
SVID DATA AP35 VCC AH35
0.1U_0402_25V6K~D

VSS VCC

RC80
1 H27 AH25
6 CPU_PWR_DEBUG PWR_DEBUG VCC
1

CAD Note: Place the PU resistors close to CPU AP34 AH27


RC63 CC192 AT35 RSVD VCC AH28

2
RC63 close to CPU 300 - 1500mils @ T157
@T157 PAD~D AR35 RSVD VCC AH30
130_0402_1%~D RSVD VCC
2 CPU_PWR_DEBUG @T158
@ T158 PAD~D AR32 AH31
@ RSVD VCC
@T162
@ T162 PAD~D AL26 AH33
2

RSVD VCC

10K_0402_5%~D
@T163
@ T163 PAD~D AT34 AH34
RSVD VCC

1
VIDSOUT AL22 AJ25
62 VIDSOUT RSVD VCC

@
AT33 AJ26
RSVD VCC

RC71
AM21 AJ27
AM25 RSVD VCC AJ28
AM22 RSVD VCC AJ29

2
AM20 RSVD VCC AJ30
AM24 RSVD VCC AJ31
+VCC_CORE AL19 RSVD VCC AJ32
AM23 RSVD VCC AJ33
AT32 RSVD VCC AJ34
VCC_SENSE RSVD VCC AJ35
0.1U_0402_25V6K~D

VCC
100_0402_1%~D

1 G25
VCC
1

H25
B VCC B
RC66

CC193 J25
VCC K25
2 +VCC_CORE VCC L25
@ VCC
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU M25
2

+1.35V_CPU_VDDQ Y25 VCC N25


CC194 @ VDDQ DECOUPLING Y26 VCC VCC P25
VCCSENSE RC67 2 @ 1 VCCSENSE_R 1 2 Y27 VCC VCC R25
62 VCCSENSE Y28 VCC VCC T25
0_0402_1% 0.1U_0402_25V6K~D
Y29 VCC VCC
VCC
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D
Y30 U25
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU @1 @1 @1 @1 @1
1 1
Y31 VCC VCC U26
1 1 1 1 1 VCC VCC

CC167

CC171
+ + Y32 V25
VCC VCC
CC180

CC170

CC169

CC168

CC161

CC162

CC163

CC164

CC165

CC166
VSSSENSE RC68 2 @ 1 VSSSENSE_R Y33 V26
62 VSSSENSE VSSSENSE_R 11 Y34 VCC VCC
0_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 Y35 VCC W26
VCC VCC
1
100_0402_1%~D

W27
VCC
RC70

INTEL_HASWELL_HASWELL 5 OF 9

CONN@
2

@
22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
1 1 1 1 1 1 1 1 1 1 1
CC181

CC182

CC183

CC184

CC185

CC186

CC187

CC188

CC189

CC190

CC191
C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW

C_0805NEW
2 2 2 2 2 2 2 2 2 2 2

@ @ @ @ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
CPU (6/7) PWR

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 10 of 56
5 4 3 2 1
5 4 3 2 1

D Haswell rPGA EDS Haswell rPGA EDS D


JCPU1F JCPU1G

A10 AK34 B34 K10


A13 VSS VSS AK5 B4 VSS VSS K2
A16 VSS VSS AL1 B7 VSS VSS K29
A19 VSS VSS AL10 C1 VSS VSS K3
A22 VSS VSS AL11 C10 VSS VSS K31
A25 VSS VSS AL12 C13 VSS VSS K33
A27 VSS VSS AL14 C16 VSS VSS K35
A29 VSS VSS AL15 C19 VSS VSS K4
A3 VSS VSS AL17 C2 VSS VSS K5
A31 VSS VSS AL18 C22 VSS VSS K7
A33 VSS VSS AL2 C24 VSS VSS K8
A4 VSS VSS AL20 C26 VSS VSS K9
A7 VSS VSS AL21 C28 VSS VSS L11
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AA31 VSS VSS AL4 C4 VSS VSS M26
AA29 VSS VSS AL5 C7 VSS VSS M28
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AC27 VSS VSS AM16 D27 VSS VSS N2
AB4 VSS VSS AM19 D29 VSS VSS N29
AB6 VSS VSS E25 D31 VSS VSS N3
AB7 VSS VSS AM32 D33 VSS VSS N31
AB9 VSS VSS AM4 D35 VSS VSS N33
AC11 VSS VSS AM7 D4 VSS VSS N35
C AD11 VSS VSS AN10 D7 VSS VSS N4 C
AC29 VSS VSS AN13 E1 VSS VSS N5
AC31 VSS VSS AN16 E10 VSS VSS N6
AC33 VSS VSS AN19 E13 VSS VSS N7
AC35 VSS VSS AN2 E16 VSS VSS N9
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 VSS VSS AN27 F10 VSS VSS P5
AE25 VSS VSS AN30 F11 VSS VSS R11
AE29 VSS VSS AN34 F12 VSS VSS R26
AE3 VSS VSS AN4 F14 VSS VSS R28
AE27 VSS VSS AN7 F15 VSS VSS R30
AE35 VSS VSS AP1 F17 VSS VSS R32
AE4 VSS VSS AP10 F18 VSS VSS R34
AE6 VSS VSS AP13 F20 VSS VSS R5
AE7 VSS VSS AP16 F21 VSS VSS T1
AE9 VSS VSS AP19 F23 VSS VSS T10
AF11 VSS VSS AP4 F24 VSS VSS T29
AF6 VSS VSS AP7 F26 VSS VSS T3
AF8 VSS VSS W25 F28 VSS VSS T31
AG11 VSS VSS AR10 F30 VSS VSS T33
AG25 VSS RSVD AR13 F32 VSS VSS T35
AE31 VSS VSS AR16 F34 VSS VSS T4
AG31 VSS VSS AR19 F4 VSS VSS T6
AE33 VSS VSS AR2 F6 VSS VSS T7
AG6 VSS VSS AR22 F7 VSS VSS T9
AH1 VSS VSS AR25 F8 VSS VSS U11
AH10 VSS VSS AR28 F9 VSS VSS U27
AH2 VSS VSS AR31 G1 VSS VSS V11
AG27 VSS VSS AR34 G11 VSS VSS V28
AG29 VSS VSS AR4 G2 VSS VSS V30
AH3 VSS VSS AR7 G27 VSS VSS V32
B AG33 VSS VSS AT10 G29 VSS VSS V34 B
AG35 VSS VSS AT13 G3 VSS VSS W1
AH4 VSS VSS AT16 G31 VSS VSS W10
AH5 VSS VSS AT19 G33 VSS VSS W3
AH6 VSS VSS AT21 G35 VSS VSS W35
AH7 VSS VSS AT24 G4 VSS VSS W4
AH8 VSS VSS AT27 G5 VSS VSS W6
AH9 VSS VSS AT3 H10 VSS VSS W7
AJ11 VSS VSS AT30 H26 VSS VSS W9
AJ5 VSS VSS AT4 H6 VSS VSS Y11
AK11 VSS VSS AT7 H7 VSS VSS H11
AK25 VSS VSS B10 J11 VSS RSVD AL24
AK26 VSS VSS B13 J26 VSS RSVD F19
AK28 VSS VSS B16 J28 VSS RSVD T26
AK29 VSS VSS B19 J30 RSVD RSVD AK35
AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE_R 10
AK32 VSS VSS B22 J34 VSS RSVD PAD~D T120
@
E19 VSS VSS J6 VSS
VSS K1 VSS
VSS

INTEL_HASWELL_HASWELL 6 OF 9 INTEL_HASWELL_HASWELL 7 OF 9

CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU (7/7) VSS

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 11 of 56
5 4 3 2 1
5 4 3 2 1

+1.35V

1
1K_0402_5%~D
RD27
@
CRB Rev 0.7 is depop
JDIMMA H=9.2mm

2
D D

DDR3_DRAMRST#_R 1 2
+DIMM0_1_VREF_CPU 13,14,15 DDR3_DRAMRST#_R DDR3_DRAMRST#_CPU 6
RD29 0_0402_5%~D
+1.35V +1.35V
JDIMA0
1 2
3 VREF_DQ VSS1 4 DDR_A_D4
All VREF traces should VSS2 DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_A_D0 5 6 DDR_A_D5
have 20 mil trace width DDR_A_D1 7 DQ0 DQ5 8
1 1 DQ1 VSS3
9 10 DDR_A_DQS#0
VSS4 DQS#0

CD1

CD2
11 12 DDR_A_DQS0
@ 13 DM0 DQS0 14
2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
14,7 DDR_A_DQS#[0..7] 25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
14,7 DDR_A_D[0..63] 29 DQS#1 DM1 30
DDR_A_DQS1 DDR3_DRAMRST#_R
31 DQS1 RESET# 32
14,7 DDR_A_DQS[0..7] 33 VSS11 VSS12 34
DDR_A_D10 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
14,7 DDR_A_MA[0..15] 37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
Layout Note: DDR_A_D19 53 DQ18 DQ23 54
Place near JDIMMA 55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
+1.35V DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
C DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31 C
71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1
DDR_CKE4_DIMMC 73 74 DDR_CKE5_DIMMC
7 DDR_CKE4_DIMMC CKE0 CKE1 DDR_CKE5_DIMMC 7
CD3

CD4

CD5

CD6

75 76
77 VDD1 VDD2 78 DDR_A_MA15
@2 2 2 2 DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
14,7 DDR_A_BS2 81 BA2 A14 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
+1.35V DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR4 101 VDD9 VDD10 102 M_CLK_DDR5 M_CLK_DDR5 7
7 M_CLK_DDR4 103 CK0 CK1 104 M_CLK_DDR#5 7
M_CLK_DDR#4 M_CLK_DDR#5
7 M_CLK_DDR#4 CK0# CK1#
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

105 106 DDR_A_BS1 14,7


VDD11 VDD12
330U_SX_2VY~D

DDR_A_MA10 107 108 DDR_A_BS1


@ DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS# DDR_A_RAS# 14,7
1 14,7 DDR_A_BS0 BA0 RAS#
@CD13
@

CD14

1 1 1 1 1 1 1 111 112
VDD13 VDD14 DDR_CS4_DIMMC# 7
CD7

CD8

CD9

CD10

CD11

CD74

CD13

+ DDR_A_WE# 113 114 DDR_CS4_DIMMC#


14,7 DDR_A_WE# 115 WE# S0# 116 M_ODT4 7
DDR_A_CAS# M_ODT4
14,7 DDR_A_CAS# 117 CAS# ODT0 118
2 2 2 2 2 2 2 2 119 VDD15 VDD16 120 M_ODT5 7 +V_SM_VREF_CNT
DDR_A_MA13 M_ODT5
DDR_CS5_DIMMC# 121 A13 ODT1 122
7 DDR_CS5_DIMMC# 123 S1# NC2 124
125 VDD17 VDD18 126
All VREF traces should
127 NCTEST VREF_CA 128 have 20 mil trace width
VSS27 VSS28

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
133 DQ33 DQ37 134
VSS29 VSS30 1 1

CD15

CD16
DDR_A_DQS#4 135 136
DDR_A_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2
B
DDR_A_D35 143 DQ34 DQ39 144 B

145 DQ35 VSS33 146 DDR_A_D44


DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
Layout Note: DDR_A_D41 149 DQ40 DQ45 150
Place near JDIMMA.203,204 151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46 CH A1 (H9.2)(Std)
DDR_A_D43 159
161
DQ42
DQ43
DQ46
DQ47
160
162
DDR_A_D47 DIMM A1
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165
167
DQ48
DQ49
DQ52
DQ53
166
168
DDR_A_D53 CH B1 (H5.2)(Std)
+0.675VS DDR_A_DQS#6
DDR_A_DQS6
169
171
VSS41
DQS#6
VSS42
DM6
170
172 CPU TOP DIMM B1
173 DQS6 VSS43 174 DDR_A_D54
@ +3VS DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DQ50 DQ55
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_A_D51 177 178


1 1 1 1
DDR_A_D56
179
181
DQ51
VSS46
VSS45
DQ60
180
182
DDR_A_D60
DDR_A_D61 BOT CH B0 (H5.2) (Rev) DIMM B0
DQ56 DQ61
CD17

CD18

CD19

CD20

DDR_A_D57 183 184


DQ57 VSS47
2

185 186 DDR_A_DQS#7


VSS48 DQS#7
2 2 2 2 RD38
10K_0402_5%~D
@ RD39
10K_0402_5%~D
187
189 DM7 DQS7
188
190
DDR_A_DQS7
CH A0 (H9.2) (Rev)
DDR_A_D58
DDR_A_D59
191
193
VSS49
DQ58
VSS50
DQ62
192
194
DDR_A_D62
DDR_A_D63
DIMM A0
1

195 DQ59 DQ63 196


197 VSS51 VSS52 198 M_THERMAL#
199 SA0 EVENT# 200 M_THERMAL# 13,14,15,43
+3VS VDDSPD SDA PCH_SMBDATA 13,14,15,19,49,50,51,53,6
201 202
SA1 SCL PCH_SMBCLK 13,14,15,19,49,50,51,53,6
0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

203 204
+0.675VS VTT1 VTT2 +0.675VS
1 1
2

CD21

CD22

205 206
RD21 @ RD22 G1 G2
10K_0402_5%~D @ 0_0402_1% TYCO_2-2013311-1
2 2 CONN@
SA0 SA1
1

1 0 DIMA0
A A
1 1 DIMB0
0 0 DIMA1
0 1 DIMB1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
DDRIII DIMMA

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 12 of 56
5 4 3 2 1
5 4 3 2 1

D
JDIMMB H=5.2mm D

+DIMM0_1_CA_CPU
+1.35V +1.35V
JDIMB0
1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
9 DQ1 VSS3 10 DDR_B_DQS#0
1 1 VSS4 DQS#0

CD23

CD24
@ 11 12 DDR_B_DQS0
13 DM0 DQS0 14
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
All VREF traces should 2 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
have 20 mil trace width 19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
15,7 DDR_B_DQS#[0..7] 27 VSS9 VSS10 28
DDR_B_DQS#1
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
15,7 DDR_B_D[0..63] 31 DQS1 RESET# 32 DDR3_DRAMRST#_R 12,14,15
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
15,7 DDR_B_DQS[0..7] DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
37 DQ11 DQ15 38
15,7 DDR_B_MA[0..15] 39 VSS13 VSS14 40
DDR_B_D16 DDR_B_D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
Layout Note: DDR_B_D19 53 DQ18 DQ23 54
Place near JDIMMB 55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
C DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30 C
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
+1.35V 71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_CKE6_DIMMD 73 74 DDR_CKE7_DIMMD
7 DDR_CKE6_DIMMD 75 CKE0 CKE1 76 DDR_CKE7_DIMMD 7
1 1 1 1 VDD1 VDD2
77 78 DDR_B_MA15
NC1 A15
CD25

CD26

CD27

CD28

DDR_B_BS2 79 80 DDR_B_MA14
15,7 DDR_B_BS2 81 BA2 A14 82
2 2 2 2 DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
@ DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
+1.35V 99 A1 A0 100
M_CLK_DDR6 101 VDD9 VDD10 102 M_CLK_DDR7
7 M_CLK_DDR6 103 CK0 CK1 104 M_CLK_DDR7 7
M_CLK_DDR#6 M_CLK_DDR#7
7 M_CLK_DDR#6 105 CK0# CK1# 106 M_CLK_DDR#7 7
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 15,7
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

DDR_B_BS0 109 110 DDR_B_RAS#


15,7 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 15,7
330U_SX_2VY~D

1 111 112
VDD13 VDD14
@ CD35

1 1 1 1 1 1 1 DDR_B_WE# 113 114 DDR_CS6_DIMMD#


15,7 DDR_B_WE# WE# S0# DDR_CS6_DIMMD# 7
CD29

CD30

CD31

CD32

CD33

CD34

CD36

@ + DDR_B_CAS# 115 116 M_ODT6


15,7 DDR_B_CAS# 117 CAS# ODT0 118 M_ODT6 7
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT7 +V_SM_VREF_CNT
2 2 2 2 2 2 2 2 121 A13 ODT1 122 M_ODT7 7
DDR_CS7_DIMMD#
7 DDR_CS7_DIMMD# 123 S1# NC2 124
125 VDD17 VDD18 126
All VREF traces should
127 NCTEST VREF_CA 128 have 20 mil trace width
VSS27 VSS28

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
DQ33 DQ37

CD37
133 134 1 1
VSS29 VSS30

CD38
DDR_B_DQS#4 135 136
DDR_B_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_B_D38
B
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 2 B

DDR_B_D35 143 DQ34 DQ39 144


Layout Note: 145 DQ35 VSS33 146 DDR_B_D44
Place near JDIMMB.203,204 DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
163 VSS39 VSS40 164
+0.675VS DDR_B_D48
DDR_B_D49 165 DQ48 DQ52 166
DDR_B_D52
DDR_B_D53 CH A1 (H9.2)(Std)
DDR_B_DQS#6
167
169
DQ49
VSS41
DQ53
VSS42
168
170
DIMM A1
DDR_B_DQS6 171 DQS#6 DM6 172
DQS6 VSS43
CH B1 (H5.2)(Std)
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

173 174 DDR_B_D54


+3VS DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
1 1 1
@
1
DDR_B_D51 177 DQ50
DQ51
DQ55
VSS45
178
CPU TOP DIMM B1
CD39

CD40

CD41

CD42

179 180 DDR_B_D60


DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61
2 2 2 2 DDR_B_D57 183 DQ56 DQ61 184
DQ57 VSS47
2

185 186 DDR_B_DQS#7


RD40
10K_0402_5%~D
RD24
10K_0402_5%~D
187
189
VSS48
DM7
DQS#7
DQS7
188
190
DDR_B_DQS7
BOT CH B0 (H5.2) (Rev) DIMM B0
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
1

DQ59 DQ63
195
197 VSS51 VSS52
196
198 M_THERMAL#
CH A0 (H9.2) (Rev)
+3VS
199
201
SA0
VDDSPD
EVENT#
SDA
200
202
M_THERMAL#
PCH_SMBDATA
12,14,15,43
12,14,15,19,49,50,51,53,6
DIMM A0
SA1 SCL PCH_SMBCLK 12,14,15,19,49,50,51,53,6
0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

+0.675VS
203 204 +0.675VS
VTT1 VTT2
1 1
2

CD44

CD43

205 206
RD23 @ @ RD41 G1 G2
SA0 SA1 10K_0402_5%~D 10K_0402_5%~D TYCO_2-2013290-1
2 2
1 0 DIMA0 CONN@
1

A 1 1 DIMB0 A

0 0 DIMA1
0 1 DIMB1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
DDRIII DIMMB

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 13 of 56
5 4 3 2 1
5 4 3 2 1

D
JDIMMC H=9.2mm D

+DIMM0_1_VREF_CPU
+1.35V +1.35V
JDIMA1
1 2
3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 7 DQ0 DQ5 8
1 1 DQ1 VSS3
9 10 DDR_A_DQS#0
VSS4 DQS#0

CD50

CD53
All VREF traces should 11 12 DDR_A_DQS0
@ 13 DM0 DQS0 14
have 20 mil trace width 2 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
12,7 DDR_A_DQS#[0..7] 25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
12,7 DDR_A_D[0..63] 29 DQS#1 DM1 30
DDR_A_DQS1 DDR3_DRAMRST#_R
31 DQS1 RESET# 32 DDR3_DRAMRST#_R 12,13,15
12,7 DDR_A_DQS[0..7] 33 VSS11 VSS12 34
DDR_A_D10 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
12,7 DDR_A_MA[0..15] 37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
Layout Note: DDR_A_D19 53 DQ18 DQ23 54
Place near JDIMMC 55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
+1.35V DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
C DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31 C
71 DQ27 DQ31 72
VSS25 VSS26
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
7 DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA 7
CD12

CD54

CD63

CD47

75 76
77 VDD1 VDD2 78 DDR_A_MA15
2 2 2 @2 DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
12,7 DDR_A_BS2 81 BA2 A14 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
+1.35V DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
7 M_CLK_DDR0 103 CK0 CK1 104 M_CLK_DDR1 7
M_CLK_DDR#0 M_CLK_DDR#1
7 M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 7
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

105 106 DDR_A_BS1 12,7


VDD11 VDD12
330U_SX_2VY~D

DDR_A_MA10 107 108 DDR_A_BS1


DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS# DDR_A_RAS# 12,7
1 12,7 DDR_A_BS0 BA0 RAS#
@CD61
@

CD45

1 1 1 1 1 1 1 111 112
VDD13 VDD14 DDR_CS0_DIMMA# 7
CD56

CD59

CD62

CD46

CD49

CD75

CD61

+ DDR_A_WE# 113 114 DDR_CS0_DIMMA#


12,7 DDR_A_WE# 115 WE# S0# 116 M_ODT0 7
DDR_A_CAS# M_ODT0
12,7 DDR_A_CAS# 117 CAS# ODT0 118
VDD15 VDD16 M_ODT1 7
@2 2 2 2 2 2 2 2 DDR_A_MA13 119 120 M_ODT1 +V_SM_VREF_CNT
DDR_CS1_DIMMA# 121 A13 ODT1 122
7 DDR_CS1_DIMMA# 123 S1# NC2 124
125 VDD17 VDD18 126
127 NCTEST VREF_CA 128
All VREF traces should
VSS27 VSS28 have 20 mil trace width

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
133 DQ33 DQ37 134
VSS29 VSS30 1 1

CD52

CD58
DDR_A_DQS#4 135 136
DDR_A_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2 2
B
DDR_A_D35 143 DQ34 DQ39 144 B

145 DQ35 VSS33 146 DDR_A_D44


DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
Layout Note: DDR_A_D41 149 DQ40 DQ45 150
Place near JDIMMC.203,204 151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
157 VSS37 VSS38 158
DDR_A_D42
DDR_A_D43 159 DQ42 DQ46 160
DDR_A_D46
DDR_A_D47 CH A1 (H9.2)(Std)
DDR_A_D48
161
163
DQ43
VSS39
DQ47
VSS40
162
164 DDR_A_D52
DIMM A1
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53

+0.675VS DDR_A_DQS#6
167
169
DQ49
VSS41
DQ53
VSS42
168
170
CH B1 (H5.2)(Std)
DDR_A_DQS6 171
173
DQS#6
DQS6
DM6
VSS43
172
174 DDR_A_D54 CPU TOP DIMM B1
+3VS DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DQ50 DQ55
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_A_D51 177 178


179 DQ51 VSS45 180 DDR_A_D60
1 1 1
@
1
DDR_A_D56 181 VSS46
DQ56
DQ60
DQ61
182 DDR_A_D61
BOT CH B0 (H5.2) (Rev) DIMM B0
CD64

CD51

CD57

CD55

DDR_A_D57 183 184


DQ57 VSS47
2

185 186 DDR_A_DQS#7


2 2 2 2 RD25 @ @ RD43 187 VSS48 DQS#7 188 DDR_A_DQS7
DM7 DQS7
10K_0402_5%~D 10K_0402_5%~D
DDR_A_D58
189
191 VSS49 VSS50
190
192 DDR_A_D62 CH A0 (H9.2) (Rev)
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 DIMM A0
1

195 DQ59 DQ63 196


197 VSS51 VSS52 198 M_THERMAL#
199 SA0 EVENT# 200 M_THERMAL# 12,13,15,43
+3VS VDDSPD SDA PCH_SMBDATA 12,13,15,19,49,50,51,53,6
201 202
SA1 SCL PCH_SMBCLK 12,13,15,19,49,50,51,53,6
0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

203 204
+0.675VS VTT1 VTT2 +0.675VS
1 1
2

CD48

CD60

RD42 205 206


RD26 G1 G2
0_0402_1% @ @ 0_0402_1% TYCO_2-2013310-1
2 2 CONN@
SA0 SA1
1

1 0 DIMA0
A A
1 1 DIMB0
0 0 DIMA1
0 1 DIMB1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
DDRIII DIMMC

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 14 of 56
5 4 3 2 1
5 4 3 2 1

JDIMMD H=5.2mm
D D
+DIMM0_1_CA_CPU
+1.35V +1.35V
JDIMB1
1 2
3 VREF_DQ VSS1 4 DDR_B_D4
VSS2 DQ4

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 7 DQ0 DQ5 8
@1 9 DQ1 VSS3 10 DDR_B_DQS#0
1 VSS4 DQS#0

CD84

CD76
11 12 DDR_B_DQS0
13 DM0 DQS0 14
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
All VREF traces should 2 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
have 20 mil trace width 19 DQ3 DQ7 20
DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
25 DQ9 DQ13 26
13,7 DDR_B_DQS#[0..7] 27 VSS9 VSS10 28
DDR_B_DQS#1
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
13,7 DDR_B_D[0..63] 31 DQS1 RESET# 32 DDR3_DRAMRST#_R 12,13,14
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
13,7 DDR_B_DQS[0..7] 35 DQ10 DQ14 36
DDR_B_D11 DDR_B_D15
37 DQ11 DQ15 38
13,7 DDR_B_MA[0..15] DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23
Layout Note: DDR_B_D19 53 DQ18 DQ23 54
Place near JDIMMD 55 DQ19 VSS19 56 DDR_B_D28
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
C +1.35V 71 DQ27 DQ31 72 C
VSS25 VSS26
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
7 DDR_CKE2_DIMMB 75 CKE0 CKE1 76 DDR_CKE3_DIMMB 7
1 1 1 1 VDD1 VDD2
@ 77 78 DDR_B_MA15
NC1 A15
CD82

CD80

CD78

CD71

DDR_B_BS2 79 80 DDR_B_MA14
13,7 DDR_B_BS2 81 BA2 A14 82
2 2 2 2 DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
+1.35V 99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
7 M_CLK_DDR2 M_CLK_DDR#2 103 CK0 CK1 104 M_CLK_DDR#3 M_CLK_DDR3 7
7 M_CLK_DDR#2 105 CK0# CK1# 106 M_CLK_DDR#3 7
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 13,7
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

DDR_B_BS0 109 110 DDR_B_RAS#


13,7 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 13,7
330U_SX_2VY~D

1 111 112
VDD13 VDD14
@CD70
@

1 1 1 1 1 1 1 DDR_B_WE# 113 114 DDR_CS2_DIMMB#


13,7 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 7
CD67

CD87

CD81

CD79

CD65

CD88

CD70

CD68

@ + DDR_B_CAS# 115 116 M_ODT2


13,7 DDR_B_CAS# 117 CAS# ODT0 118 M_ODT2 7
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +V_SM_VREF_CNT
2 2 2 2 2 2 2 2 121 A13 ODT1 122 M_ODT3 7
DDR_CS3_DIMMB#
7 DDR_CS3_DIMMB# 123 S1# NC2 124
125 VDD17 VDD18 126
127 NCTEST VREF_CA 128
All VREF traces should
VSS27 VSS28 have 20 mil trace width

2.2U_0402_6.3V6M

0.1U_0402_25V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
133 DQ33 DQ37 134
VSS29 VSS30 1 1

CD72

CD83
DDR_B_DQS#4 135 136
DDR_B_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_B_D38
DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 2
DDR_B_D35 143 DQ34 DQ39 144
B Layout Note: 145 DQ35 VSS33 146 DDR_B_D44
B

Place near JDIMMD.203,204 DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45


DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46 CH A1 (H9.2)(Std)
DDR_B_D43 159
161
DQ42
DQ43
DQ46
DQ47
160
162
DDR_B_D47 DIMM A1
+0.675VS DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165
167
DQ48
DQ49
DQ52
DQ53
166
168
DDR_B_D53 CH B1 (H5.2)(Std)
DDR_B_DQS#6
DDR_B_DQS6
169
171
VSS41
DQS#6
VSS42
DM6
170
172 CPU TOP DIMM B1
DQS6 VSS43
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

173 174 DDR_B_D54


@1 +3VS DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
1 1 1 DQ50 DQ55
DDR_B_D51 177 178
DQ51 VSS45
CH B0 (H5.2) (Rev) DIMM B0
CD89

CD77

CD86

CD85

179 180 DDR_B_D60


2 2 2 2
DDR_B_D56
DDR_B_D57
181
183
VSS46
DQ56
DQ60
DQ61
182
184
DDR_B_D61 BOT
DQ57 VSS47
2

185 186 DDR_B_DQS#7


VSS48 DQS#7
RD31 @
10K_0402_5%~D
RD32
10K_0402_5%~D
187
189 DM7 DQS7
188
190
DDR_B_DQS7
CH A0 (H9.2) (Rev)
DDR_B_D58
DDR_B_D59
191
193
VSS49
DQ58
VSS50
DQ62
192
194
DDR_B_D62
DDR_B_D63
DIMM A0
1

195 DQ59 DQ63 196


197 VSS51 VSS52 198 M_THERMAL#
199 SA0 EVENT# 200 M_THERMAL# 12,13,14,43
+3VS VDDSPD SDA PCH_SMBDATA 12,13,14,19,49,50,51,53,6
201 202
SA1 SCL PCH_SMBCLK 12,13,14,19,49,50,51,53,6
0.1U_0402_25V6K~D

2.2U_0402_6.3V6M

203 204
+0.675VS VTT1 VTT2 +0.675VS
2

RD44 1 1
CD69

CD66

@ @ RD45 205 206


0_0402_1% 10K_0402_5%~D G1 G2
TYCO_2-2013289-1
2 2 CONN@
1
1

SA0 SA1
1 0 DIMA0
A 1 1 DIMB0 A

0 0 DIMA1
0 1 DIMB1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
DDRIII DIMMD

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 15 of 56
5 4 3 2 1
5 4 3 2 1

+RTC_CELL

330K_0402_1%~D
1
RH38
D
2 D

PCH_INTVRMEN
330K_0402_1%~D
1
@ RH39
2

INTVRMEN - INTEGRATED SUS 1.05V VRM


ENABLE
High - Enable Internal VRs
Low - Enable External VRs

+3VS +3V_PCH

1 2 HDA_SPKR 1 2 PCH_AZ_SDOUT
@RH35
@ RH35 10K_0402_5%~D @RH287
@ RH287 1K_0402_1%~D

+3VS
NO REBOOT STRAP FLASH DESCRIPTOR SECURITY OVERRIDE
PCH_GPIO21 1 2
DISABLED WHEN LOW (DEFAULT) LOW = DESABLED (DEFAULT) 10K_0402_5%~D RH30
ENABLED WHEN HIGH HIGH = ENABLED RH286
BBS_BIT0_R 2 1
CH2 4.7K_0402_5%~D RH52
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1 PCH_SATALED# 1 2
@ 0_0402_1% 10K_0402_5%~D RH55
18P_0402_50V8J~D

1
+3VS
LPT_PCH_M_EDS
C YH1 RH2 UH1A C
32.768KHZ_12.5PF_Q13FC1350000~D 10M_0402_5%~D
1 2 PCH_GPIO33 BC8 SATA_PRX_DTX_N0

2
B5 5 SATA_RXN_0 BE8 SATA_PRX_DTX_N0 49
RH355 100K_0402_5%~D SATA_PRX_DTX_P0

2
RTCX1 SATA_RXP_0 SATA_PRX_DTX_P0 49
@ CH3 HDD1(Master)
1 2 PCH_RTCX2 B4 AW8 SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 49
RTCX2 SATA_TXN_0 AY8 SATA_PTX_DRX_P0

RTC
SATA_TXP_0 SATA_PTX_DRX_P0 49
+RTC_CELL RH22 1 2 20K_0402_5%~D 18P_0402_50V8J~D SRTCRST# B9
SRTCRST# BC10 SATA_PRX_DTX_N1
SATA_RXN_1 SATA_PRX_DTX_N1 49
RH11 1 2 1M_0402_5%~D INTRUDER# A8 BE10 SATA_PRX_DTX_P1
INTRUDER# SATA_RXP_1 SATA_PRX_DTX_P1 49
PCH_INTVRMEN G10 AV10 SATA_PTX_DRX_N1 SATA_PTX_DRX_N1 49
HDD2(Slave)
INTVRMEN SATA_TXN_1 AW10 SATA_PTX_DRX_P1
SATA_TXP_1 SATA_PTX_DRX_P1 49
RH23 1 2 20K_0402_5%~D PCH_RTCRST# D9
RTCRST#

SATA
BB9
SATA_RXN_2 BD9
PCH_AZ_BITCLK B25 SATA_RXP_2
CMOS_CLR1 CMOS setting HDA_BCLK AY13
1 2 1 2 PCH_AZ_SYNC A22 SATA_TXN_2 AW13
Shunt Clear CMOS 1 2 1 2 HDA_SYNC SATA_TXP_2
Open Keep CMOS HDA_SPKR AL10 BC12
45 HDA_SPKR SPKR SATA_RXN_3 BE12
@ @ PCH_AZ_RST# C24 SATA_RXP_3
ME1 SHORT PADS~D CMOS1 SHORT PADS~D HDA_RST# AR13
ME_CLR1 TPM setting 1 2 1 2 L22 SATA_TXN_3 AT13

AZALIA
PCH_AZ_CODEC_SDIN0
1U_0402_6.3V6K~D 45 PCH_AZ_CODEC_SDIN0 HDA_SDI0 SATA_TXP_3
Shunt Clear ME RTC Registers CH5 1U_0402_6.3V6K~D CH4
CMOS place near DIMM K22
HDA_SDI1 BD13 SATA_ODD_PRX_DTX_N4
Open Keep ME RTC Registers G22 SATA_RXN4/PERN1 BB13 SATA_ODD_PRX_DTX_P4
SATA_ODD_PRX_DTX_N4 50
HDA_SDI2 SATA_RXP4/PERP1 SATA_ODD_PRX_DTX_P4 50
ODD/HDD3 Bay
F22 AV15 SATA_ODD_PTX_DRX_N4 SATA_ODD_PTX_DRX_N4 50
HDA_SDI3 SATA_TXN4/PETN1 AW15 SATA_ODD_PTX_DRX_P4
SATA_TXP4/PETP1 SATA_ODD_PTX_DRX_P4 50
1 2 PCH_AZ_SDOUT A24
43 HDA_SDO HDA_SDO
RH50 1K_0402_1%~D BC14 MSATA_PRX_DTX_N5
PCH_GPIO33 B17 SATA_RXN5/PERN2 BE14 MSATA_PRX_DTX_P5 MSATA_PRX_DTX_N5 50
DOCKEN#/GPIO33 SATA_RXP5/PERP2 MSATA_PRX_DTX_P5 50
mSATA
HDA_SYNC Isolation Circuit +5VS +3V_PCH
17,31 PCH_mDP_HPD
PCH_mDP_HPD C22
HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2
AP15
AR15
MSATA_PTX_DRX_N5
MSATA_PTX_DRX_P5
MSATA_PTX_DRX_N5 50
SATA_TXP5/PETP2 MSATA_PTX_DRX_P5 50
1
0_0603_5%~D
2

B B
G

RH288

AY5 SATA_COMP
SATA_RCOMP
PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC AP3 PCH_SATALED#
SATALED# PCH_SATALED# 48
S

RH59 2 1 51_0402_1%~D PCH_JTAG_TCK AB3 AT1 PCH_GPIO21


QH8 JTAG_TCK SATA0GP/GPIO21
1M_0402_5%~D

SSM3K7002FU_SC70-3~D +3.3V_ALW_PCH_JTAG RH44 1 2 210_0402_1%~D PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R


@ JTAG_TMS SATA1GP/GPIO19
2

@
RH31

RH45 1 2 210_0402_1%~D PCH_JTAG_TDI AE2 BD4 SATA_IREF 2 1 RH41

JTAG
@ +1.5VS
JTAG_TDI SATA_IREF
@

0_0402_1%
RH46 1 2 210_0402_1%~D PCH_JTAG_TDO AD3 BA2
JTAG_TDO TP9
@

@ PAD~D T161 @
1

1 2 PCH_TP25 F8 BB2
TP25 TP8
100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

RH289 0_0402_1% PAD~D T155 @


1

@ C26
TP22
RH48

RH49

RH47

T122 PAD~D
PCH_JTAG_RST AB6
T175 PAD~D TP20
@ SATA Impedance Compensation
2

LYNXPOINT_BGA695 1 OF 11 +1.5VS

SATA_COMP 1 2
7.5K_0402_1%~D RH40

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
HDA for Codec
1 2 PCH_AZ_SDOUT
45 PCH_AZ_CODEC_SDOUT
RH29 33_0402_5%~D
1 2 PCH_AZ_SYNC_Q
45 PCH_AZ_CODEC_SYNC
RH56 33_0402_5%~D
1 2 PCH_AZ_RST#
45 PCH_AZ_CODEC_RST#
RH27 33_0402_5%~D
A 1 2 PCH_AZ_BITCLK A
45 PCH_AZ_CODEC_BITCLK
RH26 33_0402_5%~D
27P_0402_50V8J~D
@CH101
@

1
CH101

+RTC_CELL 2
W=20mils 1
CH12
1U_0603_10V6K
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
PCH (1/9) RTC,HDA,SATA,XDP

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 16 of 56
5 4 3 2 1
5 4 3 2 1

@
1 2 SYS_RESET#
D 6 XDP_DBRESET# D
RH195 0_0402_1%

+3V_PCH

1 2 SUS_STAT#
LPT_PCH_M_EV
@ RH318 10K_0402_5%~D UH1E 5
1 2 SUSPWRDNACK
RH153 10K_0402_5%~D T45 R40 PCH_DPB_HDMI_CLK
1 2 VGA_BLUE DDPB_CTRLCLK PCH_DPB_HDMI_CLK 36
@ PCIE_WAKE#
RH148 10K_0402_5%~D U44
VGA_GREEN DDPB_CTRLDATA
R39 PCH_DPB_HDMI_DAT
PCH_DPB_HDMI_DAT 36
HDMI
1 2 PCH_WAKE#
RH177 10K_0402_5%~D +3VS V45 R35 PCH_DPC_MDP_CLK
1 2 PCH_RI# VGA_RED DDPC_CTRLCLK PCH_DPC_MDP_CLK 31
RH172 10K_0402_5%~D @ 1 2 PCH_DPC_MDP_CLK M43
VGA_DDC_CLK DDPC_CTRLDATA
R36 PCH_DPC_MDP_DAT
PCH_DPC_MDP_DAT 31
mDP
RV122 2.2K_0402_5%~D
1 2 PCH_DPC_MDP_DAT M45 N40 PCH_DPD_CLK

CRT
VGA_DDC_DATA DDPD_CTRLCLK PCH_DPD_CLK 39
+3VS @RV123
@ RV123 2.2K_0402_5%~D

1 2 1 2
N42
VGA_HSYNC DDPD_CTRLDATA
N38 PCH_DPD_DAT
PCH_DPD_DAT 39
DMC
PM_CLKRUN# ME_SUS_PWR_ACK_R SUSACK#_R
RH138 8.2K_0402_5%~D RH323 0_0402_5%~D N44
1 2 ME_RESET# VGA_VSYNC H45
@ RH152 8.2K_0402_5%~D 1 2 U40 DDPB_AUXN
RH139 649_0402_1%~D DAC_IREF K43 PCH_mDP_AUXN
U39 DDPC_AUXN PCH_mDP_AUXN 31
VGA_IRTN

DISPLAY
J42
DDPD_AUXN
PCH_EDP_PWM N36 H43
UH1B LPT_PCH_M_EDS
5 40 PCH_EDP_PWM EDP_BKLTCTL DDPB_AUXP

LVDS
K36 K45 PCH_mDP_AUXP
AW22 EDP_BKLTEN DDPC_AUXP PCH_mDP_AUXP 31
DMI_CTX_PRX_N0
5 DMI_CTX_PRX_N0 AR20 DMI_RXN_0 G36 J44
DMI_CTX_PRX_N1
5 DMI_CTX_PRX_N1 DMI_RXN_1 AJ35 EDP_VDDEN DDPD_AUXP
DMI_CTX_PRX_N2 AP17 FDI_RXN_0 K40 PCH_HDMI_HPD
5 DMI_CTX_PRX_N2 AV20 DMI_RXN_2 AL35 H20 DDPB_HPD PCH_HDMI_HPD 36
DMI_CTX_PRX_N3 PCI_PIRQA#
5 DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 PIRQA# K38 PCH_mDP_HPD
AY22 AJ36 L20 DDPC_HPD PCH_mDP_HPD 16,31
DMI_CTX_PRX_P0 PCI_PIRQB#
5 DMI_CTX_PRX_P0 AP20 DMI_RXP_0 FDI_RXP_0 PIRQB# H39 PCH_DMC_HPD
DMI_CTX_PRX_P1
5 DMI_CTX_PRX_P1 DMI_RXP_1 FDI AL36 PCI_PIRQC# K17 DDPD_HPD PCH_DMC_HPD 39
C DMI_CTX_PRX_P2 AR17 FDI_RXP_1 PIRQC# C
5 DMI_CTX_PRX_P2 AW20 DMI_RXP_2 AV43 M20
DMI_CTX_PRX_P3 DMI PCI_PIRQD#
5 DMI_CTX_PRX_P3 DMI_RXP_3 TP16 PIRQD# PCI
G17 BT_ON#
BD21 AY45 PIRQE#/GPIO2 BT_ON# 51
DMI_CRX_PTX_N0 DGPU_HOLD_RST# A12
5 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 BE20 DMI_TXN_0 TP5 GPIO50 F17 DP_CBL_DET
5 DMI_CRX_PTX_N1 DMI_TXN_1 AV45 PIRQF#/GPIO3 DP_CBL_DET 31
DGPU_SELECT# B13
BD17 TP15 31,36,42 DGPU_SELECT# GPIO52 L15
DMI_CRX_PTX_N2 ODD_DA#
5 DMI_CRX_PTX_N2 BE18 DMI_TXN_2 AW44 C12 PIRQG#/GPIO4 ODD_DA# 50
DMI_CRX_PTX_N3
5 DMI_CRX_PTX_N3 DMI_TXN_3 TP10 GPIO54 M15 FFS_INT1
PIRQH#/GPIO5 FFS_INT1 49
DMI_CRX_PTX_P0 BB21 AL39 FDI_CSYNC BBS_BIT1 C10
5 DMI_CRX_PTX_P0 BC20 DMI_TXP_0 FDI_CSYNC FDI_CSYNC 5 GPIO51 AD10
DMI_CRX_PTX_P1 @ T124 PAD~D
5 DMI_CRX_PTX_P1 DMI_TXP_1 AL40 PME#
FDI_INT HDMI_IN_PWMSEL#A10
DMI_CRX_PTX_P2 BB17 FDI_INT @ FDI_INT 5 42 HDMI_IN_PWMSEL# GPIO53 Y11 PCH_PLTRST#
5 DMI_CRX_PTX_P2 BC18 DMI_TXP_2 AT45 PLTRST#
DMI_CRX_PTX_P3 FDI_IREF 2 1
+1.5VS WL_OFF# AL6
5 DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF 51 WL_OFF# GPIO55
0_0402_1% 0_0402_1% RH42
2 1 DMI_IREF BE16 AU42 PAD~D T145 @
+1.5VS DMI_IREF TP17
RH43 LYNXPOINT_BGA695 5 OF 11
@ AW17 AU44 PAD~D T146 @
@ T139 PAD~D TP12 TP13
AV17 AR44 FDI_RCOMP 2 1 +3VS +3VS
TP7 FDI_RCOMP +1.5VS
@ T123 PAD~D 7.5K_0402_1%~D RH206 CH144
+1.5VS
1 2 DMI_RCOMP AY17 1 2
DMI_RCOMP

1
RH204 7.5K_0402_1%~D
0.1U_0402_25V6K~D RH367
10K_0402_5%~D
1 2 SUSACK#_R R6 C8 DSWODVREN RH167 @
42,43 SG_AMD_BKL SUSACK# DSWVRMEN @

5
@RH114
@ RH114 0_0402_5%~D 1 2 0_0402_5%~D PCH_RSMRST#_R

2
System Power
SYS_RESET# AM1 L13 PCH_DRWROK_R 1 2 PCH_PLTRST# 1

P
SYS_RESET# Management DPWROK PCH_DPWROK 43 B 4
@ RH186 @ 0_0402_5%~D PLT_RST
1 2 SYS_PWROK_R AD7 K3 PCH_WAKE# 1 2 PCIE_WAKE# 2 O PLT_RST# 43,44,51,53,6
6 SYS_PWROK SYS_PWROK WAKE# PCIE_WAKE# 43,44,51 A

G
RH193 @ 0_0402_1% RH192 @ 0_0402_5%~D UH3

1
1 2 PCH_PWROK_R F10 AN7 PM_CLKRUN# TC7SH08FU_SSOP5~D

3
43 PCH_PWROK PWROK CLKRUN#
RH144 @ 0_0402_1% +3V_MXM RH211 1 2 100K_0402_5%~D
1 2 PM_APWROK_R AB7 U7 SUS_STAT# T129 PAD~D@ RH202 2 @ 1 0_0402_5%~D MXM_RST_A RH201
APWROK SUS_STAT#/GPIO61 43 MXM_RST DGPU_HOLD_RST# 1 2 0_0402_5%~D
RH149 0_0402_1% @ 100K_0402_5%~D
1 2 PM_DRAM_PWRGD_R H3 Y6 SUSCLK_R T143 PAD~D@ RH168

2
6 PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62
RH320 0_0402_5%~D T126 PAD~D@
1 2 PCH_RSMRST#_R J2 Y7 PM_SLP_S5# +3V_MXM
43 PCH_RSMRST# RSMRST# SLP_S5#/GPIO63 PM_SLP_S5# 43,47 +RTC_CELL
RH185 0_0402_5%~D
1 2 ME_SUS_PWR_ACK_RJ4 C6 PM_SLP_S4# T125 PAD~D @
B 43 SUSPWRDNACK SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# 43 B

330K_0402_1%~D
RH200 0_0402_5%~D +3VS @

2
1 2 SIO_PWRBTN#_R K1 H1 PM_SLP_S3# CH147
43,6 PBTN_OUT# PWRBTN# SLP_S3# PM_SLP_S3# 43,47

RH191
RH163 @ 0_0402_1% 1 2 RH215
ACIN_PCH E6 F3 100K_0402_5%~D
ACPRESENT/GPIO31 SLP_A#

5
0.1U_0402_25V6K~D @ +3VS
1 2 PCH_BATLOW# K7 F1 PM_SLP_SUS# T128 PAD~D @ MXM_RST_A 1

P
+PCH_VCCDSW3_3

1
RH156 8.2K_0402_5%~D BATLOW#/GPIO72 SLP_SUS# PM_SLP_SUS# 43 B 4 PLTRST_VGA# BT_ON# 2 1
T127 PAD~D @ O PLTRST_VGA# 29,30
PCH_RI# N4 AY3 H_PM_SYNC PCH_PLTRST# 2 8.2K_0402_5%~D RH366
RI# PMSYNCH H_PM_SYNC 6 A

G
UH6 ODD_DA# 2 1

1
@ T140 PAD~D AB10 G5 DSWODVREN TC7SH08FU_SSOP5~D 8.2K_0402_5%~D RH365

3
TP21 SLP_LAN# WL_OFF# 2 1
+3VS

330K_0402_1%~D
D2 RH196 8.2K_0402_5%~D RH362
SLP_WLAN#/GPIO29

@RH178
@
100K_0402_5%~D HDMI_IN_PWMSEL# 2 1

2
RH178
8.2K_0402_5%~D RH352

2
1 LYNXPOINT_BGA695 4 OF 11 1 2 PCI_PIRQA# 2 1
RH198 @ 0_0402_5%~D 8.2K_0402_5%~D RH324
CH41 PCI_PIRQB# 2 1
@ 0.1U_0402_16V7K 8.2K_0402_5%~D RH325

1
2 PCI_PIRQC# 2 1
8.2K_0402_5%~D RH326
5

UH9 PCI_PIRQD# 2 1
8.2K_0402_5%~D RH329
VCC

PCH_PWROK 1 DGPU_HOLD_RST# 2 1
IN1 4 SYS_PWROK 10K_0402_5%~D RH327
2 OUT Boot BIOS Strap DSWODVREN - ON DIE DSW VR ENABLE A16 SWAP OVERRIDE STRAP
GND

43,6,62 IMVP_PWRGD IN2 @


HIGH = ENABLED (DEFAULT)
1 2 BBS_BIT1
GNT1#/GPIO51 SATA1GP/GPIO19 LOW = DISABLED STP_A16OVR LOW = A16 SWAP OVERRIDE
MC74VHC1G08DFT2G_SC70-5 Boot BIOS Location
3

+3V_PCH @RH328
@ RH328 1K_0402_1%~D (BBS_BIT1) (BBS_BIT0) HIGH = DEFAULT
2 1 PCH_RSMRST#
0 0 LPC RH194 10K_0402_5%~D
2 @ 1
PCH_HDMI_HPD
1

+3V_PCH RV462 100K_0402_5%~D


R1900 0 1 Reserved (NAND) 2 @ 1
PCH_DMC_HPD
10K_0402_5% RV461 100K_0402_5%~D
1 @ 2 PM_CLKRUN#
1

1 0 PCI RH351 10K_0402_5%~D


2

R1899 ACIN_PCH
10K_0402_5%
3

A
* 1 1 SPI A
2

5 DMN66D0LDW-7_SOT363-6~D
QH13B
6

GPIO51 has internal pull up.


4

2 DMN66D0LDW-7_SOT363-6~D
29,43,47,57,64 ACIN QH13A
1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

1 2 PCH (2/9) DMI,FDI,PM,DP,CRT

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RH330 0_0402_5%~D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 17 of 56
5 4 3 2 1
5 4 3 2 1

D D

+3V_MXM

1
RH235
+3V_MXM 1K_0402_5%

+3V_PCH

2
1
PEG_CLKREQ# 29
RH378

1
10K_0402_5%~D

G
RH76 RH236
10K_0402_5%~D @

2
3 4 10K_0402_5%~D

2
D

S
2
G
LPT_PCH_M_EDS
UH1C 5 QH11B
DMN66D0LDW-7
@ 6 1
RH307 2 1 0_0402_1% PCIE_MINI1# Y43 AB35 CLK_PEG_PCH#

D
51 CLK_PCIE_MINI1# CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PEG_PCH# 29

S
MiniWLAN @ QH11A
RH308 2 1 0_0402_1% PCIE_MINI1 Y45 AB36 CLK_PEG_PCH DMN66D0LDW-7
(Mini Card 1) 51 CLK_PCIE_MINI1 RH142 2 1 10K_0402_5%~D CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PEG_PCH 29 +3V_MXM1
+3V_PCH
MINI1CLK_REQ# AB1 AF6 PEG_CLKREQ_R# 1 2
51 MINI1CLK_REQ# PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47
@ @ RH237 0_0402_5%

1
RH99 2 1 0_0402_1% PCIE_MINI2# AA44 Y39 MXM2_PEG_PCH#
51 CLK_PCIE_MINI2# 2 1 0_0402_1% PCIE_MINI2 AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B MXM2_PEG_PCH# 30
DMC (Mini Card 2) RH98 @ RH240
51 CLK_PCIE_MINI2 2 110K_0402_5%~D CLKOUT_PCIE_P_1 Y38 +3V_MXM1
RH145 MXM2_PEG_PCH 1K_0402_5%
+3VS CLKOUT_PEG_B_P MXM2_PEG_PCH 30
MINI2CLK_REQ# AF1
51 MINI2CLK_REQ# PCIECLKRQ1#/GPIO18 U4 +3V_PCH
MXM2_CLKREQ_R#

2
PEGB_CLKRQ#/GPIO56

1
RH158 2 @ 1 0_0402_1% PCIE_LAN# AB43
44 CLK_PCIE_LAN# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI# MXM2_CLKREQ# 30
RH379
CLKOUT_DMI CLK_CPU_DMI# 6

1
10/100/1G LAN RH147 2 @ 1 0_0402_1% PCIE_LAN AB45 10K_0402_5%~D

G
44 CLK_PCIE_LAN 1 2 CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI RH125 RH239
+3VS CLKOUT_DMI_P CLK_CPU_DMI 6
RH28 10K_0402_5%~D LANCLK_REQ# AF3 10K_0402_5%~D @

2
44 LANCLK_REQ# PCIECLKRQ2#/GPIO20/SMI# AJ40 3 4
CLK_CPU_SSC_DPLL# 10K_0402_5%~D
RH129 2 @ 1 0_0402_1% PCIE_EXP# AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# 6

2
53 CLK_PCIE_CD#

D
CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL 6

S
C RH124 2 @ 1 0_0402_1% PCIE_EXP AD45 C

G
53 CLK_PCIE_CD T3 CLKOUT_PCIE_P_3 AF35
Card Reader EXPCLK_REQ# CLK_CPU_DPLL# QH12B
53 CDCLK_REQ# 2 1 10K_0402_5%~D PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL# 6
RH126 CLK_CPU_DPLL DMN66D0LDW-7
+3V_PCH CLKOUT_DPNS_P CLK_CPU_DPLL 6
AF43 6 1
AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI#

D
CLKOUT_PCIE_P_4 CLKIN_DMI

S
Thunder Bolt RH128 2 1 10K_0402_5%~D V3 AW24 CLK_BUF_DMI QH12A
+3V_PCH PCIECLKRQ4#/GPIO26 CLKIN_DMI_P
@ DMN66D0LDW-7
AE44 AR24 CLK_BUF_BCLK#
AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLK_BUF_BCLK 1 2
RH132 2 1 10K_0402_5%~D AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P @RH238
@ RH238 0_0402_5%
+3V_PCH PCIECLKRQ5#/GPIO44
@ H33 CLK_BUF_DOT96#
AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
RH133 2 1 10K_0402_5%~D AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
+3V_PCH PCIECLKRQ6#/GPIO45 CLKIN_SATA
@ BC6 CLK_BUF_CKSSCD
AJ44 CLKIN_SATA_P
CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
RH127 2 1 10K_0402_5%~D AJ42 REFCLK14IN D17 CLK_PCI_LPBACK
+3V_PCH CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
Y3 AL44 XTAL25_IN RH309 2 @ 1 0_0402_1%
29,31 DGPU_PWROK PCIECLKRQ7#/GPIO46 XTAL25_IN AM43 1 2
XTAL25_OUT
RH280 2 @ 1 0_0402_1% CLK_BCLK_ITP# AH43 XTAL25_OUT RH131 1M_0402_5%~D

XTAL25_IN_R
6 CLK_CPU_ITP# CLKOUT_ITPXDP C40
RH281 2 @ 1 0_0402_1% CLK_BCLK_ITP AH45 CLKOUTFLEX0/GPIO64 PAD~D T176 @
6 CLK_CPU_ITP CLKOUT_ITPXDP_P F38 DMC_PCH_DET#
CLKOUTFLEX1/GPIO65 DMC_PCH_DET# 51
CLK_PCI_LPBACK RH169 2 1 22_0402_5%~D CLK_PCI0 D44
CLKOUT_33MHZ0 F36 PCH_GPIO66 YH4
CLK_PCI_LPC RH111 2 1 22_0402_5%~D CLK_PCI1 E44 CLKOUTFLEX2/GPIO66 25MHZ_10PF_Q22FA2380049900~D
43 CLK_PCI_LPC CLKOUT_33MHZ1 F39 3 1
CAM_DET# CAM_DET# 42
CLK_DEBUG RH151 2 1 22_0402_5%~D CLK_PCI2 B42 CLKOUTFLEX3/GPIO67 OUT IN
51 CLK_DEBUG CLKOUT_33MHZ2

8.2P_0402_50V8D~D

8.2P_0402_50V8D~D
AM45 ICLK_IREF 0_0402_1% 1 @ 2 RH54 4 2
ICLK_IREF +1.5VS GND GND
@ T142 PAD~D CLK_PCI3 F41 2 2
CLKOUT_33MHZ3

CH19
AD39

CH18
@ T138 PAD~D CLK_PCI4 A40 TP19 AD38 PAD~D T149 @
CLKOUT_33MHZ4 TP18 PAD~D T150 @
AN44 PCH_CLK_BIASREF 1 2 1 1
DIFFCLK_BIASREF +1.05V_+1.5V_RUN
CLOCK SIGNAL 7.5K_0402_1%~D RH208

LYNXPOINT_BGA695 2 OF 11
B B

RPH1
+3VS
RPH2 CLK_BUF_DMI 1 8
CLK_BUF_DMI# 2 7
CAM_DET# 1 8 CLK_BUF_BCLK 3 6
DMC_PCH_DET# 2 7 CLK_BUF_BCLK# 4 5
PCH_GPIO66 3 6
4 5

CLK_BUF_DOT96# RH143 1 2 10K_0402_5%~D


CLK_BUF_DOT96 RH130 1 2 10K_0402_5%~D

CLK_BUF_CKSSCD# RH146 1 2 10K_0402_5%~D


CLK_BUF_CKSSCD RH155 1 2 10K_0402_5%~D

CLK_PCH_14M RH205 1 2 10K_0402_5%~D

CLOCK TERMINATION for FCIM and need close to PCH

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
PCH (3/9) CLK

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 18 of 56
5 4 3 2 1
5 4 3 2 1

+3VS

+3VS

2
+3VS

SML1CLK 6 1
EC_SMB_CK2 30,40,43,53,54

1
DMN66D0LDW-7
QH10A

5
RH304 RH310

2
@ 2.2K_0402_5%~D 2.2K_0402_5%~D SML1DATA 3 4
D EC_SMB_DA2 30,40,43,53,54 D

2
MEM_SMBCLK 6 1 QH10B
PCH_SMBCLK 12,13,14,15,49,50,51,53,6
QH9A DMN66D0LDW-7

5
@ DMN66D0LDW-7_SOT363-6~D

MEM_SMBDATA 3 4
PCH_SMBDATA 12,13,14,15,49,50,51,53,6
QH9B
DMN66D0LDW-7_SOT363-6~D

RH380 1 2 0_0402_5%~D

RH381 1 2 0_0402_5%~D

+3V_PCH
@
+3VS MEM_SMBCLK 2 1
2.2K_0402_5%~D RH302
1 2 SERIRQ MEM_SMBDATA 2 @ 1
RH337 10K_0402_5%~D 2.2K_0402_5%~D RH303
DDR_HVREF_RST_PCH 2 1
1K_0402_1%~D RH300
LPT_PCH_M_EDS
UH1D PCH_GPIO74 2 1
@ 10K_0402_5%~D RH301
RH368 1 2 0_0402_1% SML1CLK 1 2
EC_LID_OUT# 43
2.2K_0402_5%~D RH298
N7 PCH_LID_SW_IN# RH3691 20_0402_5%~D SML1DATA 1 2
LPC_AD0 A20 SMBALERT#/GPIO11 LID_SW_IN# 43,45,47,48,53
@ 2.2K_0402_5%~D RH299
43,51 LPC_AD0 LAD_0 R10
SMBus MEM_SMBCLK
@ PAD~D T169 LPC_AD1 C20 SMBCLK
C 43,51 LPC_AD1 LAD_1 U11 MEM_SMBDATA C
@ PAD~D T168 LPC_AD2 A18 SMBDATA

LPC
43,51 LPC_AD2 LAD_2 N8 +3V_PCH
DDR_HVREF_RST_PCH
@ PAD~D T167 LPC_AD3 C18 SML0ALERT#/GPIO60
43,51 LPC_AD3 LAD_3 U8 SML0CLK SML0CLK 2 1
@ PAD~D T166 LPC_FRAME# B21 SML0CLK 2.2K_0402_5%~D RH305
43,51 LPC_FRAME# LFRAME# R7 SML0DATA SML0DATA 2 1
@ PAD~D T165 D21 SML0DATA 2.2K_0402_5%~D RH306
@ PAD~D T164 LDRQ0# H6 PCH_GPIO74
G20 SML1ALERT#/PCHHOT#/GPIO74
LDRQ1#/GPIO23 K6 SML1CLK
SERIRQ AL11 SML1CLK/GPIO58
43 SERIRQ SERIRQ N11 SML1DATA
SML1DATA/GPIO75

AF11
PCH_SPI_CLK AJ11 CL_CLK
SPI

SPI_CLK AF10
PCH_SPI_CS0# AJ7 C-Link CL_DATA
SPI_CS0# AF7
AL7 CL_RST#
SPI_CS1#
AJ10
SPI_CS2# BA45 PAD~D T130 @
PCH_SPI_SI AH1 TP1
SPI_MOSI BC45 PAD~D T133 @
PCH_SPI_SO AH3 Thermal TP2
SPI_MISO BE43 PAD~D T131 @
PCH_SPI_DO2 AJ4 TP4
SPI_IO2 BE44 PAD~D T132 @
PCH_SPI_DO3 AJ2 TP3
SPI_IO3 AY43 PCH_TD_IREF 1 2
B TD_IREF RH322 8.2K_0402_1% B

LYNXPOINT_BGA695 3 OF 11 5

+3V_PCH
+3V_PCH 1K

PCH_SPI_CLK
3.3K_0402_5%

1 2 PCH_SPI_DO3_R +3V_PCH
2

RH370 1K_0402_1%~D

2
RH58

1 2 PCH_SPI_DO2_R CH56
RH371 1K_0402_1%~D 200 MIL SO8 1 2 RH60 @
33_0402_5%~D
64Mb Flash ROM 0.1U_0402_25V6K~D
1

UH14

1
PCH_SPI_CS0# RH3731 2 0_0402_5%~D PCH_SPI_CS0#_R 1 8
/CS VCC

22P_0402_50V8J~D
PCH_SPI_SO RH3721 2 15_0402_5% PCH_SPI_SO_R 2 7 PCH_SPI_DO3_R RH3741 2 15_0402_5% PCH_SPI_DO3 1
DO /HOLD

@
PCH_SPI_DO2 RH3751 2 15_0402_5% PCH_SPI_DO2_R 3 6 PCH_SPI_CLK_R RH3761 2 15_0402_5% PCH_SPI_CLK
/WP CLK

CH8
4 5 PCH_SPI_SI_R RH3771 2 15_0402_5% PCH_SPI_SI 2
GND DIO

EN25Q64-104HIP SOP8

Reserve for EMI please


15 close to UH14
A A

Security Classification Compal Secret Data


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) SPI, SMBUS,LPC

www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 19 of 56
5 4 3 2 1
5 4 3 2 1

D D

LPT_PCH_M_EDS
UH1I

AW31 B37 USB20_N0


AY31 PERN1/USB3RN3 USB2N0 D37 USB20_N0 52
USB20_P0 JUSB1
PERP1/USB3RP3 USB2P0 A38 USB20_N1 USB20_P0 52
BE32 USB2N1 C38 USB20_N1 52
USB20_P1 JUSB2
BC32 PETN1/USB3TN3 USB2P1 A36 USB20_P1 52
USB20_N2
PETP1/USB3TP3 USB2N2 C36 USB20_N2 53
USB20_P2 JUSB3
AT31 USB2P2 A34 USB20_P2 53
USB20_N3
AR31 PERN2/USB3RN4 USB2N3 C34 USB20_P3 USB20_N3 53 USBRBIAS
PERP2/USB3RP4 USB2P3 B33 USB20_N4
USB20_P3 53 JUSB4
USB2N4 USB20_N4 51

22.6_0402_1%~D
BD33 D33 USB20_P4 Mini Card(WLAN)
PETN2/USB3TN4 USB2P4 USB20_P4 51

1
BB33 F31 USB20_N5
PETP2/USB3TP4 USB2N5 USB20_N5 51

RH160
G31 USB20_P5 Mini Card(DMC)
USB2P5 K31 USB20_N6 USB20_P5 51
AW33 USB2N6 L31 USB20_N6 47
PCIE_PRX_GLANTX_N1 USB20_P6 ELC LED
44 PCIE_PRX_GLANTX_N1 PERN_3 USB2P6 USB20_P6 47
PCIE_PRX_GLANTX_P1 AY33 G29

2
44 PCIE_PRX_GLANTX_P1 PERP_3 USB2N7 H29
10/100/1G LAN USB2P7 IR sensor
CH149 1 2 0.1U_0402_25V6K~D PCIE_PTX_GLANRX_N1_C BE34 A32
44 PCIE_PTX_GLANRX_N1 CH150 1 2 0.1U_0402_25V6K~D PCIE_PTX_GLANRX_P1_C BC34 PETN_3 USB2N8 C32
44 PCIE_PTX_GLANRX_P1 PETP_3 USB2P8 A30
PCIE_PRX_CARDTX_N4 AT33 USB2N9 C30
53 PCIE_PRX_CARDTX_N4 PERN_4 USB2P9 CAD NOTE:
PCIE_PRX_CARDTX_P4 AR33 B29
53 PCIE_PRX_CARDTX_P4 PERP_4 USB2N10 D29 Route single-end 50-ohms and max 500-mils length.
CARD READER USB2P10 Avoid routing next to clock pins or under stitching capacitors.
CH153 1 2 0.1U_0402_25V6K~D PCIE_PTX_CARDRX_N4_C BE36 A28
53 PCIE_PTX_CARDRX_N4 1 2 0.1U_0402_25V6K~D PCIE_PTX_CARDRX_P4_C BC36 PETN_4 USB2N11 C28
C
53 PCIE_PTX_CARDRX_P4
CH154
PETP_4 USB2P11 eDP Camera Recommended minimum spacing to other signal traces is 15 mils. C
G26 USB20_N12

PCIe
AW36 USB2N12 F26 USB20_N12 42
PCIE_PRX_WLANTX_N5 USB20_P12 LVDS Camera

USB
51 PCIE_PRX_WLANTX_N5 AV36 PERN_5 USB2P12 F24 USB20_P12 42
PCIE_PRX_WLANTX_P5 USB20_N13
51 PCIE_PRX_WLANTX_P5 PERP_5 USB2N13 G24 USB20_P13 USB20_N13 53
MiniWLAN (Mini Card 1) USB2P13 USB20_P13 53 VPK K/B
51 PCIE_PTX_WLANRX_N5 PCIE_PTX_WLANRX_N5 BD37
PCIE_PTX_WLANRX_P5 BB37 PETN_5
51 PCIE_PTX_WLANRX_P5 PETP_5 AR26 USB3RN1
AY38 USB3RN1 AP26 USB3RN1 52
PCIE_PRX_WANTX_N6 USB3RP1
51 PCIE_PRX_WANTX_N6 PCIE_PRX_WANTX_P6 AW38 PERN_6 USB3RP1 BE24 USB3TN1 USB3RP1 52
51 PCIE_PRX_WANTX_P6 PERP_6 USB3TN1 BD23 USB3TP1
USB3TN1 52 P1: JUSB1
BC38 USB3TP1 AW26 USB3TP1 52
MiniDMC (Mini Card 2) 51 PCIE_PTX_WANRX_N6 PCIE_PTX_WANRX_N6 USB3RN2
BE38 PETN_6 USB3RN2 AV26 USB3RN2 52
51 PCIE_PTX_WANRX_P6 PCIE_PTX_WANRX_P6 USB3RP2
PETP_6 USB3RP2 BD25 USB3RP2 52
USB3TN2 P2: JUSB2
AT40 USB3TN2 BC24 USB3TP2 USB3TN2 52
AT39 PERN_7 USB3TP2 AW29 USB3TP2 52
USB3RN5
PERP_7 USB3RN5 AV29 USB3RN5 53
USB3RP5
BE40 USB3RP5 BE26 USB3RP5 53
USB3TN5 P5: JUSB3
BC40 PETN_7 USB3TN5 BC26 USB3TN5 53
USB3TP5
PETP_7 USB3TP5 AR29 USB3RN6 USB3TP5 53
AN38 USB3RN6 AP29 USB3RN6 53
USB3RP6
AN39 PERN_8 USB3RP6 BD27 USB3RP6 53
USB3TN6 P6: JUSB4
PERP_8 USB3TN6 BE28 USB3TN6 53
USB3TP6
BD42 USB3TP6 USB3TP6 53
BD41 PETN_8 K24 USBRBIAS
PETP_8 USBRBIAS# K26
@ USBRBIAS
1 2 PCH_PCIE_IREF BE30 M33 PAD~D T135 @
+1.5VS PCIE_IREF TP24
RH51 0_0402_1% L33 PAD~D T137 @
TP23
@ T134 PAD~D BC30 P3 USB_OC0#
TP11 OC0#/GPIO59 V1 USB_OC1# USB_OC0# 52
OC1#/GPIO40 U2 USB_OC2# USB_OC1# 52
BB29 OC2#/GPIO41 P1 USB_OC3# USB_OC2# 53
@ T136 PAD~D
TP6 OC3#/GPIO42 M3 USB_OC4# USB_OC3# 53
OC4#/GPIO43 T1 USB_OC5#
1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC6#
+1.5VS PCIE_RCOMP OC6#/GPIO10
RH210 7.5K_0402_1%~D M1 USB_OC7#
OC7#/GPIO14

B B
LYNXPOINT_BGA695 9 OF 11 5

+3V_PCH

USB_OC0# RH154 1 2 10K_0402_5%~D


USB_OC1# RH159 1 2 10K_0402_5%~D
USB_OC3# RH173 1 2 10K_0402_5%~D
USB_OC4# RH180 1 2 10K_0402_5%~D

USB_OC5# RH183 1 2 10K_0402_5%~D


USB_OC6# RH188 1 2 10K_0402_5%~D
USB_OC7# RH189 1 2 10K_0402_5%~D
USB_OC2# RH190 1 2 10K_0402_5%~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
PCH (5/9) PCIE,USB

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 20 of 56
5 4 3 2 1
5 4 3 2 1

D D

+3VS
+3VS
GATEA20 2 1
LPT_PCH_M_EDS
1 2 DMC_RADIO_OFF# UH1F 10K_0402_5%~D RH161
RH270 10K_0402_5%~D KB_RST# 2 1
1 2 DGPU_EDIDSEL# DMC_RADIO_OFF# AT8 10K_0402_5%~D RH203
RH271 10K_0402_5%~D 51 DMC_RADIO_OFF# BMBUSY#/GPIO0
1 2 DGPU_HPD_INT# DGPU_EDIDSEL# F13
RH164 10K_0402_5%~D 31,36,42 DGPU_EDIDSEL# TACH1/GPIO1
2 1 STP_PCI# DGPU_HPD_INT# A14
36,39 DGPU_HPD_INT# TACH2/GPIO6
RH179 10K_0402_5%~D
CPU/Misc
1 2 VGA_PRSNT_R# EC_SCI# G15
43 EC_SCI# TACH3/GPIO7
RH267 10K_0402_5%~D
1 2 VGA_PRSNT_L# EC_SMI# Y1
43 EC_SMI# GPIO8
RH57 20K_0402_5%~D
1 2 GPIO22 K13
41 EDP_DETECT# LAN_PHY_PWR_CTRL/GPIO12 AN10
RH256 10K_0402_5%~D GATEA20
1 2 LVDS_CAB_DET# MXM2_PRSNT_R# AB11 TP14 GATEA20 43
30 MXM2_PRSNT_R# GPIO15 AY1 2 RH184 1
RH257 10K_0402_5%~D H_PECI 43,6
PECI

@
1 2 EDP_CAB_DET# PCH_GPIO16 AN2 0_0402_5%~D
RH258 10K_0402_5%~D SATA4GP/GPIO16 AT6 KB_RST#
C14 GPIO RCIN# KB_RST# 43
30 MXM2_PCH_PWROK TACH0/GPIO17 AV3 H_CPUPWRGD
+3V_PCH BB4 PROCPWRGD H_CPUPWRGD 6
GPIO22
SCLOCK/GPIO22 AV1 PCH_THRMTRIP#_R 1 2
2 1 Y10 THRMTRIP# H_THERMTRIP# 6
HDD2_DETECT# 390_0402_5% RH262
RH187 10K_0402_5%~D GPIO24 AU4 CPU_PLTRST#
PLTRST_PROC# CPU_PLTRST# 6
PCH_GPIO27 R11
30 PCH_GPIO27 GPIO27 N10
1 2 MXM2_PRSNT_R# PCH_GPIO28 AD11 VSS
RH354 1K_0402_1%~D GPIO28
STP_PCI# AN6
GPIO34
2 1 ODD_EN# ODD_EN# AP1
50 ODD_EN# GPIO35/NMI#
RH264 10K_0402_5%~D
ODD_DETECT# AT3
50 ODD_DETECT# SATA2GP/GPIO36
PCH_GPIO37 AK1
C 2 1 PCH_GPIO27 SATA3GP/GPIO37 C
RH269 10K_0402_5%~D VGA_PRSNT_R# AT7
29 VGA_PRSNT_R# SLOAD/GPIO38
VGA_PRSNT_L# AM3 A2
29 VGA_PRSNT_L# SDATAOUT0/GPIO39 VSS A41
FFS_INT2 AN4 VSS A43
49,50 FFS_INT2 SDATAOUT1/GPIO48 VSS A44
KB_DET# AK3 VSS B1
53 KB_DET# SATA5GP/GPIO49 VSS B2
HDD2_DETECT# U12 VSS B44
+3V_PCH 49 HDD2_DETECT# GPIO57 VSS B45
DGPU_BKL_PWM_SEL# C16 VSS BA1
42 DGPU_BKL_PWM_SEL# TACH4/GPIO68 VSS BC1
VSS
2
4.7K_0402_5%~D

EDP_CAB_DET# D13 BD1


TACH5/GPIO69 VSS BD2
VSS
RH53

LVDS_CAB_DET# G13 BD44


42 LVDS_CAB_DET# TACH6/GPIO70 VSS BD45
H15 VSS BE2
1

51 WiGi_RADIO_DIS# TACH7/GPIO71 VSS BE3


PCH_GPIO28 VSS D1
BE41 VSS E1
BE5 VSS NCTF VSS E45
VSS VSS
1
1K_0402_1%~D

C45 A4
VSS VSS
@ RH353

A5
VSS

LYNXPOINT_BGA695 6 OF 11 5
2

PLL ON DIE VR ENABLE


+3VS
ENABLED - HIGH(DEFAULT) 1 2 PCH_GPIO16
DISABLED - LOW RH272 10K_0402_5%~D
2 1 KB_DET#
RH266 10K_0402_5%~D

2 1 PCH_GPIO16
B B
RH265 @ 10K_0402_5%~D
2 1 KB_DET#
RH268 @ 10K_0402_5%~D

+3VS
Config GPIO16,49 2 1 ODD_DETECT#
RH176 1K_0402_1%~D
1@ 2 PCH_GPIO37
USB X4,PCIEX8,SATAX6 11 RH171 200K_0402_5%
2 @ 1 ODD_DETECT#
RH174 10K_0402_5%~D
* USB X6,PCIEX8,SATAX4 01 2 1 PCH_GPIO37
RH181 10K_0402_5%~D

SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.


WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
PCH (6/9) GPIO,MISC,NTFC

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 21 of 56
5 4 3 2 1
5 4 3 2 1

D D

PCH Power Rail Table

Voltage Rail Voltage S0 Iccmax Current (A)

VCC 1.05V 1.29 A

VCCIO 1.05V 3.629 A


LPT_PCH_M_EDS
UH1G
C +1.05V_+1.5V_RUN VCCADAC1_5 1.5V 0.070 A C
+1.05VS P45
VCCADAC1_5

10U_0603_6.3V6M~D
AA24 P43 VCCADAC3_3 3.3V 0.0133 A
VCC CRT DAC VSS
10U_0603_6.3V6M~D

AA26 +1.05VS
VCC
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1 AD20 M31 1
VCC VCCADACBG3_3

1U_0402_6.3V6K~D

@ CH81
AD22 VCCCLK 1.05V 0.306 A
VCC
CH30

CH32

CH33

CH31

AD24 1
AD26 VCC BB44
2 2 2 2 VCC VCCVRM +3VS 2

CH48
AD28 VCCCLK3_3 3.3V 0.055 A
AE18 VCC FDI
AN34
AE20 VCC VCCIO 2
AE22 VCC AN35
VCC VCCIO VCCVRM 1.5V 0.179 A
+3V_PCH

0.1U_0402_10V7K~D
AE24
AE26 VCC R30
VCC HVCMOS VCC3_3_R30 1
AG18 R32 VCC3_3 3.3V 0.133 A
VCC VCC3_3_R32

0.1U_0402_10V7K~D

CH38
AG20
AG22 VCC Y12 +PCH_USB_DCPSUS1
VCC DCPSUS1 1 2
AG24 VCCASW 1.05V 0.67 A
VCC

CH60
Y26 AJ30
VCC VCCSUS3_3
Core

AJ32
VCCSUS3_3 2
VCCSUSHDA 3.3V 0.01 A
+1.05V AJ26 +PCH_USB_DCPSUS3 +1.05V_+1.5V_RUN
+PCH_VCCDSW U14 USB3 DCPSUS3 AJ28
AA18 DCPSUSBYP DCPSUS3 AK20
VCCASW VCCIO +1.05VS VCCSPI 3.3V 0.022 A
U18 AK26
VCCASW VCCVRM
22U_0805_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.05V_+1.5V_RUN

10U_0603_6.3V6M~D
U20 AK28 1
VCCASW VCCVRM

@ CH82
1 1 1 U22 VCCSUS3_3 3.3V 0.261 A
U24 VCCASW BE22
VCCASW VCCVRM
CH64

CH35

CH36

V18
C_0805NEW

PCIe/DMI
VCCASW +1.05V_+1.5V_RUN 2

10U_0603_6.3V6M~D
V20 AK18 1 VCCDSW3_3 3.3V 0.015 A
2 2 2 VCCASW VCCIO +1.05VS

@ CH83
V22
V24 VCCASW AN11
VCCASW VCCVRM

10U_0603_6.3V6M~D
Y18 V_PROC_IO 1.05V 0.004 A
Y20 VCCASW SATA AK22 2
VCCASW VCCIO 1

@ CH85
Y22 +1.05VS
VCCASW AM18
VCCIO AM20
VCCIO AM22 2
VCCMPHY VCCIO AP22
B VCCIO B

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
AR22 1 1 1 1 1
VCCIO AT22
VCCIO

CH86

CH47

CH46

CH45

CH44
LYNXPOINT_BGA695 7 OF 11 5 2 2 2 2 2 +1.05V

+PCH_USB_DCPSUS1 2 1
0_0402_5%~D RH360 @

1U_0402_6.3V6K~D
1

@ CH61
1 2 +PCH_VCCDSW +1.5VS +1.05V_+1.5V_RUN
@ RH37 5.11_0402_1%~D
+PCH_VCCDSW_R

@
2 1 2
RH197 0_0603_5%~D

+1.05V
1U_0402_6.3V6K~D

+PCH_USB_DCPSUS3 1 2
0_0603_5%~D RH209 @

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D
1
@ CH34

1 1

@CH40
@

@CH39
@
CH40

CH39
2
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
PCH (7/9) Power

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 22 of 56
5 4 3 2 1
5 4 3 2 1

+3V_PCH
D D

+PCH_VCCDSW3_3

0.1U_0402_10V7K~D
1
2 1
LPT_PCH_M_EDS +3V_PCH

CH88
UH1H 0_0402_5%~D RH213

0.1U_0402_10V7K~D
2 1
+3V_PCH 2 +3VALW
0_0402_5%~D RH253
1 @

CH155
R24 R20
R26 VCCSUS3_3 VCCSUS3_3 R22
0.1U_0402_10V7K~D R28 VCCSUS3_3 VCCSUS3_3
+1.05VS U26 VCCSUS3_3 GPIO/LPC 2
1 VCCSUS3_3 A16 +PCH_VCCDSW3_3
VCCDSW3_3
CH66

M24 +3VS
VSS AA14 +PCH_VCCSST 1 2
2 DCPSST
0.1U_0402_10V7K~D
+3VS U35 CH84 0.1U_0402_10V7K~D
VCCUSBPLL AE14
1

USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
CH62

0.1U_0402_10V7K~D
AG14
VCC3_3 +3V_PCH

0.1U_0402_10V7K~D
U30 1
2 +1.05VS V28 VCCIO
1 VCCIO

CH63

CH65
V30 U36
VCCIO VCCIO +1.05VS
Y30
VCCIO +3V_PCH 2
2

0.1U_0402_10V7K~D
+1.05V_+1.5V_RUN +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2

1U_0402_6.3V6K~D
1 A26 1
AF34 VCCSUSHDA
VCCVRM

CH37

CH90
10U_0603_6.3V6M~D
+RTC_CELL

1U_0402_6.3V6K~D
1 +PCH_VCC AP45 K8 1
2 VCC VCCSUS3_3 2

CH42

CH59
Y32 A6
+PCH_VCCCLK VCCCLK VCCRTC
2 RTC 2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D
M29 P14 +PCH_DCPRTC CH70
+1.05V +PCH_VCCCLK3_3 VCCCLK3_3 DCPRTC P16 1 2 1 1 1
L29 DCPRTC
VCCCLK3_3

CH69

CH68

CH67
1 2 +PCH_USB_DCPSUS2 0.1U_0402_10V7K~D
@ RH361 0_0402_5%~D L26 AJ12 +PCH_VPROC
VCCCLK3_3 V_PROC_IO 2 2 2
1U_0402_6.3V6K~D

C M26 CPU AJ14 +3V_PCH C


VCCCLK3_3 V_PROC_IO
1
@CH87
@

U32
VCCCLK3_3
CH87

1U_0402_6.3V6K~D
ICC
V32 AD12
VCCCLK3_3 SPI VCCSPI
2 AD34
+PCH_VCCCLK VCCCLK 1
P18 +PCH_VCCCFUSE
VCC

CH74
AA30 P20
AA32 VCCCLK VCC
VCCCLK L17 2
Fuse VCCASW +1.05V
AD35
VCCCLK R18
+1.05VS +1.05VS_VCC AG30 VCCASW +1.05VS
AG32 VCCCLK @
LH100 @ VCCCLK AW40 +PCH_VPROC 2 1
VCCVRM +1.05V_+1.5V_RUN
1 2 1 2 +PCH_VCC AD36 0_0805_5%~D RH219
VCCCLK +3VS

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D
4.7UH_LQM18FN4R7M00D_20%~D RH207 0_0603_5%~D AK30
VCC3_3
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

AE30 Thermal 1 1 1
AE32 VCCCLK AK32
1 1 VCCCLK VCC3_3
CH55

CH51

0.1U_0402_10V7K~D

CH73

CH72

CH71
1 2 2 2
2 2

CH76
LYNXPOINT_BGA695 8 OF 11 5
2

Place near pin AP45

+1.05VS +PCH_VCCCLK
@
1 2 @
RH214 0_0805_5%~D +PCH_VCCCFUSE 2 1
+3VS
0_0805_5%~D RH220
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
2 1
+1.05VS
@ CH43

1 1 1 1 1 1 1 0_0805_5%~D RH221 @
CH49

CH50

CH77

CH78

CH79

CH75
B 2 2 2 2 2 2 2 B

Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32

+3VS +PCH_VCCCLK3_3

@
1 2
RH212 0_0805_5%~D
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1
CH52

CH54

CH53

CH58

2 2 2 2

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
PCH (8/9) Power

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 23 of 56
5 4 3 2 1
5 4 3 2 1

D D

UH1J LPT_PCH_M_EDS UH1K LPT_PCH_M_EDS

AL34 K39 AA16 B19


AL38 VSS VSS L2 AA20 VSS VSS B23
AL8 VSS VSS L44 AA22 VSS VSS B27
AM14 VSS VSS M17 AA28 VSS VSS B31
AM24 VSS VSS M22 AA4 VSS VSS B35
AM26 VSS VSS N12 AB12 VSS VSS B39
AM28 VSS VSS N35 AB34 VSS VSS B7
AM30 VSS VSS N39 AB38 VSS VSS BA40
AM32 VSS VSS N6 AB8 VSS VSS BD11
AM16 VSS VSS P22 AC2 VSS VSS BD15
AN36 VSS VSS P24 AC44 VSS VSS BD19
AN40 VSS VSS P26 AD14 VSS VSS AY36
AN42 VSS VSS P28 AD16 VSS VSS AT43
AN8 VSS VSS P30 AD18 VSS VSS BD31
AP13 VSS VSS P32 AD30 VSS VSS BD35
C AP24 VSS VSS R12 AD32 VSS VSS BD39 C
AP31 VSS VSS R14 AD40 VSS VSS BD7
AP43 VSS VSS R16 AD6 VSS VSS D25
AR2 VSS VSS R2 AD8 VSS VSS AV7
AK16 VSS VSS R34 AE16 VSS VSS F15
AT10 VSS VSS R38 AE28 VSS VSS F20
AT15 VSS VSS R44 AF38 VSS VSS F29
AT17 VSS VSS R8 AF8 VSS VSS F33
AT20 VSS VSS T43 AG16 VSS VSS BC16
AT26 VSS VSS U10 AG2 VSS VSS D4
AT29 VSS VSS U16 AG26 VSS VSS G2
AT36 VSS VSS U28 AG28 VSS VSS G38
AT38 VSS VSS U34 AG44 VSS VSS G44
D42 VSS VSS U38 AJ16 VSS VSS G8
AV13 VSS VSS U42 AJ18 VSS VSS H10
AV22 VSS VSS U6 AJ20 VSS VSS H13
AV24 VSS VSS V14 AJ22 VSS VSS H17
AV31 VSS VSS V16 AJ24 VSS VSS H22
AV33 VSS VSS V26 AJ34 VSS VSS H24
BB25 VSS VSS V43 AJ38 VSS VSS H26
AV40 VSS VSS W2 AJ6 VSS VSS H31
AV6 VSS VSS W44 AJ8 VSS VSS H36
AW2 VSS VSS Y14 AK14 VSS VSS H40
F43 VSS VSS Y16 AK24 VSS VSS H7
AY10 VSS VSS Y24 AK43 VSS VSS K10
AY15 VSS VSS Y28 AK45 VSS VSS K15
AY20 VSS VSS Y34 AL12 VSS VSS K20
AY26 VSS VSS Y36 AL2 VSS VSS K29
AY29 VSS VSS Y40 BC22 VSS VSS K33
AY7 VSS VSS Y8 BB42 VSS VSS BC28
B11 VSS VSS VSS VSS
B15 VSS
B VSS B
LYNXPOINT_BGA695 11 OF 11 5

LYNXPOINT_BGA695 10 OF 11 5

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) Power

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 24 of 56
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
Cactus (1/4) DP/PCIE

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 25 of 56
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
Cactus (2/4) CIO

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0,1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 26 of 56
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
Cactus (3/4) PWR/VSS/DC-DC

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 27 of 56
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 28 of 56
5 4 3 2 1
5 4 3 2 1

+3V_MXM +3V_MXM +3V_MXM +3V_MXM


PEG_HTX_C_GRX_N[0..15] +3V_MXM +3VALW
30,5 PEG_HTX_C_GRX_N[0..15] 1 2 1 2 3.3K_0402_5%
VGA_LCD_CLK RV63 4.3K_0402_5% MXM_CURI2C_CLK RV64 @
D D
PEG_HTX_C_GRX_P[0..15] VGA_LCD_DAT RV65 1 2 4.3K_0402_5% MXM_CURI2C_DATA RV66 1 @ 2 3.3K_0402_5%

10K_0402_5%~D
30,5 PEG_HTX_C_GRX_P[0..15]

10K_0402_5%~D

4.7K_0402_5%~D

4.7K_0402_5%~D
DGPU_PWROK RV67 2 @ 1 10K_0402_5%~D

1
30,5 PEG_GTX_HRX_N[0..15] PEG_GTX_HRX_N[0..15] VGA_HDMI_CEC RV68 1 2 10K_0402_5%~D

RV71
VGA_DISABLE# RV69 1 @ 2 10K_0402_5%~D AC_BATT# RV70 2 1 10K_0402_5%~D

RV72

RV73

RV74
PEG_GTX_HRX_P[0..15] VGA_WAKE# RV75 1 @ 2 10K_0402_5%~D 2
30,5 PEG_GTX_HRX_P[0..15]
2011/11/25 remove CRT conn

G
2
B+_MXM B+_MXM

G
2

2
JMXM1A
1 2
400mil(10A) 1 3 VGA_SMB_DA1

S
PWR_SRC PWR_SRC 43,57,64 EC_SMB_DA1 VGA_SMB_DA1 30
+3VALW

D
3 4 VGA_TH_OVERT# 3 1 TH_OVERT# 43 2
PWR_SRC PWR_SRC

10U_1206_25V6M~D

680P_0603_50V7K~D

68P_0402_50V8J~D

0.1U_0603_25V7K~D
5 6

G
PWR_SRC PWR_SRC QV6
7 8 1 1 1 2 1 SSM3K7002F_SC59-3~D
PWR_SRC PWR_SRC QV7

CV2
9 10
PWR_SRCE1 E2 PWR_SRC SSM3K7002F_SC59-3~D

CV1

CV3
11 12 CV5 1 3 VGA_SMB_CK1

S
PWR_SRC PWR_SRC 43,57,64 EC_SMB_CK1 VGA_SMB_CK1 30

CV4
13 14
+5VMXM +5V_MXM 15 PWR_SRC PWR_SRC 16 2 2 2 1 2 0.1U_0402_25V6K~D
PWR_SRC PWR_SRC JMXM1B QV8
J12 @ 17 18 SSM3K7002F_SC59-3~D
2 1 PWR_SRC PWR_SRC 163 162
GND GND

5
0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D
UV4 PEG_GTX_HRX_N2 165 164 PEG_HTX_C_GRX_N2
PAD-OPEN 4x4m 19 20 1 PEG_GTX_HRX_P2 167 PEX_RX2# PEX_TX2# 166 PEG_HTX_C_GRX_P2
1 1

G VCC
GND GND 17,43,47,57,64 ACIN B PEX_RX2 PEX_TX2
CV7

21 22 4 AC_BATT# AC_BATT# 30 169 168


GND GND Y GND GND
CV6

23 24 2 PEG_GTX_HRX_N1 171 170 PEG_HTX_C_GRX_N1


25 GND GND 26 43 EC_AC_BAT# A 173 PEX_RX1# PEX_TX1# 172
PEG_GTX_HRX_P1 PEG_HTX_C_GRX_P1
2 2 27 GND GND 28 MC74VHC1G09DFT2G_SC70-5 175 PEX_RX1 PEX_TX1 174

3
29 GND GND 30 2 1 PEG_GTX_HRX_N0 177 GND GND 176 PEG_HTX_C_GRX_N0
GND E3 E4 GND PEX_RX0# PEX_TX0#
31 32 PEG_GTX_HRX_P0 179 178 PEG_HTX_C_GRX_P0
+5V_MXM 33 GND GND 34 RV92 @ 0_0402_5%~D 181 PEX_RX0 PEX_TX0 180
35 GND GND 36 RV76 1 @ 2 0_0402_1% CLK_PEG_PCH#_R183 GND GND 182 PEG_CLKREQ#
GND GND 18 CLK_PEG_PCH# PEX_REFCLK# PEX_CLK_REQ# PEG_CLKREQ# 18
37 38 VGA_PRSNT_R# VGA_PRSNT_R# 21 RV77 1 @ 2 0_0402_1% CLK_PEG_PCH_R 185 184 PLTRST_VGA#
39 5V PRSNT_R# 40 18 CLK_PEG_PCH 187 PEX_REFCLK PEX_RST# 186 PLTRST_VGA# 17,30
VGA_WAKE#
41 5V WAKE# 42 DGPU_PWROK 189 GND VGA_DDC_DAT 188
5V PWR_GOOD DGPU_PWROK 18,31 RSVD VGA_DDC_CLK
43 44 VR_ON 191 190
45 5V PWR_EN 46 VR_ON 30,43 193 RSVD VGA_VSYNC 192
47 5V RSVD 48 195 RSVD VGA_HSYNC 194
100mil(2.5A, 5VIA) 49 GND RSVD 50 197 RSVD GND 196
CRT
51 GND RSVD 52 +3V_MXM 199 RSVD VGA_RED 198
Add R7 increase NV MXM PEG Swing +3VMXM LVDS_MXM_TZCLK-
53 GND RSVD 54 AC_BATT# 41 LVDS_MXM_TZCLK- LVDS_MXM_TZCLK+ 201 LVDS_UCLK# VGA_GREEN 200
RV78 1 2 0_0402_5%~D 55 GND PWR_LEVEL 56 VGA_TH_OVERT# J13 @ 41 LVDS_MXM_TZCLK+ 203 LVDS_UCLK VGA_BLUE 202
PEX_STD_SW# TH_OVERT# VGA_TH_OVERT# 30 GND GND
VGA_DISABLE# 57 58 1 2 2 1 205 204 LVDS_MXM_TXCLK-
59 VGA_DISABLE# TH_ALERT# 60 207 LVDS_UTX3# LVDS_LCLK# 206 LVDS_MXM_TXCLK- 41
C 42 DGPU_ENVDD PNL_PWR_EN TH_PWM
RV79 10K_0402_5%~D LVDS TZ LVDS_UTX3 LVDS_LCLK
LVDS_MXM_TXCLK+
LVDS_MXM_TXCLK+ 41
C

4.7U_0805_10V4Z~D
42 DGPU_BKL_EN 61 62 209 208
63 PNL_BL_EN GPIO0 64 PAD-OPEN 4x4m LVDS_MXM_TZOUT2- 211 GND GND 210
42 VGA_PNL_PWM
VGA_HDMI_CEC 65 PNL_BL_PWM GPIO1 66 41 LVDS_MXM_TZOUT2- LVDS_MXM_TZOUT2+ 213 LVDS_UTX2# LVDS_LTX3# 212
LVDS TX
HDMI_CEC GPIO2 1 41 LVDS_MXM_TZOUT2+ LVDS_UTX2 LVDS_LTX3
67 68 VGA_SMB_DA1 215 214
DVI_HPD SMB_DAT GND GND

CV8
VGA_LCD_DAT 69 70 VGA_SMB_CK1 LVDS_MXM_TZOUT1- 217 216 LVDS_MXM_TXOUT2-
42 VGA_LCD_DAT VGA_LCD_CLK 71 LVDS_DDC_DAT SMB_CLK 72 SYSTEM 41 LVDS_MXM_TZOUT1- LVDS_MXM_TZOUT1+ 219 LVDS_UTX1# LVDS_LTX2# 218 LVDS_MXM_TXOUT2+ LVDS_MXM_TXOUT2- 41
42 VGA_LCD_CLK 73 LVDS_DDC_CLK GND 74 2 41 LVDS_MXM_TZOUT1+ 221 LVDS_UTX1 LVDS_LTX2 220 LVDS_MXM_TXOUT2+ 41
LVDS DDC Module have 4.7K Pull-UP GND OEM GND GND
75 76 VGA_PS_0 LVDS_MXM_TZOUT0- 223 222 LVDS_MXM_TXOUT1-
77 OEM OEM 78 VGA_PS_1 41 LVDS_MXM_TZOUT0- LVDS_MXM_TZOUT0+ 225 LVDS_UTX0# LVDS_LTX1# 224 LVDS_MXM_TXOUT1+ LVDS_MXM_TXOUT1- 41
79 OEM OEM 80 VGA_PS_2 41 LVDS_MXM_TZOUT0+ 227 LVDS_UTX0 LVDS_LTX1 226 LVDS_MXM_TXOUT1+ 41
81 OEM OEM 82 GPU_HDMI_TXD2- 229 GND GND 228 LVDS_MXM_TXOUT0-
OEM GND 36 GPU_HDMI_TXD2- DP_C_L0# LVDS_LTX0# LVDS_MXM_TXOUT0- 41
83 84 +3V_MXM +3V_MXM +3V_MXM GPU_HDMI_TXD2+ 231 230 LVDS_MXM_TXOUT0+
GND PEX_TX15# 36 GPU_HDMI_TXD2+ DP_C_L0 LVDS_LTX0 LVDS_MXM_TXOUT0+ 41
85 86 233 232
87 PEX_RX15# PEX_TX15 88 235 GND GND 234

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D
36 GPU_HDMI_TXD1- GPU_HDMI_TXD1-
PEX_RX15 GND DP_C_L1# DP_D_L0#

2
89 90 36 GPU_HDMI_TXD1+ GPU_HDMI_TXD1+ 237 236
GND PEX_TX14# DP_C_L1 DP_D_L0

RV83

RV84

RV86
91 92 239 238
93 PEX_RX14# PEX_TX14 94 GPU_HDMI_TXD0- 241 GND GND 240
95 PEX_RX14 GND 96
@ @ @ 36 GPU_HDMI_TXD0-
GPU_HDMI_TXD0+ 243
HDMI DP_C_L2# DP_D_L1# 242
97 GND PEX_TX13# 98
36 GPU_HDMI_TXD0+
245 DP_C_L2 DP_D_L1 244
eDP

1
99 PEX_RX13# PEX_TX13 100 GPU_HDMI_TXC- 247 GND GND 246
PEX_RX13 GND 36 GPU_HDMI_TXC- DP_C_L3# DP_D_L2#
101 102 VGA_PS_2 36 GPU_HDMI_TXC+ GPU_HDMI_TXC+ 249 248
103 GND PEX_TX12# 104 251 DP_C_L3 DP_D_L2 250
105 PEX_RX12# PEX_TX12 106 VGA_PS_1 GPU_HDMI_SDATA 253 GND GND 252
PEX_RX12 GND 36 GPU_HDMI_SDATA DP_C_AUX# DP_D_L3#
107 108 36 GPU_HDMI_SCLK GPU_HDMI_SCLK 255 254
109 GND PEX_TX11# 110 VGA_PS_0 257 DP_C_AUX DP_D_L3 256
111 PEX_RX11# PEX_TX11 112 259 RSVD GND 258
113 PEX_RX11 GND 114 261 RSVD DP_D_AUX# 260
115 GND PEX_TX10# 116 263 RSVD DP_D_AUX 262
0_0402_5%~D

0_0402_5%~D

0_0402_5%~D
VGA_HDMI_DET
PEX_RX10# PEX_TX10 RSVD DP_C_HPD VGA_HDMI_DET 36
2

2
117 118 265 264
PEX_RX10 GND RSVD DP_D_HPD
RV85

RV87

RV93
119 120 267 266
121 GND PEX_TX9# 122 @ @ @ 269 RSVD RSVD 268
123 PEX_RX9# PEX_TX9 124 271 RSVD RSVD 270
125 PEX_RX9 GND 126 273 RSVD RSVD 272
1

1
127 GND PEX_TX8# 128 275 RSVD GND 274 VGA_DPC_N0
PEX_RX8# PEX_TX8 RSVD DP_B_L0# VGA_DPC_N0 31
129 130 277 276 VGA_DPC_P0
PEX_RX8 GND RSVD DP_B_L0 VGA_DPC_P0 31
131 132 PEG_HTX_C_GRX_N7 279 278
PEG_GTX_HRX_N7 133 GND PEX_TX7# 134 PEG_HTX_C_GRX_P7 281 RSVD GND 280 VGA_DPC_N1
PEX_RX7# PEX_TX7 GND DP_B_L1# VGA_DPC_N1 31
PEG_GTX_HRX_P7 135 136 39 VGA_DPD_N0 VGA_DPD_N0 283 282 VGA_DPC_P1 VGA_DPC_P1 31
137 PEX_RX7 GND 138 PEG_HTX_C_GRX_N6 VGA_DPD_P0 285 DP_A_L0# DP_B_L1 284
B GND PEX_TX6# 39 VGA_DPD_P0 DP_A_L0 GND B
PEG_GTX_HRX_N6 139 140 PEG_HTX_C_GRX_P6 287 286 VGA_DPC_N2 mDP
PEX_RX6# PEX_TX6 GND DP_B_L2# VGA_DPC_N2 31
PEG_GTX_HRX_P6 141 142 39 VGA_DPD_N1 VGA_DPD_N1 289 288 VGA_DPC_P2 VGA_DPC_P2 31
143 PEX_RX6 GND 144 PEG_HTX_C_GRX_N5 VGA_DPD_P1 291 DP_A_L1# DP_B_L2 290
GND PEX_TX5# 39 VGA_DPD_P1 DP_A_L1 GND
PEG_GTX_HRX_N5 145 146 PEG_HTX_C_GRX_P5 293 DMC 292 VGA_DPC_N3 VGA_DPC_N3 31
PEG_GTX_HRX_P5 147 PEX_RX5# PEX_TX5 148 VGA_DPD_N2 295 GND DP_B_L3# 294 VGA_DPC_P3
PEX_RX5 GND 39 VGA_DPD_N2 DP_A_L2# DP_B_L3 VGA_DPC_P3 31
149 150 PEG_HTX_C_GRX_N4 39 VGA_DPD_P2 VGA_DPD_P2 297 296
PEG_GTX_HRX_N4 151 GND PEX_TX4# 152 PEG_HTX_C_GRX_P4 299 DP_A_L2 GND 298 VGA_DPC_AUXN/DDC
PEX_RX4# PEX_TX4 GND DP_B_AUX# VGA_DPC_AUXN/DDC 31
PEG_GTX_HRX_P4 153 154 VGA_DPD_N3 301 300 VGA_DPC_AUXP/DDC
155 PEX_RX4 GND 156 PEG_HTX_C_GRX_N3 Place C102, C105, C108
39
39
VGA_DPD_N3
VGA_DPD_P3 VGA_DPD_P3 303 DP_A_L3# DP_B_AUX 302 VGA_DPC_HPD
VGA_DPC_AUXP/DDC 31
PEG_GTX_HRX_N3 157 GND PEX_TX3# 158 PEG_HTX_C_GRX_P3 305 DP_A_L3 DP_B_HPD 304 VGA_DMC_HPD VGA_DPC_HPD 31
PEG_GTX_HRX_P3 159 PEX_RX3# PEX_TX3 160
close MXM connector 307 GND DP_A_HPD 306 VGA_DMC_HPD 39
PEX_RX3 GND 39 VGA_DPD_AUXN/DDC DP_A_AUX# 3V3 +3V_MXM
161 39 VGA_DPD_AUXP/DDC 309 308
GND VGA_PS_0 @ CV9 2 1 0.01U_0402_16V7K~D 310 DP_A_AUX 3V3
VGA_PS_1 @ CV10 2 1 0.01U_0402_16V7K~D
21 VGA_PRSNT_L# PRSNT_L# 80mil(2A)
JAE_MM70-314-310B1-1-R300 VGA_PS_2 @ CV11 2 1 0.01U_0402_16V7K~D 311 312
1 2 CONN@ (Pull-UP 10K at PCH) GND GND
64 MXM_CUR_VIN+
RV88 0_0402_5%~D JAE_MM70-314-310B1-1-R300
CONN@
1
CV12 @
.1U_0402_16V7K~D UV5
2 1 8 B+_MXM_A1
1 2 2 VIN+ A1 7 B+_MXM_A0 @
64 MXM_CUR_VIN- 3 VIN- A0 6 MXM_CURI2C_DATA 0_0402_1% 2 1 VGA_SMB_DA1
RV89 0_0402_5%~D RV90
4 GND SDA 5 MXM_CURI2C_CLK 0_0402_1% 2 @ 1 RV91 VGA_SMB_CK1
+3V_MXM VS SCL
HPA00900AIDCNR_SOT23-8

For B+_MXM
MXM1 Current Monitor slave address : 1000010
+3V_MXM please placemnet near R-sense
2 @ 1 B+_MXM_A1 2 1
RV403 10K_0402_5%~D RV406 10K_0402_5%~D
2 1 B+_MXM_A0 2 1
A RV408 @ 10K_0402_5%~D RV409 10K_0402_5%~D A

DV17
@
2 1 VGA_PRSNT_R#

UCLAMP0511P.TCT_SLP1006P2-2~D

DV18
@
2 1 VGA_PRSNT_L#

UCLAMP0511P.TCT_SLP1006P2-2~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
MXMIII Connector

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 29 of 56
5 4 3 2 1
5 4 3 2 1

+3V_MXM1 +3V_MXM1 +3V_MXM1

1
RV400 RV401
02/21-109

2
+3V_MXM1 +3VMXM +5V_MXM1 +5VMXM 4.7K_0402_5%~D 4.7K_0402_5%~D

G
J14 J15 QV29
DV15

2
2 1 2 1 @ 19,40,43,53,54 EC_SMB_DA2 1 3 2N7002E-T1-E3_SOT23-3 VGA_SMB_DA2
2 1 2 1

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D

1U_0402_6.3V4Z~D
2 1 MXM2_PRSNT_R#

2
0.1U_0402_25V6K~D
JUMP_43X118 JUMP_43X118

G
1 1 1 1 1

CV387

CV368

CV367

CV359
D QV30 D
CV357@ @ UCLAMP0511P.TCT_SLP1006P2-2~D 19,40,43,53,54 EC_SMB_CK2 1 3 2N7002E-T1-E3_SOT23-3VGA_SMB_CK2
4.7U_0603_10V6K~D
04/06-118

S
2 2 2 2 2

JMXM2B
B+_MXM1 B+_MXM1 163 162
JMXM2A PEG_GTX_HRX_N10 165 GND GND 164 PEG_HTX_C_GRX_N10
160mil(4A) 1 2
5 PEG_GTX_HRX_N10
PEG_GTX_HRX_P10 167 PEX_RX2# PEX_TX2# 166 PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10 5
PWR_SRC PWR_SRC 5 PEG_GTX_HRX_P10 PEX_RX2 PEX_TX2 PEG_HTX_C_GRX_P10 5
3 4 169 168
PWR_SRC PWR_SRC GND GND

10U_0805_25V6K~D

680P_0402_50V7K~D

68P_0402_50V8J~D

0.1U_0603_50V7K~D
5 6 5 PEG_GTX_HRX_N9 PEG_GTX_HRX_N9 171 170 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N9 5
7 PWR_SRC PWR_SRC 8 PEG_GTX_HRX_P9 173 PEX_RX1# PEX_TX1# 172 PEG_HTX_C_GRX_P9
1 1 1 2 PWR_SRC PWR_SRC 5 PEG_GTX_HRX_P9 PEX_RX1 PEX_TX1 PEG_HTX_C_GRX_P9 5

CV362

CV365

CV363

CV364
9 10 175 174
11 PWR_SRCE1 E2 PWR_SRC 12 PEG_GTX_HRX_N8 177 GND GND 176 PEG_HTX_C_GRX_N8
PWR_SRC PWR_SRC 5 PEG_GTX_HRX_N8 PEX_RX0# PEX_TX0# PEG_HTX_C_GRX_N8 5
13 14 5 PEG_GTX_HRX_P8 PEG_GTX_HRX_P8 179 178 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P8 5
2 2 2 1 15 PWR_SRC PWR_SRC 16 0_0402_5%~D 181 PEX_RX0 PEX_TX0 180
17 PWR_SRC PWR_SRC 18 GND GND
PWR_SRC PWR_SRC 18 MXM2_PEG_PCH# RV407 1 2 MXM2_PEG_PCH#_R 183
PEX_REFCLK# PEX_CLK_REQ#
182 MXM2_CLKREQ# MXM2_CLKREQ# 18
18 MXM2_PEG_PCH RV412 1 2 MXM2_PEG_PCH_R 185
PEX_REFCLK PEX_RST#
184 MXM2_RST#
0_0402_5%~D 187 186
19 20 189 GND VGA_DDC_DAT 188
21 GND GND 22 191 RSVD VGA_DDC_CLK 190
23 GND GND 24 193 RSVD VGA_VSYNC 192
+3V_MXM1 25 GND GND 26 MXM_PS_3 @ CV366 1 2 0.01U_0402_16V7K~D 195 RSVD VGA_HSYNC 194
27 GND GND 28 MXM_PS_4 @ CV360 1 2 0.01U_0402_16V7K~D 197 RSVD GND 196
2 1 B+_MXM1_A1 2 1 29 GND GND 30 MXM_PS_5 @ CV361 1 2 0.01U_0402_16V7K~D 199 RSVD VGA_RED 198
GND E3 E4 GND LVDS_UCLK# VGA_GREEN
RV404 3.3K_0402_5%~D @ RV410 0_0402_5% 31 32 201 200
2 1 B+_MXM1_A0 2 1 33 GND GND 34 203 LVDS_UCLK VGA_BLUE 202
C RV411 3.3K_0402_5%~D @ RV405 0_0402_5% 35 GND GND 36 205 GND GND 204 C
37 GND GND 38 MXM2_PRSNT_R# 207 LVDS_UTX3# LVDS_LCLK# 206
+5V_MXM1 5V PRSNT_R# MXM2_PRSNT_R# 21 LVDS_UTX3 LVDS_LCLK
39 40 VGA2_WAKE# 209 208
41 5V WAKE# 42 MXM2_PCH_PWROK 211 GND GND 210
100mil(2.5A, 5VIA) 43 5V PWR_GOOD 44 MXM2_PWR_ON
MXM2_PCH_PWROK 21
213 LVDS_UTX2# LVDS_LTX3# 212
45 5V PWR_EN 46 215 LVDS_UTX2 LVDS_LTX3 214
47 5V RSVD 48 217 GND GND 216
49 GND RSVD 50 219 LVDS_UTX1# LVDS_LTX2# 218
51 GND RSVD 52 221 LVDS_UTX1 LVDS_LTX2 220
53 GND RSVD 54 AC_BATT# 223 GND GND 222 +3VMXM
GND PWR_LEVEL AC_BATT# 29 LVDS_UTX0# LVDS_LTX1#
RV415 1 2 0_0402_5%~D 55 56 VGA_TH_OVERT# VGA_TH_OVERT# 29 225 224
RV81 1 2 VGA2_DISABLE# 57 PEX_STD_SW# TH_OVERT# 58 1 2 227 LVDS_UTX0 LVDS_LTX1 226
VGA_DISABLE# TH_ALERT# +3V_MXM1 GND GND
10K_0402_5%~D 59 60 RV416 10K_0402_5%~D 229 228 2 1
61 PNL_PWR_EN TH_PWM 62 231 DP_C_L0# LVDS_LTX0# 230 RV459 10K_0402_5%~D
63 PNL_BL_EN GPIO0 64 233 DP_C_L0 LVDS_LTX0 232 1 @ 2 MXM2_RST#
PNL_BL_PWM GPIO1 GND GND 43 MXM2_EC_RST#
65 66 235 234 RV449 0_0402_5%~D
67 HDMI_CEC GPIO2 68 VGA_SMB_DA2 237 DP_C_L1# DP_D_L0# 236 1 @ 2
DVI_HPD SMB_DAT DP_C_L1 DP_D_L0 21 PCH_GPIO27
69 70 VGA_SMB_CK2 239 238 RV452 0_0402_5%~D
71 LVDS_DDC_DAT SMB_CLK 72 241 GND GND 240
73 LVDS_DDC_CLK GND 74 243 DP_C_L2# DP_D_L1# 242
75 GND OEM 76 MXM_PS_3 245 DP_C_L2 DP_D_L1 244 +3VALW
77 OEM OEM 78 MXM_PS_4 +3VMXM 247 GND GND 246 CV369
79 OEM OEM 80 MXM_PS_5 249 DP_C_L3# DP_D_L2# 248 1 2
@ 81 OEM OEM 82 251 DP_C_L3 DP_D_L2 250
OEM GND GND GND

5
MXM_CUR_DAT RV413 1 2 0_0402_1% VGA_SMB_DA1 29 83 84 253 252 0.1U_0402_25V6K~D

1
1 2 0_0402_1% 85 GND PEX_TX15# 86 255 DP_C_AUX# DP_D_L3# 254 1

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D
MXM_CUR_CLK RV414 @ MXM2_RST#

P
VGA_SMB_CK1 29 PEX_RX15# PEX_TX15 DP_C_AUX DP_D_L3 IN1
87 88 257 256 MXM2_RST# 4
89 PEX_RX15 GND 90 259 RSVD GND 258 O 2
GND PEX_TX14# RSVD DP_D_AUX# PLTRST_VGA# 17,29

G
91 92 261 260 IN2

RV419

RV420

RV421
B 93 PEX_RX14# PEX_TX14 94 263 RSVD DP_D_AUX 262 B

3
95 PEX_RX14 GND 96 265 RSVD DP_C_HPD 264 UV32
GND PEX_TX13# RSVD DP_D_HPD

1
64 MXM1_CUR_VIN+ RV423 1 2 0_0402_5%~D 97 98 @ @ @ MXM_PS_3 267 266 SN74AHC1G08DCKR_SC70-5
99 PEX_RX13# PEX_TX13 100 MXM_PS_4 269 RSVD RSVD 268 RV422
1 1 MXM2 Current Monitor 101 PEX_RX13
GND
GND
PEX_TX12#
102 MXM_PS_5 271 RSVD
RSVD
RSVD
RSVD
270 100K_0402_5%
CV370

CV371

103 104 273 272


105 PEX_RX12# PEX_TX12 106 275 RSVD GND 274 RV444 1 @ 2

2
PEX_RX12 GND RSVD DP_B_L0#

1
UV33 107 108 277 276 0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D
2 2 1 8 B+_MXM1_A1 109 GND PEX_TX11# 110 279 RSVD DP_B_L0 278
1 2 0_0402_5%~D 2 VIN+ A1 7 B+_MXM1_A0 111 PEX_RX11# PEX_TX11 112 281 RSVD GND 280
64 MXM1_CUR_VIN- VIN- A0 PEX_RX11 GND GND DP_B_L1#
RV427 3 6 113 114 283 282

RV424

RV425

RV426
MXM_CUR_DAT
GND SDA GND PEX_TX10# DP_A_L0# DP_B_L1
0.1U_0402_25V6K~D

+3V_MXM1 4 5 MXM_CUR_CLK 115 116 285 284

2
VS SCL 117 PEX_RX10# PEX_TX10 118 287 DP_A_L0 GND 286 +3VALW
PEX_RX10 GND GND DP_B_L2#
0.1U_0402_25V6K~D

INA219AIDCNRG4_SOT23-8 119 120 @ @ @ 289 288 CV372


121 GND PEX_TX9# 122 291 DP_A_L1# DP_B_L2 290 1 2
123 PEX_RX9# PEX_TX9 124 293 DP_A_L1 GND 292

5
125 PEX_RX9 GND 126 295 GND DP_B_L3# 294 0.1U_0402_25V6K~D
127 GND PEX_TX8# 128 297 DP_A_L2# DP_B_L3 296 1

P
PEX_RX8# PEX_TX8 DP_A_L2 GND IN1 MXM2_PCH_PWR_ON 43
129 130 299 298 MXM2_PWR_ON 4
131 PEX_RX8 GND 132 PEG_HTX_C_GRX_N15 301 GND DP_B_AUX# 300 O 2
GND PEX_TX7# PEG_HTX_C_GRX_N15 5 DP_A_L3# DP_B_AUX IN2 VR_ON 29,43

G
5 PEG_GTX_HRX_N15 PEG_GTX_HRX_N15 133 134 PEG_HTX_C_GRX_P15 303 302
PEX_RX7# PEX_TX7 PEG_HTX_C_GRX_P15 5 DP_A_L3 DP_B_HPD
5 PEG_GTX_HRX_P15 PEG_GTX_HRX_P15 135 136 305 304

3
137 PEX_RX7 GND 138 PEG_HTX_C_GRX_N14 307 GND DP_A_HPD 306 UV34
GND PEX_TX6# PEG_HTX_C_GRX_N14 5 DP_A_AUX# 3V3 +3V_MXM1
5 PEG_GTX_HRX_N14 PEG_GTX_HRX_N14 139 140 PEG_HTX_C_GRX_P14 309 308 SN74AHC1G08DCKR_SC70-5
PEX_RX6# PEX_TX6 PEG_HTX_C_GRX_P14 5 DP_A_AUX 3V3
5 PEG_GTX_HRX_P14 PEG_GTX_HRX_P14 141 142 310 80mil(2A)
143 PEX_RX6 GND 144 PEG_HTX_C_GRX_N13 PRSNT_L#
GND PEX_TX5# PEG_HTX_C_GRX_N13 5
5 PEG_GTX_HRX_N13 PEG_GTX_HRX_N13 145 146 PEG_HTX_C_GRX_P13 311 312
PEX_RX5# PEX_TX5 PEG_HTX_C_GRX_P13 5 GND GND
5 PEG_GTX_HRX_P13 PEG_GTX_HRX_P13 147 148 RV445 1 @ 2
149 PEX_RX5 GND 150 PEG_HTX_C_GRX_N12 JAE_MM70-314-310B1-1-R300 0_0402_5%~D
A
+3V_MXM1 GND PEX_TX4# PEG_HTX_C_GRX_N12 5 A
5 PEG_GTX_HRX_N12 PEG_GTX_HRX_N12 151 152 PEG_HTX_C_GRX_P12
PEX_RX4# PEX_TX4 PEG_HTX_C_GRX_P12 5
5 PEG_GTX_HRX_P12 PEG_GTX_HRX_P12 153 154
155 PEX_RX4 GND 156 PEG_HTX_C_GRX_N11

RV428 2 1 10K_0402_5%~D MXM2_PCH_PWROK


5 PEG_GTX_HRX_N11 PEG_GTX_HRX_N11
PEG_GTX_HRX_P11
157
159
GND
PEX_RX3#
PEX_TX3#
PEX_TX3
158
160
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P11
5
5
DELL CONFIDENTIAL/PROPRIETARY
5 PEG_GTX_HRX_P11 PEX_RX3 GND
161
GND Compal Electronics, Inc.
@ RV429 1 2 10K_0402_5%~D VGA2_WAKE# PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
JAE_MM70-314-310B1-1-R300 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, MXMIII Connector (Slave)
@ RV430 1 2 10K_0402_5%~D VGA2_DISABLE# NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-9332P
Date: Friday, December 14, 2012 Sheet 30 of 56
5 4 3 2 1

www.vinafix.vn
5 4 3 2 1

+3VS

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
+3VS

CPU DP Redriver 1 1

CV388

CV389
2 2

12
25
32
36
1
6
UV6
+3VS

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
CPU_MXM_MDP_P0_C 38 23 CPU_MDP_R_P0 CV14 2 1 0.1U_0402_10V6K~D CPU_MDP_R_C_P0
CPU_MXM_MDP_N0_C 39 IN0p OUT0p 22 CPU_MDP_R_N0 CV16 2 1 0.1U_0402_10V6K~D CPU_MDP_R_C_N0
4.7K_0402_5%~D 2 1 RV435 @ DP_PEQ CPU_MXM_MDP_P1_C 41 IN0n OUT0n 20 CPU_MDP_R_P1 CV18 2 1 0.1U_0402_10V6K~D CPU_MDP_R_C_P1
4.7K_0402_5%~D 2 1 RV436 @ DP_CFG1_INPUT CPU_MXM_MDP_N1_C 42 IN1p OUT1p 19 CPU_MDP_R_N1 CV20 2 1 0.1U_0402_10V6K~D CPU_MDP_R_C_N1
4.7K_0402_5%~D 2 1 RV437 @ DP_CFG0 CPU_MXM_MDP_P2_C 44 IN1n OUT1n 17 CPU_MDP_R_P2 CV22 2 1 0.1U_0402_10V6K~D CPU_MDP_R_C_P2
4.7K_0402_5%~D 2 1 RV438 DP_POWER_DOWN# CPU_MXM_MDP_N2_C 45 IN2p OUT2p 16 CPU_MDP_R_N2 CV24 2 1 0.1U_0402_10V6K~D CPU_MDP_R_C_N2
10K_0402_1%~D 2 1 RV431 DP_RST# CPU_MXM_MDP_P3_C 47 IN2n OUT2n 14 CPU_MDP_R_P3 CV26 2 1 0.1U_0402_10V6K~D CPU_MDP_R_C_P3
CPU_MXM_MDP_N3_C 48 IN3p OUT3p 13 CPU_MDP_R_N3 CV28 2 1 0.1U_0402_10V6K~D CPU_MDP_R_C_N3
D IN3n OUT3n D

4.7K_0402_5%~D 2 1 RV432 @ DP_PEQ


4.7K_0402_5%~D 2 1 RV440 @ DP_CFG1_INPUT 3 40 DP_CFG1_INPUT
4.7K_0402_5%~D 2 1 RV441 @ DP_CFG0 I2C_ADDR CFG1 +3VS_DP
4.7K_0402_5%~D 2 1 RV443 @ DP_POWER_DOWN# DP_PEQ 4 46
+3V_MXM DP_CFG0 5 SCL_CTL/PEQ NC
CV487 SDA_CTL/CFG0 35 DP_RST# CV29 2 1 2.2U_0402_6.3V6M~D RV433
0.1U_0402_16V4Z~D RST# DISP_DAT_AUXN_CONN 2 1 100K_0402_5%~D
UV39 1 2 DP_POWER_DOWN# 26 10 CAB_DET_SINK DISP_CLK_AUXP_CONN RV434 1 2 100K_0402_5%~D
SN74AHC1G08DCKR_SC70-5 PD# CAD_SNK

5
4.99K_0402_1% 1 2 RV446 7 11 DISP_HPD_SINK_R
1 REXT HPD_SINK

P
4 IN1 DGPU_PWROK 18,29 8 +3VS
29 VGA_DPC_HPD VGA_DPC_HPD @ T184 PAD~D MDP_CAB_DET
O 2 DP_VGA_HPD_BUF CAD_SRC
IN2

G
DISP_HPD_SINK 9 28 DISP_CLK_AUXP_CONN 2.2K_0402_5%~D 2 1 RV439 PCH_DPC_MDP_DAT
HPD_SRC AUX_SNKP 27 DISP_DAT_AUXN_CONN

3
AUX_SNKN 2.2K_0402_5%~D 2 1 RV442 PCH_DPC_MDP_CLK
DISP_CLKA_AUXP 33
DISP_DATA_AUXN 34 SCL_DDC
2 1 0_0402_5%~D SDA_DDC 22.2U_0402_6.3V6M~D 1 2 CV30
RV655 @ CEXT 15 +3V_MXM
DISP_CLKA_AUXP CV31 2 1 0.1U_0402_10V6K~D DISP_mDP_AUXP_C 30 NC2 21
DISP_DATA_AUXN CV32 2 1 0.1U_0402_10V6K~D DISP_mDP_AUXN_C 29 AUX_SRCP NC3 37 2.2K_0402_5%~D
AUX_SRCN NC4 43 1 @ 2 VGA_DPC_AUXP/DDC
NC5 RV397 2.2K_0402_5%~D
MXM_MFG_SEL GPU Source 1 @ 2 VGA_DPC_AUXN/DDC

GND1
GND2
GND3
EPAD
RV360
VGA_DPC_AUXP/DDC 0 NVDIA
29,31 VGA_DPC_AUXP/DDC
1

1 ATI

18
24
31
49
VGA_DPC_AUXN/DDC RV450 PS8330BQFN48GTR2-A0_QFN48_7X7 Check BOM
29,31 VGA_DPC_AUXN/DDC
100K_0402_5%~D
0308 change to 0402 type
1

QV5A
6 2

RV451 DMN66D0LDW-7_SOT363-6~D
D
100K_0402_5%~D
2
LT7 P/N: SM01000KM00
G DP_MXM_CARD_SEL 43
2

+5VS +3VS
C S waiting to change new symbol C
1

+3VS_DP

0.1U_0402_16V4Z~D
Need apply CIS part
3

D @ FV6

1
+3VS

2.2K_0402_5%~D

2.2K_0402_5%~D
5 +3VS 1 1 2
+3VS

100K_0402_5%~D

CV518

RV668

RV669

22U_0805_6.3V6M~D

0.1U_0402_25V6K~D
G 0.1U_0402_16V4Z~D
1.5A_6V_1206L150PR~D 1 1 1 1

10U_0603_6.3V6M~D

CV375

.1U_0402_16V7K~D
CV376

CV374

CV377
S QV5B
4

RV670
DMN66D0LDW-7_SOT363-6~D 1 UV40

2
CV373

VGA_DPC_AUXN/DDC 2 8
VGA_DPC_AUXP/DDC 5 1A VCC 3 2 2 2 2
1 2A 1B 6

2
2 MDP_CAB_DET# 7 1OE# 2B 4 +3VS
2OE# GND

0.1U_0402_16V4Z~D
CBTD3306PW_TSSOP8
UV36

1
@ D
16,17 PCH_mDP_HPD PCH_mDP_HPD 1 6 DGPU_SELECT# MDP_CAB_DET RV463 1 2 0_0402_5% 2 QV9 1
B2 S
Mini DP CONN

CV378
2 5 G BSS138_SOT23~D
DP_VGA_HPD_BUF 3 GND VCC 4 DISP_HPD_SINK_R CAB_DET_SINK RV464 1 2 0_0402_5% S

3
B1 A
SN74LVC1G3157DCKR_SC70-6 2
UV37
2 1 0_0402_5%~D 0.1U_0402_25V6K~D 2 1 CV379 VGA_DPC_SW_AUXP 6 16
2 1 29,31 VGA_DPC_AUXP/DDC 5 1B1 VCC
VGA_DPC_HPD RV656 @ JMDP1
RV460 100K_0402_5%~D 0.1U_0402_25V6K~D 2 1 CV380 PCH_DPC_AUXP_SW 4 1B2 14 DP_CBL_DET
2 1 17 PCH_mDP_AUXP 3 1B3 S0 2 CONN@
PCH_mDP_HPD PCH_DPC_CLK DGPU_SELECT#
17 PCH_DPC_MDP_CLK 1B4 S1 1
RV453 100K_0402_5%~D DGPU_SEL# Chanel Source
0.1U_0402_25V6K~D 2 1 CV381 VGA_DPC_SW_AUXN 10 7 DISP_CLKA_AUXP 0_0402_5% DISP_HPD_SINK_R 2 GND
29,31 VGA_DPC_AUXN/DDC 11 2B1 1A 9 3 HOT PLUG
0 B1 GPU DISP_DATA_AUXN CPU_MDP_R_C_P0
0.1U_0402_25V6K~D 2 1 CV382 PCH_DPC_AUXN_SW 12 2B2 2A 1 2 CAB_DET_SINK 4 LANE0_P
17 PCH_mDP_AUXN 13 2B3 15 17 DP_CBL_DET 5 CONFIG1
1 B2 CPU PCH_DPC_DAT CPU_MDP_R_C_N0
17 PCH_DPC_MDP_DAT 2B4 2OE 6 LANE0_N
RV454 DISP_CEC
1 8 7 CONFIG2
1OE GND 8 GND
SN74CB3Q3253PWR_TSSOP16 CPU_MDP_R_C_P1 9 GND

CPU/MXM AUX&LANE SW for mDP


+3VS CPU_MDP_R_C_P3 10 LANE1_P
CPU_MDP_R_C_N1 11 LANE3_P
CPU_MDP_R_C_N3 12 LANE1_N
LANE3_N
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

13
14 GND
B
CPU_MDP_R_C_P2 15 GND B
1 1 1 1 LANE2_P
CV383

CV384

CV385

+3VS DISP_CLK_AUXP_CONN 16
AUX_CH_P
CV386

S1 S0 1A 2A Y CPU_MDP_R_C_N2 17 21
DISP_DAT_AUXN_CONN 18 LANE2_N GND1 22
2 2 2 2 19 AUX_CH_N GND2 23
20 GND GND3 24
0 0 1B1 2B1 MXM_AUX +3VS_DP DP_PWR GND4
13
26
1
6

UV38 0 1 1B2 2B2 MXM_DDC JAE_DP3RB20SU32JQR400A


VDD_1
VDD_2
VDD_3
VDD_4

1 0 1B3 2B3 PCH_AUX


29 VGA_DPC_P0 CV33 2 1 0.1U_0402_10V6K~D DISP_C_A0P 42 2 CPU_MXM_MDP_P0_L CV41 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P0_C
CV34 2 1 0.1U_0402_10V6K~D DISP_C_A0N 41 NC0+ COM0+ 3 CPU_MXM_MDP_N0_L CV50 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N0_C
29 VGA_DPC_N0 NC0- COM0- 1 1 1B4 2B4 PCH_DDC
29 VGA_DPC_P1 CV35 2 1 0.1U_0402_10V6K~D DISP_C_A1P 40 4 CPU_MXM_MDP_P1_L CV51 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P1_C RV455
CV36 2 1 0.1U_0402_10V6K~D DISP_C_A1N 39 NC1+ COM1+ 5 CPU_MXM_MDP_N1_L CV52 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N1_C 1 2 DISP_HPD_SINK_R
29 VGA_DPC_N1 NC1- COM1- 1M_0402_5%~D
29 VGA_DPC_P2 CV37 2 1 0.1U_0402_10V6K~D DISP_C_A2P 38 7 CPU_MXM_MDP_P2_L CV53 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P2_C
CV38 2 1 0.1U_0402_10V6K~D DISP_C_A2N 37 NC2+ COM2+ 8 CPU_MXM_MDP_N2_L CV54 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N2_C RV456
29 VGA_DPC_N2 NC2- COM2- 1 2 CAB_DET_SINK
For ATI/Nvidia GPU 29 VGA_DPC_P3 CV39 2 1 0.1U_0402_10V6K~D DISP_C_A3P 36 9 CPU_MXM_MDP_P3_L CV55 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_P3_C 1M_0402_5%~D
CV40 2 1 0.1U_0402_10V6K~D DISP_C_A3N 35 NC3+ COM3+ 10 CPU_MXM_MDP_N3_L CV56 2 1 0.1U_0402_10V6K~D CPU_MXM_MDP_N3_C
29 VGA_DPC_N3 NC3- COM3- RV458
25 11 1 2 DISP_CEC
24 NC4+ COM4+ 12 5.1M_0402_5%
NC4- COM4-
23
22 NC5+
NC5-

8 CPU_mDP_P0 CV42 2 1 0.1U_0402_10V6K~D PCH_DPC_C_P0 34


CV43 2 1 0.1U_0402_10V6K~D PCH_DPC_C_N0 33 NO0+ 14
8 CPU_mDP_N0 NO0- COM5+ 15
CV44 2 1 0.1U_0402_10V6K~D PCH_DPC_C_P1 32 COM5-
8 CPU_mDP_P1 NO1+
8 CPU_mDP_N1 CV45 2 1 0.1U_0402_10V6K~D PCH_DPC_C_N1 31
NO1-
8 CPU_mDP_P2 CV46 2 1 0.1U_0402_10V6K~D PCH_DPC_C_P2 30
CV47 2 1 0.1U_0402_10V6K~D PCH_DPC_C_N2 29 NO2+
For Intel CPU 8 CPU_mDP_N2 NO2-
8 CPU_mDP_P3 CV48 2 1 0.1U_0402_10V6K~D PCH_DPC_C_P3 28 16 DGPU_SELECT#
NO3+ SEL1 DGPU_SELECT# 17,36,42
A
8 CPU_mDP_N3 CV49 2 1 0.1U_0402_10V6K~D PCH_DPC_C_N3 27 17 DGPU_EDIDSEL# RV457 @ 1 2 0_0402_5%~D DGPU_SELECT# A
NO3- SEL2
21
20 NO4+ DGPU_EDIDSEL# 21,36,42
NO4-
19 43 DGPU_SEL# Chanel Source
18 NO5+ EP
NO5-
0 NC GPU
MAX14998ETOLFT 1 NO CPU
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title
Mini DP/Thunder Bolt power

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 31 of 56
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title
eDP SW-CPU & MXM

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 32 of 56
5 4 3 2 1
5 4 3 2 1

LCD POWER

D D
+LCDVDD_3V +LCDVDD_5V
+3VS +LCDVDD_5V +5VS

+LCDVDD_3V UV43
1
VOUT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
10U_0805_10V4Z~D

10U_0805_10V4Z~D
UV42 5
1 VIN
1 1 VOUT 1 1 1 1

CV329

CV328

CV326

CV332

CV333

CV330
5 2
VIN GND 4
SS

2200P_0402_50V7K~D
2 1
2 @ 2 @ GND 4 2 2 2 LCDVDD_EN 3 2
SS EN

2200P_0402_50V7K~D

CV331
1 @ @
3
EN 2

CV327
APL3512ABI-TRG_SOT23-5
2
APL3512ABI-TRG_SOT23-5

RV391
DV16
LCDVDD_ON 0_0402_5%~D 1 2 LCDVDD_EN 2
41,42 LCDVDD_ON 1
0_0402_5%~D 1 2 RV393 3
43 EC_ENVDD
@ BAS40CW_SOT323-3

QV11
B+ FDC654P-G_SSOT-6~D

Back light power 6 80 mil


80 mil
D

+INVPWR_B+
4 5
S

C 2 C
1000P_0402_50V7K~D

1
G

1
1

1
3

RV157 CV93
CV94

100K_0402_5%~D 0.1U_0603_50V4Z~D
2
2
2

PWR_SRC_ON
QV12
SSM3K7002FU_SC70-3~D

1 2 1 3
D

RV158 47K_0402_5%~D
G
2

43 LCD_BKL_EN

FDC654P: P CHANNAL
Panel backlight power control by EC

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title
eDP SW-eDP CONN

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 33 of 56
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
reserved

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 34 of 56
5 4 3 2 1
A B C D E
+3VS
Close to UV35 VCC pins

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D
1 1 1 1

CV210

CV211

CV173

CV209
+3VS 2 2 2 2
+3VS

4.7K_0402_5%~D 2 1 RV305 @ HDMI2_CFG1

11
15
21
33
40
46
UV35 4.7K_0402_5%~D 2 1 RV301 @ HDMI2_CFG0
4.7K_0402_5%~D 2 1 RV309 @ HDMI2_PC0

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
4.7K_0402_5%~D 2 1 RV310 @ HDMI2_PC1
HDMI_IN_CK- 38 4.7K_0402_5%~D 2 1 RV304 @ HDMI2_PC2
HDMI_IN_CK+ 39 IN1p 2.2K_0402_5%~D 2 1 RV312 HDMI_IN_OUT_SDATA
HDMI_IN_D0- 41 IN1n 2.2K_0402_5%~D 2 1 RV302 HDMI_IN_OUT_SCLK
HDMI_IN_D0+ 42 IN2p 4.7K_0402_5%~D 1 2 RV314 @ HDMI2_DDCBUF
1
HDMI_IN_D1- 44 IN2n 23 HDMI_IN_R_CK-
1
IN3p OUT1p HDMI_IN_R_CK- 37
HDMI_IN_D1+ 45 22 HDMI_IN_R_CK+ HDMI_IN_R_CK+ 37
HDMI_IN_D2- 47 IN3n OUT1n 20 HDMI_IN_R_D0-
IN4p OUT2p HDMI_IN_R_D0- 37
HDMI_IN_D2+ 48 19 HDMI_IN_R_D0+

+3VS
IN4n OUT2n
OUT3p
17
16
HDMI_IN_R_D1-
HDMI_IN_R_D1+
HDMI_IN_R_D0+
HDMI_IN_R_D1-
37
37 CONN 4.7K_0402_5%~D
4.7K_0402_5%~D
2
2
1 RV306 @
1 RV311 @
HDMI2_CFG1
HDMI2_CFG0
OUT3n HDMI_IN_R_D1+ 37
2 14 HDMI_IN_R_D2- HDMI_IN_R_D2- 37 4.7K_0402_5%~D 2 1 RV303 @ HDMI2_PC0
+3VS POW OUT4p 13 HDMI_IN_R_D2+ HDMI_IN_R_D2+ 37 4.7K_0402_5%~D 2 1 RV307 @ HDMI2_PC1
OUT4n
1

RV280 37 HDMI_SINK_HPD_RR 30 4.7K_0402_5%~D 2 1 RV308 @ HDMI2_PC2


HPD_SINK 4.7K_0402_5%~D 1 2RV313 @ HDMI2_DDCBUF
100K_0402_5%~D +3VS RV300 1 2 4.7K_0402_5%~D 26
I2C_CTL_EN#
HDMI2_DDCBUF 32 CPU/MXM
2

QV32 NC/DDCBUF_EN#
25 7 HDMI_IN_HPD_R
NC/OE# HPD
1

D
SSM3K7002FU_SC70-3~D

HDMI_SW 2 HDMI_IN_SDATA_R 8
G HDMI_IN_SCLK_R 9 SDA +3VS +5VS
SCL 29 HDMI_DAT
S HDMI_DAT 37
3

HDMI2_CFG1 34 SDAZ 28 HDMI_CLK


SDA_CTL/CFG1 SCLZ HDMI_CLK 37

4.7K_0402_5%~D

4.7K_0402_5%~D
HDMI2_CFG0 35
SCL_CTL/CFG0

2
RV120

RV121
HDMI2_PC0 3
HDMI2_PC1 4 I2C_ADDR0/PC0 @
I2C_ADDR1/PC1
HDMI2_PC2 1

1
GND/PC2
43 HDMI_IN_OUT_DDC HDMI_IN_OUT_DDC
499_0402_1%~D 2 1 RV299 6
REXT 1 RV350 2 0_0402_5%~D HDMI_IN_OUT_HPD
43 HDMI_IN_OUT_HPD_EC

GND10
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
2.2U_0402_6.3V6M~D2 1 CV212 10
CEXT

1
+3VS

100K_0402_5%~D
RV119
PS121QFN48G_QFN48_7X7 +3VS
5
12
18
24
27
31
36
37
43
49

1
100K_0402_5%
RV394

2
1
100K_0402_5%
@ RV353

2
2 2
PS121 CFG0/ CFG1 @

2
3
SCLZ/SDAZ output voltage select;
CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V @
DMN66D0LDW-7_SOT363-6~D 5
PS121 PC0/PC1/PC2 QV34B QV34A
Inputs equalization control, default inputs equalization setting at 12 dB

6
DMN66D0LDW-7_SOT363-6~D
HDMI Input/Output Connector

4
000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB
100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB @
2
+HDMI_5V_OUT
+3VS

1
JHDMI1
HDMI_IN_OUT_HPD 19
HP_DET
0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~D

+5VS 18
+5V
0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~D

1 1 1 HDMI_IN_OUT_DDC 17
DDC/CEC_GND
CV123

CV124

CV125

1 1 1 HDMI_IN_OUT_SDATA 16
SDA
CV119

CV120

CV121

HDMI_IN_OUT_SCLK 15
2.2K_0402_5%~D 2 1 RV368 HDMI_IN_OUT_SDATA RV184 1 2 0_0402_5%~D HDMI_UART_TX 14 SCL
2 2 2 2 1 RV369 37 UART_TX_6038 Reserved
2.2K_0402_5%~D HDMI_IN_OUT_SCLK RV185 1 2 0_0402_5%~D HDMI_UART_RX 13
2 2 2 37 UART_RX_6038 12 CEC 20
HDMI_IN_OUT_TXC-
11 CK- GND 21
HDMI CONN HDMI_IN_OUT_TXC+
HDMI_IN_OUT_TXD0-
10
9
CK_shield GND
CK+ GND
22
23
8 D0- GND
17

30

D0_shield
1

UV11 HDMI_IN_OUT_TXD0+ 7
HDMI_OUT_TXC- 41 2 HDMI_IN_OUT_TXC-_R HDMI_IN_OUT_TXD1- 6 D0+
VCC

VCC

VCC

36 HDMI_OUT_TXC- HDMI_OUT_TXC+ 39 D0+A D0+ 3 HDMI_IN_OUT_TXC+_R 5 D1-


36 HDMI_OUT_TXC+ 38 D0-A D0- 4 D1_shield
HDMI_OUT_TXD0- HDMI_IN_OUT_TXD1+
36 HDMI_OUT_TXD0- 36 D1+A 4 D1+
HDMI_OUT_TXD0+ HDMI_IN_OUT_TXD0-_R 2 0_0402_5%~D @ RV180 1 HDMI_IN_OUT_TXD2- 3
36 HDMI_OUT_TXD0+ 34 D1-A D1+ 5 2 D2-
HDMI_OUT_TXD2- HDMI_IN_OUT_TXD0+_R LV11
36 HDMI_OUT_TXD2- 32 D2+A D1- 1 D2_shield
HDMI_OUT_TXD2+ DLW21SN900HQ2L_0805_4P~D HDMI_IN_OUT_TXD2+
36 HDMI_OUT_TXD2+ HDMI_OUT_TXD1- 29 D2-A 6 HDMI_IN_OUT_TXD2-_R HDMI_IN_OUT_TXD2+_R 2 1 HDMI_IN_OUT_TXD2+ D2+
36 HDMI_OUT_TXD1- 27 D3+A D2+ 7 2 1
HDMI_OUT_TXD1+ HDMI_IN_OUT_TXD2+_R SUYIN_100042GR019M23UZL
36 HDMI_OUT_TXD1+ D3-A D2- CONN@
HDMI_IN_CK- 42 11 HDMI_IN_OUT_TXD1-_R HDMI_IN_OUT_TXD2-_R 3 4 HDMI_IN_OUT_TXD2-
HDMI_IN_CK+ 40 D0+B D3+ 12 HDMI_IN_OUT_TXD1+_R 3 4
HDMI_IN_D0- 37 D0-B D3- 1 2 46@ ROYALTY HDMI W/LOGO
3
HDMI_IN_D0+ 35 D1+B @ RV181 0_0402_5%~D
3

STDP6038 HDMI_IN_D2-
HDMI_IN_D2+
33
31
D1-B
D2+B
Part Number Description

HDMI W/Logo:RO0000002HM
D2-B RO0000002HM
HDMI_IN_D1- 28 @ RV182 1 2 0_0402_5%~D
HDMI_IN_D1+ 26 D3+B LV12
D3-B DLW21SN900HQ2L_0805_4P~D
DVI_SCLK 1 RV289
2 0_0402_5%~D
25 13 1 RV278 2 0_0402_5%~D HDMI_IN_OUT_SCLK HDMI_IN_OUT_TXD1-_R 3 4 HDMI_IN_OUT_TXD1-
DVI_SDATA 1 RV320 23 AUX+A
2 0_0402_5%~D AUX+ 14 1 RV279 2 0_0402_5%~D HDMI_IN_OUT_SDATA 3 4 HDMI_IN_OUT_TXC- CV349 1@ 2 3.3P_0402_50V8C~D
AUX-A AUX-
HDMI_IN_SCLK_R 1 RV321 2 0_0402_5%~D
24 HDMI_IN_OUT_TXD1+_R 2 1 HDMI_IN_OUT_TXD1+ HDMI_IN_OUT_TXC+ CV350 1@ 2 3.3P_0402_50V8C~D
HDMI_IN_SDATA_R 22 AUX+B
1 RV322 2 0_0402_5%~D 2 1
AUX-B 1 2 HDMI_IN_OUT_TXD0- CV351 1@ 2 3.3P_0402_50V8C~D
19 16 1 RV286 2 0_0402_5%~D HDMI_IN_OUT_DDC @ RV183 0_0402_5%~D
18 CECA
HDMI_IN_DET# 1 RV448 2 0_0402_5%~D CEC HDMI_IN_OUT_TXD0+ CV352 1@ 2 3.3P_0402_50V8C~D
CECB
HDMI_SINK_HPD_R 1 RV323 2 0_0402_5%~D21 15 1 RV288 2 0_0402_5%~D HDMI_IN_OUT_HPD @ RV186 1 2 0_0402_5%~D HDMI_IN_OUT_TXD1- CV353 1@ 2 3.3P_0402_50V8C~D
HDMI_IN_HPD_R 20 HPDA
1 RV373 2 0_0402_5%~D HPD LV13
HPDB DLW21SN900HQ2L_0805_4P~D HDMI_IN_OUT_TXD1+ CV354 1@ 2 3.3P_0402_50V8C~D
2 1 8 HDMI_IN_OUT_TXD0+_R 2 1 HDMI_IN_OUT_TXD0+
+3VS EN 2 1
RH273 10K_0402_5%~D HDMI_IN_OUT_TXD2- CV355 1@ 2 3.3P_0402_50V8C~D
HDMI_SW 9
43 HDMI_SW 10 SEL1 43 3 4 1@ 2 3.3P_0402_50V8C~D
HDMI_IN_OUT_TXD0-_R HDMI_IN_OUT_TXD0- HDMI_IN_OUT_TXD2+ CV356
SEL2 GND-PAD 3 4
TS3DV621RUAR_QFN42_9X3P5 SEL OUTPUT 1 2
+5VS @ RV187 0_0402_5%~D 20120531 EMI ADD

+5VS L A
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

@ RV188 1 2 0_0402_5%~D
UV12 1 1
CV126

CV127

@
16
H B @ @
HDMI_IN_OUT_TXC-_R 3
LV14
4 HDMI_IN_OUT_TXC-
HDMI_IN_OUT_SDATA 4 Vcc 3 4
HDMI_IN_OUT_SCLK 7 1A 2 DVI_SDATA 2 2
9 2A 1B1 3 DVI_SDATA 36 2 1
HDMI_IN_OUT_HPD HDMI_IN_SDATA_R HDMI_IN_OUT_TXC+_R HDMI_IN_OUT_TXC+
HDMI_IN_OUT_DDC 12 3A 1B2 5 DVI_SCLK 2 1
4A 2B1 6 DVI_SCLK 36 DLW21SN900HQ2L_0805_4P~D
HDMI_IN_SCLK_R
15 2B2 11 HDMI_SINK_HPD_R 1 2
1 OE# 3B1 10 HDMI_SINK_HPD_R 36
HDMI_SW HDMI_IN_HPD_R @ RV189 0_0402_5%~D
S 3B2 14
4 8 4B1 13 HDMI_IN_DET# 4
GND 4B2 HDMI_IN_DET# 37

Reserve for EMI please close to JHDMI2


SN74CBT3257CPWR_TSSOP16~D
HDMI_IN_OUT_DDC
SSM3K7002FU_SC70-3~D

QV33
1

D
SEL OUTPUT 2 HDMI_IN_OUT_HPD
G Security Classification Compal Secret Data Compal Electronics, Inc.
L B1 S Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
3

HDMI In/Out SW/Connector

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H B2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 35 of 56
A B C D E
5 4 3 2 1

+3VS +3VS +3VS


Close to UV13 VCC pins
RV200 0_0603_5%~D

1
@ RV319 1 24.7K_0402_5%~D HDMI_DDCBUF_EN# 1 2

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D
RV190
@ RV191 1 2 4.7K_0402_5%~D (co-lay) LV15 100K_0402_5%~D 1 1 1 1
+3VS MBK1608221YZF_2P

CV128

CV129

CV130

CV131
@ RV192 1 2 4.7K_0402_5%~D HDMI_DDCBUF HDMI_SW_DETECT RV196 1 2 0_0402_1% 1 2 HDMI_SINK_HPD

2
220P_0402_50V7K~D
@ @ HDMI_OE#
@ RV194 1 2 4.7K_0402_5%~D +3VS 2 2 2 2
1

BAV99-7-F_SOT23-3

CV132

SSM3K7002FU_SC70-3~D
QV17

.1U_0402_16V7K~D

.1U_0402_16V7K~D

DV4 @
@ RV195 1 2 4.7K_0402_5%~D HDMI_CFG_HPD

1
D D D

10U_0603_6.3V6M~D

200K_0402_5%

11
15
21
33
40
46
1 1 1

2
2

CV135
RV197 1 2 4.7K_0402_5%~D 2 UV13

CV133

CV134

RV198
1 3 G

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
RV199 1 2 4.7K_0402_5%~D HDMI_IN2_PEQ S

3
2 2 2 HDMI_TXD2+ 38
RV201 1 2 4.7K_0402_5%~D HDMI_TXD2- 39 IN1p

1
QV16 HDMI_TXD1+ 41 IN1n
RV202 1 2 4.7K_0402_5%~D HDMI_IN1_PEQ HDMI_TXD1- 42 IN2p
+5VS IN2n
SSM3K7002FU_SC70-3~D HDMI_TXD0+ 44 23 HDMI_OUT_TXD2+ HDMI_OUT_TXD2+ 35
HDMI_TXD0- 45 IN3p OUT1p 22 HDMI_OUT_TXD2-
IN3n OUT1n HDMI_OUT_TXD2- 35
HDMI_TXC+ 47 20 HDMI_OUT_TXD1+ HDMI_OUT_TXD1+ 35
DGPU_HPD_INT# HDMI_TXC- 48 IN4p OUT2p 19 HDMI_OUT_TXD1-
Close to UV14 VCC pins
21,39 DGPU_HPD_INT# IN4n OUT2n
OUT3p
17
16
HDMI_OUT_TXD0+
HDMI_OUT_TXD0-
HDMI_OUT_TXD1-
HDMI_OUT_TXD0+
35
35 CONN
OUT3n HDMI_OUT_TXD0- 35
2 14 HDMI_OUT_TXC+ HDMI_OUT_TXC+ 35
+3VS POW OUT4p
PS8271 13 HDMI_OUT_TXC- HDMI_OUT_TXC- 35
HDMI_SINK_HPD_R 30 OUT4n
PEQ=L, Middle level receiving equalization selection 35 HDMI_SINK_HPD_R HPD_SINK
PEQ=H, High level receiving equalization selection +3VS
+3VS RV203 1 2 4.7K_0402_5%~D 26
I2C_CTL_EN#
PEQ=M, Low level receiving equalization selection
UV14 HDMI_DDCBUF_EN# 32
NC/DDCBUF_EN#
PS121 HDMI_OE# 25
NC/OE# HPD
7 HDMI_SINK_HPD
6
When DDCBUF_EN# is HIGH, the DDC channel is disabled, VDD 31 DVI_SDATA_R 8
SCL/SDA and SCLZ/SDAZ are disconnected VDD DVI_SCLK_R 9 SDA
+3VS SCL 29 HDMI_SW_SDA
25 PWDN_ASQ HDMI_CFG1 34 SDAZ 28 HDMI_SW_SCL
GPU_HDMI_TXD2- CV136 2 1 .1U_0402_16V7K~D GPU_HDMI_TXD2-_C 44 PWDN_ASQ HDMI_CFG0 35 SDA_CTL/CFG1 SCLZ
29 GPU_HDMI_TXD2- IN1_D1n SCL_CTL/CFG0
GPU_HDMI_TXD2+ CV137 2 1 .1U_0402_16V7K~D GPU_HDMI_TXD2+_C 45 28 HDMI_CFG_HPD
29 GPU_HDMI_TXD2+ IN1_D1p CFG_HPD
GPU_HDMI_TXD1- CV138 2 1 .1U_0402_16V7K~D GPU_HDMI_TXD1-_C 47 RV204 HDMI_PC0 3
29 GPU_HDMI_TXD1- IN1_D2n I2C_ADDR0/PC0
GPU_HDMI_TXD1+ CV139 2 1 .1U_0402_16V7K~D GPU_HDMI_TXD1+_C 48 40 HDMI_DDCBUF 4.7K_0402_5%~D HDMI_PC1 4
MXM 29
29
GPU_HDMI_TXD1+
GPU_HDMI_TXD0-
GPU_HDMI_TXD0- CV140 2 1 .1U_0402_16V7K~D GPU_HDMI_TXD0-_C 1 IN1_D2p
IN1_D3n
DDCBUF
PRE_EMI
34 @1 2 I2C_ADDR1/PC1
GPU_HDMI_TXD0+ CV141 2 1 .1U_0402_16V7K~D GPU_HDMI_TXD0+_C 2 7 HDMI_PC2 1
29 GPU_HDMI_TXD0+ IN1_D3p RTERM GND/PC2

2
GPU_HDMI_TXC- CV142 2 1 .1U_0402_16V7K~D GPU_HDMI_TXC-_C 4
29 GPU_HDMI_TXC- IN1_D4n
GPU_HDMI_TXC+ CV143 2 1 .1U_0402_16V7K~D GPU_HDMI_TXC+_C 5 RV399
29 GPU_HDMI_TXC+ IN1_D4p 2 1 RV205 6
4.7K_0402_5%~D 499_0402_1%~D
@ REXT

GND10
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
2.2U_0402_6.3V6M~D2 1 CV144 10

1
C
CEXT C

CPU_HDMI_N2 CV145 1 2 .1U_0402_16V7K~D CPU_HDMI_N2_C 8 PS121QFN48G_QFN48_7X7

5
12
18
24
27
31
36
37
43
49
8 CPU_HDMI_N2 1 2 9 IN2_D1n
CPU_HDMI_P2 CV146 .1U_0402_16V7K~D CPU_HDMI_P2_C
8 CPU_HDMI_P2 CPU_HDMI_N1 1 2 CPU_HDMI_N1_C 11 IN2_D1p
CV147 .1U_0402_16V7K~D
8 CPU_HDMI_N1 1 2 12 IN2_D2n 36
CPU_HDMI_P1 CV148 .1U_0402_16V7K~D CPU_HDMI_P1_C HDMI_TXD2-
CPU 8
8
CPU_HDMI_P1
CPU_HDMI_N0
CPU_HDMI_N0 CV149 1 2 .1U_0402_16V7K~D CPU_HDMI_N0_C 13 IN2_D2p
IN2_D3n
OUT_D1n
OUT_D1p
35 HDMI_TXD2+
CPU_HDMI_P0 CV150 1 2 .1U_0402_16V7K~D CPU_HDMI_P0_C 14 33 HDMI_TXD1-
8 CPU_HDMI_P0 1 2 16 IN2_D3p OUT_D2n 32
CPU_HDMI_N3 CV151 .1U_0402_16V7K~D CPU_HDMI_N3_C HDMI_TXD1+ PS121 CFG0/ CFG1
8 CPU_HDMI_N3 CPU_HDMI_P3 1 2 CPU_HDMI_P3_C 17 IN2_D4n OUT_D2p 30 HDMI_TXD0-
CV152 .1U_0402_16V7K~D
8 CPU_HDMI_P3 IN2_D4p OUT_D3n 29 HDMI_TXD0+ SCLZ/SDAZ output voltage select;
OUT_D3p 27 HDMI_TXC- CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V
OUT_D4n 26 HDMI_TXC+
OUT_D4p PS121 PC0/PC1/PC2
Inputs equalization control, default inputs equalization setting at 12 dB
29 VGA_HDMI_DET 46
IN1_HPD
000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB
17 PCH_HDMI_HPD 10 100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB
GPU_HDMI_SCLK 41 IN2_HPD
29 GPU_HDMI_SCLK 42 IN1_SCL
GPU_HDMI_SDATA
29 GPU_HDMI_SDATA PCH_DPB_HDMI_CLK 19 IN1_SDA
17 PCH_DPB_HDMI_CLK IN2_SCL
PCH_DPB_HDMI_DAT 20 +3VS
17 PCH_DPB_HDMI_DAT IN2_SDA
+3VS DGPU_EDIDSEL#_R 22 39 HDMI_SW_DETECT 4.7K_0402_5%~D 2 1 RV315 @ PWDN_ASQ
DGPU_SEL# 21 SW_DDC OUT_HPD 38 HDMI_SW_SCL 4.7K_0402_5%~D 2 1 RV206 @ HDMI_CFG1
2.2K_0402_5%~D 2 1 RV207 PCH_DPB_HDMI_DAT SW_MAIN OUT_SCL 37 HDMI_SW_SDA 4.7K_0402_5%~D 2 1 RV208 @ HDMI_CFG0
OUT_SDA 4.7K_0402_5%~D 2 1 RV209 HDMI_PC0
2.2K_0402_5%~D 2 1 RV210 PCH_DPB_HDMI_CLK HDMI_IN1_PEQ 3 4.7K_0402_5%~D 2 1 RV211 @ HDMI_PC1
HDMI_IN2_PEQ 15 IN1_PEQ 4.7K_0402_5%~D 2 1 RV212 HDMI_PC2
IN2_PEQ 2.2K_0402_5%~D 2 1 RV213 HDMI_SW_SDA
2.2K_0402_5%~D 2 1 RV214 HDMI_SW_SCL
23
24 CEXT
+3V_MXM REXT
2.2U_0603_10V7K~D

4.7K_0402_5%~D 2 1 RV215 @ HDMI_CFG1


1
CV153

2.2K_0402_5%~D 2 1 RV216 GPU_HDMI_SDATA 1 4.7K_0402_5%~D 2 1 RV217 @ HDMI_CFG0


499_0402_1%~D

RV218

18 4.7K_0402_5%~D 2 1 RV219 @ HDMI_PC0


2.2K_0402_5%~D 2 1 RV220 GPU_HDMI_SCLK 43 GND 4.7K_0402_5%~D 2 1 RV221 @ HDMI_PC1
49 GND 4.7K_0402_5%~D 2 1 RV222 @ HDMI_PC2
2 PAD 4.7K_0402_5%~D 2 1 RV316 @ PWDN_ASQ
2

PS8271QFN48GTR-A1_QFN48_7X7
B B

8/25 change RV218from 430 to


+3VS 499ohm HDMI_SW_DET 0 1
CV154 @ +HDMI_5V_OUT
2 1
Y IN1 IN2
0.01U_0402_16V7K~D
5

1
1.5K_0402_5%

RV223

1.5K_0402_5%

RV224
1
P

21,31,42 DGPU_EDIDSEL# IN1 4 DGPU_EDIDSEL#_R MXM PCH


2 O
IN2
G

UV15 @
3

2
SN74AHC1G08DCKR_SC70-5
DVI_SDATA_R DVI_SDATA DVI_SDATA 35
DVI_SCLK_R DVI_SCLK DVI_SCLK 35
DGPU_EDIDSEL# 0_0402_5%~D 2 1 RV227 DGPU_EDIDSEL#_R 39
+5VS +HDMI_5V_OUT

UV41 3
OUT
W=40mils 1
IN
1U_0603_10V6K~D

1U_0603_10V4Z~D

2 1
GND
@

1
CV158

CV157

AP2330W-7_SC59-3 2
2

@ +3VS
CV159
2 1

A 0.01U_0402_16V7K~D @ A
5

1
P

17,31,42 DGPU_SELECT# IN1 4 DGPU_SEL#


2 O
IN2
G

UV16
3

SN74AHC1G08DCKR_SC70-5

DGPU_SELECT# 0_0402_5%~D 2 1 RV229 DGPU_SEL#


Security Classification Compal Secret Data Compal Electronics, Inc.
DGPU_SEL# 39 Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
HDMI SW-CPU & MXM/Re-driver

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 36 of 56
5 4 3 2 1
5 4 3 2 1

+3.3VS_AVDD +3.3V_AVDD_LVTX +1.2VS_HDMI +1.2V_AVDD +3.3V_DDVDD


+3VS +3.3VS_AVDD
LV16 LV17 LV18 +3VS +5VS +1.2VS_HDMI @ +1.2VS
1 2 1 2 1 2 LV19 RV230 1 2 10K_0402_5%~D BS_I2C_DEV_ID2

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0402_16V4Z~D

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
BLM18BD601SN1D_0603~D BLM18BD601SN1D_0603~D BLM18BD601SN1D_0603~D RV231 1 2 100K_0402_5%~D 2 1

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
1 2 2 2 2 1 2 2 2 2 BLM18AG601SN1D_0603~D RV232 1 2 10K_0402_5%~D BS_I2C_DEV_ID1

CV160

1U_0402_6.3V6K~D
CV161

CV162

CV163

CV166

CV167

CV168

CV169
2 2 2

CV164

CV165

.1U_0402_16V7K~D
RV233 1 2 10K_0402_5%~D BS_I2C_DEV_ID0

CV170

CV171

CV172
1

CV174

10K_0402_5%~D
0_0402_5%~D
Can not place large capacitor to 1.2V

1
2 1 1 1 1 2 1 1 1 1

CV175
RV234
UV17 RV235 1 2 10K_0402_5%~D BS_UART_FUNCTION_SEL
prevent pulse happened when LVDS 1 1 1 TDC 0.52A

RV236
power switch off/on Peak Current 0.73A 2 4 5 RV237 1 2 10K_0402_5%~D BS_RESERVED_R

2
VDD NC
OCP current 3.5A

2
3 6 RV238 1 2 10K_0402_5%~D BS_SPI_R

2
D +3VS +3.3V_DDVDD VIN VOUT D

2 7 RV239 1 2 10K_0402_5%~D BS_I2C_SRC_R

10U_0805_4VAM~D
1 EN ADJ

CV176
LV21
+1.2VS_HDMI +1.2V_DVDD

20K_0402_5%~D
1 2 1 8 RV240 1 2 10K_0402_5%~D BS_I2C_ON_R
PGOOD GND

1
22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
BLM18BD601SN1D_0603~D +3.3VS_AVDD 9
+3.3V_AVDD_RPLL 2 GND

RV241
1 2 2 2 LV22 RV242 1 2 10K_0402_5%~D BS_EXTKEY_EN
LV23 1 2 APE8902CMP-A HDMI_SPI_CLK_R
CV178

CV179

CV180
CV177

1 2 BLM18AG601SN1D_0603~D

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

22U_0805_6.3VAM~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

15_0402_5%~D 15P_0402_50V8J~D
BLM18BD601SN1D_0603~D RV243 1 2 10K_0402_5%~D BS_OCM_BOOT_SEL

1
2 1 1 1

@ RV244
1 2 1 2 2 2 2 2 2
RV245 1 2 10K_0402_5%~D BS_INTERFACE_SEL1

CV182

CV184

CV185

CV186

CV187

CV188

CV189
CV181

CV183
AVDD_RPLL pin10 C610 0.1uF
RV246 1 2 10K_0402_5%~D BS_INTERFACE_SEL0
to AVSS_RPLL pin7 2 1 2 1 1 1 1 1 1
Close to respective power Pins

2
RV247 1 2 10K_0402_5%~D BS_XTAL_TCLK_SEL
1

@
RV248 1 2 10K_0402_5%~D BS_OSC_SEL

CV190
RV249 1 2 10K_0402_5%~D HDMI_IN_AUD_CODEC
2

+3.3V_DDVDD

2Mbit

.1U_0402_16V7K~D
RV250 1 2 22_0402_5% EC_HDMI_CLK 2
+3.3V_AVDD_RPLL 43 EC_SMB_CK2_R
RV251 1 2 22_0402_5% EC_HDMI_DAT

CV191
SPI ROM
43 EC_SMB_DA2_R
10P_0402_50V8J~D

10P_0402_50V8J~D

UV1
10 116 RV252 1
+3.3V_AVDD_RPLL VDDA_3V3 CVDD_12 +1.2V_DVDD
1 108 15_0402_5%~D UV18
CVDD_12 46 HDMI_SPI_CS# 2 1 HDMI_SPI_CS#_R 1 8
1 CVDD_12 S# VCC
CV192

CV193

35 HDMI_SPI_SO 1 2 HDMI_SPI_SO_R 2 7 10K_0402_5%~D 2 1 RV254


11 CVDD_12 RV253 1 2 15_0402_5%~D 3 Q RESET# 6 HDMI_SPI_CLK_R 15_0402_5%~D 1 2 RV256 HDMI_SPI_CLK
2 +3.3V_AVDD_LVTX AVDD_OUT_33 +3.3V_DDVDD W# C
23 88 RV255 10K_0402_5%~D 4 5 HDMI_SPI_SI_R 15_0402_5%~D 1 2 RV257 HDMI_SPI_SI
YV1 2 AVDD_OUT_33 ADC_DVDD_1V2 VSS D
TCLK 1 3 XTAL 50 MX25L2006EM1I-12G_SOP8
2 4 DPRX_VDDD_1V2
G1 G2 80 64
C C
+3.3VS_AVDD HDMI_VDDA_3V3 DPRX_VDDA_1V2 +1.2V_AVDD +3.3V_DDVDD
27MHZ_10PF_X3S027000BA1H-U~D 86 58
90 HDMI_VDDA_3V3 DPRX_VDDA_1V2 52 +3.3V_DDVDD
100 ADC_AVDD_3V3 DPRX_VDDA_1V2
ADC_AVDD_3V3

16KBit
6
VDDA_1V2

4.7K_0402_1%~D

0.1U_0402_16V4Z~D

4.7K_0402_1%~D

4.7K_0402_1%~D
38 1
+3.3V_DDVDD RVDD_33

NVRAM

1
+3.3V_DDVDD

@
109
RVDD_33

RV258

CV194

RV259

RV260
128
RVDD_33
2
2.2K_0402_5%~D 4700P_0402_25V7K~D

33 LVDS_6038_TXOUT0- LVDS_6038_TXOUT0- 42
O_CH0N_LV / TTL_D29 / GPIO_67
2

32 LVDS_6038_TXOUT0+ LVDS_6038_TXOUT0+ 42 UV19

2
O_CH0P_LV / TTL_D28 / GPIO_66
RV261

XTAL 8 31 LVDS_6038_TXOUT1- LVDS_6038_TXOUT1- 42 1 8


TCLK 9 XTAL O_CH1N_LV / TTL_D27 / GPIO_65 30 LVDS_6038_TXOUT1+ 2 E0 VCC 7
TCLK O_CH1P_LV / TTL_D26 / GPIO_64 LVDS_6038_TXOUT1+ 42 E1 WC
29 LVDS_6038_TXOUT2- LVDS_6038_TXOUT2- 42 3 6 RV262 1 2 22_0402_5% DHMI_IN_NV_CLK_R
36 O_CH2N_LV / TTL_D25 / GPIO_63 28 LVDS_6038_TXOUT2+ 4 E2 SCL 5 RV263 1 2 22_0402_5% DHMI_IN_NV_DAT_R
LVDS_6038_TXOUT2+ 42
1

NC O_CH2P_LV / TTL_D24 / GPIO_62 27 LVDS_6038_TXCLK- VSS SDA


O_CLKN_LV / TTL_D23 / GPIO_61 LVDS_6038_TXCLK- 42
HDMI_RST# 4 26 LVDS_6038_TXCLK+ LVDS_6038_TXCLK+ 42 CAT24C16WI-GT3_SO8
RV264 1 2 10K_0402_5%~D 125 RESETn O_CLKP_LV / TTL_D22 / GPIO_60 25
STI_TM2 O_CH3N_LV / TTL_D21 / GPIO_59 24
CV195 1 2 0.1U_0402_16V4Z~D 92 O_CH3P_LV / TTL_D20 / GPIO_58
1 ADC_A_N LVDS
CV197

CV196 1 2 0.1U_0402_16V4Z~D 93 21 LVDS_6038_TZOUT0- +HDMI_5V_OUT +5VS


ADC_A_P E_CH0N_LV / TTL_D19 / GPIO_57 LVDS_6038_TZOUT0- 42
CV198 1 2 0.1U_0402_16V4Z~D 95 20 LVDS_6038_TZOUT0+ LVDS_6038_TZOUT0+ 42
CV199 1 2 0.1U_0402_16V4Z~D 96 ADC_B_N E_CH0P_LV / TTL_D18 / GPIO_56 19 LVDS_6038_TZOUT1-
2 ADC_B_P E_CH1N_LV / TTL_D17 / GPIO_55 LVDS_6038_TZOUT1- 42
CV200 1 2 0.1U_0402_16V4Z~D 98 18 LVDS_6038_TZOUT1+ LVDS_6038_TZOUT1+ 42 2 1 1 2
CV201 1 2 0.1U_0402_16V4Z~D 99 ADC_C_N E_CH1P_LV / TTL_D16 / GPIO_54 17 LVDS_6038_TZOUT2- DV8 2 1 1 2
ADC_C_P E_CH2N_LV / TTL_D15 / GPIO_53 LVDS_6038_TZOUT2- 42
CV202 1 2 0.1U_0402_16V4Z~D 105 16 LVDS_6038_TZOUT2+ LVDS_6038_TZOUT2+ 42 1SS355TE-17_SOD323-2 DV9 1SS355TE-17_SOD323-2
CV203 1 2 0.1U_0402_16V4Z~D 106 HSYNC_IN E_CH2P_LV / TTL_D14 / GPIO_52 15 LVDS_6038_TZCLK- +5VS_HDMI_IN_EDID
VSYNC_IN E_CLKN_LV / TTL_D13 / GPIO_51 LVDS_6038_TZCLK- 42
14 LVDS_6038_TZCLK+ LVDS_6038_TZCLK+ 42 1
+3.3V_DDVDD 1 2 +3.3V_DDVDD 70 E_CLKP_LV / TTL_D12 / GPIO_50 13
VEDID_VDD_3V3 E_CH3N_LV / TTL_D11 / GPIO_49

4.7K_0402_1%~D

4.7K_0402_1%~D

4.7K_0402_1%~D
CV204 0.1U_0402_16V4Z~D 12 CV205
E_CH3P_LV / TTL_D10 / GPIO_48

1
EC_HDMI_DAT 71 EDID_WP 0.1U_0402_16V4Z~D
A_I2C_SDA
1

MMST3904-7-F_SOT323-3~D

RV265

RV266

RV267
EC_HDMI_CLK 72
4.7K_0402_5%~D HDMI_SW_DAT 73 A_I2C_SCL
HDMI_SW_CLK 74 D1_I2C_SDA / GPIO_28 3 HDMI_IN_BKL_EN
D1_I2C_SCL / GPIO_29 PBIAS / TTL_D9 / GPO_4 HDMI_IN_BKL_EN 42

1
RV418 44 2 HDMI_IN_ENVDD C
HDMI_IN_ENVDD 42

2
45 D2_I2C_SDA / GPIO_24 PPOWER / TTL_D8 / GPO_3 1 2 2 UV20
43 HDMI_IN_EN
1 2

D2_I2C_SCL / GPIO_25

QV18
RV268 22_0402_5% B 1 8
111 1 BS_OCM_BOOT_SEL E 2 E0 VCC 7 RV269 1 2 22_0402_5% EDID_WP

3
4.7K_0402_5%~D PAD~D T60 @ 112 GPIO_44 / S_I2C_SCL GPO_2 / TTL_D7 / PWM2(BS_OCM_BOOT_SEL) 127 HDMI_IN_AUD_CODEC RV270 1 2 0_0402_1% 3 E1 WC 6 HDMI_SW_CLK RV271 1 2 22_0402_5% HDMI_CLK
GPIO_43 / S_I2C_SDA STI_TM1 / PWM1 / TTL_D6 / GPO_1 HDMI_IN_AUDIO_CODEC 45 E2 SCL HDMI_CLK 35
@ PAD~D T58 @ 126 HDMI_IN_PWM @ 4 5 HDMI_SW_DAT RV272 1 2 22_0402_5% HDMI_DAT
B GPO_0 / PWM0 / TTL_D5(BS_OSC_SEL) HDMI_IN_PWM 42 VSS SDA HDMI_DAT 35 B
RV447 124 BS_I2C_DEV_ID2
48 TTL_D4 / GPIO_21(BS_I2C_DEV_ID2) 123 BS_I2C_DEV_ID1 RV273 1 2 0_0402_1% BS_OSC_SEL CAT24C02WI-GT3A_SO8
2

49 DPRX_AUXN TTL_D3 / GPIO_20(BS_I2C_DEV_ID1) 122 BS_I2C_DEV_ID0 @ RV298 1 2 0_0402_5%~D


53 DPRX_AUXP TTL_D2 / GPIO_19(BS_I2C_DEV_ID0) 121 1 2 0_0402_1% DHMI_IN_NV_CLK +3.3V_DDVDD HDMI_IN_DET# 35
DHMI_IN_NV_CLK_R 2Kbit
54 DPRX_ML_L0P TTL_D1 / GPIO18 / M_I2C_SCL 120 DHMI_IN_NV_CLK 42
DHMI_IN_NV_DAT_R RV395 1 @ 2 0_0402_1% DHMI_IN_NV_DAT
DPRX_ML_L0N TTL_D0 / GPIO17 / M_I2C_SDA DHMI_IN_NV_DAT 42

10K_0402_5%~D
56 RV396 @ 2011/11/25 remove LVDS conn
DPRX_ML_L1P HDMI_IN_CAB_DET# 43

2KBit

1
57 RV274 1 2 BS_XTAL_TCLK_SEL
DPRX_ML_L1N

RV275
59 @ 0_0402_1%
+1.2V_AVDD 60 DPRX_ML_L2P
62 DPRX_ML_L2N 119 BS_EXTKEY_EN +HDMI_5V_OUT
63 DPRX_ML_L3P TTL_CKOUT / GPIO16(BS_EXTKEY_EN) 118 UART_TX_6038

2
1 2 51 DPRX_ML_L3N UART_TX / TTL_SYNC1 / GPO_7(BS_XTAL_TCLK_SEL) 117 UART_TX_6038 35
UART_RX_6038
43 DPRX_REXT UART_RX / TTL_SYNC2 / GPO_6 UART_RX_6038 35 2 1HDMI_IN_CAB_DET#
RV276 300_0402_1% HDMI_PLUG_IN_CAB_DET
DPRX_HPD_OUT / GPO_5 RV277 33K_0402_5%

.1U_0402_16V7K~D
5 1
VBUFC_RPLL

1
D

CV206
35 HDMI_IN_R_CK- HDMI_IN_R_CK- RV281 1 @ 2 0_0402_1% HDMI_IN_CK-_R 75 @ @
HDMI_RXCN

100K_0402_5%~D
35 HDMI_IN_R_CK+
HDMI_IN_R_CK+ RV284 1 @ 2 0_0402_1% HDMI_IN_CK+_R 76 QV19 2
HDMI_IN_R_D0- RV287 1 @ 2 0_0402_1% HDMI_IN_D0-_R 78 HDMI_RXCP SSM3K7002FU_SC70-3~D G
35 HDMI_IN_R_D0- HDMI_RX0N

1
2

RV285
HDMI_IN_R_D0+ RV290 1 @ 2 0_0402_1% HDMI_IN_D0+_R 79 S

3
35 HDMI_IN_R_D0+ HDMI_RX0P
HDMI_IN_R_D1- RV292 1 @ 2 0_0402_1% HDMI_IN_D1-_R 81 RPV1
35 HDMI_IN_R_D1- HDMI_RX1N +5VS +HDMI_5V_OUT
HDMI_IN_R_D1+ RV387 1 @ 2 0_0402_1% HDMI_IN_D1+_R 82 103 1 8
35 HDMI_IN_R_D1+
HDMI_IN_R_D2- RV388 1 @ 2 0_0402_1% HDMI_IN_D2-_R 84 HDMI_RX1P HDMI LBADC_IN4 / GPIO_35 104 HDMI_PLUG_IN_CAB_DET 2 7
35 HDMI_IN_R_D2- HDMI_RX2N LBADC_IN3 / GPIO_34
HDMI_IN_R_D2+ RV390 1 @ 2 0_0402_1% HDMI_IN_D2+_R 85 101 3 6

2
35 HDMI_IN_R_D2+ HDMI_RX2P LBADC_IN2 / GPIO_33 / TTL_SYNC4

2
+3.3VS_AVDD RV291 1 2 249_0402_1%~D 87 102 4 5
HDMI_REXT LBADC_IN1 / GPIO_32 / TTL_SYNC3

0.1U_0402_16V4Z~D
HDMI_IN_SW_HPD 113 RV283
HDMI_HPD / GPIO_22

2
114 10K_8P4R_5% 1
HDMI_CEC / GPIO_23 1K_0402_1%~D

CV207
110 RV282
GPIO_45 HDMI_TOGGLE 43 4.7K_0402_5%~D

1
2

MMST3904-7-F_SOT323-3~D
45 I2S_DAT/SPDIF_IN @ RV293 1
@RV293 20_0402_5%~D BS_RESERVED_R 39

1
BS_SPI_R 40 I2S_0 (S/PDIF) / GPO_12(BS_RESERVED) HDMI_IN_HPD_RR
41 I2S_AUMCLK / GPO_13(BS_SPI_FUN_SEL) 7 HDMI_SINK_HPD_RR 35
BS_I2C_SRC_R UART_RX_6038
BS_I2C_ON_R 42 I2S_WS / GPO_14(BS_I2C_SRC_SEL) VSSA_33
I2S_SCLK / GPO_15(BS_I2C_ON_SPI_EN)

1
QV20
34 LV24 C
HDMI_SPI_CS# 65 LVVSS 22 HDMI_IN_SW_HPD 2 1 HDMI_IN_HPD 1 2 2
SPI_CSn / IRQ_IN / GPO_8 LVVSS

220P_0402_50V7K~D
BS_INTERFACE_SEL1 RV295 1 @ 2 0_0402_1% HDMI_SPI_CLK 66 MBK1608221YZF_2P 22_0402_5% RV294 B
BS_INTERFACE_SEL0 RV296 1 @ 2 0_0402_1% HDMI_SPI_SO 67 SPI_CLK / GPO_9(BS_INTERFACE_SEL1) 115 E
1

3
SPI_DI / GPO_10(BS_INTERFACE_SEL0) CRVSS
1

A BS_UART_FUNCTION_SEL RV297 1 @ 2 HDMI_SPI_SI 68 107 A


SPI_DO / GPO_11(BS_UART_FUNCTION_SEL) CRVSS

CV208
0_0402_1% 69
47 CRVSS 37
55 DPRX_VSSD CRVSS BAV99-7-F_SOT23-3 2
61 DPRX_VSSA DV10 @
DPRX_VSSA 97
3

77 ADC_VSSA 94
83 HDMI_VSSA ADC_VSSA 91 +HDMI_5V_OUT
HDMI_VSSA ADC_VSSA 89
ADC_VSSD
STDP6038-AC_PQFP128_20X14~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title
HDMI to LVDS-STDP6038

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 37 of 56
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title
LVDS to eDP-STDP4028

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 38 of 56
5 4 3 2 1
5 4 3 2 1

+3VS

PCH_DPD_CLK RV30 2 1 2.2K_0402_5%~D


PCH_DPD_DAT RV31 2 1 2.2K_0402_5%~D
+3VMXM DMC_PWDN @ RV324 1 2 4.7K_0402_5%~D
DMC_CFG_HPD @ RV325 1 2 4.7K_0402_5%~D
DMC_DDCBUF @ RV326 1 2 4.7K_0402_5%~D
1 2 VGA_DPD_AUXP/DDC +3VS DMC_PRE_EMI @ RV328 1 2 4.7K_0402_5%~D
RV327 2.2K_0402_5%~D DMC_IN1_PEQ @ RV329 1 2 4.7K_0402_5%~D
1 2 VGA_DPD_AUXN/DDC DMC_IN2_PEQ @ RV331 1 2 4.7K_0402_5%~D
RV330 2.2K_0402_5%~D
DMC_PWDN @ RV332 1 2 4.7K_0402_5%~D

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~D
DMC_CFG_HPD @ RV333 1 2 4.7K_0402_5%~D

PCH/GPU AUX&LANE SW for DPB 1 2 DMC_DDCBUF @ RV334 1 2 4.7K_0402_5%~D

CV245

CV246
DMC_PRE_EMI @ RV335 1 2 4.7K_0402_5%~D
DMC_IN1_PEQ @ RV336 1 2 4.7K_0402_5%~D
D D
DMC_IN2_PEQ @ RV337 1 2 4.7K_0402_5%~D
UV21 2 1

6
VDD 31
VDD

25 DMC_PWDN
CV247 1 2 0.1U_0402_10V6K~D VGA_DPD_SW_P0 44 PWDN_ASQ
29 VGA_DPD_P0 1 2 45 IN1_D1n 28
CV248 0.1U_0402_10V6K~D VGA_DPD_SW_N0 DMC_CFG_HPD
29 VGA_DPD_N0 1 2 47 IN1_D1p CFG_HPD
CV249 0.1U_0402_10V6K~D VGA_DPD_SW_P1
29 VGA_DPD_P1 1 2 48 IN1_D2n 40
CV250 0.1U_0402_10V6K~D VGA_DPD_SW_N1 DMC_DDCBUF
MXM 29
29
VGA_DPD_N1
VGA_DPD_P2
CV251 1 2 0.1U_0402_10V6K~D VGA_DPD_SW_P2 1 IN1_D2p
IN1_D3n
DDCBUF
PRE_EMI
34 DMC_PRE_EMI
CV252 1 2 0.1U_0402_10V6K~D VGA_DPD_SW_N2 2 7
29 VGA_DPD_N2 1 2 4 IN1_D3p RTERM
CV253 0.1U_0402_10V6K~D VGA_DPD_SW_P3
29 VGA_DPD_P3 1 2 5 IN1_D4n
CV254 0.1U_0402_10V6K~D VGA_DPD_SW_N3
29 VGA_DPD_N3 IN1_D4p

CV255 1 2 0.1U_0402_16V4Z~D CPU_DPD_SW_P0 8 +3VS


8 CPU_DPD_DMC_P0 1 2 CPU_DPD_SW_N0 9 IN2_D1n
CV256 0.1U_0402_16V4Z~D Close to UV22 VCC pins
8 CPU_DPD_DMC_N0 1 2 11 IN2_D1p
CV257 0.1U_0402_16V4Z~D CPU_DPD_SW_P1
8 CPU_DPD_DMC_P1 1 2 12 IN2_D2n 36 1 2
CV258 0.1U_0402_16V4Z~D CPU_DPD_SW_N1 DMC_SW_P0 RV338 @ 0_0402_1% DP_DMC_ML0P
CPU88 CPU_DPD_DMC_N1 IN2_D2p OUT_D1n

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D
CV259 1 2 0.1U_0402_10V7K~D CPU_DPD_SW_P2 13 35 DMC_SW_N0 RV339 1 @ 2 0_0402_1% DP_DMC_ML0N
CPU_DPD_DMC_P2 1 2 14 IN2_D3n OUT_D1p 33 1 2
CV260 0.1U_0402_10V7K~D CPU_DPD_SW_N2 DMC_SW_P1 RV340 @ 0_0402_1% DP_DMC_ML1P 1 1 1 1
8 CPU_DPD_DMC_N2 1 2 CPU_DPD_SW_P3 16 IN2_D3p OUT_D2n 32 DMC_SW_N1 RV341 1 2 DP_DMC_ML1N
CV261 0.1U_0402_10V7K~D @ 0_0402_1%
8 CPU_DPD_DMC_P3 IN2_D4n OUT_D2p

CV263

CV264

CV265

CV266
CV262 1 2 0.1U_0402_10V7K~D CPU_DPD_SW_N3 17 30 DMC_SW_P2 RV342 1 @ 2 0_0402_1% DP_DMC_ML2P
8 CPU_DPD_DMC_N3 IN2_D4p OUT_D3n 29 1 2
DMC_SW_N2 RV343 @ 0_0402_1% DP_DMC_ML2N
OUT_D3p 27 DMC_SW_P3 RV344 1 @ 2 0_0402_1% DP_DMC_ML3P +3VS 2 2 2 2
OUT_D4n 26 DMC_SW_N3 RV345 1 @ 2 0_0402_1% DP_DMC_ML3N
OUT_D4p
RV346

11
15
21
33
40
46
29 VGA_DMC_HPD 2 1 10K_0402_5%~D VGA_DMC_HPD_R 46 UV22
2 1 10K_0402_5%~D PCH_DMC_HPD_R 10 IN1_HPD

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
17 PCH_DMC_HPD IN2_HPD
RV347 41
29 VGA_DPD_AUXP/DDC 42 IN1_SCL DP_DMC_ML0P 38
29 VGA_DPD_AUXN/DDC 19 IN1_SDA 39 IN1p
C DP_DMC_ML0N C
17 PCH_DPD_CLK 20 IN2_SCL 41 IN1n
DP_DMC_ML1P
17 PCH_DPD_DAT IN2_SDA 42 IN2p
DP_DMC_ML1N
DGPU_EDIDSEL#_R 22 39 DMC_SW_DETECT DP_DMC_ML2P 44 IN2n 23 CPU_MXM_DMC_P0
36 DGPU_EDIDSEL#_R SW_DDC OUT_HPD IN3p OUT1p CPU_MXM_DMC_P0 51
DGPU_SEL# 21 38 DP_DMC_AUXP DP_DMC_ML2N 45 22 CPU_MXM_DMC_N0 CPU_MXM_DMC_N0 51
36 DGPU_SEL# SW_MAIN OUT_SCL 37 47 IN3n OUT1n 20
DP_DMC_AUXN DP_DMC_ML3P CPU_MXM_DMC_P1 CPU_MXM_DMC_P1 51
OUT_SDA DP_DMC_ML3N 48 IN4p OUT2p 19 CPU_MXM_DMC_N1
IN4n OUT2n CPU_MXM_DMC_N1 51
DMC_IN1_PEQ 3 17 CPU_MXM_DMC_P2 CPU_MXM_DMC_P2 51
DMC_IN2_PEQ 15 IN1_PEQ OUT3p 16 CPU_MXM_DMC_N2
IN2_PEQ OUT3n CPU_MXM_DMC_N2 51
2 14 CPU_MXM_DMC_P3 CPU_MXM_DMC_P3 51
+3VS POW OUT4p 13 CPU_MXM_DMC_N3 CPU_MXM_DMC_N3 51
23 DP_DMC_HPD 30 OUT4n
CEXT 51 DP_DMC_HPD HPD_SINK
24
REXT RV61 1 2 4.7K_0402_5%~D 26
+3VS I2C_CTL_EN#
2.2U_0603_6.3V6K~D

499_0402_1%~D

1 DMC_DDCBUF_EN# 32
NC/DDCBUF_EN#
CV267

RV348

18
43 GND DMC_OE# 25 7 DMC_SINK_HPD
49 GND NC/OE# HPD
2 PAD DMC_SDATA_R 8
2

PS8271QFN48GTR-A1_QFN48_7X7 DMC_SCLK_R 9 SDA


SCL 29 DP_DMC_AUXN
DMC_CFG1 34 SDAZ 28 DP_DMC_AUXP
DMC_CFG0 35 SDA_CTL/CFG1 SCLZ
SEL Y SCL_CTL/CFG0
DMC_PC0 3
DMC_PC1 4 I2C_ADDR0/PC0
0 IN1 I2C_ADDR1/PC1
1 IN2 DMC_PC2 1
GND/PC2

499_0402_1%~D 2 1 RV62 6
REXT

GND10
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
2.2U_0402_6.3V6M~D2 1 CV268 10
CEXT

PS121QFN48G_QFN48_7X7

5
12
18
24
27
31
36
37
43
49
Co-lay +3VS

RV225 0_0603_5%~D
1

B B
1 2
RV349
LV29 100K_0402_5%~D PS121 CFG0/ CFG1
MBK1608221YZF_2P
DMC_SW_DETECT RV351 1 @ 2 0_0402_1% 1 2 DMC_SINK_HPD SCLZ/SDAZ output voltage select;
2

CFG1:0=00 LOW-level input voltage: <0.40V LOW-level output voltage: 0.60V


220P_0402_50V7K~D

DMC_OE#
@ 1 PS121 PC0/PC1/PC2
1

BAV99-7-F_SOT23-3

CV269

2 1 Inputs equalization control, default inputs equalization setting at 12 dB


200K_0402_5%

DV11

QV22 D
G
2

QV23 000: 12 dB, 001: 16 dB, 010: 10 dB, 011: 7 dB


2
RV352

2 SSM3K7002F_SC59-3~D
1 3 G
100: 1.5 dB, 101: 4 dB, 110: 9 dB, 111: 7 dB
D

S
1

3
SSM3K7002F_SC59-3~D Modify 5/17
+5VS
+3VS

4.7K_0402_5%~D 2 1 RV359 @ DMC_DDCBUF_EN#


DGPU_HPD_INT# 4.7K_0402_5%~D 2 1 RV354 @ DMC_CFG1
21,36 DGPU_HPD_INT# 4.7K_0402_5%~D 2 1 RV355 @ DMC_CFG0
4.7K_0402_5%~D 2 1 RV356 DMC_PC0
4.7K_0402_5%~D 2 1 RV357 @ DMC_PC1
4.7K_0402_5%~D 2 1 RV358 DMC_PC2
2.2K_0402_5%~D 2 1 RV317 DP_DMC_AUXN
2.2K_0402_5%~D 2 1 RV318 DP_DMC_AUXP

+3VS 4.7K_0402_5%~D 2 1 RV361 @ DMC_CFG1


4.7K_0402_5%~D 2 1 RV362 @ DMC_CFG0
4.7K_0402_5%~D 2 1 RV363 @ DMC_PC0
4.7K_0402_5%~D 2 1 RV364 @ DMC_PC1
4.7K_0402_5%~D 2 1 RV365 @ DMC_PC2
1

1
1.5K_0402_5%

RV366

1.5K_0402_5%

RV367

A A
2

DMC_SDATA_R CPU_MXM_DMC_AUXN CPU_MXM_DMC_AUXN 51


DMC_SCLK_R CPU_MXM_DMC_AUXP CPU_MXM_DMC_AUXP 51

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title
DP SW for DMC

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 39 of 56
5 4 3 2 1
5 4 3 2 1

+3VS +3VS_RT +1.2VS

30mil 30mil 60 mils


@
1 2 1 2 +SWR_V12 +DVCC33
RV7 0_0805_5%~D RV8 0_0805_5% EEROM

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
@
1 1 1 1
UV23

CV272

CV273

CV274

CV275
8 1
0_0402_5% 7 VCC A0 2
2 2 2 2 MIIC_SCL RV23 1 @ 2 FW_ROM_SCL 6 WP A1 3
MIIC_SDA RV24 1 @ 2 FW_ROM_SDA 5 SCL A2 4
0_0402_5% SDA GND
D EDID_CLK RV25 @1
@ 2 0_0402_5% CAT24C64WI-GT3_SO8 D

Close to Pin15 Close to 11 pin Close to 43 pin EDID_DATA RV26 @


@1 2 0_0402_5% Addr: A8 (1010 100X)
@

UV24

RTD2136S
+DVCC33 35 LVDS_ACLK
+3VS_RT 22 TXOC+ 36 LVDS_ACLK# LVDS_ACLK 41
PVCC TXOC- LVDS_ACLK# 41
LV30 2 1 +DVCC33 40 mils 18 41 LVDS_A0
FBMA-L11-201209-221LMA30T_0805 SWR_VDD TXO0+ 42 LVDS_A0# LVDS_A0 41
TXO0- LVDS_A0# 41

PWR
LV31 2 1 +AVCC33 5
FBMA-L11-201209-221LMA30T_0805 DP_V33 39 LVDS_A1
+SWR_V12 LV32 1 2 +SW_LX 60 mils 17 TXO1+ 40 LVDS_A1# LVDS_A1 41
4.7UH_PG031B-4R7MS_1.1A_20% SWR_LX TXO1- LVDS_A1# 41
60 mils 15 37 LVDS_A2
SWR_VCCK TXO2+ 38 LVDS_A2# LVDS_A2 41
43 TXO2- LVDS_A2# 41
+AVCC33 +DVCC33 VCCK 33
11 TXO3+ 34
DP_V12 TXO3-
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1
25 LVDS_BCLK

LVDS
TXEC+ LVDS_BCLK 41
CV276

CV277

CV278

CV279

CV280

CV281

CV282

CV283
CPU_EDP_P0 CV305 1 2 0.1U_0402_16V4Z CPU_EDP_P0_C 7 26 LVDS_BCLK#
8 CPU_EDP_P0 CPU_EDP_N0 CV306 1 2 0.1U_0402_16V4Z CPU_EDP_N0_C 8 LANE0P TXEC- LVDS_BCLK# 41
2 2 2 2 2 2 2 2 8 CPU_EDP_N0 LANE0N 31 LVDS_B0
CPU_EDP_P1 CV307 1 2 0.1U_0402_16V4Z CPU_EDP_P1_C 9 TXE0+ 32 LVDS_B0# LVDS_B0 41
8 CPU_EDP_P1 CPU_EDP_N1 CV308 1 2 0.1U_0402_16V4Z CPU_EDP_N1_C 10 LANE1P TXE0- LVDS_B0# 41
8 CPU_EDP_N1 LANE1N

DP
C 29 LVDS_B1 C
CPU_EDP_AUX CV309 1 2 0.1U_0402_16V4Z CPU_EDP_AUX_C 4 TXE1+ 30 LVDS_B1# LVDS_B1 41
Close to LV9 Close to 5 pin Close to LV10 Close to 18 pin Close to 22 pin8 CPU_EDP_AUX AUX-CH_P TXE1- LVDS_B1# 41
CPU_EDP_AUX#CV310 1 2 0.1U_0402_16V4Z CPU_EDP_AUX#_C 3
8 CPU_EDP_AUX# AUX-CH_N 27 LVDS_B2
CPU_EDP_HPD# 1 TXE2+ 28 LVDS_B2# LVDS_B2 41
8 CPU_EDP_HPD# DP_HPD TXE2- LVDS_B2# 41
23
TXE3+ 24
TXE3-
PCH_EDP_PWM 21
17 PCH_EDP_PWM 2 PWMIN 46 EDID_CLK
Vendor advise reserve it 1 2 12 TESTMODE
DP_REXT
MIICSCL1
MIICSDA1
45 EDID_DATA
EDID_CLK
EDID_DATA
42
42

OTHERS
RV9 12K_0402_1%
20 TL_ENVDD
@ PANEL_VCC 19 TL_INVT_PWM TL_ENVDD 42
RV14 1 2 0_0402_5% MIIC_SCL 48 PWMOUT 44 TL_BKOFF#_R TL_INVT_PWM 42
ENBKL 42,43 MIIC_SDA 47 MIICSCL0 BL_EN
MIICSDA0

CSCL 1 RV11 2 0_0402_5% CIICSCL 13 6


TL_BKOFF#_R RV12 1 2 0_0402_5% CSDA 1 RV20 2 0_0402_5% CIICSDA 14 CIICSCL1 DP_GND
TL_INVT_BL 42 CIICSDA1

GND
16 RV15 1 2 0_0402_1%
CV284 GND @
0.1U_0402_16V7K 49
+3VS_RT +DVCC33 PAD
1 2
5

+3VS_RT RTD2136R-CG_QFN48_6X6

2
2 @
P

B 4 RV50
Y
1

1 @ 4.7K_0402_5% EEPROM
42,43 BKOFF# A
G

UV25 RV16 MIIC_SDA


3

1
B MC74VHC1G08DFT2G SC70 5P 100K_0402_5% MIIC_SCL B

1
2

RV46

2
CPU_EDP_AUX# @ 4.7K_0402_5%
CPU_EDP_AUX RV18
4.7K_0402_5% ROMLESS

2
1

1
RV19
100K_0402_5% Pull-Low 100K
2

+DVCC33

+3VS_RT EDID_DATA RV52 1 2 4.7K_0402_5%


AUX termination
EDID_CLK RV21 1 2 4.7K_0402_5% TL_BKOFF#_R

1
2

RV22
MIIC_SDA RV45 1 2 4.7K_0402_5% 100K_0402_5%
CSDA 1 6 RV13 1 2 0_0402_1% EC_SMB_DA2
EC_SMB_DA2 19,30,43,53,54

2
@ CSCL RV47 1 2 4.7K_0402_5%
QV2A
5

CSDA RV51 1 2 4.7K_0402_5%


DMN66D0LDW-7_SOT363-6~D
CSCL 4 3 RV17 1 2 0_0402_1% EC_SMB_CK2
EC_SMB_CK2 19,30,43,53,54
@
QV2B
DMN66D0LDW-7_SOT363-6~D

A A

Security Classification Compal Secret Data


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Translator RTD2136R

www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 40 of 56
5 4 3 2 1
5 4 3 2 1

STDP6038 SW STDP4028 PCH/GPU AUX for LVDS

D UV26 D

16 EDP_DETECT#
SLE1 EDP_DETECT# 21

LVDS_BCLK 2 5 LVDS_MUX_TZCLK+
40 LVDS_BCLK LVDS_BCLK# 1 0B1 A0 6 LVDS_MUX_TZCLK- LVDS_MUX_TZCLK+ 42
40 LVDS_BCLK# 1B1 A1 LVDS_MUX_TZCLK- 42
LVDS_MXM_TZCLK+ 80
29 LVDS_MXM_TZCLK+ 79 0B2
LVDS_MXM_TZCLK-
29 LVDS_MXM_TZCLK- 1B2
LVDS_B2 78 8 LVDS_MUX_TZOUT2+
40 LVDS_B2 LVDS_B2# 77 2B1 A2 9 LVDS_MUX_TZOUT2- LVDS_MUX_TZOUT2+ 42
40 LVDS_B2# 3B1 A3 LVDS_MUX_TZOUT2- 42
LVDS_MXM_TZOUT2+ 76
29 LVDS_MXM_TZOUT2+ LVDS_MXM_TZOUT2- 75 2B2
29 LVDS_MXM_TZOUT2- 3B2
LVDS_B1 73 11 LVDS_MUX_TZOUT1+
40 LVDS_B1 72 4B1 A4 12 LVDS_MUX_TZOUT1+ 42
LVDS_B1# LVDS_MUX_TZOUT1-
40 LVDS_B1# 5B1 A5 LVDS_MUX_TZOUT1- 42
LVDS_MXM_TZOUT1+ 71
29 LVDS_MXM_TZOUT1+ LVDS_MXM_TZOUT1- 70 4B2
29 LVDS_MXM_TZOUT1- 5B2
LVDS_B0 68 14 LVDS_MUX_TZOUT0+
40 LVDS_B0 LVDS_B0# 67 6B1 A6 15 LVDS_MUX_TZOUT0- LVDS_MUX_TZOUT0+ 42
40 LVDS_B0# 7B1 A7 LVDS_MUX_TZOUT0- 42
LVDS_MXM_TZOUT0+ 66
29 LVDS_MXM_TZOUT0+ LVDS_MXM_TZOUT0- 65 6B2
29 LVDS_MXM_TZOUT0- 7B2
64 17
63 8B1 A8 18
9B1 A9
RTD2136
C
Input 62
8B2 Output C

DGPU_MXM 61
9B2
34 EDP_DETECT#
SEL2

LVDS_ACLK 60 23 LVDS_MUX_TXCLK+
40 LVDS_ACLK 59 10B1 A10 24 LVDS_MUX_TXCLK+ 42
LVDS_ACLK# LVDS_MUX_TXCLK-
40 LVDS_ACLK# 11B1 A11 LVDS_MUX_TXCLK- 42
LVDS_MXM_TXCLK+ 58
29 LVDS_MXM_TXCLK+ LVDS_MXM_TXCLK- 57 10B2
29 LVDS_MXM_TXCLK- 11B2
LVDS_A2 56 26 LVDS_MUX_TXOUT2+
40 LVDS_A2 55 12B1 A12 27 LVDS_MUX_TXOUT2+ 42
LVDS_A2# LVDS_MUX_TXOUT2-
40 LVDS_A2# 13B1 A13 LVDS_MUX_TXOUT2- 42
LVDS_MXM_TXOUT2+ 54
29 LVDS_MXM_TXOUT2+ LVDS_MXM_TXOUT2- 53 12B2
29 LVDS_MXM_TXOUT2- 13B2
LVDS_A1 51 29 LVDS_MUX_TXOUT1+
40 LVDS_A1 LVDS_A1# 50 14B1 A14 30 LVDS_MUX_TXOUT1- LVDS_MUX_TXOUT1+ 42
40 LVDS_A1# 15B1 A15 LVDS_MUX_TXOUT1- 42
LVDS_MXM_TXOUT1+ 49
29 LVDS_MXM_TXOUT1+ 48 14B2
LVDS_MXM_TXOUT1-
29 LVDS_MXM_TXOUT1- 15B2
LVDS_A0 46 32 LVDS_MUX_TXOUT0+
40 LVDS_A0 LVDS_A0# 45 16B1 A16 33 LVDS_MUX_TXOUT0- LVDS_MUX_TXOUT0+ 42
40 LVDS_A0# 17B1 A17 LVDS_MUX_TXOUT0- 42
LVDS_MXM_TXOUT0+ 44
29 LVDS_MXM_TXOUT0+ LVDS_MXM_TXOUT0- 43 16B2
29 LVDS_MXM_TXOUT0- 17B2
42 35
41 18B1 A18 36
B 19B1 A19 B
40 +3VS
39 18B2
19B2
+3VS
3 4
GND1 VDD1

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D
13 10
GND2 VDD2
1

20 19 1 1 1
33,42 LCDVDD_ON GND3 VDD3

CV285

CV286

CV287
RV370 21 22
31 GND4 VDD4 28
2 100K_0402_5%~D GND5 VDD5
G

38 37
52 GND6 VDD6 47 2 2 2
2

74 GND7 VDD7 69
GND8 VDD8
S

3 1 25
7 OE2#
OE1#

QV24
SSM3K7002F_SC59-3~D PI3LVD1012BE_BQSOP80

SEL Y
L RTD2136
H DGPU_MXM

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS SW- 1 to 2 & GPU/PCH

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 41 of 56
5 4 3 2 1
5 4 3 2 1

+3VS

LCD Backlight Selector PCH/GPU MUX & 6038 MUX SW for LVDS

1
RV371
10K_0402_5%~D

UV27

2
DGPU_SELECT# @ RV372 1 2 0_0402_5%~D
16 HDMI_IN_SELECT#_R
SLE1

SSM3K7002FU_SC70-3~D
RV374 @1 2 0_0402_5%~D HDMI_IN_PWM_SELECT# QV31
17 HDMI_IN_PWMSEL#

1
+3VS D

0.1U_0402_16V4Z~D
LVDS_MUX_TZCLK+ 2 5 TZCLK+
+3VS 41 LVDS_MUX_TZCLK+ 0B1 A0
HDMI_IN_SELECT# RV398 1 2 0_0402_1% LVDS_MUX_TZCLK- 1 6 TZCLK- 2
41 LVDS_MUX_TZCLK- 1B1 A1 HDMI_IN_SELECT# 43
@ G
D LVDS_6038_TZCLK+ 80 S D
1 37 LVDS_6038_TZCLK+

3
0B2

1
0_0402_5%~D LVDS_6038_TZCLK- 79
37 LVDS_6038_TZCLK- 1B2

CV288
@ RV375 1 2 @ RV376
42,43 EC_INV_PWM
UV28 10K_0402_5%~D LVDS_MUX_TZOUT2+ 78 8 TZOUT2+
2 41 LVDS_MUX_TZOUT2+ 2B1 A2
0_0402_1% 6 16 LVDS_MUX_TZOUT2- 77 9 TZOUT2-
1B1 VCC 41 LVDS_MUX_TZOUT2- 3B1 A3
RV377 1 2 VGA_EC_PWM 5
29 VGA_PNL_PWM

2
@ HDMI_IN_PWM 4 1B2 14 HDMI_IN_PWM_SELECT# LVDS_6038_TZOUT2+ 76
37 HDMI_IN_PWM 1B3 S0 37 LVDS_6038_TZOUT2+ 2B2 +3VS +3VS_CAM
TL_INVT_PWM 3 2 LVDS_6038_TZOUT2- 75
40 TL_INVT_PWM 1B4 S1 DGPU_BKL_PWM_SEL# 21 37 LVDS_6038_TZOUT2- 3B2
RV402 1 @ 2 0_0402_5%~D QV25
42,43 EC_INV_PWM
10 7 INV_PWM LVDS_MUX_TZOUT1+ 73 11 TZOUT1+ SI2301CDS-T1-GE3_SOT23-3~D
2B1 1A 41 LVDS_MUX_TZOUT1+ 4B1 A4 +LCDVDD_5V
11 9 ENBKL LVDS_MUX_TZOUT1- 72 12 TZOUT1-
29 DGPU_BKL_EN 2B2 2A ENBKL 40,43 41 LVDS_MUX_TZOUT1- 5B1 A5

S
12 3 1

D
37 HDMI_IN_BKL_EN 2B3

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
13 15 LVDS_6038_TZOUT1+ 71
40 TL_INVT_BL 2B4 2OE 37 LVDS_6038_TZOUT1+ 4B2

100K_0402_5%~D

100K_0402_5%~D

100K_0402_5%~D

10U_0805_10V4Z~D
LVDS_6038_TZOUT1- 70
37 LVDS_6038_TZOUT1- 5B2

1
0.1U_0402_16V4Z~D

10U_0805_10V4Z~D
1 8

G
2 2 1

2
1OE GND

RV379

RV380

CV289

RV381

CV290

CV291
1 2 LVDS_MUX_TZOUT0+ 68 14 TZOUT0+ 1 1
17,43 SG_AMD_BKL 41 LVDS_MUX_TZOUT0+ 6B1 A6

CV324

CV325
RV378 0_0402_5%~D SN74CB3Q3253PWR_TSSOP16 LVDS_MUX_TZOUT0- 67 15 TZOUT0-
41 LVDS_MUX_TZOUT0- 7B1 A7
Deep S3 LVDS_6038_TZOUT0+ 66 1 1 2
37 LVDS_6038_TZOUT0+

2
LVDS_6038_TZOUT0- 65 6B2 2 2
37 LVDS_6038_TZOUT0- 7B2
S1 S0 1A 2A Y
64 17
8B1 A8

SSM3K7002F_SC59-3~D
63 18
9B1 A9 Output D
1
0 0 1B1 2B1 HDMI IN (D) CPU/MXM(MUX) Input 62
8B2

QV26
0 1 1B2 2B2 DSC 61 2
HDMI IN(6038) 9B2 43 EN_CAM G
1 0 1B3 2B3 HDMI IN (I) 34 HDMI_IN_SELECT#_R
SEL2 S
1 1 1B4 2B4 UMA LCD DDC Selector 41 LVDS_MUX_TXCLK+
LVDS_MUX_TXCLK+
LVDS_MUX_TXCLK-
60
59 10B1 A10
23
24
TXCLK+
TXCLK-
3

EN_CAM control circuit


C 41 LVDS_MUX_TXCLK- 11B1 A11 C
@ RV382
0_0402_5%~D LVDS_6038_TXCLK+ 58 +LCDVDD_3V
37 LVDS_6038_TXCLK+ 10B2 +3VS
DGPU_SELECT# 1 2 LVDS_6038_TXCLK- 57
+3VS 37 LVDS_6038_TXCLK- 11B2

0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D

LVDS_MUX_TXOUT2+ 56 26 TXOUT2+ 1
41 LVDS_MUX_TXOUT2+ 12B1 A12

CV292

0.1U_0402_16V4Z~D

10U_0805_10V4Z~D
RV383 S1 S0 1A 2A Y LVDS_MUX_TXOUT2- 55 27 TXOUT2-
41 LVDS_MUX_TXOUT2- 13B1 A13
0_0402_5%~D 1 1 1
SEL Y
CV293

CV294

CV295
1 2 DGPU_EDIDSEL_R# LVDS_6038_TXOUT2+ 54
21,31,36 DGPU_EDIDSEL# 37 LVDS_6038_TXOUT2+ 12B2 2
0 0 1B1 2B1 HDMI IN (D) LVDS_6038_TXOUT2- 53
37 LVDS_6038_TXOUT2- 13B2 L B1
UV29 2 LVDS_MUX_TXOUT1+ 51 29 TXOUT1+ 2 2
0 1 1B2 2B2 DSC 41 LVDS_MUX_TXOUT1+ 14B1 A14 H B2
6 16 LVDS_MUX_TXOUT1- 50 30 TXOUT1-
1B1 VCC 41 LVDS_MUX_TXOUT1- 15B1 A15
VGA_LCD_CLK 5 1 0 1B3 2B3 HDMI IN (I) Close to JLVDS1
29 VGA_LCD_CLK 1B2
DHMI_IN_NV_CLK 4 14 HDMI_IN_SELECT# LVDS_6038_TXOUT1+ 49
37 DHMI_IN_NV_CLK 1B3 S0 37 LVDS_6038_TXOUT1+ 14B2
EDID_CLK 3 2 DGPU_EDIDSEL_R# 1 1 1B4 2B4 UMA LVDS_6038_TXOUT1- 48
40 EDID_CLK 1B4 S1 37 LVDS_6038_TXOUT1- 15B2 RV384 @
10 7 I2CC_SCL LVDS_MUX_TXOUT0+ 46 32 TXOUT0+ BKOFF# 1 2 DISPOFF#
2B1 1A 41 LVDS_MUX_TXOUT0+ 16B1 A16 40,43 BKOFF#
VGA_LCD_DAT 11 9 I2CC_SDA LVDS_MUX_TXOUT0- 45 33 TXOUT0- 0_0402_1%
37
29

40
VGA_LCD_DAT
DHMI_IN_NV_DAT
EDID_DATA
DHMI_IN_NV_DAT
EDID_DATA
12
13
2B2
2B3
2B4
2A

2OE
15
41

37
LVDS_MUX_TXOUT0-

LVDS_6038_TXOUT0+
LVDS_6038_TXOUT0+ 44
17B1

16B2
A17
LVDS Conn.
LVDS_6038_TXOUT0- 43 JLVDS1
37 LVDS_6038_TXOUT0- 17B2
1 8 44 55 TXOUT0-
1OE GND 42 35 44 43 54 GND11 TXOUT0+
SN74CB3Q3253PWR_TSSOP16 41 18B1 A18 36 43 42 53 GND10
19B1 A19 42 41 52 GND9 TXOUT1-
40 41 40 51 GND8 TXOUT1+
39 18B2 +3VS 40 39 50 GND7
19B2 39 38 49 GND6 TXOUT2-
+3VS 38 37 48 GND5 TXOUT2+
3 4 37 36 47 GND4
13 GND1 VDD1 10 36 35 GND3

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D
46 TXCLK-
20 GND2 VDD2 19 35 34 GND2

1
1 1 1 45 TXCLK+
21 GND3 VDD3 22 34 33 GND1

CV296

CV297
B LCDVDD_ON RV385 B

CV298
33,41,42 LCDVDD_ON GND4 VDD4 28 33 32
2 100K_0402_5%~D 31 TZOUT0-
GND5 VDD5 32 31
G

38 37 TZOUT0+
52 GND6 VDD6 47 2 2 2 31 30

2
74 GND7 VDD7 69 30 29 TZOUT1-
GND8 VDD8 29 28
S

3 1 25 TZOUT1+
7 OE2# 28 27
QV27 OE1# 27 26 TZOUT2-
26 25 TZOUT2+
SSM3K7002F_SC59-3~D
25 24
PI3LVD1012BE_BQSOP80 24 23 TZCLK-
23 22 TZCLK+
+3VS +3VS 22 21
DMIC_CLK 21 20 INV_PWM
@ 20 19 DISPOFF#
1 19 18

1
1 @ CAM_DET#
18 17 CAM_DET# 18

10P_0402_50V8J~D
CV322
CV299 RV386 USB20_P12_CONN
0.1U_0402_16V4Z~D 10K_0402_5%~D 17 16 USB20_N12_CONN
UV30 2 16 15 LVDS_CAB_DET#
6 16 2 15 14 DMIC_CLK LVDS_CAB_DET# 21
DMIC_CLK 45
2
5 1B1 VCC 14 13
+3VS_CAM
4 1B2 14 HDMI_IN_SELECT# 13 12 DMIC0
DMIC0 45
3 1B3 S0 2 DGPU_SELECT# 12 11 I2CC_SDA
1B4 S1 DGPU_SELECT# 17,31,36 11 10 I2CC_SCL
10 7 10 9 LCD_TEST
2B1 1A 9 8 LCD_TEST 43
11 9 LCDVDD_ON RV389 1 2 0_0402_5%~D
29 DGPU_ENVDD 2B2 2A LCDVDD_ON 33,41,42 8 7
12 +LCDVDD_5V
37 HDMI_IN_ENVDD
13 2B3 15 @ LV33 7 6
+3VS
40 TL_ENVDD 2B4 2OE 6 5
USB20_P12 4 3 USB20_P12_CONN +LCDVDD_3V
20 USB20_P12 4 3 5 4
1 8 W=60mils +INVPWR_B+
1OE GND 4 3
SN74CB3Q3253PWR_TSSOP16 USB20_N12 1 2 USB20_N12_CONN 3 2
A 20 USB20_N12 1 2 2 1 A
DLW21SN900SQ2L_0805_4P~D 1
JAE_FI-TD44SB-VF93-R750~D
W=80mils
RV392 1 2 0_0402_5%~D CONN@
S1 S0 1A 2A Y Link Done
DELL CONFIDENTIAL/PROPRIETARY
0 0 1B1 2B1 HDMI IN Compal Electronics, Inc.
0 1 1B2 2B2 DSC PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWINGS AND SPECIFICATIONS CONTAINS CONFIDENTIAL, Title
TRADE SECRET, AND OTHER PROPRIETARY INFORMATION
1 0 1B3 2B3 HDMI IN OF DELL. ("DELL"). THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN LVDS SW- 6038/SYSTEM & CONN
AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS Size Document Number Rev
1 1 1B4 2B4 UMA SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT 0.1
DELL'S EXPRESS WRITTEN CONSENT. LA-9332P
Date: Friday, December 14, 2012 Sheet 42 of 56

www.vinafix.vn
5 4 3 2 1
5 4 3 2 1

+3VS
+5VS
RE36 1 @ 2 10K_0402_5%~D BKOFF#
RE38 1 2 10K_0402_5%~D EC_SCI# +3VALW LE3 EC_ESB_CLK
RE42 1 2 10K_0402_5%~D M_THERMAL# @ FBMA-L11-160808-800LMT_0603 TP_CLK 4.7K_0402_5%~D 2 1 RE35

2
RE43 1 2 2.2K_0402_5%~D EC_SMB_CK2 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K +3VALW_EC 1 2 +EC_VCCA
RE45 1 2 2.2K_0402_5%~D EC_SMB_DA2 RE37 1 1 1 1 2 2 @ RE40 TP_DATA 4.7K_0402_5%~D 2 1 RE41

2
RE69 1 2 100K_0402_5% VPK_DET# 0_0805_5%~D CE35 CE31 CE32 CE34 CE37 CE36 1 33_0402_5%~D

22P_0402_50V8J~D
RE44 0.1U_0402_16V7K
1000P_0402_50V7K 0_0402_5% CE33

1
2 2 2 2 1 1

@
ECAGND 1
+3VALW_EC 2

CE39
0.1U_0402_16V7K 0.1U_0402_16V7K 1000P_0402_50V7K RE72 1 2 100K_0402_5% BKOFF#

1
@
1 2 +3VLP
RE47 0_0402_1% 2
D D
RE46 1 2 2.2K_0402_5%~D EC_SMB_CK1 Reserve for EMI

111
125
RE48 1 2 2.2K_0402_5%~D EC_SMB_DA1 +3VALW_EC +3VALW_EC Reserved for KB9012

22
33
96

67
UE1 please close to UE2

9
RE51 1 2 10K_0402_5%~D EC_MUTE#

47K_0402_5%~D

47K_0402_5%~D
RE39 2 @ 1 10K_0402_5%~D EC_SMI#

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
2

1
RE53 1 2 100K_0402_5%~D DEPOP#
RE54 1 2 4.7K_0402_5%~D EC_ESB_CLK

RE55

RE56
RE57 1 2 4.7K_0402_5%~D EC_ESB_DAT
RE58 1 2 10K_0402_5%~D LID_SW_IN# 21 GATEA20 GATEA20 1 21 EN_TPLED# EN_TPLED# 48
RE59 2 1 10K_0402_5%~D EN_WOL# KB_RST# 2 GATEA20/GPIO00 GPIO0F 23 BEEP#
21 KB_RST# BEEP# 45

2
RE60 1 @ 2 10K_0402_5%~D EAPD#_R SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 SYSTEM_FAN_PWM
19 SERIRQ SERIRQ GPIO12 SYSTEM_FAN_PWM 54
RE73 1 2 100K_0402_5%~D WLES ON/OFF LED# EC_RST# RST# LPC_FRAME# 4 27 MXM1_FAN_PWM MXM1_FAN_PWM 54
19,51 LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13 2 1
LPC_AD3 ECAGND
19,51 LPC_AD3 LPC_AD3 ECAGND 57

0.1U_0402_16V4Z~D

.1U_0402_16V7K~D
EC_ESB_CLK 1 @ 2 EC_ESB_CLK_R LPC_AD2 7 PWM Output CE42 100P_0402_50V8J~D
19,51 LPC_AD2 LPC_AD1 8 LPC_AD2 63 BATT_TEMP
RE61 0_0402_1% 1 2 19,51 LPC_AD1 LPC_AD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 57,64

CE43
LPC_AD0 10 LPC & MISC 64 EAPD#_R RE63 2 @ 1 0_0402_5%~D @
19,51 LPC_AD0 LPC_AD0 AD1/GPIO39 PM_SLP_SUS# 17

CE44
65 ADP_I RE64 2 1 0_0402_5%~D RE62 1 2 DEPOP# 45
KSI[0..7] 12 ADP_I/AD2/GPIO3A 66 ADP_I 57,64 EAPD# 45
CLK_PCI_LPC AD Input AD_BID0 DEPOP#
48,53 KSI[0..7] 2 1 18 CLK_PCI_LPC CLK_PCI_EC AD3/GPIO3B

SSM3K7002FU_SC70-3~D
PLT_RST# 13 75 USBCHG_DET_EC# 0_0402_1% QE21
KSO[0..17] 17,44,51,53,6 PLT_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 ENBKL
48,53 KSO[0..17] EC_RST# IMON/AD5/GPIO43 ENBKL 40,42

1
EC_SCI# 20 D
21 EC_SCI# 38 EC_SCII#/GPIO0E 2
ACOFF DEPOP#_EC
64 ACOFF GPIO1D G

10K_0402_5%~D
68 RE68 2 1 0_0402_5%~D ODD_EJECT# 50 S

3
DAC_BRIG/GPIO3C

2
DA Output 70 M_THERMAL# M_THERMAL# 12,13,14,15
KSI0 55 EN_DFAN1/GPIO3D 71 EC_ENVDD @
KSI0/GPIO30 IREF/GPIO3E EC_ENVDD 33

RE65
KSI1 56 72 LCD_TEST LCD_TEST 42
CLK_PCI_LPC KSI2 57 KSI1/GPIO31 CHGVADJ/GPIO3F
KSI3 58 KSI2/GPIO32 83 EC_MUTE# EC_MUTE# 45

1
KSI4 59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 IMVP_PWRGD
KSI4/GPIO34 USB_EN#/GPIO4B IMVP_PWRGD 17,6,62

1
KSI5 60 85 LCD_BKL_EN LCD_BKL_EN 33
RE66 @ KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D EC_LID_OUT# 19
33_0402_5%~D KSI7 62 87 TP_CLK TP_CLK 53
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 53

Board ID
2

KSO2 41 KSO1/GPIO21
KSO2/GPIO22
22P_0402_50V8J~D
1 KSO3 42 97 CPU1.5V_S3_GATE CPU1.5V_S3_GATE 10
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 +3VALW_EC
@
KSO4 43 98 EN_WOL#
KSO4/GPIO24 WOL_EN/GPXIOA01 EN_WOL# 44
CE45

KSO5 44 99 HDA_SDO
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
HDA_SDO 16
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH 57

2
2 KSO7 46
C
KSO7/GPIO27 SPI Device Interface C
Reserve for KSO8 47
KSO9 48 KSO8/GPIO28 119 PWRSHARE_EN_EC# RE67
KSO9/GPIO29 SPIDI/GPIO5B PWRSHARE_EN_EC# 52
EMI please KSO10 49 120 PWRSHARE_OE#
PWRSHARE_OE# 52 Ra 100K_0402_5%~D
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126
close to UE1 SPI Flash ROM

1
51 KSO11/GPIO2B SPICLK/GPIO58 128 VPK_EN 53
KSO12 3V_F347_ON 47
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A AD_BID0
KSO14 53 KSO13/GPIO2D RE114
KSO14/GPIO2E

2
KSO15 54 73 HDMI_MONITOR_EC 1 2 0_0402_5%~D HDMI_MONITOR 45 RE70 1
KSO15/GPIO2F ENBKL/AD6/GPIO40

18K_0402_5%~D
KSO16 81 74 PCIE_WAKE#_EC RE82 1 @ 2 0_0402_1% CE46
82 KSO16/GPIO48 PECI_KB930/AD7/GPIO41 89 PCIE_WAKE# 17,44,51
KSO17 PCH_DPWROK Rb 0.1U_0402_16V4Z~D
KSO17/GPIO49 FSTCHG/GPIO50 PCH_DPWROK 17
90 BATT_CHG_LED# BATT_CHG_LED# 47
BATT_CHG_LED#/GPIO52 91 CAPS_LED# 2
CAPS_LED# 53

1
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92
29,57,64 EC_SMB_CK1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54 Power_LED# 53
EC_SMB_DA1 78 93 BATT_LOW_LED# BATT_LOW_LED# 47
29,57,64 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55
RE75 1 2 0_0402_5%~D EC_SMB_CK2 79 SM Bus 95 SYSON SYSON 56,59,60
37 EC_SMB_CK2_R EC_SMB_CK2/GPIO46 SYSON/GPIO56
RE76 1 2 0_0402_5%~D EC_SMB_DA2 80 121 IMVP_VR_ON IMVP_VR_ON 62
37 EC_SMB_DA2_R EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 1 2
19,30,40,53,54 EC_SMB_CK2 PM_SLP_S4#_R
PM_SLP_S4#/GPIO59 PM_SLP_S4# 17
RE81 @ 0_0402_1%
19,30,40,53,54 EC_SMB_DA2
2 0_0402_5%~D PM_SLP_S3#_R RE77 1 6 100 PCH_RSMRST# PCH_RSMRST# 17
BOARD ID Table
17,47 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03
2 0_0402_5%~D PM_SLP_S5#_R RE78 1 14 101 Board PCB
17,47 PM_SLP_S5# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 MXM2_FAN_FB 54
EC_SMI# VCIN1_PH
21 EC_SMI# PS_ID 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 H_PROCHOT#_EC
VCIN1_PH 57 ID Revision Rb
57 PS_ID EC_ESB_CLK_R 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 VCOUT0_PH#
@ T182 PAD~D
EC_ESB_DAT 18 GPIO0B VCOUT0_PH/GPXIOA07
GPO BKOFF#/GPXIOA08 105 BKOFF#
VCOUT0_PH# 58
* 0 0.1 (SSI) 0
@ T183 PAD~D GPIO0C BKOFF# 40,42
SUSPWRDNACK 19 GPIO 106 PBTN_OUT#
17 SUSPWRDNACK 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PCH_PWR_EN
PBTN_OUT# 17,6 1 0.2 (PT) 8.2K +/- 5%
54 MXM2_FAN_PWM 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 PCH_PWR_EN 56
SYSTEM_FAN_FB VPK_DET#
54 SYSTEM_FAN_FB MXM1_FAN_FB 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 VPK_DET# 53 2 0.3 (ST) 18K +/- 5%
54 MXM1_FAN_FB E51TXD_P80DATA 30 EC_PME#/GPIO15 CE47 2 1100P_0402_50V8J~D
50 E51TXD_P80DATA
E51RXD_P80CLK 31 EC_TX/GPIO16 110 ACIN
3 0.4 (QT) 33K +/- 5%
50 E51RXD_P80CLK EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN 17,29,47,57,64
PCH_PWROK 32 112 EC_ON
WLES ON/OFF LED# 2
17 PCH_PWROK
1 RE83 EC_GPIO19 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 ON/OFF
EC_ON 58 4 1.0 (MP) 56K +/- 5%
51,53 WLES ON/OFF LED# SG_AMD_BKL 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 LID_SW_IN# ON/OFF 55
0_0402_5%~D GPI LID_SW#/GPXIOD04
17,42 SG_AMD_BKL NUM_LED#/GPIO1A 116 SUSP#
LID_SW_IN# 19,45,47,48,53 5 100K +/- 5%
SUSP#/GPXIOD05 SUSP# 10,56,59,60,61
117 USB_PWR_EN#
GPXIOD06 118 EC_PECI RE74 1
USB_PWR_EN#
2 43_0402_1%
52,53 6
PECI_KB9012/GPXIOD07 H_PECI 21,6
122

AGND/AGND
48 KP_DET# 123 XCLKI/GPIO5D 124 +V18R
Please place RE74 7
GND/GND
GND/GND
GND/GND
GND/GND

B 57 ADP_SEL XCLKO/GPIO5E V18R close to EC with in 750mil B

4.7U_0805_10V4Z~D
1
GND0

CE48
2
PCH_PWR_EN H_PROCHOT#_EC need add
11
24
35
94
113

69

20mil 1 2
@ TH_OVERT#_EC
KB9012QF-A4_LQFP128_14X14 29 TH_OVERT#
2 ECAGND

H_PROCHOT# 1 2 RE79 0_0402_5%~D


57,6 H_PROCHOT# VR_HOT# 62
RE80 0_0402_1%

1
D

2 H_PROCHOT#_EC LE44 UE2


G FBMA-L11-160808-800LMT_0603 EC_ESB_CLK 1 13 PAD~D T181 @
SSM3K7002F_SC59-3~D ESB_CLK TEST_EN#
S 37 HDMI_TOGGLE HDMI_TOGGLE 2 14 HDMI_IN_OUT_HPD_EC 35
1

3 QE22 GPIO00 GPIO08/CAS_DAT


RST# 3 15 HDMI_SW
RST# GPIO09 HDMI_SW 35
EC_ESB_DAT 4 16 MXM_RST 17
ESB_DAT GPIO0A
DEPOP#_EC 5 17
GPIO01 GPIO0B MXM2_EC_RST# 30

42 HDMI_IN_SELECT# HDMI_IN_SELECT# 6 18 EC_INV_PWM EC_INV_PWM 42


GPIO02 GPIO0C/PWM0
37 HDMI_IN_CAB_DET# HDMI_IN_CAB_DET#7 19 HDMI_IN_EN 37
DE83 RE85 10K_0402_5%~D GPIO03 GPIO0D/PWM1
BAT54CW_SOT323-3 1 2 56 DGPU_PWR_EN 8 20 TH_OVERT#_EC
+3VALW_EC GPIO04 GPIO0E/PWM2
RE52 1 2 10K_0402_5%~D PCH_PWROK
3 USBCHG_DET_EC# 9 21 DP_MXM_CARD_SEL DP_MXM_CARD_SEL 31
29,30 VR_ON GPIO05 GPIO0F/PWM3
RE71 1 2 VPK_EN
1 10 22 EC_AC_BAT# 29
52 USBCHG_DET# VL +3VLP 30 MXM2_PCH_PWR_ON GPIO06 GPIO10/ESB_RUN#
100K_0402_5%
2 11 23 EN_CAM 42
35 HDMI_IN_OUT_DDC GPIO07/CAS_CLK GPIO11/BaseAddOpt
2

12 24

GND
GND VCC +3VALW_EC
RE86

0.1U_0402_16V4Z~D
1

100K_0402_5%~D 1 60 mil

CE50
A RE87 KC3810_QFN24_4X4 A

25
100K_0402_5%~D
1

USBCHG_DET_D 58 2
2

D
USBCHG_DET_PWR_EN# 2 QE321
G SSM3K7002FU_SC70-3~D
S
3
2

RE88
150K_0402_1%~D
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title


EC ENE-KB9012QF,KC3810

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 43 of 56
5 4 3 2 1
5 4 3 2 1

UL1

+LAN_IO 2 1 PCIE_PRX_GLANTX_P1_C 30 1
W=40mils
20 PCIE_PRX_GLANTX_P1 TX_P VDD33 +LAN_IO
CL1 0.1U_0402_16V7K~D 16
AVDD33
1

2 1 PCIE_PRX_GLANTX_N1_C 29
RL7 20 PCIE_PRX_GLANTX_N1 CL4 0.1U_0402_16V7K~D TX_N
0_0402_5%~D PCIE_PTX_GLANRX_P1 35 13 +AVDDL
20 PCIE_PTX_GLANRX_P1 RX_P AVDDL 19
PCIE_PTX_GLANRX_N1 36 AVDDL 31
20 PCIE_PTX_GLANRX_N1
2

RX_N AVDDL 34
CLK_PCIE_LAN 33 AVDDL 6
18 CLK_PCIE_LAN REFCLK_P AVDDL_REG
CLK_PCIE_LAN# 32
18 CLK_PCIE_LAN# REFCLK_N
4.7K_0402_5%~D 2 @ 1 PLT_RST# 22 +AVDDH
RL10 2 1 CLKREQ_LAN#_R 4 AVDDH 9
4.7K_0402_5%~D 2 1 PCIE_WAKE# 18 LANCLK_REQ# RL12 0_0402_5%~D CLKREQ# AVDDH_REG
RL11 PLT_RST# 2
17,43,51,53,6 PLT_RST# PERST#
4.7K_0402_5%~D 2 @ 1 CLKREQ_LAN#_R 37 +DVDDL
D
RL15 PCIE_WAKE# 3 DVDDL_REG D
17,43,51 PCIE_WAKE# WAKE#
11 LAN_MDIP0
The pull-up resisters might not be 25 TRXP0 12 LAN_MDIN0
SMCLK TRXN0
necessory due to existence 26
SMDATA TRXP1
14
15
LAN_MDIP1
LAN_MDIN1
on PCH side. 28
NC
TRXN1
TRXP2
17 LAN_MDIP2
27 18 LAN_MDIN2
41 TESTMODE TRXN2 20 LAN_MDIP3
GND TRXP3 21 LAN_MDIN3
XTLI 8 TRXN3
XTLO 7 XTLI
XTLO 40
LX

25MHZ_10PF_7V25000014
1 2 5
+LAN_IO ISOLAT#
RL13 30K_0402_5% 24
PPS

4
1
LAN_ACTIVITY# 38 10 +RBIAS 1 RL14 2

0_0402_5%

GND

GND
LAN_LINK#_R 39 LED_0 RBIAS 2.37K_0402_1%~D
RL28 LAN_LED2#_R 23 LED_1
1 LED_2

2
OSC

OSC
CL55 RL29

2
YL1 5.1K_0402_1%~D S IC E2201-BL3A-R QFN 40P E-LAN CTRL

470P_0402_50V7K
2

3
15P_0402_50V8J~D

15P_0402_50V8J~D

1
2 2
CL51 CL52
1 1

W=40mils del 直直Short


C W=40mils W=20mils W=20mils W=20mils C

+3VALW QL1
FDC655BN_NL_SSOT6~D
+LAN_IO
close to Lan pin31 close to Lan pin19
D

6 1A +AVDDL +AVDDH +DVDDL


S

1 5 4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
4.7U_0603_6.3V6K~D
CL20 2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
1000P_0402_50V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
1U_0402_6.3V6K~D 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CL54
G

B+_BIAS 2 CL35 CL28 CL29 CL53 CL30 CL31 CL32 CL33 CL26 CL34 CL39 CL27
1 1 1 1 1 1 1
3

+3VALW
CL21 CL22 CL23 CL24 CL25 CL50 CL41 2 2 2 2 2 2 2 2 2 2 2 2 2
2

2 2 2 2 2 2 2
RL17
2

470K_0402_5%~D
RL18 close to Lan pin6 close to Lan pin34
10K_0402_5%~D close to Lan pin9 close to Lan pin22 close to Lan pin37
1

EN_WOL close to Pin 1 close to Pin 16 close to Lan pin13


1

D
1
1.5M_0402_5%~D

2 QL2
43 EN_WOL#
G SSM3K7002FU_SC70-3 RL19 CL36
S 0.1U_0402_25V6
3

2
1

JLAN1 CONN@
LAN_ACTIVITY# 9
Yellow LED-
2 1 10
+LAN_IO Yellow LED+
RL26 330_0402_5%
B B
TL1 RJ45_MDI3- 8
RL22 PR4-
+VDDCT_L 1 24 RJ45_CT3 1 2 RJ45_MDI3+ 7
LAN_MDIP3 2 TCT1 MCT1 23 RJ45_MDI3+ 75_0402_1%~D PR4+
LAN_MDIN3 3 TD1+ MX1+ 22 RJ45_MDI3- RJ45_MDI1- 6
TD1- MX1- RL23 +LAN_IO PR2-
4 21 RJ45_CT2 1 2 RJ45_MDI2- 5
LAN_MDIP2 5 TCT2 MCT2 20 RJ45_MDI2+ 75_0402_1%~D PR3-
LAN_MDIN2 6 TD2+ MX2+ 19 RJ45_MDI2- RJ45_MDI2+ 4
TD2- MX2- RL25 PR3+

1
7 18 RJ45_CT1 1 2 RJ45_MDI1+ 3
LAN_MDIP1 8 TCT3 MCT3 17 RJ45_MDI1+ 75_0402_1%~D RL30 PR2+
LAN_MDIN1 9 TD3+ MX3+ 16 RJ45_MDI1- RJ45_MDI0- 2 15
TD3- MX3- QL3 1K_0402_1%~D PR1- SHLD2
RL27
10 15 RJ45_CT0 1 2 2N7002_SOT23 RJ45_MDI0+ 1 14

2
LAN_MDIP0 11 TCT4 MCT4 14 RJ45_MDI0+ 75_0402_1%~D PR1+ SHLD1
TD4+ MX4+

D
LAN_MDIN0 12 13 RJ45_MDI0- 3 1 2 1 LAN_LINK# 11
TD4- MX4- RL21 130_0402_1%~D Green LED-
2 1 0_0402_5%~D 12
+LAN_IO LED+
RL24

G
2

2
350UH_GST5009-CLF LAN_LINK#_R LAN_LED2#_R 2 1 LAN_LED2# 13
CL40 RL20 CL38 ORANGE_LED-
TIMAG: S X'FORM_ IH-160 LAN , SP050006F00
BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00 150P_1808_3KV7K~D 130_0402_1%~D 1 2 TYCO_2041332-1
1
CL37

470P_0402_50V7K
1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

2 1
CL42

CL43

CL44

CL45

CL46

CL47

CL48

CL49

2 1 2 1 2 1 2 1

470P_0402_50V7K
@ @ @ @
1 2 1 2 1 2 1 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title
GLAN AR8151 AL1A/ RJ45

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9332P
Date: Friday, December 14, 2012 Sheet 44 of 56
5 4 3 2 1
A B C D E F G H
+5VS Close to Pin39
+3VS +3.3V_DVDD +3.3V_DVDD +3.3V_AVDD

0.1U_0402_10V6K~D

4.7U_0805_25V6-K
2

1
1 2
RA1 0_0805_5%~D CA2 CA1
RA2 1 2 0_0402_5%

2
1 RA3 1 2 0_0402_5%
RA4 1 2 0_0402_5%
MIC2-L 1 2 LINE_B_L_R
+3.3V_DVDD CA21 22U_A_6.3VM_R180M

10U_0805_10V4Z~D

0.1U_0402_10V6K~D
MIC2-R 1 2 LINE_B_R_R
1 2 CA24 22U_A_6.3VM_R180M
CA3 CA4

UA8
2 1
2 1 2 PC_BEEP
+3.3V_DVDD 23 PCBEEP CA5 0.1U_0402_10V6K~D +3.3V_AVDD
1 HVDD 1
0.1U_0402_10V6K~D

10U_0805_10V4Z~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

4.7U_0805_25V6-K
2 LA1 1 39
FBMA-L11-201209-221LMA30T_0805 2 LDO-IN 46 CA119 2 1 1U_0603_16V6K~D
1 LINE1-R
CA8 CA9 CA10 CA11 CA12 45 CA118 2 1 1U_0603_16V6K~D INT-SUB-SPK JAUDIO
+3.3V_DVDD LINE1-L 46
2 2 11 32 1 2 LINE_B_L_R
DVDD LINE2-IN-R/SLEEVE SLEEVE 45 1 2

1
7 31 3 4 LINE_B_R_R
1 2 DVDD-IO LINE2-IN-L/RING2 RING2 45 3 4
25 HP1_A_L 5 6 LINE2-VREFO
DVDD-IO-CP HP1_A_R 7 5 6 8 HP_MUTE#

2
1 1 9 7 8 10 MIC_B_PLUG#
45 RING2 9 10
1 2 RA6 8 37 11 12 HPOUT-JD_B
16 PCH_AZ_CODEC_SDIN0 SDATA-IN MIC1-R 45 SLEEVE 11 12
22_0402_5% 4 36 1 2 HP2_D_L 13 14 HPOUT2-JD
16 PCH_AZ_CODEC_SDOUT SDATA-OUT MIC1-L/MIC-CAP 13 14
RA8 1 2 2 5 48 MIC2-R CA13 10U_0805_10V4Z~D HP2_D_R 15 16
16 PCH_AZ_CODEC_BITCLK BCLK MIC2-R QA10 15 16
22_0402_5% 9 47 MIC2-L 17 18
16 PCH_AZ_CODEC_SYNC SYNC MIC2-L SSM3K7002FU_SC70-3~D 17 18 LID_SW_IN# 19,43,47,48,53
CA15 6 MIC2-VREFO-L 19 20
16,45 PCH_AZ_CODEC_RST# RESETB 19 20
MIC2-VREFO-R 21 22
1 21 22 +3VALW
22P_0402_50V8J~D 1 2 1 3

S
MIC2-VREFO-L 1 34 1 2 MIC_B_PLUG# RA23 10K_0402_1% 23 24
LINE2-VREFO 29 MIC2-VREFO SENSE A 33 RA9 39.2K_0402_1% 1 2 HPOUT2-JD 25 G1 G2 26
MIC2-VREFO-R 30 LINE2-VREFO SENSE B RA11 10K_0402_1% @ 27 G3 G4 28

G
2
MIC1-VREFO 1 2 HPOUT-JD 1 2 G5 G6
27 HP1_A_R RA12 5.1K_0402_1% CA114 10U_0805_10V4Z~D TYCO_2041301-1~D
SURR-R

2
1 2 24 26 HP1_A_L
CA16 1U_0402_6.3V6K~D 21 CBP SURR-L 19 HP2_D_L RA22
CBN CEN CONN@
35 18 HP2_D_R 10K_0402_5%~D
40 JDREF LFE
LDO-CAP
1
20K_0402_1%~D

0.1U_0402_10V6K~D

RA14 41

1
VREF HDMI_MONITOR 43
10U_0805_10V4Z~D

1 2 38 44
VRP FRONT-R INT-SPK-R 46
2.2U_0402_6.3V6M~D

CA17 CA18 2 1 43
FRONT-L INT-SPK-L 46
CA19
+ CA20
2

2 1 100U_B3_6.3VM_R55M 15
1 20 SPDIF-OUT 16
2 CPVEE SPDIF-in I2S_DAT/SPDIF_IN 37 +RTC_CELL +3VLP
CA22 10
REGREF
10U_0805_10V4Z~D

1 1 CA23 12 DMIC_CLK 42 +3.3V_AVDD


GPIO/DMIC-CLK
1U_0402_6.3V6K~D

RA63
28 13 DMIC0 42 SLEEVE Place closely to Pin 33.
22 CPVREF GPIO1/DMIC-DATA 17 GPIO2 RA16
AVSS1 GPIO2/Combo-Jack1

RA65
42 3

100K_0402_5%~D
2.49K_0402_1%~D
AVSS2 GPIO3/Combo-Jack2

1
2 2 HPOUT-JD 2 1

100K_0402_5%~D
@
49
Thermal PAD

0.1U_0402_10V7K~D
2 14 @ 2
EAPD EAPD# 43 +3VS
RA15 1

3
0_0402_5%~D

CA60
ALC3661-CG_MQFN48_6X6~D

1
5 2
RA18
CA84 1 2 0.1U_0402_16V7K QA109B 100K_0402_5%~D

4
DMN66D0LDW-7_SOT363-6~D

3
CA83 1 2 0.1U_0402_16V7K

2
ESD Place under codec
RA50 1 2 0_0402_5%~D RA26 1 2 0_1206_5%~D
+3VS RA21 2 1 10K_0402_1% 2 2 5 JACK_SENSE#
RA52 1 2 0_0402_5%~D 1
RA53 1 2 0_0402_5%~D RA29 1 2 0_1206_5%~D QA109A QA108A QA108B

4
RA24 2 @ 1 10K_0402_1% DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D @ CA61
1 2 0_1206_5%~D 16,45 PCH_AZ_CODEC_RST#
RA32 0.1U_0402_25V6K~D
2

GND AGND Add for solve pop noise and detect issue

GND AGND

JACK_PLUG Delay cricutis


+3.3V_DVDD +3.3V_AVDD

+3VS
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

10U_0603_6.3V6M~D

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

10U_0603_6.3V6M~D

1
1 1 1 1 1 1 1 1 JACK_SENSE#
CA27

CA28

CA29

CA30

CA31

CA59

CA37

CA35

RA7
100K_0402_5%

3
3 2 2 2 2 2 2 2 2 3
RA66

2
0_0402_5%~D QA4B
46 SPK_MUTE# 1 2 RA20
SPK_MUTE# EC_MUTE# EC_MUTE# 43
QA4A 2 1 5 DMN66D0LDW-7_SOT363-6

6
DMN66D0LDW-7_SOT363-6

4
RA10 100K_0402_5%
HPOUT-JD_B 1 2 2 1
CA6
10K_0402_1%

1
1 10U_0603_6.3V6M
2
CA7
RA64 10U_0603_6.3V6M
1 2 1 2 2
46 AMP_RIGHT_C
CA40 0.1U_0402_16V4Z~D 1K_0402_1%~D
RA60
0_0402_5%~D
1 2 BEEP_C# 1 RA59 2 1 2 PC_BEEP
43 BEEP#
CA38 0.1U_0402_16V4Z~D 100K_0402_5%~D
@
2

1 2 PCH_SPKR_C 1 RA61 2 HPOUT-JD_B 0_0402_5% 2 1 RA19 JACK_SENSE#


16 HDA_SPKR
CA39 0.1U_0402_16V4Z~D 100K_0402_5%~D
RA62 @ Reserve for cancel Delay cricutis
10K_0402_5%~D
1 2 1 RA96 2
1

37 HDMI_IN_AUDIO_CODEC +3.3V_DVDD
CA58 0.1U_0402_16V4Z~D 100K_0402_5%~D

Need double check this pin


RB751V40_SC76-2
2

DA11
RA17 2 1 EAPD#

10K_0402_1%
DA10
1

3 DEPOP#
DEPOP# 43
HP_MUTE# 1

4 2 GPIO2 4

BAT54AW_SOT323-3~D

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title
HD Audio ALC3661

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 45 of 56
A B C D E F G H
5 4 3 2 1

LA10
FBMA-L11-160808-121LMA30T_0805
1 2 +PVDD
40mil
B+_BIAS
Close to LA9

CA68

CA69

CA70

CA71

CA72
1 1

1U_0603_25V6K

1U_0603_25V6K

1U_0603_25V6K

1U_0603_25V6K

1U_0603_25V6K
1

1
CA66 CA67 UA9 CA74
10U_1206_25V6M 0.1U_0402_16V7K +PVDD 1 2 +PAVDD 7 0.22U_0603_25V7K Int. Speaker Connector

2
2 2 AVCC

10U_0805_25V6K
RA116 10_0402_1% 26 BSPL 1 2
BSPL

1
+PVDD 15
CA78 16 PVCCR 25 OUTPL LA9 20mil
27 PVCCR OUTPL CA43
Close to UA2 HCB2012KF-121T50_0805 1000P_0402_50V7K

2
28 PVCCL 23 OUTNL OUTPL 1 2 SPK_L2+_CONN 2 1
Pin7,15,16,27,28 PVCCL OUTNL
5A/120ohm/100MHz
RA82 CA73 22 BSNL 1 2 CA75
CA87 1 2 SPK_CD_L 1 2 13.3K_0402_1% 1 2 1U_0402_6.3V6K~D AMP_LEFT_C 3 BSNL 0.22U_0603_25V7K LA11
45 INT-SPK-L LINP CA44
1U_0603_25V6K RA99 CA76 HCB2012KF-121T50_0805 1000P_0402_50V7K
1 2 1 2 4 CA77 OUTNL 1 2 SPK_L1-_CONN 2 1
D
10.7K_0402_5% 1 2 5.9K_0402_5% 1U_0402_6.3V6K~D LINN 17 BSPR 1 2 0.22U_0603_25V7K
D
BSPR
5A/120ohm/100MHz
RA83
45 AMP_RIGHT_C 18 OUTPR LA12
OUTPR CA45
RA84 CA79 HCB2012KF-121T50_0805 1000P_0402_50V7K
45 INT-SPK-R CA88 1 2 SPK_CD_R 1 2 1 2 1U_0402_6.3V6K~D AMP_RIGHT_C 12 20 OUTNR OUTPR 1 2 SPK_R2+_CONN 2 1
1U_0603_25V6K CA81 RINP OUTNR +GVDD 5A/120ohm/100MHz
12.4K_0402_1% 2 1 RA98 1 2 11 21 BSNR 1 2
5.76K_0402_5% 1U_0402_6.3V6K~D RINN BSNR LA13
CA46

1
2 1 CA82 HCB2012KF-121T50_0805 1000P_0402_50V7K
RA85 RA87 0.22U_0603_25V7K RA86 OUTNR 1 2 SPK_R1-_CONN 2 1
10.7K_0402_5% 100K_0402_5% 51K_0402_1% 5A/120ohm/100MHz
@ GIN0 5 14
1 2 GAIN0 PBTL
+3VALW EMI

2
GIN1 6 10 PLIMIT JSPK1
RA88 GAIN1 PLIMIT +GVDD SPK_L2+_CONN 1
0_0402_5% SPK_L1-_CONN 2 1
2

1
1U_0603_25V6K

1U_0603_25V6K
TPA3113 for Speaker 1 2 EAPD_R 1 9 +GVDD SPK_R2+_CONN 3 5
45,46 SPK_MUTE# SD# GVDD 3 G5

CA86
RA89 SPK_R1-_CONN 4 6
4 G6

CA85
1 2 2 10K_0402_1%
+5VS RA90 RA97 0_0402_5% FAULT# 24 MOLEX_53398-0471

2
100K_0402_5% 13 PGND 19

2
29 NC PGND 8
INPUT GND AGND
GAIN1 GAIN0 AV(inv)

2
IMPEDANCE
2

@ @ TPA3113D2PWPR_HTSSOP28
RA91 RA92
100K_0402_1% 100K_0402_1% 0 0 20dB 60Kohm
2 1

2 1

GIN0 GIN1 0 1 26dB 30Kohm


RA93 RA94
100K_0402_1% 100K_0402_1% 1 0 32dB 15Kohm
1

1 1 36dB 9Kohm
RA54 1 2 0_0402_5%~D

C C

Speaker amp impedance of JBL is 4 ohm.

B+_BIAS

2 1
RA109 0_1206_5%

10U_1206_25V6

10U_1206_25V6

10U_1206_25V6

10U_1206_25V6

10U_1206_25V6

10U_1206_25V6
1 1 1 1 1 1
RC

CA123

CA124

CA125

CA126

CA127

CA128
2 2 2 2 2 2

15
16

27
28
UA10
2 1 14 26

PVCC
PVCC

PVCC
PVCC
B+_BIAS PBTL BSPL
RA112 10K_0402_1%
1
1 EMI
45,46 SPK_MUTE# SD# CA129 0.47U_0402_6.3V6K
1 2 2
RA95 0_0402_5% FAULT# 25 2
3 OUTPL
INPL
4 TPA3110D1 23 1 2 FBM-11-160808-601-T_0603
INT-SUB-SPK RA118 1 2 9.31K_0402_1% INNL OUTNL LA14
45 INT-SUB-SPK

1
2
RA117 1 2 10,5K_0402_1% 1 2 12 CA130 CA41
CA133 0.1U_0402_25V6 INPR
330P_0402_50V7K~D

2
2 1 1 2 11 22 1 2
4.99K_0402_1% RA101 CA134 0.1U_0402_25V6 INNR BSNL RA110 10_0402_1% 1000P_0402_50V7K 1 JWFER1
1 2 7 21 W=40mil SUB_L+ 1
Woofer Amp Table B+_BIAS AVCC BSNR 1
10U_0805_25V6K

RA113 10_0402_1% SUB_R- 2


2
1

B
CA135
W=40mil 3 B
4 G
Input Impedance
2

8 20 1 2 G
G1 G0 GAIN(dB) (Rl) (Kohm) AGND OUTNR LA15 FBM-11-160808-601-T_0603 MOLEX_53398-0271~D

1
CONN@
18 CA131 2
OUTPR
0 0 20 60 1 330P_0402_50V7K~D CA42

2
9 1 2
GVDD CA132 RA111 10_0402_1% 1000P_0402_50V7K
2 1 10 1
0 1 26 30 PLIMIT 2
RA114 17
B+_BIAS 45.3K_0402_1% GAIN01 5 BSPR
GAIN0
PGND
PGND
1U_0603_25V6K

13 0.47U_0402_6.3V6K
1 0 32 15
GND

NC
1

GAIN11 6
GAIN1
1

CA136

RA115
100K_0402_1%

100K_0402_1%
1

1 1 36 9 10K_0402_5%
19
24
29

TPA3111D1PWPR_TSSOP28~D
2

RA105 @ RA106
2

@
2

GAIN01 GAIN11
2

RA107 RA108
0_0402_5% 0_0402_5% For 32dB design, RA24 populated and
RA36 is depopulated.
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/02 Deciphered Date 2012/06/02 Title
Amp TPA6017/subwoofer/ Audio Jack

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9332P
Date: Friday, December 14, 2012 Sheet 46 of 56
5 4 3 2 1
5 4 3 2 1

+3.3V_F347 0_0603_5%~D
@
D D
R1 1 2 +3.3V_F347_R

0.1U_0402_16V4Z~D

22P_0402_50V8J~D
1U_0805_10V7

0.1U_0402_16V4Z~D
1 2

C1

C2
1 1

C3
+3.3V_F347

C4
2 1 I2C_DAT 4.7K_0402_5%~D 2 1 R2
2 2
place R1564 as close as U602 I2C_CLK 4.7K_0402_5%~D 2 1 R3
U1
6 2 SPI_MOCLK 1 2 SPI_MOCLK_R
VDD P0.0 1 SPI_MOSO R4 0_0402_5%~D
USB20_P6 4 P0.1 32 SPI_MOSI
20 USB20_P6 USB20_N6 5 D+ P0.2 31 SPI_MOCS#
1 2 0_0603_5%~D 20 USB20_N6 D- P0.3 30
R5 I2C_DAT
+5VALW P0.4 I2C_DAT 48,53
W=40mils 7 29 I2C_CLK
+3.3V_F347 REGIN P0.5 I2C_CLK 48,53
R6 1 @ 2 0_0603_5%~D 8 28 C5 @ 1 2 0.1U_0402_16V4Z~D
+5VS VBUS P0.6 27 R7 1 2 1K_0402_5%~D +3.3V_F347
1 2 9 P0.7
+3.3V_F347 RST#/C2CK
R8 10 26 SLP_S3
P3.0/C2D P1.0

1U_0805_10V7

0.1U_0402_16V4Z~D
1 1 1K_0402_1%~D 25 BATT_CHG_LED 10K_0402_5% 2 1 R9
P1.1 +3.3V_F347

C6

C7
18 24 ACIN#
17 P2.0 P1.2 23 LID_SW_IN#_D 2 1 LID_SW_IN#
16 P2.1 P1.3 22 BATT_LOW_LED LID_SW_IN# 19,43,45,48,53
D70
2 2 15 P2.2 P1.4 21 SLP_S5 SDMK0340L-7-F_SOD323-2~D
14 P2.3 P1.5 20 C8 @ 1 2 0.1U_0402_16V4Z~D
13 P2.4 P1.6 19 C9 @ 1 2 0.1U_0402_16V4Z~D
12 P2.5 P1.7
+3.3V_F347 11 P2.6 3
P2.7 GND
+3.3V_F347 JP1 C8051F347-GQ_LQFP32_7X7

@
1
1
0.1U_0402_16V4Z

C11

C12

C13

C14

C15

C16

C17

C18
2
2 3
1 3 We are Green SA00003IR90
C10

4
4 5 U2
5 1 1 1 1 1 1 1 1
6 SPI_MOSI 15_0402_5% 2 1 R10 5 2 R11 1 2 15_0402_5% SPI_MOSO
2 6 +3.3V_F347 DI SO
7 SPI_MOCLK_R 15_0402_5% 2 1 R12 6
C
GND1 8 2 2 2 2 2 2 2 2 CLK C
GND2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
Cloase to JP1 CONN@ 1 2 SPI_MOCS# 1
R13 10K_0402_5%~D CS
AMPHE_G846A06201EU
1 2 7
R14 10K_0402_5%~D HOLD
1 2 3
R15 10K_0402_5%~D WP
8 4
+3.3V_F347 VCC VSS

0.1U_0402_16V4Z~D

22P_0402_50V8J~D
1 EN25Q80A-100HIP_SO8

C19
1

C20
2
2

+3.3V_F347
1

R16 DEVICE SMBUS ADDRESS


8PR4 100K_0402_5%
MAXIM - LED 0100 000b
2

SLP_S3 MAXIM - GPIO 0100 001b


SSM3K7002FU_SC70-3~D

Q1
I2C EEPROM 1010 000b
1

D +3.3V_F347
2
17,43 PM_SLP_S3#
G
1

S +3VALW +3.3V_F347
3

R17
100K_0402_5% J11 @
2 1
2 1
2

SLP_S5 JUMP_43X118
SSM3K7002FU_SC70-3~D

Q2
+3.3V_F347 Q3
1

B D B
SI3456DDV-T1-GE3_TSOP6~D
2
17,43 PM_SLP_S5#
1

D
G 6

S
R18 S 5 4
3

4.7U_0603_6.3V6M~D
100K_0402_5% 2

0.1U_0402_25V6K~D

100K_0402_1%~D
1

1
1 1

G
2

R19

C22
C21
ACIN#

3
SSM3K7002FU_SC70-3~D

Q4
B+_BIAS +3.3V_F347 behavior
1

D 2 2
STATE

2
2 +3.3V_F347 +3VALW R20 @
17,29,43,57,64 ACIN
G 100K_0402_5%
S
S0 S3 S4 S5
3

1 2
R21 R22
100K_0402_5% AC IN ON ON ON ON

300K_0402_5%~D

0.1U_0402_25V6K~D
100K_0402_5%

2
1
2

R23

C23
+3.3V_F347 BATT_LOW_LED BAT only ON ON OFF OFF
SSM3K7002FU_SC70-3~D

Q6 5
6

Q24B
AC mode battery full in S5:turn off ELC controller
1

D 2

1
R24 2 DMN66D0LDW-7_SOT363-6~D
43 BATT_LOW_LED# 2 DMN66D0LDW-7_SOT363-6~D
100K_0402_5% G
43 3V_F347_ON Q24A
S
3

1
2

BATT_CHG_LED R25
SSM3K7002FU_SC70-3~D

Q8
100K_0402_5%
1

D
2

2
43 BATT_CHG_LED#
G
S
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
ELC (1)

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 47 of 56
5 4 3 2 1
5 4 3 2 1

KSI[0..7]
43,53 KSI[0..7]

53 7313_INT#
L/R Tron, Logo, Alien Head, TP
D
+3.3V_F347
+3.3V_F347
Hot Key Conn. Hot Key Conn. D

PWM Key Pad

0.1U_0402_16V4Z~D
1 R26 2 1

C24
4.7K_0402_1%~D
4.7K_0402_1%~D
JKB3
1 U3 +5V_KP_BL
1 JKB2
2 1
R27

22 21 2 43 KP_DET# KP_DET# 1 2 KP_DET#


INT#/O16 V+ KB_LED_R5_DRV# 3 2 KSO16 3 1 2 4 KSO16
53 KB_LED_R5_DRV# 3 43,53 KSO16 3 4
I2C_CLK 19 1 LTRON_LED_R_DRV# KB_LED_G5_DRV# 4 KSI0 5 6 KSI0
47,53 I2C_CLK 20 SCL P0 2 53 KB_LED_G5_DRV# 5 4 7 5 6 8
I2C_DAT LTRON_LED_G_DRV# KB_LED_B5_DRV# KSI5 KSI5
2

47,53 I2C_DAT SDA P1 3 53 KB_LED_B5_DRV# 6 5 9 7 8 10


LTRON_LED_B_DRV# KSI1 KSI1
AD0_0 18 P2 4 RTRON_LED_R_DRV# 6 KSI4 11 9 10 12 KSI4
AD0_1 23 AD0 P3 5 RTRON_LED_G_DRV# 7 KSI2 13 11 12 14 KSI2
AD0_2 24 AD1 P4 6 RTRON_LED_B_DRV# 8 GND KSI3 15 13 14 16 KSI3
4.7K_0402_1%~D

AD2 P5 7 ALIEN_LED_R_DRV#_1 9 GND GND 17 15 16 18 GND


P6 GND 17 18
1

53 TP_LED_R_DRV# TP_LED_R_DRV# 14 8 ALIEN_LED_G_DRV#_1 10 GND 19 20 GND


P12 P7 GND 19 20
R28

R29

53 TP_LED_G_DRV# TP_LED_G_DRV# 15 10 ALIEN_LED_B_DRV#_1


TP_LED_B_DRV# 16 P13 P8 11 LOGO_LED_R_DRV# MOLEX_52559-0652 ACES_50611-0100N-001_10P
53 TP_LED_B_DRV# P14 P9
17 12 LOGO_LED_G_DRV# CONN@
OSC P10
4.7K_0402_1%~D

13 LOGO_LED_B_DRV#
CONN@
2

9 P11 25
GND GND
MAX7313DATG+T_TQFN-EP24_4X4~D

+3.3V_F347 +3.3V_F347

Reserve for Viking


4.7K_0402_1%~D

4.7K_0402_1%~D

4.7K_0402_1%~D

0.1U_0402_16V4Z
1
1

C25
Indicator, Power
R30

R31

R32

+5VS
U4 2
22 21
2

INT#/O16 V+

0.1U_0402_16V4Z
7313_INT# I2C_CLK 19 1
C I2C_DAT 20 SCL P0 2 C
SDA P1 1

C26
3 +5VS
P2

0.1U_0402_16V4Z
AD2_0 18 4 LED_R_7313#_1 LED_R_7313#_1 53 20mil
AD2_1 23 AD0 P3 5 LED_G_7313#_1 JLOGO1
AD1 P4 LED_G_7313#_1 53 2
AD2_2 24 6 LED_B_7313#_1 LED_B_7313#_1 53 1 1
AD2 P5 1

C27
7 2
P6 2
1
4.7K_0402_1%~D

HDD_R_7313# 14 8 LID_SW 3 JTRONF


P12 P7 3
R33

HDD_G_7313# 15 10 LOGO_LED_R_DRV# 4 1
HDD_B_7313# 16 P13 P8 11 PWR_R_7313# LOGO_LED_G_DRV# 5 4 2 2 1
P14 P9 PWR_R_7313# 53 5 2
17 12 PWR_G_7313# PWR_G_7313# 53 LOGO_LED_B_DRV# 6 RTRON_LED_R_DRV# 3
OSC P10 13 PWR_B_7313# 7 6 RTRON_LED_G_DRV# 4 3
PWR_B_7313# 53
2

9 P11 25 ALIEN_LED_R_DRV#_1 8 7 RTRON_LED_B_DRV# 5 4


GND GND ALIEN_LED_G_DRV#_1 9 8 LTRON_LED_R_DRV# 6 5
MAX7313DATG+T_TQFN-EP24_4X4~D ALIEN_LED_B_DRV#_1 10 9 LTRON_LED_G_DRV# 7 6
11 10 13 LTRON_LED_B_DRV# 8 7
HDD_B 12 11 GND 14 9 8 11
HDD_B 53 12 GND 9 G11
10 12
10 G12
3

ACES_50228-01271-001 ACES_50228-01071-001

DMN66D0LDW-7_SOT363-6~D CONN@ CONN@


5
Q9B

LOGO Board CONN


4

+5VS
HDD_B_7313#
TRON LED Board (F) CONN
100K_0402_5%~D

HDD_R HDD_R 53
1
R34

+5VALW
6

100K_0402_5%~D
2

DMN66D0LDW-7_SOT363-6~D
R35

SATA_LED_ACT 2
Q10A
B+_BIAS +5VS Q11 +5VS_TP_LED
1

SI3456DDV-T1-GE3_TSOP6~D +5VS +5VS


2

D
6

S
300K_0402_5%~D

0.1U_0402_16V4Z

0.1U_0402_16V4Z
HDD_R_7313# 5 4

2
B B

0.1U_0402_16V4Z
HDD_G HDD_G 53 LID_SW 2
DMN66D0LDW-7_SOT363-6~D

R36

1U_0603_10V4Z~D
2 1 1 1 1
16 PCH_SATALED# Q9A

C29

C30

C31
1

G
6

C32
1

3
3

1
2 2 2
2 DMN66D0LDW-7_SOT363-6~D 2 JTRONL JTRONR
5 19,43,45,47,53 LID_SW_IN# Q12A 1 1
EN_TPLED
Q10B 2 1 2 1
SSM3K7002FU_SC70-3~D
LTRON_LED_R_DRV# RTRON_LED_R_DRV#
1

3 2 3 2

1.5M_0402_5%~D

0.1U_0402_25V6K~D
1 LTRON_LED_G_DRV# RTRON_LED_G_DRV#
4

4 3 4 3
1

1
D

R37
DMN66D0LDW-7_SOT363-6~D LTRON_LED_B_DRV# RTRON_LED_B_DRV#
5 4 5 4

C33
2
43 EN_TPLED# 6 5 6 5
HDD_G_7313# G
SATA_LED_ACT Q15 2 6 6
S
3

7 7

2
8 GND 8 GND
GND GND
3

Reference AD2 AD1 AD0 MAX7313 ACES_50228-0067N-001 ACES_50228-0067N-001

CONN@ CONN@

Tron Lights,TP
LID_SW 5
Q12B Touchpad LED circuit
U605 0 1 0 TRON LED Board (L) CONN TRON LED Board (R) CONN
4

A-panel,B-Panel Logo DMN66D0LDW-7_SOT363-6~D

Power Button,
U608 0 1 1 Media and Status LED Color

Button,
U? 1 0 0 Indicator Brightness

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
ELC (2)

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 48 of 56
5 4 3 2 1
A B C D E

1 1

RF
+5VS

Close to JHDD1
+3VS
Free Fall Sensor

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D

47P_0402_50V8J~D
1 1 1 1 1

CN4

CN10
0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

CN2

CN3

CN5
2 2 2 2 2
1 1

C34

C35
@ @

2 @2
UN4
LNG3DM 10
CONN@
1 RES 13 +5VS +5VS
14 VDD_IO RES 15 ACES_88279-20041-FN-P01
VDD RES 16 41 42
FFS_INT1 11 RES G1 G2
17 FFS_INT1 INT 1
21,50 FFS_INT2 FFS_INT2 9 5 39 40
INT 2 GND 12 37 39 40 38
7 GND 35 37 38 36
PCH_SMBDATA 6 SDO/SA0 33 35 36 34
12,13,14,15,19,50,51,53,6 PCH_SMBDATA 4 SDA / SDI / SDO 31 33 34 32
PCH_SMBCLK
12,13,14,15,19,50,51,53,6 PCH_SMBCLK SCL/SPC 2 29 31 32 30
8 NC 3 SATA_PTX_DRX_P0_C 27 29 30 28 SATA_PTX_DRX_P0_C
CS NC SATA_PTX_DRX_N0_C 25 27 28 26 SATA_PTX_DRX_N0_C
LNG3DMTR_LGA16_3X3~D 23 25 26 24
FFS_INT1 connect to PCH GPIO & EC SATA_PRX_DTX_N0_C 21 23 24 22 SATA_PRX_DTX_N0_C
discuss with BIOS to use which pin SATA_PRX_DTX_P0_C 19 21 22 20 SATA_PRX_DTX_P0_C
17 19 20 18
SATA_PRX_DTX_P1_C 15 17 18 16 SATA_PRX_DTX_P1_C
2 SATA_PRX_DTX_N1_C 13 15 16 14 SATA_PRX_DTX_N1_C 2
11 13 14 12
SATA_PTX_DRX_N1_C 9 11 12 10 SATA_PTX_DRX_N1_C
SATA_PTX_DRX_P1_C 7 9 10 8 SATA_PTX_DRX_P1_C
5 7 8 6
3 5 6 4
21,49 HDD2_DETECT# 3 4 HDD2_DETECT# 21,49
FFS_INT2_CONN 1 2 FFS_INT2_CONN
49,50 FFS_INT2_CONN 1 2 FFS_INT2_CONN 49,50
JHDD1

+3VS

+3VS

0.01U_0402_16V7K

0.1U_0402_25V6K
1 1
@
0.01U_0402_16V7K

0.1U_0402_25V6K

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1

1
CN66

CN62
1 1 @ @
2 2

RN50

RN49

RN58

RN54
@
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
+3VS
1

1
CN23

CN24

@ @
2 2
RN5

RN46

RN6

RN7
UN5

2
+3VS RN48 1 2 0_0402_5% 7 10
EN VDD 20
UN1 CN6 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_R 1 VDD
2

2
1 2 0_0402_5% 7 10 16 SATA_PTX_DRX_P0 1 2 0.01U_0402_16V7K~D 2 A_INp 6
RN1 CN7 SATA_PTX_DRX_N0_R
EN VDD 20 16 SATA_PTX_DRX_N0 A_INn NC 16 HDD_REXT_SATA0
CN15 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_R 1 VDD CN9 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P0_RC 5 NC
16 SATA_PTX_DRX_P1 A_INp 16 SATA_PRX_DTX_P0 B_OUTp
CN16 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N1_R 2 6 16 SATA_PRX_DTX_N0 CN8 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_RC 4 9 HDD_A0_PRE0
16 SATA_PTX_DRX_N1 A_INn NC 16 HDD_REXT_SATA B_OUTn A_PRE0 8 HDD_B0_PRE0
3
CN18 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P1_RC 5 NC RN51 1 @ 2 0_0402_5% HDD_A0_PRE1 19 B_PRE0 3
16 SATA_PRX_DTX_P1 B_OUTp +3VS A_PRE1
16 SATA_PRX_DTX_N1 CN17 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N1_RC 4 9 HDD_A_PRE0 RN52 1 @ 2 0_0402_5% HDD_B0_PRE1 17 15 SATA_PTX_DRX_P0_RC CN65 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_C
B_OUTn A_PRE0 8 HDD_B_PRE0 B_PRE1 A_OUTp 14 SATA_PTX_DRX_N0_RC CN60 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N0_C
RN3 1 @ 2 0_0402_5%
HDD_A_PRE1 19 B_PRE0 RN55 1 @ 2 0_0402_5% 18 A_OUTn
+3VS A_PRE1 TEST
RN2 1 @ 2 0_0402_5%
HDD_B_PRE1 17 15 SATA_PTX_DRX_P1_RC CN19 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P1_C 3 11 SATA_PRX_DTX_P0_R CN59 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P0_C
B_PRE1 A_OUTp 14 SATA_PTX_DRX_N1_RC CN20 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N1_C 13 GND B_INp 12 SATA_PRX_DTX_N0_R CN67 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_C
RN4 1 @ 2 0_0402_5% 18 A_OUTn 21 GND B_INn
3 TEST 11 SATA_PRX_DTX_P1_R CN21 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P1_C EPAD
13 GND B_INp 12 SATA_PRX_DTX_N1_R CN22 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N1_C PS8520CTQFN20GTR2-A_TQFN20_4X4
21 GND B_INn
EPAD
PS8520CTQFN20GTR2-A_TQFN20_4X4

HDD_B0_PRE0 RN53 1 @ 2 0_0402_5%

HDD_B0_PRE1 RN56 1 @ 2 0_0402_5%


HDD_B_PRE0 RN8 1 @ 2 0_0402_5%
HDD_A0_PRE1 RN47 1 @ 2 0_0402_5%
HDD_B_PRE1 RN9 1 @ 2 0_0402_5%
HDD_A0_PRE0 RN29 1 2
HDD_A_PRE1 RN10 1 @ 2 0_0402_5% 2K_0402_5%
Pin 20: Pin 9: HDD_REXT_SATA0 RN57 1 2
HDD_A_PRE0 RN11 1 2 5.1K_0402_1%
PARADE PS8250B: PARADE PS8250B:
2K_0402_5% Pin 20: Pin 9:
Reserve RN46, Mount RN12 Reserve RN11. HDD_REXT_SATA 1 2
PARADE PS8250B: PARADE PS8250B:
RN12 5.1K_0402_1%
Reserve R49, Mount R57 Reserve R29.
PERICOM PI3EQX6741ST: PERICOM PI3EQX6741ST:
Mount RN46, Reserve RN12 Reserve RN11
PERICOM PI3EQX6741ST: PERICOM PI3EQX6741ST:
Mount R49, Reserve R57 Reserve R29
ASMEDIA ASM1466: ASMEDIA ASM1466:
Mount RN46, Reserve RN12 Mount RN11 to pull down
ASMEDIA ASM1466: ASMEDIA ASM1466:
Mount R49, Reserve R57 Mount R29 to pull down

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
SATA HDD1 & HDD2/FFS

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 49 of 56
A B C D E
A B C D E

ODD_DA#_R
+5VS_ODD SATA ODD Conn.
ODD power

1
+5VS QN2 +5VS_ODD D

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D
SI3456DDV-T1-GE3_TSOP6~D 2 QN4
43 ODD_EJECT#
1 1 1 1 G 2N7002E-T1-E3_SOT23-3 JODD1

CN35

CN36

CN37

CN38
6 S 1

3
+3VS 1

1U_0402_6.3V6K~D
B+_BIAS 5 4 2
2 3 2
1 2 2 2 2 3

CN39
1 4
+5VS_ODD 4

2
1 1
5

G
RN26 6 5
1, Host generate Low pulse 40ms to eject ODD

3
300K_0402_5%~D 2 RN45 1 2 0_0402_5%~D ODD_DA#_R 7 6
17 ODD_DA#
2, After this pulse, signal remain high and no 21 ODD_DETECT# 8 7
9 8
pulse is allowed within 7s

1
ODD_EN SATA_PRX_DTX_P4_C 10 9
Placea caps. near ODD CONN. +5VS SATA_PRX_DTX_N4_C 11 10
11

2
1.5M_0402_5%~D

0.1U_0402_25V6K~D
1 12
12

1
D

CN40
SATA_PTX_DRX_N4_C 13
13

1
RN27
2 QN1 +3VS SATA_PTX_DRX_P4_C 14
21 ODD_EN# 15 14
G SSM3K7002FU_SC70-3~D
2 @ RN28
@RN28 16 15
S

1
100K_0402_5%~D FFS_INT2_CONN 17 16 21
49,50 FFS_INT2_CONN 17 GND1

2
G
18 22

2
+5VS 19 18 GND2 23
FFS_INT2 3 1 1 2 FFS_INT2_CONN 20 19 GND3 24
21,49 FFS_INT2 FFS_INT2_CONN 49,50 20 GND4

D
DN1 SDM10U45-7_SOD523-2~D
E-T_0870K-F20C-22L
QN3 CONN@
SSM3K7002FU_SC70-3~D
+3VS

ODD Redriver

0.01U_0402_16V7K

0.1U_0402_25V6K
1 1
@

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1

1
CN33

CN34
@ @ ODD_B_PRE0 RN21 1 @ 2 0_0402_5%
2 2

RN17

RN18

RN19

RN20
+3VS ODD_B_PRE1 RN22 1 @ 2 0_0402_5% Pin 20: Pin 9:
PARADE PS8250B: PARADE PS8250B:
UN2 ODD_A_PRE1 RN23 1 @ 2 0_0402_5%

2
RN13 1 2 0_0402_5% 7 10 Reserve RN18, Mount RN25 Reserve RN24.
EN VDD 20 ODD_A_PRE0 RN24 1 @ 2
CN27 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P4_R 1 VDD 2K_0402_5%
16 SATA_ODD_PTX_DRX_P4 A_INp PERICOM PI3EQX6741ST: PERICOM PI3EQX6741ST:
2 CN28 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N4_R 2 6 ODD_REXT_SATA 1 2 2
16 SATA_ODD_PTX_DRX_N4 A_INn NC 16 ODD_REXT_SATA RN25 4.42K_0402_1%
Mount RN18, Reserve RN25 Reserve RN24
CN25 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P4_R 5 NC
16 SATA_ODD_PRX_DTX_P4 B_OUTp
16 SATA_ODD_PRX_DTX_N4 CN26 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N4_R 4 9 ODD_A_PRE0 ASMEDIA ASM1466: ASMEDIA ASM1466:
B_OUTn A_PRE0 8 ODD_B_PRE0
B_PRE0 Mount RN18, Reserve RN25 Mount RN24 to pull down
+3VS RN15 1 @ 2 0_0402_5%
ODD_A_PRE1 19
RN14 1 @ 2 0_0402_5%
ODD_B_PRE1 17 A_PRE1 15 SATA_PTX_DRX_P4_RC CN29 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P4_C
B_PRE1 A_OUTp 14 SATA_PTX_DRX_N4_RC CN30 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N4_C
RN16 1 @ 2 0_0402_5% 18 A_OUTn
3 TEST 11 SATA_PRX_DTX_P4_RC CN31 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P4_C
13 GND B_INp 12 SATA_PRX_DTX_N4_RC CN32 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N4_C
21 GND B_INn
EPAD
PS8520CTQFN20GTR2-A_TQFN20_4X4

+3VS

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D
1 1 1 1
CN51

CN52

CN53

CN54
+1.5VS
2 2 2 2

1000P_0402_50V7K~D

0.1U_0402_16V4Z~D

1U_0402_6.3V4Z~D

10U_0805_10V4Z~D
1 1 1 1

CN55

CN56

CN57

CN58
3 3
Placea caps. near JMSATA1 CONN.
@2 @2 @2 @2
+3VS +3VS +1.5VS

JMSATA
1 2 Placea caps. near JMSATA1 CONN.
PAD~D T62 @ 3 1 2 4
PAD~D T63 @ 5 3 4 6
7 5 6 8
9 7 8 10
11 9 10 12
13 11 12 14
15 13 14 16
15 16

PAD~D T61 @ 17 18
PAD~D T59 @ 19 17 18 20
21 19 20 22
CN43 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P5_C 23 21 22 24
16 MSATA_PRX_DTX_P5 23 24
16 MSATA_PRX_DTX_N5 CN44 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N5_C 25 26
27 25 26 28
29 27 28 30 PCH_SMBCLK
1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N5_C 31 29 30 32 PCH_SMBDATA PCH_SMBCLK 12,13,14,15,19,49,51,53,6
CN42
16 MSATA_PTX_DRX_N5 1 2 0.01U_0402_16V7K~D 33 31 32 34 PCH_SMBDATA 12,13,14,15,19,49,51,53,6
CN41 SATA_PTX_DRX_P5_C
16 MSATA_PTX_DRX_P5 35 33 34 36
37 35 36 38
39 37 38 40
41 39 40 42
43 41 42 44
PAD~D T65 @ 45 43 44 46
PAD~D T64 @ 47 45 46 48
RN43 1 2 0_0402_5%~D EC_TX_DAT 49 47 48 50
43 E51TXD_P80DATA 49 50
RN44 1 2 0_0402_5%~D EC_RX_CLK 51 52
43 E51RXD_P80CLK 53 51 52 54
G1 G2
2
100K_0402_5%~D
RN59

FOX_AS0B221-S90Q-7H
4 4

CONN@
1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
SATA ODD/mSATA

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 50 of 56
A B C D E
A B C D E

RF
RF
+1.5VS +3VS

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
47P_0402_50V8J~D

47P_0402_50V8J~D
1 1 1 1 1 1 1 1 1 1

C36

C37

C38

C48

C39

C40

C41

C47
WLAN @
2
@
2
@
2 2 2 @2 @2 2

JMINI1
17,43,44 PCIE_WAKE# PCIE_WAKE# @ RE12 1 2 0_0402_5%~D 1 2
WAKE# 3.3V +3VS
COEX2 R38 1 @ 2 0_0402_1% 3 4
COEX1 R39 1 @ 2 0_0402_1% 5 NC GND 6
NC 1.5V +1.5VS
18 MINI1CLK_REQ# MINI1CLK_REQ# 7 8 RE31 1 @ 2 0_0402_1%
9 CLKREQ# NC 10 1 2 LPC_FRAME# 19,43
RE26 @ 0_0402_1%
11 GND NC 12 1 2 LPC_AD3 19,43
CLK_PCIE_MINI1# RE27 @ 0_0402_1%
18 CLK_PCIE_MINI1# 13 REFCLK- NC 14 1 2 LPC_AD2 19,43
CLK_PCIE_MINI1 RE28 @ 0_0402_1%
18 CLK_PCIE_MINI1 15 REFCLK+ NC 16 1 2 LPC_AD1 19,43
RE29 @ 0_0402_1%
GND NC LPC_AD0 19,43
RE32 1 @ 2 0_0402_1% 17 18
17,43,44,51,53,6 PLT_RST# 19 NC GND 20 WL_OFF#
18 CLK_DEBUG 21 NC NC 22 WL_OFF# 17
PLT_RST#
23 GND PERST# 24 PLT_RST# 17,43,44,51,53,6
20 PCIE_PRX_WLANTX_N5 PCIE_PRX_WLANTX_N5
PCIE_PRX_WLANTX_P5 25 PERn0 +3.3Vaux 26
20 PCIE_PRX_WLANTX_P5 PERp0 GND
27 28
C68 0.1U_0402_10V7K~D 29 GND +1.5V 30
PCIE_PTX_WLANRX_N5 1 2 PCIE_PTX_WLANRX_N5_C 31 GND SMB_CLK 32 WiGi_RADIO_DIS#_R RE22 1 2 0_0402_5%~D
20 PCIE_PTX_WLANRX_N5 1 2 PCIE_PTX_WLANRX_P5_C 33 PETn0 SMB_DATA 34 WiGi_RADIO_DIS# 21
PCIE_PTX_WLANRX_P5
20 PCIE_PTX_WLANRX_P5 35 PETp0 GND 36 +3VS
USB20_N4
37 GND USB_D- 38 USB20_P4 USB20_N4 20
C60 0.1U_0402_10V7K~D
39 NC USB_D+ 40 USB20_P4 20
+3VS NC GND
41 42 WIGI_LED#
43 NC LED_WWAN# 44 WLAN_LED#
45 NC LED_WLAN# 46 BT_LED#
NC LED_WPAN#

1
47 48
49 NC +1.5V 50
NC GND

2
BT_ON# 1 2 BT_ON#_R 51 52 @ R45
17 BT_ON# NC +3.3V D3
1K_0402_1%~D RE119 100K_0402_5%~D
53 54 WiGi_RADIO_DIS#_R 2 1 WiGi_RADIO_DIS# WIGI_LED# 1 6 WLES ON/OFF LED# WLES ON/OFF LED# 43,53

2
GND GND

1
2 Q23A 2
BELLW_80003-4041 SDMK0340L-7-F R59 DMN66D0LDW-7_SOT363-6~D

5
CONN@ 100K_0402_5%~D

WLAN_LED# 4 3

2
1
Q23B
R66 DMN66D0LDW-7_SOT363-6~D

2
G
100K_0402_5%~D

BT_LED# 3 1

D
Q18
SSM3K7002FU_SC70-3~D

Display Mini Card (DMC)


+1.5VS +1.5VS_DMC
+3VS +3VS_DMC L1
L2 2 1
2 1 BLM18AG601SN1D_0603~D

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
BLM18PG330SN1D_2P~D
+3VS_DMC

4.7U_0805_10V4Z~D

0.1U_0402_16V4Z~D
1 1 1

C42

C43

C44
JDMC1 1 1
+1.5VS_DMC

C45

C46
PCIE_WAKE# @ RE30 1 2 0_0402_5%~D 1 2
COEX2 R40 1 @ 2 0_0402_1% 3 1 2 4
COEX1 R41 1 @ 2 0_0402_1% 5 3 4 6 2 2 2
18 MINI2CLK_REQ# MINI2CLK_REQ# 7 5 6 8 2 2
9 7 8 10
CLK_PCIE_MINI2# 11 9 10 12
18 CLK_PCIE_MINI2# 13 11 12 14
CLK_PCIE_MINI2
18 CLK_PCIE_MINI2 15 13 14 16
15 16

17 18
19 17 18 20 DMC_RADIO_OFF#
21 19 20 22 DMC_RADIO_OFF# 21
PLT_RST#
PCIE_PRX_WANTX_N6 23 21 22 24
3 20 PCIE_PRX_WANTX_N6 23 24 3
20 PCIE_PRX_WANTX_P6 PCIE_PRX_WANTX_P6 25 26
27 25 26 28
C70 0.1U_0402_10V7K~D 29 27 28 30 MINI2_SMBCLK RE33 1 @ 2 0_0402_5%~D PCH_SMBCLK
1 2 PCIE_PTX_WANRX_N6_C 31 29 30 32 PCH_SMBCLK 12,13,14,15,19,49,50,53,6
PCIE_PTX_WANRX_N6 MINI2_SMBDATA RE34 1 @ 2 0_0402_5%~D PCH_SMBDATA
20 PCIE_PTX_WANRX_N6 PCIE_PTX_WANRX_P6 1 2 PCIE_PTX_WANRX_P6_C 33 31 32 34 PCH_SMBDATA 12,13,14,15,19,49,50,53,6
20 PCIE_PTX_WANRX_P6 35 33 34 36 USB20_N5
37 35 36 38 USB20_N5 20
C69 0.1U_0402_10V7K~D USB20_P5
39 37 38 40 USB20_P5 20
+3VS_DMC 39 40
41 42
43 41 42 44
45 43 44 46
47 45 46 48
49 47 48 50 R44
51 49 50 52 1M_0402_5%~D
51 52 1 2

18 DMC_PCH_DET# DMC_PCH_DET# 53 54 DP_DMC_HPD DP_DMC_HPD 39


CPU_MXM_DMC_AUXN 55 53 54 56 +3VS_DMC
39 CPU_MXM_DMC_AUXN 57 55 56 58
CPU_MXM_DMC_AUXP
39 CPU_MXM_DMC_AUXP 59 57 58 60 CPU_MXM_DMC_N3
61 59 60 62 CPU_MXM_DMC_N3 39
CPU_MXM_DMC_P3
63 61 62 64 CPU_MXM_DMC_P3 39
CPU_MXM_DMC_N2 CPU_MXM_DMC_AUXN R42 1 @ 2 100K_0402_5%~D
39 CPU_MXM_DMC_N2 65 63 64 66
CPU_MXM_DMC_P2 CPU_MXM_DMC_AUXP R43 1 @ 2 100K_0402_5%~D
39 CPU_MXM_DMC_P2 67 65 66 68 CPU_MXM_DMC_N1
69 67 68 70 CPU_MXM_DMC_P1 CPU_MXM_DMC_N1 39
71 69 70 72 CPU_MXM_DMC_P1 39
CPU_MXM_DMC_N0
39 CPU_MXM_DMC_N0 73 71 72 74
CPU_MXM_DMC_P0
39 CPU_MXM_DMC_P0 75 73 74 76
75 76

77 78
GND1 GND2
LOTES_AAA-PCI-112-K01

CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
Mini Card -WLAN/DMC/BT

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 51 of 56
A B C D E
5 4 3 2 1

+5VALW

EMI SA00006L600
@ RI1 1 2 0_0402_5%~D
Power share CI18
1 1
LI3 +5VALW CI16
SW_USB20_P0 4 3 USB20_P0_CONN

0.1U_0402_16V7K
4.7U_0805_10V4Z
4 3 UI1 2.0A

2
PWRSHARE_OE# 8 1 PWRSHARE_EN +3VALW 2 2 +USB3_VCCA
43 PWRSHARE_OE# CB CEN

100K_0402_5%
SW_USB20_N0 1 2 USB20_N0_CONN USB20_N0 7 2 SW_USB20_N0
1 2 20 USB20_N0 USB20_P0 6 TDM DM 3 SW_USB20_P0 UI2
20 USB20_P0 TDP DP

RI81
DLW21SN900SQ2L_0805_4P~D 5 4 PWRSHARE_SEL# 1 8 80mil
+5VALW VDD SELCDP GND VOUT

1
9 2 7

1
Thermal Pad VIN VOUT

0.1U_0402_16V4Z~D
@ RI2 1 2 0_0402_5%~D 2 3 6 @
VIN VOUT

CI1
4 5 1 2 0_0402_1%

EPAD
SLGC55584AVTR_TDFN8_2X2 RI82 PWRSHARE_EN_R# RI80 USB_OC0# 20
10K_0402_5% EN FLG
1 1

2
D 1 D

SSM3K7002FU_SC70-3~D
CI13 CI15

9
1
@ RI3 1 2 0_0402_5%~D RH86 @ D AP2301MPG-13_MSOP8

0.1U_0402_16V7K
PWRSHARE_EN 1 2 0_0402_1% 2 0.1U_0402_16V7K
LI1 2 2
G

QI1
USB3RN1_R_C 2 1 USB3RN1_R +5VALW S

3
2 1
1 2
3 4 43 PWRSHARE_EN_EC# 1 2
USB3RP1_R_C USB3RP1_R
3 4 PWRSHARE_SEL# RI9 1 2 10K_0402_5%~D DI7
1SS355TE-17_SOD323-2
DLW21SN900HQ2L_0805_4P~D PWRSHARE_OE# RI8 1 @ 2 10K_0402_5%~D
@ RI4 1 2 0_0402_5%~D PWRSHARE_SEL# RI10 1 @ 2 10K_0402_5%~D
PWRSHARE_EN RI7 1 @ 2 10K_0402_5%~D

@ RI5 1 2 0_0402_5%~D +3VS


LI2
CI7 USB CONN
0.01U_0402_16V7K~D
USB3TN1_R_C 2 1 USB3TN1_R 1 2 +USB3_VCCA
2 1 1 2

USB3TP1_R_C 3 4 USB3TP1_R CI6 JUSB1 +USB3_VCCA


3 4 .1U_0402_16V7K~D USB3TP1_R 9
UI3 1 SSTX+
DLW21SN900HQ2L_0805_4P~D 1 7 RI56 1 2 4.99K_0402_1% USB3TN1_R 8 VBUS
VCC NC SSTX-

47U_0805_6.3V4Z~D

10U_0603_6.3V6M~D
@ RI6 1 2 0_0402_5%~D 13 24 @RI57
@ RI57 1 2 0_0402_5%~D USB20_P0_CONN 3
VCC NC 7 D+
GND 1 1

CI20

CI22
20 USB3RN1 USB3RN1 CI9 1 2 0.1U_0402_10V6K~D USB3RN1_L 11 20 USB3RN1_R_C USB20_N0_CONN 2 11
+3VS USB3RP1 CI8 1 2 0.1U_0402_10V6K~D USB3RP1_L 12 TX2- RX2- 19 USB3RP1_R_C USB3RP1_R 6 D- GND 12
20 USB3RP1 TX2+ RX2+ SSRX+ GND
4 13
RI55 1 @ 2 3.3K_0402_5% USB3_P1_PIN6 USB3_OS2_P0 15 USB3RN1_R 5 GND GND 14 2 2
RI54 1 @ 2 3.3K_0402_5% USB3_P1_PIN18 USB3_DE2_P0 16 OS2 5 USB3_ERD_P0 10 SSRX- GND
DE2 EN_RXD 43 USBCHG_DET# Plug_DET
USB3_EQ2_P0 17 14 USB3_CM_P0
RI53 1 @ 2 3.3K_0402_5% USB3_P0_PIN6 EQ2 CM TAIWI_USB006-107CRL-TWD
RI52 1 @ 2 3.3K_0402_5% USB3_P0_PIN18 USB3TN1 CI4 1 2 0.1U_0402_10V6K~D USB3TN1_L 8 23 USB3TN1_RC CI11 1 2 0.1U_0402_10V6K~D USB3TN1_R_C CONN@
20 USB3TN1 USB3TP1 1 2 0.1U_0402_10V6K~D USB3TP1_L 9 RX1- TX1- 22 USB3TP1_RC CI10 1 2 0.1U_0402_10V6K~D USB3TP1_R_C
CI5
20 USB3TP1 RX1+ TX1+
C RI421 @ 2 4.7K_0402_5%~D USB3_CM_P0 C
RI431 @ 2 4.7K_0402_5%~D USB3_CM_P1 USB3_OS1_P0 4
RI441 @ 2 4.7K_0402_5%~D USB3_ERD_P0 USB3_DE1_P0 3 OS1 6 USB3_P0_PIN6 USB20_P0_CONN
RI411 @ 2 4.7K_0402_5%~D USB3_ERD_P1 USB3_EQ1_P0 2 DE1 GND 10
SN65LVPE502
EQ1 GND 18 USB3_P0_PIN18 USB20_N0_CONN For ESD request
RI191 @ 2 4.7K_0402_5%~D USB3_OS2_P0 25 GND 21 DI2
RI201 @ 2 4.7K_0402_5%~D USB3_DE2_P0 EN== PGND GND USB3TP1_R 1 10 USB3TP1_R

2
RI211 @ 2 4.7K_0402_5%~D USB3_EQ2_P0
1:normal operation(default) PS8713BTQFN24GTR2-A0_TQFN24_4X4

L30ESDL5V0C3-2
RI221 @ 2 4.7K_0402_5%~D USB3_OS1_P0 Vendor PS8710B PCB footprint and CIS symbol use TI USB3TN1_R 2 9 USB3TN1_R
RI261 @ 2 4.7K_0402_5%~D USB3_DE1_P0 TI 0:sleep mode (SN65LVPE502CPRGER)
RI231 @ 2 4.7K_0402_5%~D USB3_EQ1_P0 pin (default) USB3RP1_R 4 7 USB3RP1_R
RI241 @ 2 4.7K_0402_5%~D USB3_OS2_P1
CM== Compal P/N and value use Parade
pin15 AEQ1 OS2
0:normal operation(default)

DI3
RI251 @ 2 4.7K_0402_5%~D USB3_DE2_P1 (PS8710B) USB3RN1_R 5 6 USB3RN1_R
RI301 @ 2 4.7K_0402_5%~D USB3_EQ2_P1 pin16 ADE0 DE2
RI271 @ 2 4.7K_0402_5%~D USB3_OS1_P1 1:Compliance test mode 3
RI281 @ 2 4.7K_0402_5%~D USB3_DE1_P1 pin17 AEQ0 EQ2

1
RI291 @ 2 4.7K_0402_5%~D USB3_EQ1_P1 PS8710 8
pin4 BEQ1 OS1 [A(B)_DE1, A(B)_DE0] ==
RI871 @ 2 4.7K_0402_5%~D USB3_OS2_P0 TVWDF1004AD0
RI311 @ 2 4.7K_0402_5%~D USB3_DE2_P0 pin3 BDE0 DE1 LL: 3.5dB de-emphasis ESD
RI361 @ 2 4.7K_0402_5%~D USB3_EQ2_P0
RI401 @ 2 4.7K_0402_5%~D USB3_OS1_P0 pin2 BEQ0 EQ1 LH: No de-emphasis
RI351 @ 2 4.7K_0402_5%~D USB3_DE1_P0
RI321 @ 2 4.7K_0402_5%~D USB3_EQ1_P0
HL: 7dB de-emphasis
pin5 PD EN_RXD
RI331 @ 2 4.7K_0402_5%~D USB3_OS2_P1 HH: 5dB with boost output swing
RI341 @ 2 4.7K_0402_5%~D USB3_DE2_P1 pin14 TEST CM
RI391 @ 2 4.7K_0402_5%~D USB3_EQ2_P1 [A(B)_EQ1, A(B)_EQ0] ==
RI371 @ 2 4.7K_0402_5%~D USB3_OS1_P1 pin18 ADE1 LL: reserved
RI381 @ 2 4.7K_0402_5%~D USB3_DE1_P1
RI841 @ 2 4.7K_0402_5%~D USB3_EQ1_P1 LH: program EQ for channel loss up to 7dB
pin6 BDE1
HL: program EQ for channel loss up to 14.5dB
RI461 @ 2 4.7K_0402_5%~D USB3_CM_P0 [Parade suggest]
RI471 @ 2 4.7K_0402_5%~D USB3_CM_P1 HH: program EQ for channel loss up to 11.5dB
RI481 @ 2 4.7K_0402_5%~D USB3_ERD_P0 PS8710 AEQ0,BEQ0 adjust 7db, TEST ==
RI451 @ 2 4.7K_0402_5%~D USB3_ERD_P1 +3VS
REXT use 3.3 K well get btter test result. L: Normal operation (default)
RI49 1 @ 2 0_0402_5%~D USB3_P0_PIN6 H: Test mode enable CI26
RI50 1 @ 2 0_0402_5%~D USB3_P0_PIN18 0.01U_0402_16V7K~D
1 2 +USB3_VCCB
RI85 1 @ 2 0_0402_5%~D USB3_P1_PIN6 1 2 +USB3_VCCB
B B
RI51 1 @ 2 0_0402_5%~D USB3_P1_PIN18
CI25 JUSB2
.1U_0402_16V7K~D USB3TP2_R 9
UI4 SSTX+

47U_0805_6.3V4Z~D

10U_0603_6.3V6M~D
1
1 7 RI77 1 2 4.99K_0402_1% USB3TN2_R 8 VBUS
VCC NC SSTX- 1 1

CI32

CI34
13 24 @ RI76 1 2 0_0402_5%~D USB20_P1_CONN 3
VCC NC 7 D+
1 2 0_0402_5%~D USB3RN2 CI27 1 2 0.1U_0402_10V6K~D USB3RN2_L 11 20 USB3RN2_R_C USB20_N1_CONN 2 GND 10
@RI13
@ RI13 EMI 20 USB3RN2
USB3RP2 CI28 1 2 0.1U_0402_10V6K~D USB3RP2_L 12 TX2- RX2- 19 USB3RP2_R_C USB3RP2_R 6 D- GND 11 2 2
20 USB3RP2 TX2+ RX2+ SSRX+ GND
LI6 4 12
USB20_P1 4 3 USB20_P1_CONN USB3_OS2_P1 15 USB3RN2_R 5 GND GND 13
20 USB20_P1 4 3 16 OS2 5 SSRX- GND
USB3_DE2_P1 USB3_ERD_P1
USB3_EQ2_P1 17 DE2 EN_RXD 14 USB3_CM_P1 TAITW_PUBAU5-09FLBS1NN4H0
USB20_N1 1 2 USB20_N1_CONN EQ2 CM CONN@
20 USB20_N1 1 2 USB3TN2 1 2 0.1U_0402_10V6K~D USB3TN2_L 8 23 USB3TN2_RC CI29 1 2 0.1U_0402_10V6K~D USB3TN2_R_C
CI23
20 USB3TN2 1 2 0.1U_0402_10V6K~D USB3TP2_L 9 RX1- TX1- 22 1 2 0.1U_0402_10V6K~D
WCM2012F2S-900T04_0805 USB3TP2 CI24 USB3TP2_RC CI30 USB3TP2_R_C
20 USB3TP2 RX1+ TX1+
@RI14
@ RI14 1 2 0_0402_5%~D USB3_OS1_P1 4
USB3_DE1_P1 3 OS1 6 USB3_P1_PIN6
USB3_EQ1_P1 2 DE1 GND 10
EQ1 GND 18 USB3_P1_PIN18 For ESD request
25 GND 21 USB20_N1_CONN
PGND GND
@ RI17 1 2 0_0402_5%~D PS8713BTQFN24GTR2-A0_TQFN24_4X4 USB20_P1_CONN DI8
PCB footprint and CIS symbol use TI USB3RN2_R 1 10 USB3RN2_R
LI5
(SN65LVPE502CPRGER)

2
USB3TN2_R_C 2 1 USB3TN2_R USB3RP2_R 2 9 USB3RP2_R
2 1 +5VALW Compal P/N and value use Parade

L30ESDL5V0C3-2
(PS8710B) USB3TN2_R 4 7 USB3TN2_R
USB3TP2_R_C 3 4 USB3TP2_R
3 4 USB3TP2_R 5 6 USB3TP2_R

DI9
DLW21SN900HQ2L_0805_4P~D 1 1
CI35 CI36 3
@ RI18 1 2 0_0402_5%~D
4.7U_0805_10V4Z 0.1U_0402_16V7K 2.0A 8

1
2 2 +USB3_VCCB
TVWDF1004AD0
UI5
1 8 80mil ESD
A 2 GND VOUT 7 <BOM Structure> A
@ RI15 1 2 0_0402_5%~D 3 VIN VOUT 6 RH83 @
4 VIN VOUT 5 1 2 0_0402_1%
EPAD

USB_PWR_EN# USB_OC1# 20
LI4 43,53 USB_PWR_EN# EN FLG
USB3RN2_R_C 2 1 USB3RN2_R 1 1
2 1 CI37 CI38
9

AP2301MPG-13_MSOP8
0.1U_0402_16V7K

USB3RP2_R_C 3 4 USB3RP2_R 0.1U_0402_16V7K


3 4 2 2

DLW21SN900HQ2L_0805_4P~D
@ RI16 1 2 0_0402_5%~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/05/24 Deciphered Date 2013/05/23 Title
USB 3.0/2.0 x2 (left side)

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 52 of 56
5 4 3 2 1
5 4 3 2 1

1 2 0_0402_5%~D +5VALW +USB3_VCCC +USB3_VCCC +USB3_VCCC


@R343
@ R343 EMI JUSB3

USB20_N2 4
L41
3 USB20_N2_CONN
C256
1
U27 2.0A 8
W=60mils USB3TP5_R 9
1 SSTX+
.1U_0402_16V7K~D
20 USB20_N2 4 3 GND VOUT VBUS

47U_0805_6.3V4Z~D

10U_0603_6.3V6M~D
1 2 2 7 USB3TN5_R 8
3 VIN VOUT 6 USB20_P2_CONN 3 SSTX-
VIN VOUT D+ 1 1

C250

C795
1 2 4 5 7

EPAD
USB20_P2 USB20_P2_CONN USB_PWR_EN#
20 USB20_P2 1 2 43,52,53 USB_PWR_EN# EN FLG USB_OC2# 20 GND
USB20_N2_CONN 2 10
DLW21SN900SQ2L_0805_4P~D USB3RP5_R 6 D- GND 11
1 SSRX+ GND 2 2
C72 4 12

9
@R344
@ R344 1 2 0_0402_5%~D USB3RN5_R 5 GND GND 13
AP2301MPG-13_MSOP8 0.1U_0402_16V7K SSRX- GND
2 TAITW_PUBAU5-09FLBS1NN4H0
CONN@

@R342
@ R342 1 2 0_0402_5%~D
USB20_P2_CONN
L39
D
20 USB3RN5 USB3RN5 2 1 USB3RN5_R USB20_N2_CONN For ESD request D
2 1 DI5
USB3RN5_R 1 10 USB3RN5_R

2
20 USB3RP5 USB3RP5 3 4 USB3RP5_R USB3TN5 C61 1 2 0.1U_0402_10V6K~D USB3TN5_L
3 4 20 USB3TN5

L30ESDL5V0C3-2
USB3TP5 C62 1 2 0.1U_0402_10V6K~D USB3TP5_L USB3RP5_R 2 9 USB3RP5_R
20 USB3TP5
DLW21SN900HQ2L_0805_4P~D USB3TN5_R 4 7 USB3TN5_R
@R392
@ R392 1 2 0_0402_5%~D

DI4
USB3TP5_R 5 6 USB3TP5_R

1
8
@R391
@ R391 1 2 0_0402_5%~D
TVWDF1004AD0
L40
USB3TN5_L 2 1 USB3TN5_R
ESD
2 1

USB3TP5_L 3 4 USB3TP5_R +USB3_VCCD


3 4 +5VALW +USB3_VCCD +USB3_VCCD

DLW21SN900HQ2L_0805_4P~D
1 2 0_0402_5%~D
C257
1
U28 2.0A 8
W=60mils
USB3TP6_R 9
JUSB4
@R390
@ R390 .1U_0402_16V7K~D
GND VOUT SSTX+

47U_0805_6.3V4Z~D

10U_0603_6.3V6M~D
1 2 2 7 1
3 VIN VOUT 6 USB3TN6_R 8 VBUS
VIN VOUT SSTX- 1 1

C251

C796
4 5 3

EPAD
USB_PWR_EN# USB_OC3# 20 USB20_P3_CONN
43,52,53 USB_PWR_EN# EN FLG 7 D+
1 GND
C71 USB20_N3_CONN 2 10
@R347
@ R347 1 2 0_0402_5%~D USB3RP6_R 6 D- GND 11 2 2

9
AP2301MPG-13_MSOP8 0.1U_0402_16V7K 4 SSRX+ GND 12
L50 2 USB3RN6_R 5 GND GND 13
USB20_N3 4 3 USB20_N3_CONN SSRX- GND
20 USB20_N3 4 3 TAITW_PUBAU5-09FLBS1NN4H0
CONN@
USB20_P3 1 2 USB20_P3_CONN
20 USB20_P3 1 2
DLW21SN900SQ2L_0805_4P~D

C @R346
@ R346 1 2 0_0402_5%~D USB20_P3_CONN C

USB20_N3_CONN For ESD request


DI10
USB3RN6_R 1 10 USB3RN6_R

2
L30ESDL5V0C3-2
USB3RP6_R 2 9 USB3RP6_R

@R345
@ R345 1 2 0_0402_5%~D USB3TN6 C63 1 2 0.1U_0402_10V6K~D USB3TN6_L USB3TN6_R 4 7 USB3TN6_R
20 USB3TN6 USB3TP6 1 2 0.1U_0402_10V6K~D USB3TP6_L
C64
L42 20 USB3TP6

DI6
USB3TP6_R 5 6 USB3TP6_R
20 USB3RN6 USB3RN6 2 1 USB3RN6_R
2 1 3

1
20 USB3RP6 USB3RP6 3 4 USB3RP6_R 8
3 4
TVWDF1004AD0
DLW21SN900HQ2L_0805_4P~D
@R403
@ R403 1 2 0_0402_5%~D ESD
CONN@
CVILU_CF25602D0R0-05-NH
60 61
+5VS_TP_LED
+5VS 59 60 G1 62
+5V_KP_BL 58 59 G2
48 KB_LED_B5_DRV# 57 58
TP_CLK
43 TP_CLK 56 57
TP_DATA
43 TP_DATA 55 56
@R394
@ R394 1 2 0_0402_5%~D 54 55
F5 12,13,14,15,19,49,50,51,6 PCH_SMBDATA 53 54
L43 1 2 12,13,14,15,19,49,50,51,6 PCH_SMBCLK 52 53
TP_LED_R_DRV#
2 1 48 TP_LED_R_DRV# 51 52
USB3TN6_L USB3TN6_R TP_LED_G_DRV#
2 1 48 TP_LED_G_DRV# 50 51
TP_LED_B_DRV#
48 TP_LED_B_DRV# 49 50
0.5A_13.2V_NANOSMDC050F-13.2-2 1
USB3TP6_L 3 4 USB3TP6_R 48 49
3 4 C1856 47 48
0.1U_0402_25V6K~D VPK_DET# 46 47
DLW21SN900HQ2L_0805_4P~D 2 43 VPK_DET# 45 46
VPK_EN
1 2 0_0402_5%~D 43 VPK_EN 44 45
@R393
@ R393
48 KB_LED_R5_DRV# 43 44
B 48 KB_LED_G5_DRV# 42 43 B
+5VS
41 42
40 41
+3VS
39 40
38 39
30pin Connector to CardReader
CONN@
19,30,40,43,54
19,30,40,43,54
EC_SMB_DA2
EC_SMB_CK2
37 38
36 37
35 36
20 USB20_P13 34 35
JIO2
30 20 USB20_N13 33 34
PCIE_PTX_CARDRX_P4 29 30 34 I2C_CLK 32 33
20 PCIE_PTX_CARDRX_P4 28 29 G4 33 47,48 I2C_CLK 31 32
PCIE_PTX_CARDRX_N4 I2C_DAT
20 PCIE_PTX_CARDRX_N4 27 28 G3 32 47,48 I2C_DAT 30 31
26 27 G2 31 48 7313_INT# 29 30
PCIE_PRX_CARDTX_P4 +3.3V_F347
20 PCIE_PRX_CARDTX_P4 PCIE_PRX_CARDTX_N4 25 26 G1 KB_DET# 28 29
20 PCIE_PRX_CARDTX_N4 25 21 KB_DET#
24 KSI0 27 28
CLK_PCIE_CD 23 24 KSI1 26 27
18 CLK_PCIE_CD 22 23 25 26
CLK_PCIE_CD# KSI2
18 CLK_PCIE_CD# 21 22 24 25
KSI3
PLT_RST# 20 21 KSI4 23 24
17,43,44,51,6 PLT_RST# 19 20 22 23
CDCLK_REQ# KSI5
18 CDCLK_REQ# 18 19 21 22
+3VALW KSI6
ON/OFFBTN# 17 18 KSI7 20 21
+3VS 17
+5VS
16 KSO0 19 20
15 16 KSO1 18 19
+5VALW 15
14 KSO2 17 18
48 LED_R_7313#_1 13 14 16 17
KSO3
48 LED_B_7313#_1 13 15 16
3

12 KSO4
48 LED_G_7313#_1 11 12 KSI[0..7] 14 15
D72 KSO5
43 CAPS_LED# 10 11 43,48 KSI[0..7] KSO[0..17] KSO6 13 14
PESD24VS2UT_SOT23-3~D 43,48 KSO[0..17]
43,51 WLES ON/OFF LED# 9 10 12 13
KSO7
48 HDD_R 8 9 11 12
KSO8
48 HDD_G 7 8 10 11
KSO9
1

48 HDD_B 6 7 9 10
KSO10
Place close to JIO2 55 ON/OFFBTN# Power_LED# 5 6 KSO11 8 9
43 Power_LED# 4 5 7 8
@ LID_SW_IN# KSO12
19,43,45,47,48 LID_SW_IN# 3 4 6 7
ESD 48 PWR_G_7313# 2 3
KSO13
KSO14 5 6
48 PWR_R_7313# 1 2 4 5
KSO15
48 PWR_B_7313# 1 KSO16 3 4
A A
E-T_6700K-Y30N-00L KSO17 2 3
1 2
1
JP3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/02/28 Deciphered Date 2013/02/27 Title
IO BTB CONN

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 53 of 56
5 4 3 2 1
A B C D E

+3VS

System FAN Controller +3VS +5VS

0.1U_0402_10V7K~D
1

C49

22U_0805_6.3VAM~D
2

100P_0402_50V8J~D
1 @ 1
1

C52
SENSOR_DIODE_P1 R46 1 2 0_0402_1% REMOTE_P1

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D
1 U5

2
@ C51
1 C 1 8 EC_SMB_CK2 EC_SMB_CK2 19,30,40,43,53
VDD SCLK 2

R49

R50

R51
2 C50
B 470P_0402_50V7K~D 2 7 EC_SMB_DA2
E 2 D+ SDATA EC_SMB_DA2 19,30,40,43,53
Q17 @

3
2 MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N1 R47 1 2 0_0402_1% REMOTE_N1 3 6

1
D- ALERT#
R48 1 2 4.7K_0402_5%~D 4 5 JFAN1 CONN@
+3VS THERM# GND 1
Diode circuit s used for skin temp sensor SYSTEM_FAN_PWM 2 1
43 SYSTEM_FAN_PWM 2
(placed between CPU and MXM). ADM1032ARMZ-REEL_MSOP8 SYSTEM_FAN_FB 2 1 3 5
Place C1814 close to Q276 as possible. Address:100_1100 43 SYSTEM_FAN_FB D65
SDMK0340L-7-F_SOD323-2~D
4 3
4
G5
G6
6

MOLEX_53398-0471~D

Pull up resistor
on thermtrip pin SMBUS address
4.7k 1111
6.8k 1011
2 10k 1001 2

15k 1101
22k 0011
33k 0111

+3VS +5VS
+3VS

MXM1 FAN Controller

22U_0805_6.3VAM~D
0.1U_0402_10V7K~D
1 1

C53

C56
10K_0402_5%~D
2
10K_0402_5%~D

10K_0402_5%~D
2

2
2 2

R55
R56

R57
@
SENSOR_DIODE_P2 R52 1 2 0_0402_1% REMOTE_P2
1 U6

1
1
100P_0402_50V8J~D

1 C 1 8 EC_SMB_CK2 JFAN2 CONN@

1
VDD SCLK
C55

2 C54 1
B 470P_0402_50V7K~D 2 7 EC_SMB_DA2 MXM1_FAN_PWM 2 1
E Q19 2 D+ SDATA 43 MXM1_FAN_PWM MXM1_FAN_FB 2 1 3 2 5
@
3

2 43 MXM1_FAN_FB 3 G5
@

MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N2 R53 1 2 0_0402_1% REMOTE_N2 3 6 D66 4 6


D- ALERT# SDMK0340L-7-F_SOD323-2~D 4 G6
R54 1 2 6.8K_0402_5%~D 4 5 MOLEX_53398-0471~D
+3VS THERM# GND

ADM1032ARMZ-2REEL_MSOP8
3
Address:100_1101 3

+3VS +5VS
+3VS

MXM2 FAN Controller

22U_0805_6.3VAM~D
0.1U_0402_10V7K~D

1 1
C65

C59
10K_0402_5%~D
2
10K_0402_5%~D

10K_0402_5%~D
2

2
2 2

R62
R60

R61
@
SENSOR_DIODE_P3 R63 1 2 0_0402_1% REMOTE_P3
U7
1

1
1
100P_0402_50V8J~D

1 C 1 8 EC_SMB_CK2 JFAN3 CONN@

1
VDD SMCLK
C66

2 C67 1
B 470P_0402_50V7K~D 2 7 EC_SMB_DA2 MXM2_FAN_PWM 2 1
2 DP SMDATA 43 MXM2_FAN_PWM 2 1 3 2 5
E Q22 @ MXM2_FAN_FB
3

2 43 MXM2_FAN_FB 3 G5
@

MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N3 R64 1 2 0_0402_1% REMOTE_N3 3 6 D67 4 6


DN ALERT SDMK0340L-7-F_SOD323-2~D 4 G6
R65 1 2 6.8K_0402_5%~D 4 5 MOLEX_53398-0471~D
+3VS THERM#/ADDR GND

W83L771AWG-2

4
Address:1001_101Xb 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/14 Deciphered Date 2013/05/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thermal Sensor & FAN

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 54 of 56
A B C D E
A B C D E

ON/OFF switch
1 TOP Side 1
SW1 +3VLP
SMT1-05-A_4P
1 3 ON/OFFBTN#

Power Button

2
2 4

R58

6
5
100K_0402_5%~D

1
D26
2
1 ON/OFF 43
53 ON/OFFBTN# ON/OFFBTN#

0.1U_0402_25V6K~D
3
1

C58
DAN202UT106_SC70-3
Bottom Side
SW2
SMT1-05-A_4P 2
1 3

2 4

6
5
2 2

Pop only for


SSI debug
@ H1 @ H2 @ H3 @ @H4
H4 @@H5
H5 @ H6 @ H7 @ H8
A H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
1

@ H9 @ H10 @ H13 @ H17 @ H16


@H17
B H_3P8 H_3P8 H_3P8 H_3P8 H_3P3
1

@ H20 @ H21 @ H22 @


@H23
H23
3 C H_4P0 H_4P0 H_4P0 H_4P0
3
1

@ H24 @ H25 @ H26


D H_3P0 H_3P0 H_3P0
1

@ H27 FD1 FD2 FD3 FD4


E H_2P6N @ H30
@H30
H_3P3
ZZZ1 @ @ @ @

1
1

FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80


1

@ H28 @ H29
H_2P6X3P6N
H_2P1X2P6N
F
4
PCB-MB Fiducial Mark 4
1

@ H11 @ H12 @ H14 @


@H15
H15 @
@H18
H18 @ H19
H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3
Security Classification Compal Secret Data
G 2012/05/28 2013/05/27 Title
Issued Date Deciphered Date
KB & Power Button & IR
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 55 of 56
A B C D E

www.vinafix.vn
A B C D E

DC to DC +5VALW to +5VS +3VALW to +3V_PCH


+3VALW to +3VS +3VALW
QZ6
+3V_PCH +3VALW to +3VMXM Transfer
+5VALW +5VS SI4800BDY-T1-E3_SO8~D
QZ1 8 1 +3VALW +3VMXM
SI4800BDY-T1-E3_SO8~D +3VALW +3VS 7 2 UZ2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

10U_0805_10V4Z~D
8 1 QZ3 6 3 SI4800BDY-T1-E3_SO8~D
SI4800BDY-T1-E3_SO8~D
80mil(2A)
10U_0805_10V4Z~D

10U_0805_10V4Z~D

1U_0603_10V4Z~D

10U_0805_10V4Z~D
7 2 1 1 5 1 1 8 1

10U_0805_10V4Z~D

1U_0603_10V4Z~D

CZ11

CZ12

CZ13
1 1 6 3 8 1 1 7 2
CZ1

CZ2

10U_0805_10V4Z~D

10U_0805_10V4Z~D

CZ14

CZ20

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
5 1 1 @ 7 2 6 3

4
CZ5

CZ3
1 1 6 3 5 1 1
2 2 2 2

CZ6

CZ7

10U_0805_10V4Z~D

1U_0603_10V4Z~D

CZ23
@ 5

4
2 @2 @2

CZ21
@ 1 @ @

4
2 2

CZ8
1

4
2 2 2 2

CZ9
RZ30
1 2 1
200K_0402_5%
2 1 2 +3VMXM_GATE
B+_BIAS
1 2 +3VS_GATE
B+_BIAS RZ5

6
D

DMN66D0LDW-7_SOT363-6~D

0.1U_0603_25V7K~D
RZ3 1 2 +3V_PCH_GATE
B+_BIAS

@
1
0.1U_0603_25V7K~D

QZ8A

0_0402_5%~D
1 2 +5VS_GATE 102K_0402_1% 1 1 102K_0402_1% DGPU_PWR_EN# 2 1
B+_BIAS

RZ31
DMN66D0LDW-7_SOT363-6~D

SSM3K7002F_SC59-3~D

0_0402_5%~D

0.1U_0603_25V7K~D

CZ22
RZ1 D 1 1 G

0_0402_5%~D
1
@
0.1U_0603_25V7K~D

CZ10

SSM3K7002F_SC59-3~D

CZ15
D

@
102K_0402_1% 1
3

2
D

QZ4

RZ4
SUSP 2

0_0402_5%~D
S

RZ6

1
@
2 2
QZ2B

CZ4

QZ5
SUSP 5 G PCH_PWR_EN# 2

2
2

RZ2
G G

2
2 S

2
S 3 S
4

1
3

+1.05V
+1.05VS +5VALW to +5VMXM
+5VALW to +5VS +5VALW +5VMXM
UZ3
@ SI4800BDY-T1-E3_SO8~D 100mil(2.5A)
+3VALW to +3VS

10U_0805_10V4Z~D
JP6 8 1

+1.05V to +1.05VS

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
1 2 1 7 2
6 3 1 1
+5VALW

CZ24
+5VS PAD-OPEN 4x4m @ 5

CZ25

CZ26
@
Shape Shape 2
10U_0805_10V6K

UZ1 QZ20

4
1 14 SI4164DY-T1-GE3_SO8~D 2 2
2 VIN1 VOUT1 13 8 1
CZ33

VIN1 VOUT1

10U_0805_10V6K

1U_0603_10V6K
7 2
10U_0805_10V6K

1 1 1 1

10U_0805_10V4Z~D
SUSP# 1 2 3 12 CZ37 CZ38 6 3 RZ32
ON1 CT1

1U_0603_10V4Z~D
5
CZ34

RZ27 @ 0_0402_5%~D 1 1 200K_0402_5%

CZ16
@ 4 11 @ @ B+_BIAS
1 2 +5VMXM_GATE
2 2 VBIAS GND 2 2

CZ17
@ @ @

6
D

DMN66D0LDW-7_SOT363-6~D

0.1U_0603_25V7K~D
DGPU_PWR_EN# 1 2 5 10 +5VMXM
+5VALW to +5VMXM

@
0_0402_5%~DON2 CT2

1
+5VALW 2 2

QZ9A

0_0402_5%~D
RZ25 @ DGPU_PWR_EN# 2 1

RZ33
CZ27
2 6 9 G 2
7 VIN2 VOUT2 8
VIN2 VOUT2 1 2 +1.05VS_GATE +3VALW to +3VMXM
10U_0805_10V6K

10U_0805_10V6K

1U_0603_10V6K
B+_BIAS S

1
15 2
10U_0805_10V6K

RZ53
1 1
Shape Shape 1 1

2
GPAD

100P_0402_50V8J~D
330K_0402_5%~D

1
1M_0402_5%~D
+3VALW
CZ35

CZ36

CZ39

CZ40
TPS22966DPUR_SON14_2X3 @ +3VS

RZ54
2 2 2 2 1 1
Shape Shape

SSM3K7002F_SC59-3~D
D @ @ UZ4
@

CZ32
@ @ @ @ 1 14
VIN1 VOUT1
1000P_0402_50V7K

QZ7
2 2 13
470P_0402_50V7K

SUSP

10U_0805_10V6K
2
2 VIN1 VOUT1

10U_0805_10V6K

1U_0603_10V6K
G

10U_0805_10V6K
1 1 1 1 1 1
CZ19

CZ18

CZ43
SUSP# 1 2 3 12 CZ47 CZ48
ON1 CT1

CZ44
@ S @ RZ28 0_0402_5%~D
3 4 11 @ @
@ 2 2 @ @ 2 2 VBIAS GND 2 2
+3VALW @ 1
DGPU_PWR_EN# 2 5 10 +3VMXM
@ RZ26 0_0402_5%~D ON2 CT2
6 9
7 VIN2 VOUT2 8
VIN2 VOUT2

10U_0805_10V6K

10U_0805_10V6K

1U_0603_10V6K
15

10U_0805_10V6K
1 1
Shape GPAD Shape 1 1

CZ45

CZ46

CZ49

CZ50
TPS22966DPUR_SON14_2X3

Discharge Circuit
2 2 2 2
@
@ @ @ @

1000P_0402_50V7K

470P_0402_50V7K
@ @
1 1

CZ42

CZ41
+1.35V +5VS +1.5VS +3VMXM +5VMXM
2 2
1

2
RZ37 RZ34 RZ40 RZ36
470_0603_5% 470_0603_5% 470_0603_5% RZ35 470_0603_5% +5VALW
470_0603_5% +3VALW +5VALW
2

2 +1.5VS_D

3+3VMXM_D1

3+5VMXM_D1

1
+1.35V_D

+5VS_D

3 3
RZ46

1
DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D

2
RZ45
SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

@ RZ44 100K_0402_5%~D

2
1

D D D D D 10K_0402_5%~D
QZ2A

QZ8B

QZ9B
SYSON# 2 SUSP 2 SUSP 2 DGPU_PWR_EN# 5 DGPU_PWR_EN# 5 SUSP

2
G G G G G PCH_PWR_EN#

1
QZ12 S QZ10 S 1 1
3

SSM3K7002F_SC59-3~D

SSM3K7002F_SC59-3~D
S S S D D
1

QZ15

QZ16
2 2
43 PCH_PWR_EN G 10,43,59,60,61 SUSP# G

100K_0402_5%~D

100K_0402_5%~D
1

1
0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
1 S 1 S
3 3

@
RZ47
RZ52

CZ28

CZ29
2 2

2
+3V_PCH +3VS +1.05VS

+1.35V_CPU_VDDQ +0.675VS +5VALW +5VALW


1

1
220_0603_5%~D

22_0603_5%~D
1

2
RZ42 RZ43 RZ49
470_0603_5% 470_0603_5% RZ41 @ 100K_0402_5%~D RZ48
470_0603_5%
RZ38

RZ39

100K_0402_5%~D
2

2
+3V_D

SYSON#
+1.05VS_D
+3VS_D

1
DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

+1.35V_CPU_VDDQ_CHG

1 DGPU_PWR_EN#
+DDR_CHG

SSM3K7002F_SC59-3~D
D 1
6

D D

SSM3K7002F_SC59-3~D
D
SSM3K7002FU_SC70-3~D
QZ11A

QZ11B

QZ17
PCH_PWR_EN# 2 SUSP 5 2
43,59,60 SYSON
1

QZ18
G G G 2
2 43 DGPU_PWR_EN
SUSP G
100K_0402_5%~D

0.1U_0603_25V7K~D

@ S

100K_0402_5%~D
4 S S G 1 4
1

1
3

0.1U_0603_25V7K~D
@

QZ19 S S
RZ50

1
3

SSM3K7002FU_SC70-3~D

3
SSM3K7002FU_SC70-3~D

CZ30

@
RZ51

CZ31
1

D D 2
2

2 2 2
QZ14

2
10,6 RUN_ON_CPU1.5VS3#
G G
QZ13 S S
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
DC/DC Interface

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-9332P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 14, 2012 Sheet 56 of 56
A B C D E
A B C D

+3VALW
PL4
C8B BPH 853025_2P
1 2

PL1
VIN
C8B BPH 853025_2P
ADPIN 1 2

2.2K_0402_5%
2
rating current = 18A

1000P_0402_50V7K

1000P_0402_50V7K

PR3
100P_0402_50V8J

100P_0402_50V8J
1

1
@ PJPDC1 PR4

PC1

PC2

PC3

PC4
5 33_0402_5%
Erp lot6 Circuit VIN

1
9 DETECT 1 3 PSID-3 1 2

S
PS_ID 43

2
1
GND_4 1 +DCIN_JACK PQ7
1

8 DC+_1 FDV301N_NL_SOT23-3~D
GND_3 2

3.3K_1206_5%~D

G
2
DC+_2

100K_0402_1%
1

2
7 3
GND_2 DC-_1 PR8

PR5

PR6
6 4 @ PR7 PSID-2 2 1
GND_1 DC-_2 +5VALW

2
@
PL2 17,29,43,47,64 ACIN 1M_0402_1%

32

1
10K_0402_1%

1
BLM18BD102SN1D_2P C
FOX_JPD113D-DB570-7F PSID 2 1 PSID-1 2 PQ2

SSM6N7002FU-2N_SOT363-6
PQ1B
B

15K_0402_1%
MMST3904-7-F_SOT323~D

1
1

2
5 E

SSM6N7002FU-2N_SOT363-6

3
PR9
@ PR1

2
@ @

1
PQ1A
200K_0402_1% PD1
PR10 @ SM24_SOT23

1
2
BATT+ BATT++ @ 1M_0402_1%

1
1
PL5 @ PC5

1
SMB3025500YA_2P
1 2 0.1U_0402_25V6
BATT+

2
PL3
SMB3025500YA_2P
1 2 BATT++
100P_0402_50V8J
1

PQ3
1000P_0402_50V7K
100P_0402_50V8J

0.01U_0402_25V7K
1

PC8

PC9
PC6

PC7

SI3457CDV-T1-GE3_TSOP6
2

@ PR2 6
2

@ @ JRTC1 1K_0402_5% PD5 5


2
PD2 @ 1 1 2 2 2 2

1 6 1 2 1 4 1
B+_BIAS

D
+RTC_CELL
V I/O V I/O 2 3
G1 4
3 B+
2 5

100K_0402_1%

0.1U_0402_25V6
0.22U_0603_25V7K
Ground V BUS G2

1
BAS40CW _SOT323-3

G
1

1
3 4

PR12

PC10

PC11
ACES_50271-00201-001

3
V I/O V I/O
IP4223CZ6_SO6-6 +3VLP

2
2
PBATT1 @
+5VALW PR13
1 100K_0402_1%
1 BATT_TEMP 43,57,64
2 1 2 VSB_N_001
2

1VSB_N_003
3
3 4 PR14
4 5 CLK_SMB PR15 PR16 100K_0402_1%
5 6 DAT_SMB 100_0402_5% 10K_0402_1%
6 7 BATT_PRS 1 2 1 2 PR17
+3VALW

1
7 8 SYS_PRES 0_0402_5% D
8 9 1 2VSB_N_002 2 PQ4
9 58 POK
10 PR18 G 2N7002KW _SOT323-3
10 11 100_0402_5%

.1U_0402_16V7K
S

3
11

1
12 1 2

PC12
12 13 EC_SMB_CK1 29,43,64
13 PR20

2
MOLEX_87437-1342 100_0402_5%
1 2
EC_SMB_DA1 29,43,64

3 3

PBATT1 battery connector (Follow VAS00)


PH1 under CPU botten side :
43,64 ADP_I
CPU thermal protection at 93 +/- 3 degree C

+3VALW +3VLP

2
43,6 H_PROCHOT#
PR23

2
110K_0402_1%
PR24 PR25 @
12.1K_0402_1% 12.1K_0402_1%

1
Adapter ADP_SEL
43 VCIN1_PH

1
@ PC14

.1U_0402_16V7K
1

1U_0603_25V6K D 43 VCIN0_PH
2

2
PC13
43,57,64 BATT_TEMP 1 2 2 PQ8 @ 240W LOW PR26
2
PR27
G SSM3K7002FU_SC70-3

1
196K_0402_1%
2

S 169K_0402_1% @
3

@
1

PR28 2N7002KW _SOT323-3


330W HIGH
1

11
100K_0402_1% D
PQ5 2 PH1
ADP_SEL 43

2
G 100K_0402_1%_TSM0B104F4251RZ
1

S
3

4 4

43 ECAGND

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
PWR-DCIN / BATT CONN / OTP

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9332P
Date: Friday, December 14, 2012 Sheet 57 of 66
A B C D
A B C D E

PR100
6.49K_0402_1%
1 2

1 2 @ PC122

100P_0402_50V8J
@ 100P_0402_50V8J 1 2
PC121 +3VLP
PR101
15K_0402_1%
1 2 1 1

1U_0603_10V6K
PR102 PR104

2
0_0603_5%~N
10K_0402_5% 10K_0402_5%

1
PR103

PC114
1 2 2 1

2
1

68.1K_0402_1%
2
120K_0402_1%
B++

PR106
PR105
B++
FB_3V FB_5V

1
1
PL103
1UH_NRS4018T1R0NDGJ_3.2A_30%
1 2

10U_0805_25V6K

10U_0805_25V6K
1

1
PC109

PC104
PU100

CS2

VFB2

VREG3

VFB1

CS1
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

21
PAD
1

1
PC105

PC106

PC110

PC107

3V_EN 6
MDV1528URH 1N PDFN33-8

2
EN2
5
14 @
VO1

5
2

@ 7

MDV1525URH 1N PDFN33-8
57 POK PGOOD
@ 19
VCLK
PQ101

PQ102
4 UG_3V 10
B+ PC112 PR108 DRVH2 TPS51225_QFN20_3X3 16 UG_5V 4
0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR107 PC111
1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 1 2
1
2
3

2 VBST1 2

3
2
1
SW2 8 PL102
SW2 18 SW1

VREG5
DRVL2

DRVL1
+3VALWP PL101 SW1 3.3UH +-20% PIMB104T-3R3MS 10A
+5VALWP

EN1
VIN
3.3UH_PCMB063T-3R3MS_6.5A_20%
1 2 2 1

11

12

13

5V_EN 20

15
MDV1526URH 1N PDFN33-8
1

1
150U_B2_6.3VM_R35M

4.7_1206_5%

4.7_1206_5%
LG_3V LG_5V

MDU1512RH_POWERDFN56-8-5
PR109

PR110
1

220U_6.3V_M
PC101

+
1
PQ103

@ @
1 SNUB_3V 2

2
PQ104

PC102
4 4 +
2

1SNUB_5V
2

1U_0603_10V6K
0.1U_0603_25V7K

2
680P_0603_50V7K

680P_0603_50V7K
0_0603_5%~N
1
2
3

3
2
1
1

1
PC117

PC118

PR118
PC116

PC119
2

2
2

2
@ @

B++ VL

3 3
3V_EN 1 2
3VALWP
TDC 6.08A PR111 0_0402_5%

Peak Current 8.11A 5V_EN 1 2

OCP current 9.73A PR112 0_0402_5%


PD102 PR113
TYP MAX 2 2.2K_0402_5%
5VALWP
43 EC_ON
H/S Rds(on) 11.2mohm , 14mohm 3
1 1 2 TDC 11A
L/S Rds(on) 3.7mohm , 5mohm 43 USBCHG_DET_D Peak Current 16A
BAS40CW_SOT323-3
PR114 OCP current 20A
0_0402_5%
1 2 TYP MAX
43 VCOUT0_PH#
PJP100 PJP101 H/S Rds(on) 11.2mohm , 14mohm
@ PD101 @ PR115
+3VALWP
1 2 +3VALW +5VALWP
1 2
+5VALW L/S Rds(on) 3.7mohm , 5mohm
LL4148_LL34-2 1M_0402_1%
2 1 1 2
VIN PAD-OPEN 4x4m PAD-OPEN 4x4m
PJP102
200K_0402_1%

4.7U_0603_6.3V6K
1
PR116

1 2
1

PC120

PAD-OPEN 4x4m
2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-3VALWP/5VALWP

www.vinafix.vn
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 58 of 66
A B C D E
5 4 3 2 1

PJP201 0.675Volt +/- 5%


VLDOIN_1.35V 2 1 +1.35VP TDC 0.7A
Peak Current 1A
B+ @ PJP200 PAD-OPEN1x1m
2
2 1
1 1.35V_B+ 1
PR200
2 BOOT_1.35V OCP Current 1.2A
2.2_0603_5%
JUMP_43X118

DH_1.35V

MDU1516URH 1N POWERDFN56-8
10U_0805_25V6K

2200P_0402_50V7K
0.1U_0402_25V6
D D

4.7U_0805_25V6-K
+0.675VSP

10U_0603_6.3V6M

10U_0603_6.3V6M
1

1
PC206 SW _1.35V

PC202

PC203

PC204

PC205
0.22U_0603_10V7K

1
2

1
DL_1.35V

PC207

PC208
16

17

18

19

20
5
@ @ PU200

PQ201

VLDOIN
PHASE

UGATE

BOOT

VTT

2
21
PAD
15 1
4 LGATE VTTGND

14 2
PL201 PR201 PGND VTTSNS
1UH_PCMB063T-1R0MS_12A_20% 6.04K_0402_1%

1
2
3
1 2 1 2 CS_1.35V 13 3
+1.35VP CS RT8207MZQW _W QFN20_3X3 GND

5
PC213 1U_0603_10V6K

4.7_1206_5%
2 1VDDP_1.35V 12 4

PQ203
PR203 VTTREF_1.35V

PR202
5.1_0603_5% VDDP VTTREF

MDU1511RH 1N POWERDFN56-8
1
+ PC201 @ +5VALW 1 2 VDD_1.35V 11 5
+1.35VP PC209
1 SNUB_1.35V 2 VDD VDDQ

PGOOD
330U_2.5V_M 4 0.033U_0402_16V7~D

TON
2 PC210

FB
S5

S3
+3VALW 1U_0603_10V6K

2
PC211 220P_0402_50V8J
680P_0603_50V7K

1
2
3

10

6
C 1 2 C
+5VALW

100K_0402_1%
2
PC212

PR209
PR204
@ 7.68K_0402_1%
2

1.35V_FB 2 1

1
6 1.35V_SUS_PW RGD
PR205
1M_0402_1%

2
PR206 1.35V_B+ 1 2

1
0_0402_5% PR207
1 2 S5_1.35V 10K_0402_1% PC214
43,56,60 SYSON @ @ .1U_0402_16V7K

2
1

PC215 PR208

1
0_0402_5%
1U_0402_6.3VX5R 1 2 S3_1.35V
2

10,43,56,60,61 SUSP#

0.1U_0402_10V7K
PC216
1
1.35VP
TDC 13.75A

2
+1.35VP
Peak Current 19.64A
OCP current 23.57A @
TYP MAX
B H/S Rds(on) :12.2mohm , 15mohm B

L/S Rds(on) :2.7mohm , 3.3mohm @


PJP202
@ PJP203
+0.675VS 2 1 +0.675VSP 1 2
+1.35V +1.35VP
PAD-OPEN 4x4m
PAD-OPEN1x1m
@ PJP204
1 2

PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.35VP/0.675VSP
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 59 of 66
5 4 3 2 1
5 4 3 2 1

@ PJP300
+1.05VP_B+ 2 1
2 1 B+
JUMP_43X118

+3VS

2200P_0402_50V7K

10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0402_25V6
1

1
PC303
PC302

PC304

PC305
2
D D

2
5
@ PR300
100K_0402_5% @ @

1
4
PQ301
PC306 MDV1528URH 1N PDFN33-8
PU300 .1U_0603_25V7K
PR301
1 10 BST_+1.05VP 1 2 2 1

3
2
1
PGOOD VBST
PR302 2.2_0603_5%
@ PR303 1 2 TRIP_+1.05VP 2 9 UG_+1.05VP PL301
0_0402_5% TRIP DRVH 1UH_PCMB063T-1R0MS_12A_20%
69.8K_0402_1%
43,56,59 SYSON 1 2 EN_+1.05VP 3 8 SW _+1.05VP 1 2
PR308 EN SW
+1.05VP
0_0402_5% FB_+1.05VP 4 7 +1.05VP_5V

10,43,56,59,61 SUSP#
1 2 VFB V5IN
+5VALW
RF_+1.05VP 5 6 LG_+1.05VP PC308 1
TST DRVL
1

1
@ 1 2
PC307 11 + PC301
0.22U_0402_16V7K TP 1U_0603_10V6K @ PR304 330U_2.5V_M
2

TPS51212DSCR_SON10_3X3 4.7_1206_5%
SNB_1.05VP 2

2
PR305 4
470K_0402_1%

1
PQ303 @ PC309
2

MDV1525URH 1N PDFN33-8 1000P_0402_50V7K

3
2
1

2
C C

PR306

4.99K_0402_1%
2 1

+1.05VP
2

PR307 TDC 4.56A


10K_0402_1%
Peak Current 6.51A
OCP current 7.81A
1

TYP MAX
@ PJP301
B 1 2 H/S Rds(on) 23mohm , 30mohm B
+1.05V +1.05VP L/S Rds(on) :10.8mohm , 13.6mohm
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.05VP
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 60 of 66
5 4 3 2 1
A B C D

1 1

@PR400
@ PR400

2 1
+1.5VSP
+3VS
TDC 0.66A
10K_0402_5%
Peak Current 0.88A
OCP current 1.06A

PU400 PL401

4
PJP400 1UH +-30% NRS4018T1R0NDGJ 3.2A
+3VALW 2 1 1.5VSP_VIN 10 2 1.5VSP_LX 1 2

PG
PVIN LX +1.5VSP

22P_0402_50V8J
@ PAD-OPEN 1x2m~D 9 3
PVIN LX

1
1

1
4.7_0603_5%
2 2

PC402
PC400 @ PC401 8
SVIN

PR401
22U_0805_6.3V6M~N 0.1U_0402_25V6 PR402
6 1.5VSP_FB 30.1K_0402_1%

2
FB

47P_0402_50V8J
22U_0805_6.3V6M~N

22U_0805_6.3V6M~N
5

2
EN

PC405
NC

NC
TP

PC403

PC404
0_0402_5% @

11

2
SNUB_1.5VSP
1 2EN_1.5VSP
10,43,56,59,60 SUSP#

1
@

.1U_0402_16V7K
PR403

PC406
SYN470DBC_DFN10_3X3 PR405

1
@ PR404 20K_0402_1%
47K_0402_5%

2
2

680P_0402_50V7K
PC407
@

2
@

3 3

PJP401
2 1
+1.5VS +1.5VSP
@ PAD-OPEN 1x2m~D

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9332P
Date: Friday, December 14, 2012 Sheet 61 of 66
A B C D

www.vinafix.vn
5 4 3 2 1

CPU_B+ PL500 B+
FBMA-L11-453215-800LMA90T_1812

MDU1516URH 1N POWERDFN56-8
+5VS 1 2

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2

MDU1516URH 1N POWERDFN56-8
PC501

1
@ PQ501

1U_0603_10V6K

PC502

PC503

PC506

PC504

PC505
0.22U_0603_16V7K PQ502

1
1
2

0_0402_5%

PC500

2
1
PR503
PR501 @ @
+VCCIO_OUT

2
PR500 130_0402_1% 4.12K_0402_1% PR502
2 1 1 2 2.2_0603_5% 4 4

1
D @ PR504 75_0402_5% PR505 D

2
2 1 154K_0402_1%
1 2 PU501

3
2
1

3
2
1
PR506 54.9_0402_1% 6 1 UGATE1
2 1 PR507 VCC UGATE
21K_0402_1% DRCTRL 7 2 BOOT1 PL501
PR508 0_0402_5% 1 2 FCCM BOOT 0.22UH +-20% PCMB104T-R22MS 35A
10 VIDSOUT 1 2 PWM1 3
PWM PHASE
8 PHASE1 4 1 +VCC_CORE

680P_0603_50V7K
PR510 0_0402_5% PR509

MDU1511RH 1N POWERDFN56-8
10 VIDALERT_N 1 2 102K_0402_1% 4 5 LGATE1 PQ503 PQ504 P1_SW 3 2 V1N V1N 63

MDU1511RH 1N POWERDFN56-8
GND LGATE

PC507
PR511 0_0402_5% 1 2 9
1 2 TP PR513
10 VIDSCLK
PR512 ISL6208BCRZ-T_QFN8_2X2 10K_0603_1%

2
10K_0402_1% @ 2 1
1 2 4 4 SNB_CPU_P1

4.7_1206_5%

3.65K_0603_1%
1 2 VR_EN 62 ISEN1 ISEN1

10_0402_1%
43 IMVP_VR_ON

PR514
PR519 0_0402_5%

PR515

PR516
@PR518
@ PR518
PR521 1.91K_0402_1% SDA PR517 1_0402_5%
+5VALW

3
2
1

3
2
1
2 1 ALERT# 10K_0402_1% @ V2N 1 2
+3VS SCLK 1 2
63 V2N

1
17,43,6 IMVP_PWRGD @PR520
@ PR520
1_0402_5%

ISUMP
V3N 1 2

32
31
30
29
28
27
26
25
63 V3N

ISUMN
PC508 PU500
1 2 @PR522
@ PR522

SCLK

SDA
SLOPE
ALERT#

PROG1
PROG2
PROG3
DRSEL
1_0402_5% ISUMN 62,63
0.01U_0402_50V7K 63 V4N V4N 1 2
PR538
PR523 0_0402_5% 1 24 PWM4 63 ISUMP 62,63
100K_0402_1% 1 2 VCC_PGOOD 2 VR_ON PWM4 23
PGOOD PWM3 PWM3 63
2 1 IMON 3 22 PWM2 63
PR524 4 IMON PWM2 21
1 2VR_HOT#1 NTC 5 VR_HOT# NC 20 PWM1
COMP 6 NTC PWM1 19
C 43 VR_HOT# COMP PHASE1 C
PR525 0_0402_5% FB 7 18 DRCTRL
1 2 2 1 FB2 8 FB DRCTRL 17
FB2 VIN VCC_core (Base on PDDG rev 0.8)
2

PR528
+1.05VS @PR526
@ PR526 3.83K_0402_1% PH500 0_0402_5% TDC 33A

ISUMN
ISUMP
ISEN4
ISEN3
ISEN2
ISEN1
47P_0402_50V8J

1 2 470K_0402_5%_ TSM0B474J4702RE 33 1 2CPU_B+

VDD
RTN
EP Peak Current 95A
PC509

PR529
1

0.22U_0603_25V7K
0_0402_5% 27.4K_0402_1%
DC Load line -1.5mV/A
1

2 1
9
10
11
12
13
14
15
16

1
@PR527
@ PR527 ISL95816HRTZ-T_QFN32_4X4
Icc_Dyn_VID1 60A
2

0_0402_5%

PC510
OCP current 114A

2
@PC511
@ PC511 39P_0402_50V8J
DCR 0.82m ohm
2
0_0402_5%

2 1
PR530

PC512 PR531
2 1 FB2 1_0402_1% +5VS
1 2
39P_0402_50V8J @
1

4700P_0402_50V7K~D

PC514

1
PC513 PR532 PR533 100P_0402_50V8J
COMP 2 1 2 1 FB 2 1 2 1 PC515
1U_0603_10V6K
2
1

PC516

1200P_0402_50V7K 30.9K_0402_1% 301_0402_1%

PC517 PR534
2

357_0402_1%
0_0402_5%

2 1 2 1
2
PR536

PR537
2

4700P_0402_50V7K~D 909_0402_1%

33P_0402_50V8J 2.87K_0402_1%
2
PR535

PR539
2
2

1.5K_0402_1%

2K_0402_1%
1

PR540

@ @ PC518
2 1

39P_0402_50V8J
1

2 1
PC519

B B
1

PC520
1

680P_0402_50V7K
1

PC521
0.15U_0402_10V6K
63 ISEN4
1 2

63 ISEN3
PC522
0.15U_0603_16V7K
PR541 1 2
63 ISEN2
0_0402_5%
1 2
PC523
62 ISEN1
0.068U_0603_16V7K
PC524 1 2
0.22U_0402_6.3V6K
2 1
PR543
10 VCCSENSE
PC525 11K_0402_1%
0.22U_0402_6.3V6K @ PC526 1 2
2 1 ISUMN 1 2
0.082U_0402_16V7K

PR544
PC528

PC527 330P_0402_50V7K PH501


1

0.22U_0402_6.3V6K 10KB_0402_5%_ERTJ0ER103J 2.61K_0402_1%


2 1 1 2 1 2
2

PC529 PC530 @
0.22U_0402_6.3V6K 1 2
2 1 ISUMP
ISUMP 62,63
.1U_0402_16V7K

0.01U_0402_50V7K
1

A 10 VSSSENSE A
PC531

ISUMN
ISUMN 62,63
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VCORE_ISL95816
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 62 of 66
5 4 3 2 1
5 4 3 2 1

CPU_B+
+5VS CPU_B+

MDU1516URH 1N POWERDFN56-8
1 1 1 1

100U_25V_M

100U_25V_M

100U_25V_M

100U_25V_M
MDU1516URH 1N POWERDFN56-8
PC533 + + + +

PC534

PC535

PC536

PC537
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
5

5
0.22U_0603_16V7K @ PQ505 PQ506

1U_0603_10V6K

1
1
2

1
2 2 2 2

PC532

PC538

PC539

PC540
0_0402_5%

1
PR546

2
PR547

2
2.2_0603_5% 4 4 @
D D

2
PU502

3
2
1

3
2
1
6 1 UGATE2
VCC UGATE
7 2 BOOT2 PL502
FCCM BOOT 0.22UH +-20% PCMB104T-R22MS 35A
62 PWM2
3
PWM PHASE
8 PHASE2 4 1 +VCC_CORE

680P_0603_50V7K
5

5
4 5 LGATE2 PQ507 PQ508 P2_SW 3 2 V2N

MDU1511RH 1N POWERDFN56-8
GND LGATE

1
9

PC543
MDU1511RH 1N POWERDFN56-8
TP PR548
ISL6208BCRZ-T_QFN8_2X2 10K_0603_1%

2
@ 2 1
4 4 SNB_CPU_P2
ISEN2

4.7_1206_5%

3.65K_0603_1%
62 ISEN2

10_0402_1%
@ PR552

PR549

PR550

PR551
1_0402_5%

3
2
1

3
2
1
V1N 1 2
62,63 V1N
@

ISUMN 1
@ PR553
1_0402_5%

ISUMP
62,63 V3N V3N 1 2

@ PR554
1_0402_5% ISUMN 62,63
V4N 1 2
62,63 V4N

ISUMP 62,63

+5VS CPU_B+

MDU1516URH 1N POWERDFN56-8
2

C C

MDU1516URH 1N POWERDFN56-8
PC544

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
5

5
0.22U_0603_16V7K @ PQ510 PQ509
1U_0603_10V6K

1
1
2

1
PC545

PC546

PC547

PC548
0_0402_5%

1
PR555

PR556

2
2.2_0603_5% 4 4 @
1

PU503

3
2
1

3
2
1
6 1 UGATE3
VCC UGATE
7 2 BOOT3 PL503
FCCM BOOT 0.22UH +-20% PCMB104T-R22MS 35A
62 PWM3
3
PWM PHASE
8 PHASE3 4 1 +VCC_CORE

680P_0603_50V7K
5

5
4 5 LGATE3 PQ511 PQ512 P3_SW 3 2 V3N

MDU1511RH 1N POWERDFN56-8
GND LGATE

1
9

PC551
MDU1511RH 1N POWERDFN56-8
TP PR557
ISL6208BCRZ-T_QFN8_2X2 10K_0603_1%

2
@ 2 1
4 4 SNB_CPU_P3
ISEN3

4.7_1206_5%

3.65K_0603_1%
62 ISEN3

10_0402_1%
@ PR561

PR558

PR559

PR560
1_0402_5%
3
2
1

3
2
1
V1N 1 2
62,63 V1N
@

ISUMN 1
@ PR562
1_0402_5%

ISUMP
62,63 V2N V2N 1 2

@ PR563
1_0402_5% ISUMN 62,63
V4N 1 2
62,63 V4N
B B
ISUMP 62,63

+5VS CPU_B+
MDU1516URH 1N POWERDFN56-8
2

MDU1516URH 1N POWERDFN56-8

PC552
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
5

0.22U_0603_16V7K @ PQ514 PQ513


1U_0603_10V6K

1
1
2

1
PC553

PC554

PC555

PC556
0_0402_5%

1
PR564

PR565
2

2.2_0603_5% 4 4 @
1

PU504
3
2
1

3
2
1

6 1 UGATE4
VCC UGATE
7 2 BOOT4 PL504
FCCM BOOT 0.22UH +-20% PCMB104T-R22MS 35A
62 PWM4 3
PWM PHASE
8 PHASE4 4 1 +VCC_CORE
680P_0603_50V7K
5

4 5 LGATE4 PQ515 PQ516 P4_SW 3 2 V4N


MDU1511RH 1N POWERDFN56-8

GND LGATE
1

9
PC559
MDU1511RH 1N POWERDFN56-8

TP PR566
ISL6208BCRZ-T_QFN8_2X2 10K_0603_1%
2

@ 2 1
4 4 SNB_CPU_P4
ISEN4
4.7_1206_5%

3.65K_0603_1%

62 ISEN4
1

10_0402_1%

@ PR570
PR567

PR568

PR569

1_0402_5%
3
2
1

3
2
1

62,63 V1N V1N 1 2


@
2

ISUMN 1

@ PR571
A 1_0402_5% A
1 2
ISUMP

62,63 V2N V2N

@ PR572
1_0402_5% ISUMN 62,63
62,63 V3N V3N 1 2

ISUMP 62,63

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title
PWR_VCORE_ISL6208

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9332P
Date: Friday, December 14, 2012 Sheet 63 of 66
5 4 3 2 1
A B C D

VIN VIN P2
Iada=0~4.62A(90W) PQ705 SI7149DP SI7149DP PQ706 P3
PQ702 SI7149DP SI7149DP PQ703 P3
P2 1 1
1 1 ADP_I = 19.9*Iadapter*Rsense 2 2 CC = 3.52A (Normal)
2 2 5 3 3 5
5 3 3 5
CV = 13.3V
PR703

4
0.005 +-1% 2512

4
Back_G1 B+ Back_G1 Back_G2

1
Back_G2 1 4 SI7149DP PQ704

200K_0402_1%
0.1U_0603_25V7K
3

PR702
PQ707 2 3 CSIN 1

PC702
PDTA144EU PNP_SOT323 2

5600P_0402_25V7K
1

1 1
CSIP 3 5

2
2
200K_0402_1%

CHG_B+
PR704

PL701
1UH_PCMB053T-1R0MS_7A_20%

4
1 2 PR705
2

Dis_G 200K_0402_1%
1

PC703
1 2

0.1U_0603_25V7K
1 VIN
PQ709

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K
DDTC115EUA-7-F_SOT323

PC704

PC705

PC706
1

2
2

PC707
V1

10_0402_5%

10_0402_5%
P2 100K_0402_1%
1

1
PR708

PR709
PR710
PR711
PR707 @ 47K_0402_1%

0.1U_0402_25V6K

2
150K_0402_1% 1 2 V1

SSM6N7002FU-2N_SOT363-6
@

0.1U_0402_25V6K
3

1
3
2

2
PQ716B
PR717 DMN66D0LDW-7 2N SOT363-6

2
PR712
DMN66D0LDW-7 2N SOT363-6

1
5

PC708

PC711
43,57,64 BATT_TEMP 10_1206_1%
6

2
1 2
PQ710B

PC713

0.1U_0402_10V7K

DDTC115EUA-7-F_SOT323
1
1

PC710
PQ710A

0.047U_0603_25V7M PC709

1
1
1U_0603_10V6K

PQ711
5 1 2

1
2 PC712 2

2
@ 1U_0603_25V6K PR713
4

2
1VDDP_LDO

4.7_0603_5%
1

VIN 2 1
ISL8731_ICREF PC715

232K_0402_1%

3
PC714 PR716

2
1000P_0402_50V7K 0_0603_5% 0.1U_0603_25V7K

28

27
1
1 2

PR715
PU700 1 2BST_CHGA 1 2
100K_0402_1%

ICREF

CSSP

CSSN
2
DCIN 22 26 PQ701 2

DCIN ICOUT PC716

1
1 PR719 2 ACSETIN 2
2

ACIN

5
PR720 49.9K_0402_1% 25 BST 1 2
200K_0402_5% ACIN 13 BOOT
17,29,43,47,57 ACIN ACOK

MDU1516URH 1N
ACIN 1 2 +5VALW 1U_0603_10V6K
1

11
158K_0402_1%

@ PR722 VDDSMB
0.1U_0402_10V7K
DDTC115EUA-7-F_SOT323

PR721

0_0402_5% 10 4
SCL
1

1
PC717

2 1
29,43,57 EC_SMB_CK1 9 21 VDDP_LDO
2

@ PR724 SDA VDDP


2

PR723 0_0402_5% 14 PR725

3
2
1
NC
PQ713

1 2 2 2 1 24 DH_CHG PL702 0.01_1206_1%


29,43,57 EC_SMB_DA1 UGATE
8
VICM
5.6UH_PCMB104T-5R6MS_8A_20% BATT+
10K_0402_5% 23 LX_CHG 1 2 CHG
1 4
6 PHASE

4.7_1206_5%
FBO 2 3
DMN66D0LDW-7 2N SOT363-6

1
4 ACOFF ISL8731_EAJ 5 PQ714
EAI
6

PR728
4 20
PQ718A

DL_CHG
4.7K_0402_5%

EAO LGATE

MDV1525URH 1N

10U_0805_25V5K~D

10U_0805_25V5K~D

10U_0805_25V5K~D

10U_0805_25V5K~D
2

10_0402_5%
BATT_TEMP @

1
PR730

PC720

PC721

PC722

PC723
PR729 SNUB_CHG
100_0402_1% ISL8731_REF 3 19 4
1

VREF PGND

1
18

PR731
680P_0402_50V7K
0.01U_0402_25V7K

2
CSOP

PC719
33K_0402_1%

@
1

1
PC735

7 17

2
CE CSON
PR738

3
2
1
15 VFB 1 PR734 2 @
BATT+
2

12 VFB
33K_0402_1%

43,57 ADP_I GND


@ 16 100_0402_5%
0.1U_0402_10V7K
2

@ 29 NC PC726
3

ISL8731_REF TP 1 2
1

1
PC728

ISL8731_ICREF
PR735

ISL88731CHRTZ-T_QFN28_5X5~D 0.22U_0603_25V7K
@ PC731
2

1 2
33K_0402_1%

@
2

1
0.01U_0402_25V7K

1 2

PR739
33K_0402_1%

PC732 0.1U_0402_25V6
1
PC733

.1U_0402_16V7K
1

PR736

@
2

@
2

PR740 PR741
For DT Mode 0.004_1206_1% PL703 0.004_1206_1% PL704
FBMA-L11-453215800LMA90T_2P FBMA-L11-453215800LMA90T_2P
B+_MXM 1 4 1 2 B+_MXM1 1 4 1 2
B+ B+
VIN V1 2 3 2 3
1 1 1 1
100U 25V M

100U 25V M

100U 25V M

100U 25V M
DMN66D0LDW-7 2N SOT363-6 3.3K_1206_5%~D

+ + + +
PC736

PC737

PC738

PC739
SSM6N7002FU-2N_SOT363-6
1

6
PR737

2 2 2 2
PQ716A

MXM_CUR_VIN+ 29 MXM1_CUR_VIN+ 30
4
2 4
43,57,64 BATT_TEMP
2

MXM_CUR_VIN- 29 MXM1_CUR_VIN- 30
@
1
3

PQ718B

5
43,64 ACOFF
Security Classification Compal Secret Data Compal Electronics, Inc.
4

Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title


PWR-Charger

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9332P
Date: Friday, December 14, 2012 Sheet 64 of 66
A B C D
5 4 3 2 1

Based on PDDG rev 0.8 Table 5-1.

+VCC_CORE +VCC_CORE

1 1 1 1 1
D 1 1 1 1 1 D
+ PC905 + PC906 + PC907 + PC908 + PC915
PC900 PC901 PC902 PC903 PC904
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
2 2 2 2 2 2 2 2 2 2

1 1 1 1 1 1
PC909 PC910 PC911 PC912 PC913 PC914
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM
2 2 2 2 2 2

+VCC_CORE
1 1 1 1 1
PC917 PC918 PC919 PC920 PC921
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

C 1 1 1 1 1 C

PC922 PC923 PC924 PC925 PC926


22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

1 1 1 1 1
PC935 PC936 PC937 PC938 PC939
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2

1 1 1 1
PC940 PC941 PC942 PC943
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/05/28 Deciphered Date 2013/05/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_PROCESSOR DECOUPLING
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9332P
Date: Friday, December 14, 2012 Sheet 65 of 66
5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1 for PWR

Item Reason for change Rev. PG# Modify List Date Phase

1 Adjust 1.5V output volatge P61 change PR402 to 30.1K_0402_1% 2012.7.30 SSI
PR405 to 20K_0402_1%
D D

2 Adjust 3.3V OCP seeting P58 change PR105 to 120K_0402_1%. 2012.7.30 SSI

3 Adjust 3V/5V always OTP seeting P58 modify PD100 to PR114 0_0402_1%. 2012.7.30 SSI

4 Adjust Vcore OTP seeting P62 PR531 connect to +5VS 2012.7.30 SSI

5 Add PD3 PD4 for EMD requirement P57 add PD3 PD4 to PESD24VS2UT_SOT23-3 2012.8.16 SSI

6 hiccup mode issue is not happen so we haven't need solution. P57 remove Erp lot6 Circuit 2012.8.16 SSI

7 change diode for EMI requirement P57 use PD2 (6 PIN) to combine combine PD3(2PIN) PD4(2PIN ). 2012.8.31 SSI

8 adjust the component for the 88731 schematic P64 change PR722 and PR724 to short footprint 2012.9.10 SSI
remove PR701 PR706 PC701 PC734 PR732

C 9 adjust RTC circuit for safety concern P57 add PR2 1K_0402_5% 2012.9.10 SSI C

10 change ACIN bead for current limit rating P57 change PL1 PL4 to C8B BPH 853025_2P 2012.9.10 SSI

11 add PR116 for 3v 5v_EN delay time solution P58 add PR116 402K_0402_1% 2012.9.18 SSI

12 change output choke to improve efficiency P59 change PL201 to 1UH_PCMC063T-1R0MN 2012.9.18 SSI

13 change PR500 value to meet INTEL SPEC. P62 change PR500 to 130_0402_1%~D 2012.10.4 SSI

P67

B B

14

15

16

17

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_PIR 1

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7902P
Date: Friday, December 14, 2012 Sheet 66 of 66
5 4 3 2 1

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