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CMOS Amplifier Design: An Introduction

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CMOS Amplifier Design: An Introduction

Copyright 2016 Arjuna Marzuki

ii
iii
Preface
CMOS amplifier is a very important sub block in any integrated circuits whether they are simple
analog mixed signal IC or a complex system on chip. This short engineering book is the first in
the series of ‘An Introduction’.

How this book be useful to the readers?

This short book is arranged or organized for quick reading and ‘exercise’of simple cmos analog
amplifier. Several examples in LTSpice is shown and can be requested by email
[email protected].

iv
 1. Introduction
This section provides a brief introduction to the basic cmos amplifier in particular 2-stage CMOS
amplifier.

1.1 CMOS Amplifier

M11 M13
30/5 30/5 30/5 30/5
90/5
M18
100/2 100/2 100/2 100/2
40/2 40/2 M12 M14

Current mirror 1 Current mirror 3

100/2 100/2 50/25
Iref M17

M16
10/5 10/5 M15 20/3
Current mirror as 20/3
active load
Current mirror 2

Figure 1.1: 2-Stage CMOS Amplifier

Figure 1.1 shows two stage operational amplifier. Iref is generated/sourced from a voltage reference
circuit. Input stage together with M12 and M14 forms folded cascade configuration. M15 and M16 acts as
active load for the first stage amplifier. Output stage is a common source amplifier with a compensation
capacitor. M18 acts as a load. Important parameters describe behavior of CMOS amplifier are: Input
voltage range, frequency response, noise, current consumption and numerous others. These parameters
are discussed in next sections.

1
 2. Input Voltage Range
The range describes the ‘allowable’ input voltage which will produce a linear, non-distorted
output signal.

2.1 Theory
VDD VDD

IN+
IN-

M12 M14

M15
M16

Figure 2.1: Input stage of cmos amplifier

The maximum input voltage must not make the input transistor as in Figure 2.1 move into a linear region
mode.

VDS  VGS  VT (1)

VG is input voltage, VD is VDD - VDSAT (PMOS)

From the above topology, the input voltage is able to swing to slightly above VDD . MI5 and MI6 are
configured to oppose to that current flowing out of MI4. (ie. MI6 current will mirror current of MI5).
However VDM12 is not equal to VDM14.

2
2.2 Example

Figure 2.2: Basic Differential Amplifier

If VI1 is varied from 2 to 3 V (VI2 is fixed at 2.5 V), the drain current of both transistors is shown in
Figure 2.2. The characteristics of the drain current have indicated that there is a working range of
differential voltage for the differential amplifier. Ideally both transistors should turn ON when they are
working as differential amplifier; therefore the limit of the range of differential amplifier is the applied
input voltage which would turn OFF one of the transistor pair.

3
 Figure 2.3: Drain currents vs Input Voltage

If that the case, when one of the transistors is OFF, the applied Vgs is therefore either very high or low
and this set the limit for the input voltage.

I ds 
W
2L

Cox  n Vgs  Vt 2 , so Vgs  Vt  2L
WC ox 
I ds , if the input differential voltage is Vid  Vgs1  Vgs 2 , then
n

we have Vid 
2L
WC ox  n
 I ds1  I ds 2 .

4
 The maximum input differential voltage is found by setting I ds1  I ss and I ds2 0, therefore

(2.1)

Exercise:

Given KPn is 120 μA/V2

Based on Figure 2.2, calculate Vid max , VI1min and VI1max.

5
 3. Signal Path of CMOS Operational Amplifier

The signal path is considered the path of ‘signal flow’ from the input to the output. Signal path can be
used to analyze the frequency response, stability and numerous others.

3.1 Overall Signal Path

-IN

OUT

Signal Phase

Figure 3.1: Signal Path of the CMOS amplifier (based Figure 1.1)

Figure 3.1 shows the signal path, with arrows indicate the ‘signal phase’. The circuit, a folded cascode
with its gain = 1, it also reduces miller effect at high frequency. From Figure 3.1, output signal is 180
phase shift of the input signal.

3.2 Load
There are basically two type of active load; diode connected MOS or current source MOS.

M1

Figure 3.2: output stage of cmos amplifier

6
Figure 3.2 shows the output stage with a current source as the load.

Figure 3.3 shows curve of the active load and M1 IV curve. Due to Vgs of the active is fixed, thus we
have only one curve.

IDS
I vs V (M1)

Active load

Linear of active load

VDS
Figure 3.3: IV curve of the active
load and M1

IDS I vs V (active
load)

VDS

Figure 3.4: IV curve of the active

load

Current source load small signal resistance value is ro = 1/λId while diode connected load small signal
resistance is 1/gm.

The low frequency gain (DC gain),

AV  g mn (roM 16 // rocasp ) g M 17 (roM 18 // roM 17 ) (3.1)

Typical Load problem:

7
 - Buffer configuration is severe test for instability (you need to have bigger compensation capacitor)
- Cannot drive low load.

Output resistance and capacitance typically will affect the output stage. The f3dB,

1
f 3dB  (3.2)
2 (roM 18 // roM 17 )C L

While, the transition frequency,

g mn
fT  (3.1)
2C L

3.3 Cascode current source

M1 M3
100/2 100/2

0.4

M2 M4
10/5 0.7V 10/5

Figure 3.5: Cascode current source

The lower devices (M2 and M4) are dimensioned so that the gate voltage has the required value for
cascode biasing. The top devices (M1 and M3) are made wide enough to leave a comfortable margin
between their source potential and VDSAT of the bottom devices.

8
3.4 Example
Figure 3.6 depicts amplifier with simple current source as the load.

Figure 3.6: Amplifier with simple current source as a load

Figure 3.7-3.9 show the simulation results of the amplifier with simple current source as the load.

9
Figure 3.7: output resistance

10
Figure 3.8: Output Voltage
11
Figure 3.9: Drain current of M2 and M3

12
Figure 3.10: Amplifier with load (cascode current source)

Figure 3.10 shows the amplifier with cascode current source as the load.

13
 Figure 3.11: Output resistance of cascode-load

Figure 3.11 describes the output resistance of the simulated amplifier. It has lower output
resistance, but higher gain due to Id is high.

14
 4. CMOS Amplifier Parameters

4.1 Input offset

+ Vout
-

Vin
Vref

Figure 4.1a: Input offset Simulation Configuration

Vout

Vin
VI Vref
Figure 4.1b: Input offset Simulation Results

Offset voltage is Vref - VI (4.1)

The offset voltage of the amplifier, resulting from mismatches in threshold voltage, load
resistance and etc.

15
4.2 Common mode input voltage range
+
Vout
-

Vin

Figure 4.2a: Input voltage Range Simulation Configuration

Vout

Vin
Input voltage range
Figure 4.2b: Input voltage Range Simulation Results

16
Figure 4.3: Folded CMOS amplifier with input voltage range configuration

V1 which set the main current source plays significant role in the input voltage range.

Exercise: KCL of the current sources.

17
Figure 4.4: Input Voltage Range Simulation Results

18
4.3 Current consumption

Vcc

A I

+
-

Vin

Figure 4.5a: Current Consumption Simulation Configuration

Vin
I

Icc

o
Vin
Figure 4.5b: Current Consumption Simulation Results

19
4.4 Common Mode Rejection Ratio (CMRR)
CMRR is ratio of differential gain over common mode gain.

R2

R1
+
Vout (ac)
-
R3

Vin ac ~ R4

Vac

Figure 4.6a: CMRR Simulation Configuration

o

(V ) in
Vout
CMRR
(dB)
Very bad due to
high frequency
effect
-90

freq
Figure 4.6B: CMRR Simulation Results

20
4.5 Power Supply Rejection Ratio (PSRR)
PSRR is ratio of Vout over Vin (signal at power supply). It can be defined as how well the
amplifier can reject noise or changes on the VDD and ground power buses.

~ ac input (V )
in

Vcc
+ Vout
- Vcc

DC Vref

Figure 4.7a: PSRR Simulation Configuration

( )
Vout
Vin
PSSR
(dB)

Figure 4.7b: PSRR Simulation Results freq ( ac input )

Typical approach to increase PSRR is by using cascode current source or sink (this is due to its
high output resistance).

21
4.6 Slew rate and setting time

 High slew rate

i. Small compensation capacitor
ii. Increase the operating current.

+
Vout
-
Vin =
Big
signal

Figure 4.8a: Slew Rate and Settling time Simulation Configuration

Vout

90%
Vout

10% Vin

Slew
Rate TSettling
Time
Figure 4.8a: Slew Rate and Settling time Simulation Results

Settling time is equal to Tsettling. Slew rate is

(4.2)

22
4.7 DC Gain, fc(3dB) and fT
+
Vout
-
VI

1MH

1F

~ ac

Figure 4.9a: DC Gain,fc and fT configuration

or -180° Phase

180°
DC gain

80 dB 3 dB

0 dB

100 Hz fc fT
Figure 4.9b: DC Gain,fc and fT simulation results Freq

fc is frequency when gain drop by 3 dB. fT is transition frequency or unity gain. DC gain is low frequency
gain.

23
Figure 4.10: Example of open loop response of cmos amplifier

24
Figure 4.11: open loop response simulation result of cmos amplifier

25
4.8 Noise
For 1 μA, electron pass every second will create 7800 GHz ripple (noise).

i) Use a larger input transistor to reduce noise.

ii) Increase operating current.
iii) White noise/short noise – flat/constant the entire operation.
iv) Flicker noise.

+
-

Figure 4.12a: Noise Simulation Configuration

Output noise = input noise

12 n

10 100 1000
Freq
Figure 4.12b: Noise Simulation Results

Example of noise calculation between 100-1000Hz,

26
Figure 4.13: Example of Noise simulation configuration

27
Figure 4.14: Noise simulation Results
28
4.9 Distortion:

waveform is not
sinusoidal - it is distorted

Figure 4.15a: Distorted Output Signal

550mV

2nd

5th

25kHz
Figure 4.15b: Distorted Output Signal in Frequency
domain

Figure 4.15a and 4.15b describe the output signal in time domain and frequency domain respectively.

To convert time domain to frequency domain, Algorithm called FFT or DFT can be used.

Harmonic = (4.3)

Fundamental = 550 mV. Using equation (4.3), Harmonic is 42 mV.

Harmonic
Therefore, Distortion =  0.07 or 7%.
Fundamental

CAUTION -> Watch out FFT setting. Please do a Test case.

29
 5. Common mode feedback

M3 M4
M7

V3 V4

V1 V2
M1 M2

IBIAS

M6 M5

Figure 5.1: Differential Amplifier with load (current source)

Amplifier in Figure 5.1 has the advantage of a larger input common mode range because M3 is no longer
connected in diode connection configuration. IBIAS sets the current in M3, M4 and M5. It is likely that
these currents will not be exactly equal.

30
 MC3
M3 M4
MC4

RCM1 V3 V4
IBIAS Vcm RCM2 V1
MC1 MC2 M1 M2

MB MC5 M5

Common Mode Feedback Circuit

Figure 5.2: Differential Amplifier with CMFB Circuit

Figure 5.2 shows how a feedback circuit is used to stabilize the common mode output voltage V3 and V4.
In this circuit, the arrange value of V3 and V4 are adjusted until average of V3 and V4 is equal to VCM.
The resistors RCM1 and RCM2 must be large enough so as not to degrade performance in the differential
signal.

31
 6. Compensation in Amplifier

A compensation is required to ensure stability in on opamp. A loop gain and phase are normally
used to indicate the stability of the Opamp. For an application, the opamp is normally configured
in closed-loop configuration for the loop gain and phase analysis.

6.1 Loop Response

Figure 6.1: 2 stage CMOS amplifier with open loop frequency response

The feedback capacitor, C1 and resistor, R1 form a time constant so that none of the AC output
is fed back to the inverting input. Nevertheless, the DC bias level is fed back so that the input
stage of amplifier is properly biased. Cc is the compensation capacitor used to ‘split’ the lower
frequency pole and higher frequency pole further apart. While Rz is used to eliminate zero.

32
Figure 6.2: The open loop frequency response

From Figure 6.2, the phase shift when gain it unity is -88°, so taking the difference between this
value and 180° gives a Phase Margin of 92°. The gain margin is approximately 25 dB. Phase
margin, PM should be >60° to ensure stability, this to cater process variation and so on. It is
advisable to run some statistical analysis to ensure the phase margin is ‘good’ in all conditions.

33
 VCC

Iref

Cc
IN - IN +
Out

VEE

Figure 6.3: Simple Bipolar Opamp

Figure 6.3 shows an example of a simple bipolar Opamp, which employs 3 –Stage design. Cc is
the compensation capacitor.

34
 + Out

R2 R1
L1, (1MH)

CI ( IF )

~ Vac

Figure 6.4: Simulation of the loop gain and phase

Figure 6.4 shows another the simulation of loop gain and phase with closed – loop gain
determined by R1 and R2 (Non-inventing amplifier). C1 and L1 are used to ‘break’ the closed –
loop for the loop gain and phase analysis.

Exercise of Figure 6.4, without LC what happen, what about DC biasing voltage.

35
 Phase

Phase Gain
( dB )
-180° or 180°

PM = 60°

60°
Larger
40 dB
CC
Loop gain
PM

0° 0 dB

0 1K 10K 100K 1M 10M Freq ( Hz )

Figure 6.5: Loop analysis shows greater PM with ‘suitable’ Cc

36
6.2 Pulse Response
Pulse response is another method which also can be used to study stability in the OPamp.

+ Out
-

R1

R2

Figure 6.6a: Simulation of the Pulse response

37
 V

-1

Time ( s )

Figure 6.6b: Output pulse response

Of the circuit in Figure 6.6a

The stability is achieved by ensuring fewer than 4 peaks are in the damped oscillation.

38
 Additional Reading

Advances in RFID Components Design: Integrated Circuits

Problems
1. If the differential amplifier is single-ended drive of signal (transient), the output
currents of both output are sometimes not the same. Current source, Iss and M1 and M2 size play
significant roles.

2. If both PMOS folded and NMOS folded are employed at the input, what will be
the input voltage range.

Index
cascode, 6, 8, 13, 14, 21 gain, 6, 7, 14, 20, 23, 32, 33, 35

compensation, 1, 8, 22, 32, 34 noise, 1, 21, 26

current source, 6, 7, 8, 9, 13, 17, 21, 30 Phase Margin, 33

Distortion, 29 pole, 32

feedback, 30, 31, 32 stability, 6, 32, 33, 37, 38

folded, 1, 6, 39 transition, 8, 23

39

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