Lab report 2

Name: GHULAM JILLANI Reg#: FA19-BCE-059

Lab 2: To Explain the Universality of NAND and NOR GATES in ORDER to Design Other Logic
Gates
Objectives:
 To construct different logic gates using NAND gates.
 To construct different logic gates using NOR gates.

Lab Tasks
Part 1
Task 1: Verification of AND function by NAND gate:
Description:
In this task I had verified the AND gate by using NAND gate and verify the output by giving the input
both on hardware and software(proteus) as shown in fig 1.1 and I get the required result accurately.

Schematics:

Fig 1.1 shows schematic diagram of the required function

Truth table:
Table 1.1 shows output of AND gate

A B Output
0 0 0
0 1 0
1 0 0
1 1 1
Task 2 : Verification of OR function by NAND
Description:
In this task I had verified the OR gate by using NAND gate and verify the output by giving the input both
on hardware and software(proteus) as shown in fig 1.2 and I get the required result effectively.

Schematic:

Fig 1.2 shows the stimulated circuit of required function

Truth table:
Table 1.2 shows output and verification of required function

A B Output
0 0 0
0 1 1
1 0 1
1 1 1
Task 3:Verification of NOT function by NAND
Description:
In this task I had verified the NOT gate by using NAND gate and verify the output by giving the input
both on hardware and software(proteus) as shown in fig 1.3 and I get the required result effectively.

Schematics:
 Fig 1.3 shows the stimulated circuit of required function

Truth table:
Table 1.3 shows output of required function

A Output
0 1
1 0
Part 2
Task 1:Verification of AND function by NOR gate
Schematic:

Fig 1.4 shows the stimulated circuit of required function

A B Output
0 0 0
0 1 0
1 0 0
1 1 1

Task 2:Verification of OR function by NOR gate

Fig 1.5 shows the stimulated circuit of required function

Truth table:
Table 1.5 shows output of required function

A B Output
0 0 0
0 1 1
1 0 1
1 1 1
Task 3:Verification of NOT function by NOR gate
Schematic:

Fig 1.6 shows the stimulated circuit of required function

A Output
0 1
1 0

Post Lab
1: Design NOR, XOR and XNOR gate using NAND gate only
NOR using NAND gate
Description:
In this section, I have stimulated NOR gate using NAND gate both on proteus and hardware by using four
NAND gate with their combination used in fig 1.7 below. Then I verified the result and match my results
with proteus and hardware each other.

Schematic:

Fig 1.7 shows the stimulated circuit of required function

Truth table:
Table 1.7 shows NOR table

A B A+B (A+B)’
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
XOR Using NAND
Description:
I have stimulated XOR gate using NAND gate both on proteus and hardware. The equation of XOR gate is
first converted by bubbling method to all set of NAND gate . Then I verified the result and match my
results with proteus and hardware each other.

Schematic:

Fig 1.8 shows the stimulated circuit of required function

Truth table:
Table 1.8 shows output of required function

A B AꚛB
0 0 0
0 1 1
1 0 1
1 1 0
XNOR using NAND
Schematic:
 Fig 1.9 shows the stimulated circuit of required function

Truth table:
Table 1.9 shows output of required function

A B Output
0 0 1
0 1 0
1 0 0
1 1 1
2: Design NAND, XOR and XNOR gate using NOR gate
NAND gate by NOR
Description:
In this section, I have stimulated NAND gate using NOR gate both on proteus and hardware by using four
NOR gate with their combination used in fig 1.10 below. Then I verified the result and match my results
with proteus and hardware each other.

Schematic:

Fig 1.10 shows the required circuit

Truth table:
 Table 1.10 shows the output of the required gate

A B Output
0 0 1
0 1 1
1 0 1
1 1 0
XOR using NOR
Description:
I have stimulated XOR gate using NOR gate both on proteus and hardware. The equation of XOR gate is
first converted by bubbling method to all set of NOR gate . Then I verified the result and match my
results with proteus and hardware each other.

Schematic:

Fig 1.11 shows the required stimulated circuit

Truth table:
Table 1.11 shows output of required function

A B Output
0 0 0
0 1 1
1 0 1
1 1 0
XNOR using NOR
Schematic:
 Fig 1.12 shows the required schematic

Truth table:
Table 1.12 shows output of required function

A B Output
0 0 1
0 1 0
1 0 0
1 1 1
Conclusion:
After performing this lab, I am able to convert gates by using universal gates i.e. NAND and NOR also
their implementation on hardware and software.