I/O fundamentals

Introduction
• The I/O subsystem provides an efficient mode of
communication between CPU and outside
environment
• Devices that are under the direct control of
computer are said to be connected on-line
• Input or output devices attached to the computer
are also referred as peripherals.
• I/O interface provides a method for transferring
information between internal storage and
external i/o devices.
 I/O interface
Resolves the differences between the computer and peripheral devices
• Peripherals - Electromechanical Devices
• CPU or Memory - Electronic Device

• - Data Transfer Rate

• Peripherals - Usually slower
• CPU or Memory - Usually faster than peripherals
• Some kinds of Synchronization mechanism may be needed

• - Unit of Information
• Peripherals - Byte
• CPU or Memory - Word

• - Operating Modes
• Peripherals - Autonomous, Asynchronous
• CPU or Memory - Synchronous
 I/O Bus and Memory Bus
Functions of Buses

MEMORY BUS is for information transfers between CPU and

the Main Memory

* I/O BUS is for information transfers between CPU and I/O

devices through their I/O interface

* Many computers use a common single bus system for both

memory and I/O interface units
- Use one common bus but separate control lines for
each function
- Use one common bus with common control lines for
both functions

* Some computer systems use two separate buses,

one to communicate with memory and the other with I/O
interfaces
Accessing I/O devices
Processor Memory

Bus

I/O device 1 I/O device n

•Multiple I/O devices may be connected to the processor and the memory via a bus.
•Bus consists of three sets of lines to carry address, data and control signals.
•Each I/O device is assigned an unique address.
•To access an I/O device, the processor places the address on the address lines.
•The device recognizes the address, and responds to the control signals.
Accessing I/O devices (contd..)
 I/O devices and the memory may share the same
address space:
 Memory-mapped I/O.
 Any machine instruction that can access memory can be used to transfer
data to or from an I/O device.
 Simpler software.

 I/O devices and the memory may have different address

spaces:
 Special instructions to transfer data to and from I/O devices.
 I/O devices may have to deal with fewer address lines.
 I/O address lines need not be physically separate from memory address
lines.
 In fact, address lines may be shared between I/O devices and memory, with
a control signal to indicate whether it is a memory address or an I/O
address.
Accessing I/O devices (contd..)
Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers interface

Input device

•I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
•Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
•Data register holds the data being transferred to or from the processor.
•Status register holds information necessary for the operation of the I/O device.
•Data and status registers are connected to the data lines, and have unique addresses.
•I/O interface circuit coordinates I/O transfers.
 Peripheral Devices

PERIPHERAL DEVICES
Input Devices Output Devices
• Keyboard • Card Puncher, Paper Tape Puncher
• Optical input devices • CRT
- Card Reader • Printer (Impact, Ink Jet,
- Paper Tape Reader Laser, Dot Matrix)
- Bar code reader • Plotter
- Digitizer • Analog
- Optical Mark Reader • Voice
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices
Bar Code Reader
A barcode reader (or barcode
scanner) is an electronic device
for reading printed barcodes.
Like a flatbed scanner, it consists
of a light source, a lens and a light
sensor translating optical
impulses into electrical ones.
Additionally, nearly all barcode
readers contain decoder circuitry
analyzing the barcode's image
data provided by the sensor and
sending the barcode's content to
the scanner's output port.
 Digitizer

A graphics tablet or digitizer

is a computer input device that
enables a user to hand-draw
images, animations and
graphics, similar to the way a
person draws images with a
pencil and paper.
magnetic stripe reader
A magnetic stripe reader, also
called a magstripe reader, is a
hardware device that reads
the information encoded in
the magnetic stripe located on
the back of a plastic badge.
Magnetic stripe readers can be
read by a computer program
through a serial port , USB
connection, or keyboard
wedge , and are generally
categorized by the way they
read a badge.
Paper Tape Reader

paper tape reader and

punch provides input
and output of
information to and from
the central processor by
means of reading and
punching paper tape
under program control
Paper tape Reader

Punched tape :
• form of data storage, consisting of a
long strip of paper in which holes are
punched to store data.
• Now effectively obsolete,
• it was widely used during much of the
Paper tape twentieth century for teleprinter
communication, for input to computers
of the 1950s and 1960s, and later as a
storage medium for minicomputers and
CNC machine tools.
 Paper tape Puncher
With paper tape, the
characters are punched
into a long tape in
sequence. This has also
provided the model for
the simple file formats
used by the Unix
operating system, the
Internet and
microprocessors
 Punched Cards
Another storage medium, developed by IBM at the beginning
of the century, was standard-sized punchcards, which were
used in mainframe computers.
There was room for 80 characters on each card, and this line-
length was later adopted by many file formats used in data
communication in mainframes, and later in terminals.
 I/O BUS AND INTERFACE MODULES
I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

Each peripheral has an interface module associated with it

Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Typical I/O instruction
Op. code Device address Function code
(Command)
 CONNECTION OF I/O BUS
Connection of I/O Bus to CPU
Op. Device Function Accumulator Computer
code address code register I/O
control
CPU
Sense lines
Data lines
Function code lines
I/O
bus
Device address lines
 I/O BUS AND MEMORY BUS
Functions of Buses
* MEMORY BUS is for information transfers between CPU and the MM
* I/O BUS is for information transfers between CPU
and I/O devices through their I/O interface

Physical Organizations
* Many computers use a common single bus system
for both memory and I/O interface units
- Use one common bus but separate control lines for each function
- Use one common bus with common control lines for both functions
* Some computer systems use two separate buses,
one to communicate with memory and the other with I/O interfaces
I/O Bus
- Communication between CPU and all interface units is via a common
I/O Bus
- An interface connected to a peripheral device may have a number of
data registers , a control register, and a status register
- A command is passed to the peripheral by sending
to the appropriate interface register
- Function code and sense lines are not needed (Transfer of data, control,
and status information is always via the common I/O Bus)
 Input/Output Interfaces

ISOLATED vs MEMORY MAPPED I/O

Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions

Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can be used for I/O
transfers
- Considerable flexibility in handling I/O operations
 I/O INTERFACE
Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

CPU Chip select CS

I/O
Register select RS1 Control Control Device
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Programmable Interface
- Information in each port can be assigned a meaning depending on the
mode of operation of the I/O device
→ Port A = Data; Port B = Command; Port C = Status
- CPU initializes(loads) each port by transferring a byte to the Control Register
→ Allows CPU can define the mode of operation of each port
→ Programmable Port: By changing the bits in the control register, it is
possible to change the interface characteristics
 ASYNCHRONOUS DATA TRANSFER
Synchronous and Asynchronous Operations
Synchronous - All devices derive the timing
information from common clock line
Asynchronous - No common clock

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted

Two Asynchronous Data Transfer Methods

Strobe pulse
- A strobe pulse is supplied by one unit to indicate the other unit
when the transfer has to occur

Handshaking
- A control signal is accompanied with each data being transmitted to
indicate the presence of data
- The receiving unit responds with another control signal to acknowledge
receipt of the data
 STROBE CONTROL
* Employs a single control line to time each transfer
* The strobe may be activated by either the source or
the destination unit

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe
 HANDSHAKING

Strobe Methods

Source-Initiated

The source unit that initiates the transfer has

no way of knowing whether the destination unit
has actually received data

Destination-Initiated

The destination unit that initiates the transfer

no way of knowing whether the source has
actually placed the data on the bus

To solve this problem, the HANDSHAKE method

introduces a second control signal to provide a Reply
to the unit that initiates the transfer
 Asynchronous Data Transfer
SOURCE-INITIATED TRANSFER USING
HANDSHAKE
Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
 Asynchronous Data Transfer
DESTINATION-INITIATED TRANSFER USING
HANDSHAKE
Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

* Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism
References
 Morris Mano, “Computer System Architecture”,
Pearson Education, 3rd edition.