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Pico VHDL

This document describes a VHDL design for a Pico processor. It includes the entity declaration for the top-level Pico module with its ports. It also describes two components - an ALU and a controller. There are signals declared to connect the various registers and control signals. Behavior is defined through two processes - one to model the registers and another to drive the 7-segment displays. An ALU and controller are instantiated to complete the design.

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135 views6 pages

Pico VHDL

This document describes a VHDL design for a Pico processor. It includes the entity declaration for the top-level Pico module with its ports. It also describes two components - an ALU and a controller. There are signals declared to connect the various registers and control signals. Behavior is defined through two processes - one to model the registers and another to drive the 7-segment displays. An ALU and controller are instantiated to complete the design.

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api-584316598
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pico is
Port ( fclk : in std_logic;
rst_btn : in std_logic;
go_btn : in std_logic;
sw : in std_logic_vector(1 to 8);
led : out std_logic_vector(1 to 8);
anode : out std_logic_vector(1 to 4);
CA : out std_logic;
CB : out std_logic;
CC : out std_logic;
CD : out std_logic;
CE : out std_logic;
CF : out std_logic;
CG : out std_logic);
end pico;

architecture Behavioral of pico is

component alu
Port ( rega : in std_logic_vector(3 downto 0);
regb : in std_logic_vector(3 downto 0);
controls : in std_logic_vector(3 downto 0);
alu_out : out std_logic_vector(3 downto 0);
ccr_out : out std_logic_vector(3 downto 0));
end component alu;

component pico_cntrl
Port ( clk : in std_logic;
rst : in std_logic;
go : in std_logic;
ir : in std_logic_vector(3 downto 0);
ld_in : out std_logic;
ld_out : out std_logic;
sel : out std_logic;
ld_ir : out std_logic;
ld_a : out std_logic;
ld_b : out std_logic;
ld_ccr : out std_logic;
ld_tmp : out std_logic);
end component pico_cntrl;

signal rega, regb, in_reg, out_reg, ir : std_logic_vector(3


downto 0);
signal alu_out, tmp_reg, ccr_out, ccr : std_logic_vector(3 downto
0);
signal clk, sclk, rst, go, rst_deb, go_deb, fclk2 : std_logic;
signal ld_in, ld_out, sel, ld_ir, ld_a, ld_b, ld_ccr, ld_tmp :
std_logic;

begin

clk <= sclk; -- used for demo on board


go <= go_deb; -- used for demo on board
rst <= rst_deb; -- used for demo on board

-- Wire CCR register to LEDs


led(5 to 8) <= ccr(3 downto 0);

-- Wire IN register to LEDs


led(1 to 4) <= in_reg(3 downto 0);

-- Debounce the buttons


process (clk)
variable sreg1, sreg2 : std_logic_vector(3 downto 0);
begin
if rising_edge(clk) then
if (sreg1 = "1000") then go_deb <= '1'; else go_deb <= '0';
end if;
if (sreg2 = "1000") then rst_deb <= '1'; else rst_deb <=
'0'; end if;
sreg1 := go_btn & sreg1(3 downto 1);
sreg2 := rst_btn & sreg2(3 downto 1);
end if;
end process;

-- This models all of the registers


process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
in_reg <= "0000"; out_reg <= "0000";
ir <= "0000"; ccr <= "0000";
rega <= "0000"; regb <= "0000"; tmp_reg <= "0000";
else
if ld_in = '1' then in_reg <= sw(1 to 4); end if;
if ld_out = '1' then out_reg <= rega; end if;
if ld_ir = '1' then ir <= sw(5 to 8); end if;
if ld_ccr = '1' then ccr <= ccr_out; end if;
if ld_a = '1' then
if (sel = '1') then rega <= in_reg; else rega <= tmp_reg;
end if;
end if;
if ld_b = '1' then regb <= rega; end if;
if ld_tmp = '1' then tmp_reg <= alu_out; end if;
end if;
end if;
end process;

-- Wire other registers to seven segment digits


process (fclk2)
variable selected_digit: std_logic_vector(3 downto 0);
variable anode_vector: std_logic_vector(1 to 4);
begin
if rising_edge(fclk2) then
if (rst = '1') then
anode_vector := "0111";
else
-- CA through CG output (default is on)
CA <= '0'; CB <= '0'; CC <= '0';
CD <= '0'; CE <= '0'; CF <= '0'; CG <= '0';
case (selected_digit) is
when "0000" => CG <= '1';
when "0001" =>
CA <= '1'; CD <= '1'; CE <= '1'; CF <= '1'; CG <= '1';
when "0010" => CC <= '1'; CF <= '1';
when "0011" => CE <= '1'; CF <= '1';
when "0100" => CA <= '1'; CD <= '1'; CE <= '1';
when "0101" => CB <= '1'; CE <= '1';
when "0110" => CB <= '1';
when "0111" =>
CD <= '1'; CE <= '1'; CF <= '1'; CG <= '1';
when "1000" => null;
when "1001" => CD <= '1'; CE <= '1';
when "1010" => CD <= '1';
when "1011" => CA <= '1'; CB <= '1';
when "1100" => CB <= '1'; CC <= '1'; CG <= '1';
when "1101" => CA <= '1'; CF <= '1';
when "1110" => CB <= '1'; CC <= '1';
when others => -- include "1111"
CB <= '1'; CC <= '1'; CD <= '1';
end case;

-- digit selection (account for pipelining by rotating)


case (anode_vector) is
when "1110" => -- digit 2
selected_digit := rega;
when "1011" => -- digit 4
selected_digit := out_reg;
when "0111" => -- digit 3
selected_digit := regb;
when others => -- digit 1
selected_digit := ir;
end case;

anode_vector := anode_vector(4) & anode_vector(1 to 3);


end if; -- if rst
anode <= anode_vector;
end if; -- if rising_edge
end process;
-- divide down fclk to produce fclk2
process (fclk)
variable sreg : std_logic_vector(0 to 7);
begin
if rising_edge(fclk) then
if (conv_integer(sreg) = 0) then
fclk2 <= not fclk2;
end if; -- equals zero
sreg := sreg + "01";
end if; -- rising_edge
end process;

-- divide down fclk to produce sclk


process (fclk)
variable sreg : std_logic_vector(1 to 21);
begin
if rising_edge(fclk) then
if (conv_integer(sreg) = 0) then
sclk <= not sclk;
end if; -- equals zero
sreg := (sreg(19) xnor sreg(21)) & sreg(1 to 20);
end if; -- rising_edge
end process;

-- Instantiate the ALU


alu0: alu port map
( rega => rega,
regb => regb,
controls => ir,
alu_out => alu_out,
ccr_out => ccr_out);

-- Instantiate the controller


fsm0: pico_cntrl port map
( clk => clk,
rst => rst,
go => go,
ir => ir,
ld_in => ld_in,
ld_out => ld_out,
sel => sel,
ld_ir => ld_ir,
ld_a => ld_a,
ld_b => ld_b,
ld_ccr => ld_ccr,
ld_tmp => ld_tmp);

end Behavioral;

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