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EE3032 Introduction To VLSI Design-Homework 2

The document discusses four questions related to VLSI circuit design: 1) An inverter driving a capacitive load has a shorter fall time for input stimulus a compared to b because stimulus a has a shorter rise time. 2) As the number of inputs to a NOR gate increases, the transition times (tr and tf) increase because more diffusion capacitances are added in parallel. 3) If the PMOS transistor is half the size of the NMOS, and the output voltage is half the input voltage, then the mobility of NMOS must be twice that of PMOS. 4) Given transistor sizes and assumptions about equivalent beta and mobility, the capacitance at node x can be calculated.

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53 views1 page

EE3032 Introduction To VLSI Design-Homework 2

The document discusses four questions related to VLSI circuit design: 1) An inverter driving a capacitive load has a shorter fall time for input stimulus a compared to b because stimulus a has a shorter rise time. 2) As the number of inputs to a NOR gate increases, the transition times (tr and tf) increase because more diffusion capacitances are added in parallel. 3) If the PMOS transistor is half the size of the NMOS, and the output voltage is half the input voltage, then the mobility of NMOS must be twice that of PMOS. 4) Given transistor sizes and assumptions about equivalent beta and mobility, the capacitance at node x can be calculated.

Uploaded by

陳大立
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Homework 1 1-1

EE3032 Introduction to VLSI Design—Homework 2

1. Fig. 1(a) shows an inverter driving a capacitive load CL . If two input stimuli as shown in
Fig. 1(b) are applied, the fall time of the output Vout for the input stimulus a is shorter than
that for the input stimulus b. Why? Explain the reasons. (3 points)

Vin

Vin Vout VDD


a b
CL

t
(a) (b)

Figure 1: (a) An inverter drives a load CL . (b) Two input waveforms with different rise times.

2. A MOS transistor can be modeled as a π-model. For example, Fig. 2(a) shows the π-model
of an NMOS transistor, which consists of a turn-on equivalent resistance R and two diffusion
capacitance Cd . Derive the relationship between the number of inputs (fanin) and the tr and
tf of the x-input NOR gate without loading. (3 points)

fanin
...

Cd R Cd
(b)
(a)

Figure 2: (a) MOS transistor and its RC model. (b) A x-input NOR gate.

3. Assume that the size of the two transistors of an inverter is as follows: M1=Wp /Lp = 4 and
M2=Wn /Ln = 2. If Vin= 21 VDD , the Vout= 21 VDD . Calculate the ratio of the µn to µp . (2
points)
4. Fig. 4 shows a simple logic circuit. Assume that the gate capacitance of the invert is Cg ; the
β value of the PMOS and NMOS of the inverter is βp and βn , respectively. Also, βn = βp . If
the equivalent β of PMOS network and NMOS network of the two-input NOR gate is βpeq
and βneq , respectively. Assume that βpeq = βp and βneq = βn ; µn = 2µp . Calculate the
capactiance of the node x without considering the parasitic capacitances of wire and drain.
(2 points)

Jin-Fu Li, EE. NCU Fall 2018

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