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F Computer Architecture and Organization CSE205 F1-3

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43 views3 pages

F Computer Architecture and Organization CSE205 F1-3

Uploaded by

Akash Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Term End Examination - November 2012

Course : CSE205 - Computer Architecture and Organization Slot: F1

Class NBR : 3130

Time : Three Hours Max.Marks:100

Answer ALL Questions


(10 X 10 = 100 Marks)
1. a) The content of the top of a memory stack is 5320. The content of the stack pointer [5]
SP is 3560. A two word call subroutine instruction is located in memory address
1120 followed by the address field of 6720 at location 1121. What are the content
of PC, SP, and the top of the stack:
i. Before the call instruction is fetched from memory.
ii. After the call instruction is executed?
iii. After the return from subroutine
b) Design a Register file that stores eight 32 – bit numbers and has four read ports and [5]
one write Port.

2. Compute Memory traffic, total memory for encoding and storing code for 3,2,1,0
address machines that implements the expression evaluation A= (B-C)*D. Assume that
the opcode occupy one byte, addresses occupy two bytes, data values also occupy two
bytes and 1 byte world length.

3. a) Give the advantage of using biased exponent. Express the number 178.187510 in [2+3]
IEEE single precision and double precision formats.
b) Perform the division of (117) ÷ (-9) using 2’s complement Division algorithm. [5]

4. Solve (15) x (-13) using signed magnitude multiplication algorithm and give the
flowchart.

5. A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. Design the
memory system which needs 512 x 8 of RAM, 2K x 8 of ROM and 2 interface units
with 512 registers each.
a) How many RAM and ROM chips are needed? [2]

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b) Draw the memory address map for the system. [4]
c) Give address range in hexadecimal for RAM and ROM. [2]
d) Draw a neat sketch to interface it with the CPU. [2]

6. a) Explain various update policies in cache memory. [5]


b) A digital computer has a memory unit of 64K x 16 and a cache memory of 1K
words. The cache uses direct mapping with a block size of four words.
i. How many bits are there in the tag, index, block and word fields of the [2]
address format?
ii. How many bits are there in each word of cache, and how they are [2]
divided into functions? Include a valid bit ?
iii. How many blocks can the cache accommodate? [1]

7. Explain Direct Memory Access in detail.

8. a) State how address mapping is done using random access memory page table in [5]
virtual memory.
b) Explain the operation of CDROM in detail. [5]

9. a) Consider the following code:


for( i=0;i<20;i++)
for(j=0;j<10;j++)
a[i]=a[i]*j;
i. Give one example of the spatial locality in the code. [2.5]

ii. Give one example of the temporal locality in the code. [2.5]

b) Write short notes on Input/output Performance. [5]

10. a) Give the importance of parallel computing and its applications. [5]
b) Perform Matrix multiplication using openmp. [5]

⇔⇔⇔

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