Lab Assignment 0
1. Implement 4 input AND Gate
VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
entity AND_Gate is
port( A, B, C, D: in std_logic;
Y: out std_logic);
end AND_Gate;
architecture behav of AND_Gate is
begin
Y <= A and B and C and D;
end behav;
Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_AND_Gate is
end tb_AND_Gate;
architecture Behavioral of tb_AND_Gate is
component AND_Gate is
port( A, B, C, D: in std_logic;
Y: out std_logic);
end component;
signal A, B, C, D: std_logic := '0';
signal Y : std_logic;
begin
uut: AND_Gate PORT MAP (A => A, B => B, C => C, D => D, Y => Y);
stim_proc: process
begin
wait for 10 ns;
A <= '0'; B <= '0'; C <= '0'; D <= '0';
wait for 10 ns;
A <= '0'; B <= '0'; C <= '0'; D <= '1';
wait for 10 ns;
A <= '0'; B <= '0'; C <= '1'; D <= '0';
wait for 10 ns;
A <= '0'; B <= '0'; C <= '1'; D <= '1';
wait for 10 ns;
A <= '0'; B <= '1'; C <= '0'; D <= '0';
wait for 10 ns;
A <= '0'; B <= '1'; C <= '0'; D <= '1';
wait for 10 ns;
A <= '0'; B <= '1'; C <= '1'; D <= '0';
wait for 10 ns;
A <= '0'; B <= '1'; C <= '1'; D <= '1';
wait for 10 ns;
A <= '1'; B <= '0'; C <= '0'; D <= '0';
wait for 10 ns;
A <= '1'; B <= '0'; C <= '0'; D <= '1';
wait for 10 ns;
A <= '1'; B <= '0'; C <= '1'; D <= '0';
wait for 10 ns;
A <= '1'; B <= '0'; C <= '1'; D <= '1';
wait for 10 ns;
A <= '1'; B <= '1'; C <= '0'; D <= '0';
wait for 10 ns;
A <= '1'; B <= '1'; C <= '0'; D <= '1';
wait for 10 ns;
A <= '1'; B <= '1'; C <= '1'; D <= '0';
wait for 10 ns;
A <= '1'; B <= '1'; C <= '1'; D <= '1';
wait;
end process;
end Behavioral;
Waveform:
2. Implement 4 input NAND Gate
VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
entity NAND_Gate is
port( A, B, C, D: in std_logic;
Y: out std_logic);
end NAND_Gate;
architecture behav of NAND_Gate is
begin
Y <= (A nand B) nand (C nand D);
end behav;
Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_NAND_Gate is
end tb_NAND_Gate;
architecture Behavioral of tb_NAND_Gate is
component NAND_Gate is
port( A, B, C, D: in std_logic;
Y: out std_logic);
end component;
signal A, B, C, D: std_logic := '0';
signal Y : std_logic;
begin
uut: NAND_Gate PORT MAP (A => A, B => B, C => C, D => D, Y => Y);
stim_proc: process
begin
wait for 10 ns;
A <= '0'; B <= '0'; C <= '0'; D <= '0';
wait for 10 ns;
A <= '0'; B <= '0'; C <= '0'; D <= '1';
wait for 10 ns;
A <= '0'; B <= '0'; C <= '1'; D <= '0';
wait for 10 ns;
A <= '0'; B <= '0'; C <= '1'; D <= '1';
wait for 10 ns;
A <= '0'; B <= '1'; C <= '0'; D <= '0';
wait for 10 ns;
A <= '0'; B <= '1'; C <= '0'; D <= '1';
wait for 10 ns;
A <= '0'; B <= '1'; C <= '1'; D <= '0';
wait for 10 ns;
A <= '0'; B <= '1'; C <= '1'; D <= '1';
wait for 10 ns;
A <= '1'; B <= '0'; C <= '0'; D <= '0';
wait for 10 ns;
A <= '1'; B <= '0'; C <= '0'; D <= '1';
wait for 10 ns;
A <= '1'; B <= '0'; C <= '1'; D <= '0';
wait for 10 ns;
A <= '1'; B <= '0'; C <= '1'; D <= '1';
wait for 10 ns;
A <= '1'; B <= '1'; C <= '0'; D <= '0';
wait for 10 ns;
A <= '1'; B <= '1'; C <= '0'; D <= '1';
wait for 10 ns;
A <= '1'; B <= '1'; C <= '1'; D <= '0';
wait for 10 ns;
A <= '1'; B <= '1'; C <= '1'; D <= '1';
wait;
end process;
end Behavioral;
Waveform:
Implement Half Adder
VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
entity Half_Adder is
port( A, B: in std_logic;
S, C: out std_logic);
end Half_Adder;
architecture behav of Half_Adder is
begin
S <= A xor B;
C <= A and B;
end behav;
Testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_Half_Adder is
end tb_Half_Adder;
architecture Behavioral of tb_Half_Adder is
component Half_Adder is
port( A, B: in std_logic;
S, C: out std_logic);
end component;
signal A, B: std_logic := '0';
signal S, C : std_logic;
begin
uut: Half_Adder PORT MAP (A => A, B => B, S => S, C => C);
stim_proc: process
begin
wait for 10 ns;
A <= '0'; B <= '0';
wait for 10 ns;
A <= '0'; B <= '1';
wait for 10 ns;
A <= '1'; B <= '0';
wait for 10 ns;
A <= '1'; B <= '1';
wait;
end process;
end Behavioral;
Waveform
