THIẾT KẾ VI MẠCH TƯƠNG TỰ

CHƯƠNG
ƯƠ 5: CURRENT MIRRORS

Hoàng Trang-bộ môn Kỹ Thuật Điện Tử

[email protected]
1 TP.Hồ Chí Minh 04/2012
 Content

 Basic current mirrors

 Cascode current mirrors
 Active current mirrors

11 - 4 - 2012 Analog IC Design 2

 Basic current sources

W
I D  μ n C ox
1
2
VGS  VTH 2
L

W R2
I Out  μ n C ox
1
2  R1 R2 VDD  VTH 2
L

Simple
p Resistive Biasing
g For Current Source

11 - 4 - 2012 Analog IC Design 3

 Problems

 Output current depends on

 Supply (Vdd)
 Process
ocess (W/L,V
( / , TH)):VTH vary
a y fromo wafer
ae
to wafer
 Temperature (R1,R2, μ n ,V TH )
 Output current is poorly defined

IS THERE A WAY OF GENERATING

RELIABLE CURRENTS ?

11 - 4 - 2012 Analog IC Design 4

 Basic Idea

A
Assume that
h IIreff iis available
il bl and
d pricise
i i
How do we guarantee Iout = IREF ?

11 - 4 - 2012 Analog IC Design 5

 Basic current mirror

W
 μ n C ox ( )1 VGS  VTH 
2
I REF 1
2
L

W
 μ n C ox ( ) 2 VGS  VTH 
2
I out 1
2
L
(W/L) 1
I out  I REF
((W/L)) 2

This structure is called current

mirror (For NMOS)
11 - 4 - 2012 Analog IC Design 6
 Basic current mirror

Current mirror for PMOS

11 - 4 - 2012 Analog IC Design 7

 Multiple current sources

11 - 4 - 2012 Analog IC Design 8

 Problems

If we don’t nelect channel length modulation

While
How to copy the IREF in
but VDS2 may
y not equal
q VDS1
this case ?
11 - 4 - 2012 Analog IC Design 9
 Cascode Current Mirrors

How do we generate Vb to ensure Vx = Vy ?

(
(W/L)
) 3 ((W/L)) 2
 If we chose
h M0 and
d M3
M3, so that
h 
(W/L) 0 (W/L) 1
then we have Vgs33 = Vgs00 and Vx = Vy
11 - 4 - 2012 Analog IC Design 10
 Cascode Current Mirrors (cont)

In (b) : the minimum allowable voltage at P is :

V P,min = VN – VTH = VGS0 + VGS1 – VTH = (Vgs0 – VTH ) + (Vgs1 – VTH ) + VTH
In (a) : V b is chosen to allow the lowest possible value of Vp but I out does
not accurately keep track I REF because V DS1 differ V DS2
In (b) : I out keep track I REF at higher accuracy but the minimum level Vp
is higher by VTH
11 - 4 - 2012 Analog IC Design 11
 Cascode Current Mirrors (cont)

11 - 4 - 2012 Analog IC Design 12

 Low-voltage cascode mirror

Modification of cascode mirror for low voltage operation

M1 and M2 are in saturation:

M2: Vb – VTH2 ≤ VX (= VGS1)
M1: = VGS1 – VTH1 ≤ VA (= Vb - VGS1)
 VGS2 + (VGS1 – VTH1 ) ≤ Vb ≤ VGS2 – VTH2

11 - 4 - 2012 Analog IC Design 13

 Low-voltage cascode mirror (cont)

If Vb = VGS2 + (VGS1 – VTH1 )= VGS4 + (VGS3 – VTH3 )

Then the casecode current source M3-M4
consumes minimum headroom while M1
and M3 sustain equal drain-souce voltage
,allowing accurate copy IREF

11 - 4 - 2012 Analog IC Design 14

 Low-voltage cascode mirror (cont)
Generate Vb for cascode current mirror

M1 and M2 are in saturation:

Vb,min = VGS2 + (VGS1 – VTH1 )
Select: VGS5 ≈ VGS2
VDS6 = VGS5 - Rb I1 ≈VGS1 - VTH1

M7 : large (W/L)7 so that VGS7≈VTH7

VDS6 ≈ VGS6 – VTH7
Vb = VGS5 + VGS6 – VTH7

11 - 4 - 2012 Analog IC Design 15

 Low-voltage cascode mirror (cont)
Low voltage cascode using a source follower level shifter

If MS is biased at a very low current density,ID/(W/L),

then VGSS ≈ VTHS ≈ VTH3, i.e., VN’≈ VN − VTH3, and
VB = VGS1 + VGS0 − VTH3 − VGS3 = VGS1 − VTH3
implying that M2 is at the edge of the triode region.
In this topology, however,
VDS2≠ VDS1
If the body effect is considered for M0 , MS and M3,
it is different to guarantee that M2 operates in
saturation.
saturation

11 - 4 - 2012 Analog IC Design 16

 Active current mirrors
Current mirror processing a signal

M1 and M2 are identical:

Iout = Iin (for λ = 0)

11 - 4 - 2012 Analog IC Design 17

 Differential pair with current source load

Calculate Gm
Calculate Rout
Assuming γ = 0
I out R out  (1  g m2 ro2 )(1 / g m1 )  ro2
Gm  
Vin
 2 ro2  (1 / g m1 )  2 ro2
g .V /2 g
 m1 in  m1 Thus , R out  2 ro2 // ro4
Vin 2

| A v |  G m .R out
| A v |  G m2 . 2 ro2 // ro4

11 - 4 - 2012 Analog IC Design 18

 Differential pair with current source load (cont)
Calculate Vout /Vp
Calculate Vp /Vin
Vout 1 G m2 .rro2
1 ro4 1 ro4
Vp  r
R eq  
G m2 G m2.ro2

G m2
(1 
ro2
) 1 o4
ro2
r
1 o4 G m2
VP R eq r 2 .rro2
2
  o2  r
Vin R  1
eq G
r
2 o4 1 o4
m1 ro2 ro2
Note: if ro4 → 0,, Vp
p /Vin → 1/2,, and if
ro4 →∞, Vp /Vin → 1.

Calculate Vout /Vin

r
1  o4
V out V out Vp ro2 G m2 .r o2 G m2 .r o2 .r o4 G m2
 .  ro4 . r   [(2r o2 )//r o4 ]
V in Vp V in
2 1  o2 o2  ro
2r o o4 2
ro2 ro4

11 - 4 - 2012 Analog IC Design 19

 Differential pair with active current mirrors

Concept of combining the drain currents of M1 and M2

M3 and M4 are identical

11 - 4 - 2012 Analog IC Design 20

 Differential pair with active current mirror
((large
g signal
g analysis)
y )

Operation:
+ If Vin1 << Vin2, M1 is off and so are M3 and M4.
M2 and M5 operate in triode region, carrying zero current.
Thus, Vout = 0.
+ As Vin1 approaches Vin2 for a small difference, M2 and M4
are saturated, providing a high gain.
+ As Vin1 becomes more positive than Vin2, ID1, |ID3|, and
|ID4| increase and ID2 decreases, eventually driving M4 into
the
h triode
i d region.
i
+ If Vin1 >> Vin2, M2 turns off, M4 operates in deep triode
region with zero current, and Vout = VDD.

 The choice of the input common-mode voltage:

For M2 to be saturated, Vout ≥ Vin,CM − VTH. Thus, to allow
maximum output swings, the input CM level must be as low as
possible with
possible, ith Vin,CM = VGS1,2 + VDS5,min

11 - 4 - 2012 Analog IC Design 21

 Differential pair with active current mirror
((small signal
g analysis)
y )

 Asymmetric swings in a differential

pair with active current mirror

 Calculate Gm ,node P can be viewed

as a virtual ground

g m1.V
in
I D1  I D3  I D4 
2
g m2.V
I D2   in
2

 I outt  I D2  I D4   g m1,2.V
1 2 Vin

11 - 4 - 2012 Analog IC Design 22

 Differential pair with active current mirror
((small signal
g analysis)(cont)
y )( )

Calculate Rout VX VX
IX  2 1 
ro4
o1 2 G //r01,2
2ro1,2 01 2
m3

where the factor 2 accounts for current copying action of M3 and M4.
For 2ro1,2
2ro1 2 >> (1/gm3)||ro3,
(1/gm3)||ro3 we have Rout ≈ ro2 || ro4
Calculate Av

| Av | = GmRout = gm1,2
gm1 2 (ro2 || ro4)

11 - 4 - 2012 Analog IC Design 23

 Differential pair with active current mirror
((small signal
g analysis)(cont)
y )( )

Substitution of the input differential pair by a Thevenin equivalent

Calculate Veq
q and Req
q
Veq  gm1,2.ro1,2.Vin
R eq  2ro1,2
11 - 4 - 2012 Analog IC Design 24
 Differential pair with active current mirror
((small signal
g analysis)(cont)
y )( )
Calculate Av = Vout / Vin
The current through Req is
Vout  g m1,2.r01,2.Vin
I X1  2 1
2ro1,2 //r
g m3 o3
The fraction of this current that flows through
1/gm3 is mirrored into M4 with unity gain. That is
Vout g m1,2.r01,2.Vin ro Vou
o3 out
I X1  2 1 . 1 . 0
2ro1,2 //r ro3  ro4
g m3 o3 g m3

Assuming 2ro1,2
2ro1 2 >> (1/gm3,4)||ro3,4,
(1/gm3 4)||ro3 4 we obtain

Vout g m1,2.r03,4.r01,2
Vin

r  r
 gm1,2, (ro1,2, // ro3,4, )
i o1,2
1 2 03 03,4
4

11 - 4 - 2012 Analog IC Design 25

 Differential pair with active current mirror
common mode p properties(cont)
p ( )

Differential pair with active current mirror sensing a common-mode change

The CM gain is defined in terms of

the single-ended output component
produced by the input CM change:

Vout
ACM  Vin

11 - 4 - 2012 Analog IC Design 26

 Differential pair with active current mirror
common mode p properties(cont)
p ( )
Simplified circuit of CM circuit
1 ro3,4
//
2g m3,4 2
A CM   1 .
2  RSS
2g m1,2
12

1 g m1,2
  .
1 2 g m1,2 . RSS g m3,4

where we have assumed 1/(2gm3,4) << ro3,4 and neglected the effect of ro1,2 /2.
Even with perfect symmetry, the output signal is corrupted by input CM variations, a
d
drawback
b k ththatt d
does nott exist
i t iin th
the ffully
ll differential
diff ti l circuits
i it

CMRR
A DM g m3,4 (1 2g m1,2 R SS )
CMRR   g m1,2 ((ro1,2 //r
// o3,4 ).
)  g m3,4 (1 2g
2 m1,2 R SS )(r
)( o1,2 //r
// o3,4 )
A CM g m1,2

11 - 4 - 2012 Analog IC Design 27

 END OF
CHAPTER 5

CURRENT MIRROR

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