Journal of Power Electronics (2021) 21:27–37

https://doi.org/10.1007/s43236-020-00157-w

ORIGINAL ARTICLE

Z‑domain modeling of peak current mode control for full‑bridge

DC‑DC buck converters
Xiaohong Wang1 · Qisong Huang1 · Bo Zhang1 · Di Chen1 · Quanxue Guan2 

Received: 1 August 2020 / Revised: 8 September 2020 / Accepted: 11 September 2020 / Published online: 8 October 2020
© The Author(s) 2020

Abstract
Traditional local-averaged state-space modeling for peak current mode (PCM) controls fails to explain the subharmonic
oscillation phenomenon when the spectrum is higher than half of the switching frequency. To address this problem, this
paper presents a small-signal modeling method in the z-domain, and builds a discrete linear model for the current loop of a
full-bridge DC-DC converter. This discrete model is converted into a second-order continuous model that is able to represent
the system performance with a wider frequency range. A frequency-domain analysis shows that this model can be used to
explain the subharmonic oscillations and unstable characteristics. This provides an engineering guideline for the practical
design of slope compensation. The effectiveness of the proposed modeling method has been verified by simulation and
experimental results with a prototype working in the Buck mode.

Keywords  DC-DC converter · Peak current mode control · Slope compensation · Subharmonic oscillation · Z-domain
modeling method

1 Introduction subharmonic oscillations. These oscillations result in poor

system stability. Thus, it is necessary to have an appropriate
Peak current mode (PCM) control has been widely used in control [8, 9].
power electronic converters due to its accuracy, fast dynamic The key to a good PCM control is to accurately model
response and software flexibility [1, 2]. Flying capacitor and analyze the characteristics of the current control loop.
Buck converters [3], flyback converters [4] and Buck LED The numerical calculation in [10–12] uses a piecewise linear
drivers [5] are some examples of this PCM control. In full- discrete model to iteratively calculate the circuit response.
bridge DC-DC converter applications, PCM control has a However, this method, which ignores the influence of para-
simple structure and an inherent built-in overcurrent pro- sitic parameters such as the dead-time, and the on–off volt-
tection mechanism [6]. Implementation is easy due to the age drop of the switches, is only suitable for simulations.
absence of a large inertia filtering link in the current feed- The state space averaging method eases the parameter design
back control loop [7]. This also results in the PCM control for closed-loop controllers [13–17]. However, it is only valid
having a fast response. for the low-frequency range below half of the switching fre-
In general, PCM control is implemented in cascaded quency. Modeling methods in z-domain [18–20] are prob-
double-loop control structures with the stability mainly lematic in terms of high-frequency characteristics since they
depending on the inner current loop. However, when the are based on the same local-averaged state space method.
steady-state duty ratio is higher than 50%, the converters The describing function analysis method in [21] expresses
have alternating wide pulses and narrow pulses, namely non-linearity with the fundamental component and har-
monic components using the Fourier series. However, since
* Quanxue Guan the sampling characteristics of the switches are not taken
[email protected] into account, this method cannot illustrate characteristics
higher than half of the switching frequency, which are of
1
School of Automation Science and Engineering, South special importance in the design of high bandwidth control-
China University of Technology, Guangzhou, China
lers. In addition, the aforementioned methods are relatively
2
Department of Electrical and Electronic Engineering,
University of Nottingham, Nottingham, UK

13
Vol.:(0123456789)

28 X. Wang et al.

complicated, which means they are not intuitive enough for sampling transfer function determined by the sensor and the
practical engineers. Thus, they have limited applications. conditioning circuit. The compensated voltage error signal
The high-frequency characteristics and subharmonic is used to obtain the current loop setting value, and the cur-
oscillation phenomenon are still less-explored for PCM rent comparator is used to modulate the switching duty cycle
control in DC-DC converter applications. In this paper, a signal. Then, the average voltage on the inductor is changed
z-domain modeling method is proposed. By analyzing the by adjusting the turn-on time of the switches.
small signal step response of the PCM current loop, the To simplify the analysis, it is assumed that the trans-
geometric constraint relationship between the inductance former is ideal and that the voltages of the DC-bus and the
current and the setting current at each sampling instant is supercapacitor are constant during each switching period.
established. Then, the iterative equation of the current and During the steady-state, waveforms of the gate signals and
duty cycle are obtained. As a result, the discrete transfer inductance currents can be obtained as shown in Fig. 2.
function of the system is derived, which can represent the US1–US4 are the driving gate signals for the switches
frequency characteristics above half of the switching fre- Q1–Q4, IM is the magnetic current, IP is the current of the
quency. Afterward, the model is converted to the s-domain, transformer primary, and IL is the output inductor current.
so that it is possible to design an appropriate slope compen- Once the closed loop controller becomes asymptoticly
sation to suppress the subharmonic oscillations. stable, the current loop model in Fig. 1 is equivalent to a
The main contribution of this paper is to propose a simplified PCM circuit in a non-isolated topology as shown
z-domain modeling method describing the subharmonic in Fig. 3. VD = UD/N is the referred voltage of the DC-bus
oscillation in the high frequency band, which can explain voltage with respect to the supercapacitor side according to
the instability of the PCM current loop. On the basis of this the turns ratio of the transformer, UC is the supercapacitor
model, an optimal coefficient adjustment method is provided voltage, L is the inductor, and I2 is the current flowing at the
for slope compensation, which is of great significance to transformer secondary side.
engineering design. An ideal waveform of the inductor current is shown in
Fig. 4, where Iset is the setting current, Io is the average cur-
rent, and T is a switching period.
2 Model analysis and current loop modeling

2.1 PCM control system description

A circuit and control diagram of a full-bridge DC-DC con-

verter is shown in Fig. 1. This converter is used for the
charging and discharging of a supercapacitor. For the sake
of brevity only the charging power flow in the Buck opera-
tion mode is investigated, which means the secondary side
switches work as if in a synchronous rectifier.
A double closed-loop structure is adopted to control the
converter, where PCM control regulates the inner current
loop. The control loop includes a voltage feedback compen-
sation network Gc(s), a current comparator, a switching logic
control unit, a voltage sensor and a current sensor, where Fig. 2  Steady-state waveforms of a converter in the Buck mode
Fv is the voltage feedback coefficient, and Ki is the current
Current sensor
I2 L IL
IL L D
ID
Ki
Q1
D1
Q4 D4 T D5 Q5 D6 Q6 VD=UD/N UC
UD UC
IP Super-capacitor
DC CD Q3 Q2 Q7 D Q8 module
Bus D3 D2 N:1 D7 8

Voltage Ki Current Uset Voltage S Comp

Iset
Fv Sensor
DC Controller Q
Sensor
Voltage
T R
Switching Bus Voltage
USet controller
GC(s)
Logic Comp
ISet Sensor T

Fig. 1  Full-bridge DC-DC converter with PCM control Fig. 3  Simplified non-isolated PCM circuit in the Buck mode

13
Z‑domain modeling of peak current mode control for full‑bridge DC‑DC buck converters 29

Iset IL Io Uˆ C
I
Iˆset D̂ − 1
L
1 IˆL
G1 UD NL s

0 1T 2T 3T 4T 5T 6T t D Uˆ D
Ki
Fig. 4  Inductor current according to volt-second balancing
Fig. 5  Control block diagram based on the state-space averaging
The inductor current waveform is continuous. However, method
its derivative is not equal to 0, and the overall system is not
at equilibrium. Therefore, it is a typical nonlinear system. Therefore, the AC small signal transfer function is as
To facilitate the design of the PI controllers, it is necessary follows:
to linearize the overall system around its steady-state opera-
tion point. �IL (S) || 1 1
GBuck (s) = | = (6)
�Iset (S) || ̂ Ki NL
s +1
UD (S)=Û C (S)=0 U D G1
2.2 Traditional linear approximation models
It can be seen from the transfer function that the system
The local-averaging method in [22, 23] is a mainstream has only one pole in the left half plane and that the system
modeling method for power electronic converters. Based is stable at any duty cycle. However, in actual situations, the
on the simplified structure diagram in Fig. 3, the first-order inductor current oscillates when D > 0.5. Obviously, Eq. (6)
approximated current loop model with the inductor current cannot describe this unstable phenomenon.
IL as the state variable is established as follows:
( )
2.3 Analysis of subharmonic oscillation
UD UC U D U
̇IL = − ⋅ D − C ⋅ (1 − D) = UD − C (1)
NL L L NL L Subharmonic oscillation and instability are the two main
problems of PCM control [5, 24, 25]. When VC/VD is close
Consider the small-signal model IL, D, UD, and UC which to 0.5, the angle between the rising curves of IL and Iset is
are composed of an average value and ripple components: smaller than the angle between the falling curves of IL and
Iset. When there is a disturbance in the input, after a gradual
IL = I L + ÎL , D = D + D,
̂ UD = U D + Û D , UC = U C + Û C
accumulation of disturbances over several switching cycles,
(2)
the duty cycle of two adjacent switching cycles has one large
After substituting (2) into (1) and removing the static val- and one small response, which are asymmetric at the switch-
ues, the nonlinear state model can be established as: ing frequency [26]. The current loop causes subharmonic
oscillation, as shown in Fig. 6.
D ̂ U Û
İ L = ̂ − C
UD + D D (3) Suppose the current loop input is added to a disturbance
NL NL L signal with an amplitude of one thousandth of the setting
Suppose K1 is the on-time slope of the inductor current. current and a frequency of one-half of the switching fre-
Then, the duty cycle reference in the current loop can be quency. When VC/VD is close to 0.5, the current loop exhibits
expressed below:
Ton (I − IL Ki )
D= = set = (Iset − IL Ki )G1 (4) 20.05
T T ⋅ K1 Ki Iset 20
20
19.9 Iset
19.95
19.9 19.8
where G1 = .
VD −VC
Current/A
Current/A

1 19.7
, K1 = 19.85
19.6
T⋅K1 Ki L 19.8

According to (2) and (4), the small signal of the duty 19.75
19.7
19.5
19.4
cycle in the peak current mode can be the approximately 19.65
19.6
19.3
19.55 IL 19.2
IL
expressed as: 4.0 4.5 5.0 5.5 6.0 6.5 7.0 3.5 4.0 4.5 5.0 5.5 6 . 0 6.5 7.0 7.5 8.0 8.5
Time/s ×10 -4
Time/s ×10 -4
( ) (a) (b)
̂ ≈ �Iset − �IL Ki G1
D (5)
Fig. 6  Time-domain response of a current loop under a sinusoidal
From Eqs. (1)–(5), a block diagram of the current loop disturbance input at half the switching frequency: a VC/VD = 0.25; b
can be drawn as shown in Fig. 5. VC/VD = 0.5

13

30 X. Wang et al.

an amplitude amplification at the selective frequency of ½ relationship of each variable under the step response, as shown
the switching frequency [27, 28]. in Fig. 8, a recurrence relationship can be created.
This amplification effect can weaken the disturbance
suppression capability of the system, reduce the equiva- (1) Using the tangent theorem of the triangle, the duty
lent switching frequency by half, or even lead the system to cycle D[n] can be calculated by Iset[n], IL[n], and the
instability. The results in Fig. 7 show that when the output rising slope of the inductor current.
voltage approaches half the input voltage, a low damping (2) The increment of the inductor current ∆IL[n] during this
characteristic is exhibited by the signal in the band around period is determined by the difference between D[n]
the half the switching frequency. In addition, the amplifica- and the steady-state duty cycle DDC[n], which is deter-
tion of the loop amplitude at this frequency increases sharply mined by the volt-second balance.
until it reaches the critical stability condition. In this process, (3) By accumulating the values of IL[n] and ∆IL[n] of the
the current loop gradually evolves into an oscillator at half present cycle, the inductor current value IL[n + 1] of the
the switching-frequency. next cycle can be derived.
Phase lag information of the current loop under different
input and output conditions is also obtained by frequency- A step response diagram of the current loop operating at a
domain analysis. duty cycle of 0.33 is illustrated in Fig. 8. A dynamic structure
The bifurcation and oscillation phenomenon in the PCM diagram of this recurrence relation is shown in Fig. 9. Ki is
current loop structure have been explained in [29]. During the current feedback constant coefficient in the actual circuit
the process of a proportional increase between the output shown in Fig. 1, and ILF[n] is the current feedback signal.
voltage and the input voltage of a full-bridge DC-DC con- From the geometric relationship of Fig. 8, the duty cycle of
verter, the steady state of the current loop enters the bifurca- each sampling time is:
tion state from the volt-second equilibrium state. Then, the
1
oscillation phenomenon occurs. D[n] = (Iset [n] − ILF [n]) (7)
K1 Ki T

The incremental change in the inductor current between two

3 Stability analysis and slope compensation sampling instants can be expressed as:

3.1 The proposed discrete modeling method ΔIL [n] = (D[n] − DDC [n])
VD
T (8)
L
It can be seen from the steady-state operating waveforms of
DDC is the steady-state duty cycle determined by the volt-
the full-bridge DC-DC converter in Fig. 4, that the rising and
second balancing principle, which results in:
falling slopes of the inductor current, the setting current and
the current of the starting points at two adjacent switching
cycles form a geometric constraint relationship.
Let Iset[n], IL[n], and D[n] be the discretization values of ILF(t) Iset
the setting current Iset, the inductor current IL at the start of
the sampling period and the duty cycle D during the switching I
period in the current loop, respectively. Based on the geometric
ILF[n]
D[n]
0 1T 2T 3T 4T 5T 6T t

Fig. 8  Typical small-signal step response of PCM current control

Fig. 7  Amplitude-frequency characteristics of GI(Z) with various out-

put-input voltage ratios Fig. 9  Block diagram for the proposed PCM current control

13
Z‑domain modeling of peak current mode control for full‑bridge DC‑DC buck converters 31

VD − VC V Therefore, the s-domain transfer function of the discrete

K1 = , DDC [n] = C (9) model can be obtained as follows:
L VD

The transfer functions of the overall dynamic structure dia- k

GI (S) = e−sTs ⋅ (14)
gram in Fig. 9 can be obtained according to (7)–(9): s2 + 6fs rs + 12fs2

L V where k = 12fs2/Ki, and r = 1 − 2DDC.

G1 = , G2 = D T (10) An example using the parameters listed in Table 1 is pre-
(VD − VC )Ki ⋅ T L
sented below to show the advantages of the proposed dis-
Therefore, the system shown in Fig. 9 is a simple first-order crete model over the traditional state-space averaging model.
discrete linear time-invariant system. With the current achiev- Bode diagrams of both models are shown in Fig. 10. When
ing volt-second balance, the steady-state duty cycle DDC[n] in compared with the traditional linear model, the proposed
the structure diagram can be removed to sort out the z-domain discrete model is more consistent with the actual perfor-
small-signal model of the PCM current loop so that the trans- mance of a system in the high-frequency band.
fer function of GI(Z) can be obtained as follows: This can be seen more clearly from a spectrum compari-
VD son of three current signals after processing by the Cheby-
G1 G2 (VD −VC )Ki shev window as shown in Fig. 11. Among them, IL(t) is the
GI (Z) = = (11) actual inductor current, while ILt(t) and ILd[t] are obtained by
Z + (G1 G2 Ki − 1) Z + ( VD − 1)
V −V D C the traditional state-space averaging model and the discrete
model, respectively.
The pole position is used to determine the stability and
The spectrum difference between ILd[t] and IL(t) is small
frequency response characteristics of the current loop on the
within a quarter of the switching frequency. The accuracy
z-domain. In practice, it is necessary to further manipulate
of the model is still acceptable when the frequency is close
GI(Z) in Eq. (11) by quantifying the frequency domain charac-
to half the switching frequency since the effect of the duty
teristics in a unit circle of the s-domain to provide a theoretical
cycle on the inductor current can be correctly reflected. For
basis for system stability analysis and oscillation suppression.
practical engineering purposes, it is convenient to carry out
Therefore, by replacing Z in Eq. (11) with esTs, and multiplying
the transfer function of the zero-order sample-hold effect [30],
the continuation of the discrete model GI(Z) can be obtained
as follows:
VD
(VD −VC )Ki 1 − e−sTs
GI (S) = VD
⋅ ⋅ fs (12)
esTs + ( V −V − 1) s
D C

According to the second-order Pade function, esTs can be

approximately equal to:
( )
s2 + 6fs s + 12fs2 1
esTs ≈ , Ts = (13)
s2 − 6fs s + 12fs 2 fs
Fig. 10  Bode diagram of the traditional approximation linear model
and the proposed discrete model

Table 1  DC-DC converter parameters

Parameter Value

Switching frequency (fs) 40 kHz

Transformer turns ratio (N) 4:3
Inductance of L 1 mH
Capacitance of supercapacitor module 20 F
Voltage of DC-bus (UD) 550 V
Voltage of supercapacitor module (VC) 250 V
Current feedback coefficient (Ki) 0.1
Fig. 11  Spectrum comparison of traditional and discrete methods

13

32 X. Wang et al.

the analysis using the traditional approximation. However, changing the system internal parameters cannot eliminate
the large discrepancy between IL(t) and ILt(t) after half of the instability. When the switching device is turned on, the
switching frequency shows the inherent disadvantages in the lack of a rise rate causes the gain of the current loop to be
traditional state space average method. The spectrum of the too large. Therefore, the crux of the problem is to reduce
inductor current is not well matched and cannot reflect the the loop gain of the current loop without changing the
oscillation at ½ the switching frequency. input and output voltage conditions. The solution adopted
in this paper is to superimpose a rising slope signal on
3.2 Slope compensation model mechanism the current feedback signal, as shown in Fig. 13. In this
way, the error at the starting point of the switching cycle
According to the analysis in Sect. 3.1, in order to stabilize results in a lower duty cycle output, which is equivalent to
the current loop of the system, feedback correction is usu- a reduction in the loop gain.
ally considered to reconfigure the unstable pole of GI(z). For The expressions of the compensated current open-loop
example, the average current mode control in [31] can be gain are as follows:
used. Slope compensation that superimposes a rising slope
1 V 1 VD
signal on the current feedback signal is used to stabilize the G1 G2 Ki = ( ) ⋅ D T ⋅ Ki = VD −VC
PCM current loop [32–35]. K1 +Kcp Ki ⋅ T L + Kcp L
L
As shown in Fig. 12, Iset is the setting current, IL is the (16)
inductor current without disturbances added, ILdb is the The condition for system stability is shown below:
inductor current with disturbances added, ∆I 0 and ∆I 1
indicates the current error at the beginning and end of the |G1 G2 Ki − 1| < 1 (17)
| |
period, K1 and K2 are the on-time and off-time slopes of the
inductor current (K1 = (VD − VC)/L, K2 = VC/L), Kcp is the or:
compensation slope, and Ts is the switching period. VD
With the help of slope compensation, the disturbance G1 G2 Ki =
VD − VC + LKcp
<2 (18)
influence on the current can be suppressed or even elimi-
nated, as shown in Fig. 12. However, it is still not suffi- Therefore, the inequality for the critical compensation
cient to explain and solve the problem of subharmonic condition is:
oscillations. ( )
To address this, it is interesting to analyze the effect of VC − 0.5VD DDC − 0.5 VD
Kcp > = (19)
slope compensation. Then, the analytical optimal value of L L
the compensation slope Kcp should be derived by analyzing
the z-domain system model presented in Sect. 3.1. If the compensation slope increases to the critical value,
According to Fig. 9 and Eq. (9), the pole of the current the compensation slope is equal to the absolute value of
loop is: the inductor current falling slope. At this time, Kcp = VC/L
and the pole of the current loop are pushed towards the ori-
1 VD VD gin of the Z-plane. Then, the current loop becomes a time-
1 − G1 G2 Ki = 1 − Ki = 1 − (15) delayed first-order system. For step inputs in the range of
K1 Ki L VD − VC
the small signal, the subharmonic oscillation of the current
This indicates that instability only depends on the oper- loop is well suppressed. However, the adjusting time is as
ating points of the input and output voltage, and that it has
nothing to do with other parameters, which means that

VD Sensor VC
L

D IL

Kcp

GND S GND
Comp
Q
R Iset

Fig. 12  Current waveforms and slope compensation Fig. 13  Slope compensation circuit

13
Z‑domain modeling of peak current mode control for full‑bridge DC‑DC buck converters 33

It is important to note that with an increase of the coef-

ficient X, the damping for the high-frequency signal gradu-
ally increases. In addition, the phase shift also increases.
In other words, increasing the slope compensation Kcp can
improve the stability of the system. However, it also affect
the response speed of the system.
Following the analysis in Sect.  3.1, the s-domain
expression of Gd(Z) can be obtained by Eqs. (20)-(21) as
follows:

⎧ 12fs2
⎪ G (S) = e−sTs ⋅ = e−sTs ⋅ Gk (S)
⎪ d s2 + 6fs rd s + 12fs2
⎨ (22)
Fig. 14  Current loop step responses with Kcp = VC/L  ⎪ r = 1 − 2 ⋅ (V − LK ) = X
⎪ d VD C cp
⎩

According to Eq. (22), the dynamic performance and

the steady-state performance of the system are mainly
determined by Gk(S). Therefore, comparing this with a
standard second-order system yields:
√
⎧ 𝜔 = 2 3f
⎪ n s
⎨ 3fs rd (23)
⎪𝜉 =
⎩ 𝜔n

where ωn is the natural oscillation frequency, and ζ is the

damping of the system.
Fig. 15  Current loop amplitude-frequency characteristic with various Substituting Eq.  (23) into Eq.  (22), the normalized
compensation slopes slope adjustment parameter X can be calculated as:
√
long as one switching period, as shown in Fig. 14, where 𝜉𝜔n 2 3
(24)
X= = ⋅𝜉
Dcp[n] is the duty cycle with slope compensation. 3fs 3
Since the fixed slope rate is not suitable for all of the
operating conditions, the compensation slope is parameter- In engineering applications, while ensuring the stabil-
ized for easy adjustments. ity of the system, the response speed of the system should
( ) be increased as much as possible. Therefore, the damping
DDC − 0.5 + 0.5X VD coefficient ζ for the system is often set to 0.707, which is
Kcp = (20) the optimal damping coefficient.
L
However, the introduction of the coefficient X brings
where X is the normalized slope adjustment parameter with a peak inductor current errors. When X increases, the error
value range of (0, 1]. Accordingly, the range of the slope Kcp increases. As can be seen from Fig. 14, when the slope
is in the range of [(VC − 0.5VD)/L, VC/L]. In these cases, the compensation reaches its maximum value, the actual
z-domain small signal transfer function of the PCM current inductor current cannot approach its reference setting.
loop can be expressed as follows: Therefore, the current setting value needs to be modified
V according to the slope compensation Kcp together with the
D
⋅ 1
G1 G2 (VD −VC )+LKcp Ki steady-state duty cycle D, as shown below:
Gd (Z) = = ( )
Z + (G1 G2 Ki − 1) Z + VD ∗
(VD −VC )+LKcp
− 1 Iset = Iset + KCP ⋅ D ⋅ T (25)
(21)
After modifying the setting value, the actual peak
To observe the effect of slope compensation, the compen- inductor current is equal to Iset
∗
 . In an ideal case, the error
sation coefficient X is increased in steps of 0.25. The current caused by the peak current control can be eliminated.
loop Bode diagram characteristics for different values of X
are shown in Fig. 15.

13

34 X. Wang et al.

Transformer
(the ratio is 4:3)
Diode power board on
power board on
rectifier bridge supercapacitor side
DC-Bus side

from the
AC power source

capacitor

Inductor
slope compensation
circuit Control board connected to the
(DSP28335) super-capacitor module

Fig. 18  Experimental prototype set-up

AC IP: primary current IL: inductor current 250V Super-capacitor

power source 550V DC-Bus
module
L
VD Voltage
R VC
Voltage
Fig. 16  Current loop step responses under different slope compen- sensor
sensor
E

sation coefficients: a X = −  0.38, Kcp = 0; b X = 0, Kcp = 43,750; c Transformer

Current
sensor
X = 0.8164, Kcp = 212,130; d X = 3, Kcp = 662,500 (the ratio is 4:3)
Diode drive signals
rectifier bridge
Controller

Fig. 19  Control structure of the experimental full-bridge DC-DC

Buck converter

suppressed. However, if X is too large, the response speed

of the current loop becomes slow, as shown in Fig. 16.
When X is equal to 0.8164, the steady-state performance
of the current loop is greatly improved. Meanwhile, it
also ensures that the system has fast response. This vali-
Fig. 17  Steady-state current waveforms with different slope compen- dates the theoretical analysis in Sect. 3, where the system
sation coefficients: a X = 0, Kcp = 43,750; b X = 0.8164, Kcp = 212,130 achieves good dynamic and steady-state performances by
adding an appropriate slope compensation.
4 Simulation and experimental results
4.2 Experimental results
4.1 Simulation results
Experiments were carried out to validate the discrete model
A current loop model is built in MATLAB/Simulink to and the slope compensation technique. The experimental
control a full-bridge DC-DC converter working in the set-up is shown in Fig. 18. The structure diagram and ini-
Buck mode. The specified parameters set according to an tial condition settings are shown in Fig. 19. Supercapacitor
actual system are shown in Table 1. The target inductor cur- modular energy storage devices were used as loads at the
rent range of the current loop is 0-20A. In this subsection, low-voltage side with the rated voltage being 360 V. The
the effects of the slope compensation on the dynamic and DC-bus supply was used at the high-voltage side, which was
steady-state performances are analyzed by simulations. made up of an AC power source and a diode rectifier bridge.
In this example, X is chosen as 0.8164 to have the opti- During the experiments, the sampled value of the induc-
mal damping coefficient of 0.707. Then, the slope com- tor current was superimposed with a ramp signal, and
pensation Kcp can be obtained by Eq. (20). The current compared with the setting value, which generates a duty
setting value Iset is modified based on Eq. (25). When the cycle modulation signal. In Fig. 20, CH1 is the ramp signal
current loop is suddenly set at 20A, the current of systems generated by the ramp circuit according to Kcp, CH3 is the
steps up, and the results are shown in Fig. 16 and Fig. 17. inductor current, CH2 represents the inductor current of the
With an increase of the slope compensation coefficient superimposed ramp signal after gain adjustment, and CH4 is
X, the subharmonic oscillation phenomenon is gradually the duty cycle signal. The dotted line in the figure indicates
the simulated setting value of the inductor current.

13
Z‑domain modeling of peak current mode control for full‑bridge DC‑DC buck converters 35

signal, a corresponding peak error was generated, which had

CH1 been compensated by the correction formula (25).
Under the effect of the step response, the system worked
CH3 in the maximum duty cycle, and the inductor current rose
rapidly. However, the subharmonic oscillation phenomenon
CH2 appeared as shown in Fig. 21a. The optimal value of the
slope compensation can be calculated by Eqs. (20), (24),
(25) and the corresponding current waveforms are shown in
Fig. 21b. When compared with Fig. 21a, it can be seen that
CH4
the subharmonic oscillation with the new slope compensa-
tion was well suppressed. Thus, the inductor current and the
primary current were more stable.
Steady-state results are given in Fig. 22 with the same
initial conditions. CH1 and CH2 are the PWM drive signals
Fig. 20  Ramp signal and duty cycle waveforms of the full-bridge switches, CH3 is the primary current, and
CH4 is the inductor current.
The waveforms in Fig. 22 show that the duty cycles of
The system was set according to the initial conditions two adjacent switching cycles have one large and one small
shown in Table 1. When the current loop was suddenly set response when no slope compensation is added. This is con-
to 10A, the current of the system steps up, and the experi- sistent with the analysis in Sect. 3. The presented inductor
mental waveform is shown in Fig. 21. In this figure, CH1 is current and primary current waveforms exhibited subhar-
the inductor current waveform, CH4 is the primary current monic oscillations, and the transformer emitted significant
waveform, and CH2 and CH3 are the PWM drive signals noise. With the addition of appropriate slope compensation,
of the full-bridge module. Due to the addition of the ramp all of the current waveforms remained stable and the subhar-
monic oscillations were eliminated.

CH4

CH3
CH1
CH4
CH2
CH2

CH3
CH1

(a) (a)
CH4

CH3
CH1

CH4
CH2
CH2

CH3 CH1

(b) (b)

Fig. 21  Step response transient waveforms with different slope com- Fig. 22  Steady-state waveforms with different slope compensation
pensation coefficients when: a X = 0, Kcp = 43,750; b X = 0.8164, coefficients in experiments when: a X = 0, Kcp = 43,750; b X = 0.8164,
Kcp = 212,130 Kcp = 212,130

13

36 X. Wang et al.

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Z‑domain modeling of peak current mode control for full‑bridge DC‑DC buck converters 37

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in Automation, and his M.S.
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degree in Control Engineering at
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the South China University of
logue peak current mode control for DC–DC converter. IET Power
Technology, Guangzhou, China,
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in 2013 and 2016, respectively.
His current research interests
include power electronics,
Xiaohong Wang  received his B.S.
motion control technology and
degree in Industrial Automation
its application in servo systems.
from the Harbin University of
Science and Technology, Harbin,
China, in 1999; his M.S. degree
in Power Electronics and Power
Drives from the Harbin Institute
of Technology, Harbin, China, in
2003; and his Ph.D. degree in
Control Theory and Control Quanxue Guan  received his B.S.
Engineering from the South degree in Automation Engineer-
China University of Technology, ing from the South China Uni-
Guangzhou, China, in 2009. versity of Technology, Guang-
From 2009 to 2012, he was a zhou, China, in 2007. He started
Post-Doctoral Researcher at the his combined M.Sc./Ph.D. pro-
Hitachi Elevator (China) Co., gram in Control Theory and
Ltd., Guangzhou, China. Since 2010, he has been an Associate Profes- Control Applications since 2009
sor in the School of Automation, South China University of Technol- and received his Ph.D. degree in
ogy. He has authored or co-authored over 80 papers in international Power Electronics and Motor
journal and conference proceedings. His current research interests Drives from the South China
include power electronic topologies and applications in renewable University of Technology,
energy generation and energy-saving systems, motion control, and Guangzhou, China, in 2016. He
servo and robot systems. has been a Research Fellow in
the Power Electronics and Motor
Control Group, University of
Nottingham, Nottingham, UK since 2017.

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