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Assignment 3

The laboratory assignment involves designing and testing pulse generator circuits with different frequency and duty cycle requirements. In Experiment 1, the student is able to successfully design and test circuits to generate pulses at 15KHz, 10KHz and 5KHz with 70% duty cycle. However, one circuit with a 50% duty cycle at 10KHz does not work as expected. In Experiment 2, a colleague suggests switching the resistances in the charging and discharging paths to allow the duty cycle to be adjusted below 50%. Following this advice, the student is able to generate the remaining required waveforms. Some analysis confirms the new design can change but not reduce the duty cycle below 50%.

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Salman H Yousafzai
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113 views5 pages

Assignment 3

The laboratory assignment involves designing and testing pulse generator circuits with different frequency and duty cycle requirements. In Experiment 1, the student is able to successfully design and test circuits to generate pulses at 15KHz, 10KHz and 5KHz with 70% duty cycle. However, one circuit with a 50% duty cycle at 10KHz does not work as expected. In Experiment 2, a colleague suggests switching the resistances in the charging and discharging paths to allow the duty cycle to be adjusted below 50%. Following this advice, the student is able to generate the remaining required waveforms. Some analysis confirms the new design can change but not reduce the duty cycle below 50%.

Uploaded by

Salman H Yousafzai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Laboratory Assignment 3

Experiment 1: Use the design equation (18) or (19) to compute the component values for the
experiment. Build the circuit in Fig. 9 to meet the following requirements:

A. Design a pulse generator for frequencies = 15 KHz, 10 KHz, and 5 KHz with a 70% duty cycle. Use
C 1 = 9.4 nF.

Figure 1: F=15Khz

Figure 2:10Khz
Figure 3:5Khz

B. For frequency = 10 kHz, generate the waveform for the following duty cycles: 90%, 70%, 50%,
30%, and 10%. Display the output signal. Explain if the output is what you expected.

Figure 4: F=10Khz, Duty cycle=90%


Figure 5: F=10Khz, Duty cycle=70%

Figure 6: F=10Khz, Duty cycle=50%


Figure 7: F=10Khz, Duty cycle=30%

Figure 8: F=10Khz, Duty cycle=10%

Questions:
1. Were you able to design, build, and test all the circuits to meet the requirement of part (A)?
Please explain any discrepancies in your expected and actual results.
Yes successfully made the oscillator circuit as shown in figure 1,2,3

2. Were you able to design, build, and test all the circuits to meet the requirement of part (B)?
Please explain the issues, if any, you encountered while designing the oscillators for the duty
cycles mentioned in the part (B) of the experiment.
Yes successfully made the oscillator circuit as shown in figures (4-8) except figure 6.
Experiment 2: Being unable to design the oscillator to meet all the requirements of the part (B) of
experiment 1, you sought help from a colleague who is heading out to attend a meeting. Your
colleague takes a quick look at you design (equations, circuit diagram etc.) and suggests the resistance
in the charging path is always larger than the resistance in the discharging path, which prevents you
from meeting the some of the duty cycle requirements. He then suggests a quick solution:
Switch the resistances in the charging and discharging paths, which would allow you to make the
resistance in the charging path less than the resistance in the discharge path (see circuit in Fig. 10).
You can then build the oscillator to meet the missing duty cycle requirements. He further suggests to
do the math again to make sure everything adds up. You decide to follow your colleague’s suggestion
but do the theoretical analysis and the design implementation in parallel.

Questions:
1. Were you able to build the oscillator to generate the waveforms with for the remaining duty
cycles? Either way explain as to why the circuit behaved the way it did.
Yes successfully made the oscillator circuit by making a few changes ...
change 1. charging the capacitor C1 With R1 and R2 instead of R2 only
change 2. discharging via R2 only not R2 and R1 like before
If we choose a low voltage at the R terminal of RS FF the output will always be 0V or ground
voltage (whatever be the reference value according to the system

2. Do the new/modified design equations meet the duty cycle requirements? Either way, explain
why or why not
Duty cycle = Tc / ( Tc+Td ) = (R1+R2) / ( R1+ 2R2 )
Duty cycle = Independent of frequency of oscillation
If R1=R2 Then duty cycle = 66.6%
Duty cycle of 555 timer Astable vibrator > 50% (always)
Therefore switching charging and discharging resistances can change the duty cycle but can
not decrease it less than 50%

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