Expt No. 6 Integrator: S.E E&Tc Electronic Circuits
Expt No. 6 Integrator: S.E E&Tc Electronic Circuits
EXPT No. 6
INTEGRATOR
Title:- INTEGRATOR
Aim: To design, build & test integrator using Op-amp for given frequency fa
Objectives:
1. 1. Design Integrator for given f a.
2. Verify practical and theoretical frequencies f a and f b.
3. Observe output waveform at f a and f b for Sine and Square wave input.
4. Plot frequency response for integrator.
Instruments & Components:- Dual Power supply, CRO, Function Generator, bread
board LF356
Theory:
Ideal Integrator circuit :The operational amplifier integrator is an electronic integration
circuit. Based around the operational amplifier (op-amp), it performs the mathematical
operation of integration with respect to time; that is, its output voltage is proportional to
the input voltage integrated over time.
Intuitively, the circuit operates by passing a current that charges or discharges the
capacitor over time. If the op-amp is assumed ideal, nodes v1 and v2 are held equal,and so
The ideal integrator seen above is not a practical circuit design. Non-ideal op-amps have
a finite open-loop gain, an input offset voltage and input bias currents ( in the ideal
importantly, if , both the output offset voltage and the input bias current can
cause current to pass through the capacitor, causing the output voltage to drift over time
until the op-amp saturates. Similarly, if were a signal centered about zero volts (i.e.
without a DC component), no drift would be expected in an ideal circuit, but may occur
in a real circuit.
In DC steady state, the capacitor acts as an open circuit. The DC gain of the ideal circuit
is therefore infinite (or the open-loop gain of a non-ideal op-amp). A large resistor
can be inserted in parallel with the feedback capacitor, as shown in the figure above. This
limits the DC gain of the circuit to a finite value, and hence changes the output drift into a
finite, preferably small, DC error.
whereV iosis the input offset voltage and I Bis the input bias current on the inverting
terminal. R F∨¿ R 1indicatetwo resistance values in parallel.To negate the effect of the
input bias current, set. Ron=R 1∨|Rf |∨R L The error voltage then becomes:
The input bias current causes the same voltage drops at both the positive and negative
terminals.
The frequency responses of the practical and ideal integrator are shown in the above
figure. For both circuits, the crossover frequency , at which the gain is 0 dB, is given
fa
by: The 3 dB cutoff frequency of the practical circuit is given by:
The practical integrator circuit is equivalent to an active first-order low-pass filter. The
gain is relatively constant up to the cutoff frequency decreases by 20 dB per decade
beyond it. The integration operation occurs for frequencies in the range ( f a , f b ), provided
that f a <f b. This condition can be achieved by appropriate choice of R F C Fand R1 C Ftime
constants. The Input signal will be integrated properly if the time period T of the signal is
larger than or equal to R F C F. That is T≥ RF C F .
Circuit Diagram:-
Procedure:-
Result :
2. fb
3. Range of Integration
Conclusion:-