Fundamental Algorithms

for System Modeling,

Analysis, and Optimization

Edward A. Lee, Jaijeet Roychowdhury,

Sanjit A. Seshia
UC Berkeley
EECS 144/244
Fall 2010

Copyright © 2010, E. A. Lee, J. Roychowdhury, S. A.

Seshia, All rights reserved

Lecture 3: Timing Analysis – Part 2

Thanks to S. Devadas and K. Keutzer for several slides

RTL Synthesis Flow

FSM,
HDL
Verilog,
HDL Simulation/ VHDL
Verification
RTL
Synthesis
a

b
0
1
d
q Boolean circuit/network
netlist s clk
Library/
module logic
generators optimization
a

b
0
1
d
q Boolean circuit/network
netlist
s clk

physical Timing Analysis

design Graph / Rectangles

layout

K. Keutzer EECS 144/244, UC Berkeley: 2

 Timing Analysis / Verification
Verifying a property about system timing
Arises in many settings:
 Integrated circuits
 Embedded software
 Distributed embedded systems
 Biological systems
 …
Illustrates many concepts of this course
 Graph algorithms
 Optimization
 SAT solving
 Numerical simulation
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Graph vs. Circuit

Delay of a combinational circuit depends on

 Circuit topology (graph model)
 Delay model
 Boolean behavior

We have only considered circuit topology so far.

Longest/shortest path found on the graph can be very

pessimistic:
 Paths can be FALSE
 Delay values are BOUNDS

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 False Paths
A path is false if it cannot be responsible for the delay of a circuit

Graph model implies path of length 6

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False Paths
A path is false if it cannot be responsible for the delay of a circuit

Graph model implies path of length 6

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False vs. True Paths

TRUE path = one that can be responsible for the delay of

a circuit

Need techniques to find whether a path is TRUE or

FALSE

Incremental k-longest path algorithms are useful here.

WHY?

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The Fixed Delay Model: Constant delay for each

gate (or wire)

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Paradoxical Behavior with the Fixed Delay Model?

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Problems with Fixed Delay Model

Fixed gate delays are unrealistic, due to manufacturing

process variations

More realistic: Lower and upper bounds on delay

Perform timing analysis for a whole family of circuits that

share the same lower/upper bounds

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Fixed Delays  Bounded Delays

Want algorithms that report the critical path delay

of the slowest circuit in the circuit family

Report a delay of 6 for the above circuit

(longest path that can propagate a transition)
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Floating-Mode Delay Model

Input transition  Single input vector condition

Pessimistic, but easier to compute

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Floating-Mode Delay Model
Assume an input pair <v1, v2> has been applied, but we only
look at v2 -- i.e. node values are unknown until set by v2
(pessimistic because we assume any v1 can be adversarially
selected for long paths)

Assume the 1 at the input of the AND arrives before the

0 (even if in reality it arrives later and the gate output
stays at 0 throughout, and no path is sensitized).

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Roadmap for rest of lecture

Consider conditions under which paths are TRUE or

FALSE under the floating-mode delay model
+ key point: under floating-mode model, fixed and bounded
delays yield same circuit delay (for same upper bound)

Reference (posted on bSpace):

S. Devadas, K. Keutzer, S. Malik:
“Computation of Floating Mode Delay in Combinational
Circuits: Theory and Algorithms”
IEEE TCAD, December 1993.

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Controlling and Non-Controlling Values

A controlling value at a gate input is the value that

determines the output value of that gate irrespective of
the other input value.
(the output value is called a controlled value)

A controlling value for an AND gate is 0 and for an OR

gate is 1.
A non-controlling value for an AND gate is 1 and for an
OR gate is 0.
What about NAND and NOR gates?

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Static Sensitization
Definition: A path is statically sensitized by a vector V, if
along each gate on the path, if the gate output is a
controlling value, the input corresponding to the path is the
only input with a controlling value

Input vector 100X statically sensitizes red path

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Static Sensitization

Static sensitization is sufficient for a path to

be responsible for the delay of a circuit

WHY?

Input vector 100X statically sensitizes red path

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Is this path statically sensitizable?

Definition: A path is statically sensitized by a vector V, if along each gate

on the path, if the gate output is a controlling value, the input
corresponding to the path is the only input with a controlling value
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Is this path statically sensitizable?

No, red path is NOT statically sensitizable

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More on Static Sensitization

Are paths a,d,f,g and b,d,f,g statically sensitizable?

Are they true paths?

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Static Sensitization is too strong

A true path (one that is responsible for delay of a circuit)

need not be statically sensitizable

Paths a,d,f,g and b,d,f,g are NOT statically sensitizable.

But they are TRUE paths.
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Static Co-sensitization

Definition: A path is statically co-sensitized by a

vector V, if the input corresponding to the path
presents a controlling value at each gate along
the path whose output is a controlling value.
Not necessarily the ONLY controlling value

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Static Co-sensitization

Definition: A path is statically co-sensitized by a

vector V, if the input corresponding to the path
presents a controlling value at each gate along
the path whose output is a controlling value.
Not necessarily the ONLY controlling value

Paths a,d,f,g and b,d,f,g are statically co-sensitizable

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Static Co-sensitization and Delay

Static co-sensitization is necessary for a path to
be responsible for the delay of a circuit

Is it sufficient?

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Static Co-sensitization and Delay
Static co-sensitization is necessary for a path to
be responsible for the delay of a circuit

But NOT sufficient

Path of length 6 is statically co-sensitized

Delay of circuit is 5

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Summary

Static sensitization (SS) sufficient for true path, but not

necessary

Static co-sensitization (SC) necessary for true path, but

not sufficient

All paths
True
SS paths SC

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 Timing Analysis for Embedded Software

Latency from reading sensor values to writing

actuator commands is determined by
execution time of compute()

while(1) {
read_sensors(); This code is known to be
terminating:
compute();  loops with finite bounds

 no unbounded recursion

write_actuators() Typically:
}  No interrupts/threads

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Example of ComputationalTask
altitude_control_task() from implementation of software controller of
“Paparazzi UAV”
main.c:
…
switch(…) {
while(1) {
case 0: …
…
altitude_control_task(…);
periodic_task(…);
…
…
}
}

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 Path Space in Program

Must find:
Longest path in the control-flow
graph (CFG)

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Are All Program Paths Executable (Feasible) ?

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Longest Path as a Linear Optimization Problem

Linear Program

max c1 x1 + c2 x2 + … + cm xm

subject to
ai1 x1 + ai2 x2 + … + aim xm · bi i=1,2,…,n

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Longest Path as a Linear Optimization Problem

Linear Program

max c1 x1 + c2 x2 + … + cm xm

subject to A x · b
A is a n x m matrix
x is a m x 1 vector (of variables)
b is a n x 1 vector

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Longest Path as a Linear Optimization Problem
Linear Program for Longest path in a DAG
xi = 1 iff ith edge in the DAG is on the path, 0 o.w.

max w1 x1 + w2 x2 + … + wm xm

subject to
E x = (1, 0, 0, …, 0, -1)T ………………… (*)
0 · xj · 1 j = 1,2,…,m
E is the incidence matrix of the graph
The * constraints encode the condition that a single path
is taken from source to sink
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Impact of Variability on Timing Analysis

Delays of gates and wires are a function of

manufacturing process and environment conditions

Process parameters:
 Oxide thickness
 Dopant concentration
 Transistor width
 Interconnect height and width
 …
Environment parameters:
 Temperature
 Supply voltage variation
 …
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Longest Path under Variability is a Non-Linear
Optimization Problem
Linear Program for Longest path in a DAG
xi = 1 iff ith edge in the DAG is on the path, 0 o.w.
pk is the value of the kth process/environmental parameter
(k=1,…,K)

max w1 x1 + w2 x2 + … + w xm
m
where wi = k k + jk pk

subject to
E x = (1, 0, 0, …, 0, -1)T ………………… (*)
0 · xj · 1 j = 1,2,…,m Lk · pk · Uk, k=1,…,K
E is the incidence matrix of the graph
The * constraints encode the condition that a single path is taken
from source to sink

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