CAT24C44

256-Bit Serial Nonvolatile CMOS Static RAM

FEATURES
■ Single 5V Supply ■ JEDEC Standard Pinouts:
■ Infinite EEPROM to RAM Recall –8-lead DIP
–8-lead SOIC
■ CMOS and TTL Compatible I/O
■ 100,000 Program/Erase Cycles (EEPROM)
■ Low CMOS Power Consumption:
–Active: 3mA Max. ■ Auto Recall on Power-up
–Standby: 30µA Max. ■ Commercial, Industrial and Automotive
■ Power Up/Down Protection Temperature Ranges

■ 10 Year Data Retention

DESCRIPTION
The CAT24C44 Serial NVRAM is a 256-bit nonvolatile store protection circuitry prohibits STORE operations
memory organized as 16 words x 16 bits. The high when VCC is less than 3.5V (typical) ensuring EEPROM
speed Static RAM array is bit for bit backed up by a data integrity.
nonvolatile EEPROM array which allows for easy trans-
The CAT24C44 is manufactured using Catalyst’s ad-
fer of data from RAM array to EEPROM (STORE) and
vanced CMOS floating gate technology. It is designed to
from EEPROM to RAM (RECALL). STORE operations
endure 100,000 program/erase cycles (EEPROM) and
are completed in 10ms max. and RECALL operations
has a data retention of 10 years. The device is available
typically within 1.5µs. The CAT24C44 features unlim-
in JEDEC approved 8-lead plastic DIP and SOIC
ited RAM write operations either through external RAM
packages.
writes or internal recalls from EEPROM. Internal false

PIN CONFIGURATION PIN FUNCTIONS

Pin Name Function
DIP Package (L) SOIC Package ( V) SK Serial Clock

CE 1 8 VCC CE 1 8 VCC DI Serial Input

SK 2 7 STORE SK 2 7 STORE DO Serial Data Output
DI 3 6 RECALL DI 3 6 RECALL
DO 4 5 VSS DO 4 5 VSS CE Chip Enable
RECALL Recall
STORE Store
VCC +5V
VSS Ground

© 2008 SCILLC. All rights reserved. Doc. No. MD-1083, Rev. T

Characteristics subject to change without notice 1
CAT24C44

BLOCK DIAGRAM
EEPROM ARRAY

RECALL
ROW STATIC RAM
STORE
DECODE ARRAY STORE
256-BIT CONTROL
LOGIC RECALL
CE
INSTRUCTION COLUMN
DI DO
REGISTER DECODE
SK VCC
VSS

INSTRUCTION 4-BIT
DECODE COUNTER

MODE SELECTION(1)(2)
Software Write Enable Previous Recall
Mode STORE RECALL Instruction Latch Latch
Hardware Recall(3) 1 0 NOP X X
Software Recall 1 1 RCL X X
Hardware Store(3) 0 1 NOP SET TRUE
Software Store 1 1 STO SET TRUE
X = Don’t Care

POWER-UP TIMING(4)
Symbol Parameter Min. Max. Units
VCCSR VCC Slew Rate 0.5 0.005 V/m
tpur Power-Up to Read Operations 200 µs
tpuw Power-Up to Write or Store Operation 5 ms

Note:
(1) The store operation has priority over all the other operations.
(2) The store operation is inhibited when VCC is below ≈ 3.5V.
(3) NOP designates that the device is not currently executing an instruction.
(4) This parameter is tested initially and after a design or process change that affects the parameter.

© 2008 SCILLC. All rights reserved.

Doc. No. MD-1083, Rev. T 2 Characteristics subject to change without notice
 CAT24C44

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
Voltage on Any Pin with of the device at these or any other conditions outside of
Respect to Ground(2) ............. –2.0 to +VCC +2.0V those listed in the operational sections of this specifica-
VCC with Respect to Ground ............... –2.0V to +7.0V tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
Package Power Dissipation mance and reliability.
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA

RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Typ. Max. Units
NEND(1) Endurance 100,000 Cycles/Byte
TDR(1) Data Retention 10 Years
VZAP(1) ESD Susceptibility 2000 Volts
ILTH(1)(4) Latch-up 100 mA

D.C. OPERATING CHARACTERISTICS

VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Unit Conditions
ICCO Current Consumption (Operating) 3 mA Inputs = 5.5V, TA = 0°C
All Outputs Unloaded
ISB Current Consumption (Standby) 30 µA CE = VIL
ILI Input Current 2 µA 0 ≤ VIN ≤ 5.5V
ILO Output Leakage Current 10 µA 0 ≤ VOUT ≤ 5.5V
VIH High Level Input Voltage 2 VCC V
VIL Low Level Input Voltage 0 0.8 V
VOH High Level Output Voltage 2.4 V IOH = –2mA
VOL Low Level Output Voltage 0.4 V IOL = 4.2mA

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Parameter Max. Unit Conditions
CI/O (1) Input/Output Capacitance 10 pF VI/O = 0V
CIN(1) Input Capacitance 6 pF VIN = 0V
Note:
(1) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

© 2008 SCILLC. All rights reserved. Doc. No. MD-1083, Rev. T

Characteristics subject to change without notice 3
CAT24C44

A.C. CHARACTERISTICS
VCC = 5V ±10%, unless otherwise specified.
Symbol Parameter Min. Max. Units Conditions
FSK SK Frequency DC 1 MHz
tSKH SK Positive Pulse Width 400 ns
tSKL SK Negative Pulse Width 400 ns CL = 100pF + 1TTL gate
tDS Data Setup Time 400 ns VOH = 2.2V, VOL = 0.65V
tDH Data Hold Time 80 ns VIH = 2.2V, VIL = 0.65V
tPD SK Data Valid Time 375 ns Input rise and fall times = 10ns
tZ CE Disable Time 1 µs
tCES CE Enable Setup Time 800 ns
tCEH CE Enable Hold Time 400 ns
tCDS CE De-Select Time 800 ns
A.C. CHARACTERISTICS, Store Cycle
VCC = 5V ±10%, unless otherwise specified.
Limits
Symbol Parameter Min. Max. Units Conditions
tST Store Time 10 ms CL = 100pF + 1TTL gate
tSTP Store Pulse Width 200 ns VOH = 2.2V, VOL = 0.65V
tSTZ Store Disable Time 100 ns VIH = 2.2V, VIL = 0.65V

A.C. CHARACTERISTICS, Recall Cycle

VCC = 5V ±10%, unless otherwise specified.
Symbol Parameter Min. Max. Units Conditions
tRCC Recall Cycle Time 2.5 µs
tRCP Recall Pulse Width 500 ns CL = 100pF + 1TTL gate
tRCZ Recall Disable Time 500 ns VOH = 2.2V, VOL = 0.65V
tORC Recall Enable Time 10 ns VIH = 2.2V, VIL = 0.65V
tARC Recall Data Access Time 1.5 µs

INSTRUCTION SET
Format
Instruction Start Bit Address OP Code Operation
WRDS 1 XXXX 000 Reset Write Enable Latch (Disables, Writes and Stores)
STO 1 XXXX 001 Store RAM Data in EEPROM
WRITE 1 AAAA 011 Write Data into RAM Address AAAA
WREN 1 XXXX 100 Set Write Enable Latch (Enables, Writes and Stores)
RCL 1 XXXX 101 Recall EEPROM Data into RAM
READ 1 AAAA 11X Read Data From RAM Address AAAA
X = Don’t care
A = Address bit

© 2008 SCILLC. All rights reserved.

Doc. No. MD-1083, Rev. T 4 Characteristics subject to change without notice
 CAT24C44

DEVICE OPERATION from the device: If the CE pin is prematurely deselected

while shifting in an instruction, that instruction will not be
The CAT24C44 is intended for use with standard micro- executed, and the shift register internal to the CAT24C44
processors. The CAT24C44 is organized as 16 registers will be cleared. If there are more than or less than 16
by 16 bits. Seven 8-bit instructions control the device’s clocks during a memory data transfer, an improper data
operating modes, the RAM reading and writing, and the transfer will result. The SK clock is completely static
EEPROM storing and recalling. It is also possible to allowing the user to stop the clock and restart it to
control the EEPROM store and recall functions in hard- resume shifting of data.
ware with the STORE and RECALL pins. The CAT24C44
operates on a single 5V supply and will generate, on Read
chip, the high voltage required during a RAM to EEPROM Upon receiving a start bit, 4 address bits, and the 3-bit
storing operation. read command (clocked into the DI pin), the DO pin of
the CAT24C44 will come out of the high impedance state
Instructions, addresses and write data are clocked into
and the 16 bits of data, located at the address specified
the DI pin on the rising edge of the clock (SK). The DO
in the instructions, will be clocked out of the device.
pin remains in a high impedance state except when
When clocking data from the device, the first bit clocked
outputting data from the device. The CE (Chip Enable)
out (DO) is timed from the falling edge of the 8th clock,
pin must remain high during the entire data transfer.
all succeeding bits (D1–D15) are timed from the rising
The format for all instructions sent to the CAT24C44 is edge of the clock.
a logical ‘1’ start bit, 4 address bits (data read or write
Write
operations) or 4 “Don’t Care” bits (device mode opera-
tions), and a 3-bit op code (see Instruction Set). For data After receiving a start bit, 4 address bits, and the 3-bit
write operations, the 8-bit instruction is followed by 16 WRITE command, the 16-bit word is clocked into the
bits of data. For data read instructions, DO will come out device for storage into the RAM memory location speci-
of the high impedance state and enable 16 bits of data fied. The CE pin must remain high during the entire write
to be clocked from the device. The 8th bit of the read operation.
instruction is a “Don’t Care” bit. This is to eliminate any
bus contention that would occur in applications where
the DI and DO pins are tied together to form a common
DI/DO line. A word of caution while clocking data to and

Figure 1. RAM Read Cycle Timing

CE

1 2 3 4 5 6 7 8 9 10 11 12 22 23 24
SK

(1)
(8)
DI 1 A A A AX 1 1

HIGH-Z
DO D0 D1 D2 D3 D14 D15 D0

Figure 2. RAM Write Cycle Timing

CE

1 2 3 4 5 6 7 8 9 10 11 12 22 23 24
SK

DI 1 A A A A1 0 1 D0 D1 D2 D3 D13 D14 D15

Note:
(1) Bit 8 of READ instruction is “Don’t Care”.

© 2008 SCILLC. All rights reserved. Doc. No. MD-1083, Rev. T

Characteristics subject to change without notice 5
CAT24C44

WREN/WRDS The WRDS (write/store disable) can be used to disable

The CAT24C44 powers up in the program disable state all CAT24C44 programming functions, and will prevent
(the “write enable latch” is reset). Any programming after any accidental writing to the RAM, or storing to the
power-up or after a WRDS (RAM write/EEPROM store EEPROM.
disable) instruction must first be preceded by the WREN Data can be read normally from the CAT24C44 regard-
(RAM write/EEPROM store enable) instruction. Once less of the “write enable latch” status.
writing/storing is enabled, it will remain enabled until
power to the device is removed, the WRDS instruction is
sent, or an EEPROM store has been executed (STO).

Figure 3. Read Cycle Timing

SK CYCLE # 6 7 8 9 10 11

SK

VIH
CE
tPD

DI

tPD tZ
HIGH-Z HIGH-Z
DO D0 D1 Dn

Figure 4. Write Cycle Timing

1/FSK
tSKH tSKL

SK x 1 2 n

tCES tCEH tCDS

CE

tDS tDH

DI

© 2008 SCILLC. All rights reserved.

Doc. No. MD-1083, Rev. T 6 Characteristics subject to change without notice
 CAT24C44

RECALL
RCL/RECALL
inadvertent store operations, the following conditions
Data is transferred from the EEPROM data memory to must each be met before data can be transferred into
RAM by either sending the RCL instruction or by pulling nonvolatile storage:
the RECALL input pin low. A recall operation must be
performed before the EEPROM store, or RAM write • The “previous recall” latch must be set (either a
operations can be executed. Either a hardware or soft- software or hardware recall operation).
ware recall operation will set the “previous recall” latch
• The “write enable” latch must be set (WREN
internal to the CAT24C44.
instruction issued).
POWER-ON RECALL • STO instruction issued or STORE input low.
The CAT24C44 has a power-on recall function that During the store operation, all other CAT24C44 func-
transfers the EEPROM data to the RAM. After Power- tions are inhibited. Upon completion of the store opera-
up, all functions are inhibited for at least 200ns (Tpur) tion, the “write enable” latch is reset. The device also
from stable Vcc. provides false store protection whenever VCC falls below
a 3.5V level. If VCC falls below this level, the store
STORE
STO/STORE operation is disabled and the “write enable” latch is
Data in the RAM memory area is stored in the EEPROM reset.
memory either by sending the STO instruction or by
pulling the STORE input pin low. As security against any

Figure 5. Recall Cycle Timing

tRCC
tRCP

RECALL

tRCZ tARC
HIGH-Z
DO VALID DATA

tORC UNDEFINED DATA

Figure 6. Hardware Store Cycle Timing

tST
tSTP

STORE

tSTZ
HIGH-Z
DO

© 2008 SCILLC. All rights reserved. Doc. No. MD-1083, Rev. T

Characteristics subject to change without notice 7
CAT24C44

Figure 7. Non-Data Operations

CE

1 2 3 4 5 6 7 8
SK

DI 1 X X X X

OP-CODE

ORDERING INFORMATION

Prefix Device # Suffix

CAT 24C44 V I – G T3

Company ID Product Number Temperature Range T: Tape & Reel

24C44 I = Industrial (-40°C to +85°C) 3: 3,000/Reel
E = Extended (-40°C to +125°C)(4)

Package Lead Finish

L: PDIP G: NiPdAu
V: SOIC, JEDEC Blank: Matte-Tin

Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The device used in the above example is a CAT24C44VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel).
(3) For additional package option please contact your nearest ON Semiconductor Sales office.
(4) Extended Temperature available upon request.

© 2008 SCILLC. All rights reserved.

Doc. No. MD-1083, Rev. T 8 Characteristics subject to change without notice
 CAT24C44

REVISION HISTORY
Date Revision Description
17-Apr-04 O Add Lead Free Logo
Update Features
Update Pin Configuration
Update Block Diagram
Update Instruction Set
Update Device Operation
Update Ordering Information
Add Revision History
Update Rev Number
16-Nov-04 P Update Pin Configuration
Update Ordering Information
17-Apr-04 Q Update Ordering Information
03-Aug-05 R Update Pin Configuration
Update Reliability Characteristics
Update Ordering Information
24-Jun-08 S Update Pin Configuration
Update Example of Ordering Information
04-Dec-08 T Change logo and fine print to ON Semiconductor

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any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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© 2008 SCILLC. All rights reserved. Doc. No. MD-1083, Rev. T

Characteristics subject to change without notice 9