UNIT-III

Review of Basic MEMS fabrication modules:

Review of Basic MEMS fabrication modules:

SYLLABUS:MEMS fabrication modules, Oxidation, Deposition Techniques,

Lithography (LIGA), and Etching

A.MEMS fabrication modules

(module=each of a set of standardized parts or independent units that can be used to construct a
more complex structure, such as an item of furniture or a building.)

1. Typically, a MEMS device is first designed with a Computer Aided Design (CAD) tool. There
are many tools currently available from companies such as MEMSCAP Inc. which allow the user
to design a MEMS device, optimize it, simulate it, verify its functionality, and generate its layout.
2. Existing CAD tools compute the equilibrium solutions in a lengthy iterative process. Ideally,
the MEMS CAD tool would be capable of rapid solving, mechanical, thermal, electrostatic,
magnetic, fluidic, RF, and optical solutions in a coupled fashion.
3.This layout is then sent to a foundry, where the chip is fabricated, a mask-less post-processing
release step is performed where sacrificial layers are etched away, allowing the structural layers to
move and rotate. Following the release, the devices are assembled and tested. Unfortunately, the
cost of a microfabrication facility capable of producing MEMS is prohibitively expensive for
most companies and universities. In order to maximize the utility of the foundries, some
microfabrication facilities make their processes publicly available for modest fees. The most
prominent MEMS foundries include MUMPS process by Cronos , the SUMMiT process by
Sandia National Laboratories, the iMEMS process by Analog Devices , and the IC foundry broker
MOSIS.
4. There are two main fabrication classes for manufacturing MEMS devices, namely surface
micromachining and bulk micromachining .
1.Some other micromachining processes are:
2.deep reactive ion etching (DRIE),
3.substrate bonding, LIGA ,
4.plastic molding with PDMS ,
5.micromolding (HEXSIL), etc.
5.The permutations of materials and processes for depositing and etching make it impossible to
discuss them in sufficient detail. For a thorough understanding of deposition and etching
processes, the reader is directed to the book by Madou.
6. Surface micromachining is an additive fabrication technique which involves the building of the
device on top the surface of the supporting substrate. This technique is relatively independent of
the substrate utilized, and therefore can be easily mixed with other fabrication techniques which
modify the substrate first.
7. An example is the fabrication of MEMS on a substrate with embedded control circuitry, in
which MEMS technology is integrated with IC technology. Surface micromachining has been
used to produce a wide variety of MEMS devices for many different applications; some of the
commercially available MEMS devices were fabricated in large volumes of over 2 million parts
per month.
8. On the other hand, bulk micromachining is a subtractive fabrication technique which converts
the substrate, typically a single-crystal silicon, into the mechanical parts of the MEMS device. 9.
Packaging of the device tends to be more difficult, but structures with increased heights are easier
to fabricate when compared to surface micromachining. This is because of the substrates can be
thicker resulting in relatively thick unsupported devices.
10.Exploiting the predictable anisotropic etching characteristic of single crystal silicon, many
high precision complex three-dimensional shapes, such as Vgrooves, channels, pyramidal pits,
membranes, vias, and nozzles can be achieved.
11. Most MEMS devices and systems involve some form of lithography-based microfabrication,
borrowed from the microelectronics industry and enhanced with specialized techniques generally
called “micromachining.” The batch fabrication that is characteristic of the microelectronics
industry offers the potential for great cost reduction when manufacturing in high volume.
12. Fabrication processes include lithography, film growth, diffusion, ion implantation, thin film
deposition, etching, metallization, et cetera.
13. Micromachining is the set of design and fabrication tools that precisely machine and form
structures and elements at a scale well below the limits of our human perceptive faculties—the
micro scale.
MEMS Fabrication Modules
3.1 Photolithography
3.2 Materials for Micromachining
3.2.1 Substrates
3.2.2 Additive Films and Materials
3.3 Bulk Micromachining
3.3.1 Wet Etching
3.3.2 Dry Etching
3.4 Surface Micromachining
3.4.1 Fusion Bonding
3.5 High-Aspect-Ratio-Micromachining
3.5.1 LIGA
3.5.2 Laser Micromachining
3.6 Computer Aided Design
3.7 Assembly and System Integration
3.8 Packaging
3.8.1 Multi-Chip Modules
3.8.2 Passivation and Encapsulation
3.9 Foundry Services

B. Oxidation

It is a chemical process by which the atoms of an element lose electrons. In an aqueous solution,
neutral atoms become positive ions.
High-quality amorphous silicon dioxide is obtained by oxidizing silicon in either dry oxygen or in
steam at elevated temperatures (850º–1,150ºC). Oxidation mechanisms have been extensively
studied and are well understood. Charts showing final oxide thickness as function of temperature,
oxidizing environment, and time are widely available.
Thermal oxidation of silicon generates compressive stress in the silicon dioxide film. There are
two reasons for the stress: Silicon dioxide molecules take more volume than silicon atoms, and
there is a mismatch between the coefficients of thermal expansion of silicon and silicon dioxide.
The compressive stress depends on the total thickness of the silicon dioxide layer and can reach
hundreds of MPa. As a result, thermally grown oxide films cause bowing of the underlying
substrate.
Moreover, freestanding membranes and suspended cantilevers made of thermally grown silicon
oxide tend to warp or curl due to stress variation through the thickness of the film.
Oxide Film Formation by Thermal Oxidation

The silicon-silicon dioxide interface transverses the silicon during the oxidation process. Using
the densities and molecular weights of silicon and SiO2, it can be shown that growing an oxide of
thickness x consumes a layer of silicon that is 0.44x thick. The basic structural unit of thermal
SiO2 is a silicon atom surrounded tetrahedrally by four oxygen atoms, The silicon-oxygen and
oxygen-oxygen interatomic distances are 1.6 and 2.27 A, respectively. SiO2 or silica has either a
crystalline structure (e.g. quartz in Figure 2.2(b)) or an amorphous structure (Figure 2.2(c)).
Typically, amorphous SiO2 has a density of ~2.2 gm/cm3, whereas quartz has a density of ~2.7
gm/cm3. Thermally grown oxides are usually amorphous in nature. Oxidation of silicon in a high-
pressure atmosphere of steam (or oxygen) can produce substantial acceleration in the growth rate
and is often used to grow thick oxide layers.
One advantage of high-pressure oxide growth is that oxides can be grown at significantly lower
temperatures and at acceptable growth rates.
C.Lithography (LIGA)

LIGA  is a German acronym

for Lithographie, Galvanoformung, Abformung(Lithography, Electroplating, and Molding) that
describes a fabrication technology used to create high-aspect-ratio microstructures.

The LIGA consists of three main processing steps;

1.Lithography,

2.Electroplating and

3.Molding.

There are two main LIGA-fabrication technologies, X-Ray LIGA, which uses X-rays produced

by a synchrotron to create high-aspect ratio structures, and UV LIGA, a more accessible method
which uses ultraviolet light to create structures with relatively low aspect ratios.

The notable characteristics of X-ray LIGA-fabricated structures include:

 high aspect ratios on the order of 100:1

 parallel side walls with a flank angle on the order of 89.95°
 smooth side walls with  = 10 nm, suitable for optical mirrors
 structural heights from tens of micrometers to several millimeters
 structural details on the order of micrometers over distances of centimeters

Lithography (or patterning) refers to the series of steps that establish the shapes,
dimensions, and location of the various components of the integrated circuit (IC). The current
progress in IC design, with the decreased dimensions (miniaturization) of the chip and
increased density of transistors, is possible only if smaller areas on the wafer surface can be
patterned. This is primarily the function of lithography. Thus, the success of modern IC
design is due largely to lithography. This can be summarized in the process goals
1.Create a pattern with the dimensions established by the circuit design.
2.Place the pattern correctly with respect to the crystal orientation and other existing
patterns.
After the pattern is created, either the defined part of the wafer surface is removed (trench
creation) or left behind (island creation) or new material is deposited. Lithography is also
used to expose certain parts of the wafer surface for doping (either with a hard mark for
thermal diffusion or with a soft mask for ion implantation).
The correct placement of the circuit pattern involves alignment or registration of various
masks. An IC wafer fabrication process can require forty or more patterning steps.
Alignment of these individual steps is critical to form a working IC.

Process overview

For lithography processing, a hard copy of the pattern has to be first generated. This is
called a reticle or mask. The design on the mask has to be transferred to the wafer, as shown
in figure 1. The transfer can be 1:1 (i.e. with no reduction in size) but usually the size is
reduced so that the pattern is transferred to a smaller region on the wafer. This is done by
using suitable lens to demagnify the pattern.

Lithography can be broadly divided into two stages, each of which consists of several
steps.

1.First, the pattern is transferred to a photoresist layer on the wafer. Photoresist is a light
sensitive material whose properties change on exposure to light of specified wavelength.
This process is called developing . The pattern formed in this step is temporary and can be
removed easily. This is especially important if the pattern is not properly alignment with the
wafer or with any existing patterns on the wafer, improper registry.

2.The transfer of the pattern takes place from the photoresist to the wafer. Exposed wafer
surfaces can be etched (removal of material) or layers deposited on it. Dopant materials can
also be added to sections of the wafer through the pattern. This stage is final and it is very
hard to remove the formed patterns without causing damage to the underlying wafer.

The overall lithography process is summarized in figure 2. After the pattern is formed on
the photoresist and the wafer surface is exposed (developing process) the exposed wafer
surface is etched. It is also possible to deposit material on the exposed surface.
Figure 1: Typical IC fabrication process showing the different features on the die with
increasing magnification from (a) - (c). A mask can be made of many chips, each chip will
also have a variety of device features. These patterns will be transferred to the wafer during
lithography. Adapted from Fundamentals of semiconductor manufacturing and process
control - May and Spanos.
Figure 2: Overview of the lithography process. In this example, lithography
is used to remove material (etching) from the wafer surface by selectively
exposing part of it. Adapted from Microchip fabrication - Peter van Zan
Photoresists

The use of photoresists in the wafer fabrication industry was started in the 1950s. The
technology was adapted from the photo industry. There are both general purpose resists and
resists for specific applications. They are usually tuned to a specific wavelength. The
components of a photoresist are as follows.

1. Polymer - this is a light sensitive polymer whose structure changes on exposure

to light. The desired property is usually change in solubility in a specific solvent.

2. Solvent - The solvent is used to thin the resist so that is can be applied on the
wafer by a spin on process. The solvent is usually removed by heating to around
100 ◦C, called soft bake process.

3. Sensitizers - these are used to control the chemical reaction during exposure.

4. Additives - various chemicals that are added to achieve specific process results, like
dyes.

Photoresists usually react to UV or visible light and hence these are called optical resists.
There are also specific resists for other type of radiations like x-ray and e-beam.
Overall, photoresists are divided into two main types.

1. Positive resists - on exposure to UV light these become more soluble.

2. Negative resists - on exposure to UV light these resists becomes less soluble.

The difference in working of the two resist types are summarized in figure 3. Positive resists
directly transfer the pattern from the mask onto the wafer. This is because the mask protects
the portion of the resist below it from exposure to UV radiation. The rest of the resist, that is
exposed, becomes more soluble and can be easily removed. Negative resists, on the other
hand, transfer the negative of the mask pattern to the wafer. This is similar to the negative
process in film photography. For negative resists, the portion that is protected by the mask
pattern is more soluble, since it is not exposed to UV radiation, while the radiation hardens
the rest of the resist.
SU-8 is an example of a commonly used epoxy-based negative photoresist. The structure of
the molecule is shown in figure 4. It is a viscous polymer based resist. When exposed to UV
light of wavelength 365 nm, the polymer
Figure 3: (a) - (e) Steps in exposure of a wafer using positive and negative photoresists with
the same mask. The positive resist directly transfers the mask pattern on the wafer while the
negative resist transfers a negative of the pattern on the wafer. Adapted from Fundamentals
of semiconductor manufacturing and process control - May and Spanos.

Figure 4: Structure of the SU-8 photoresist. It is a negative photoresist and has maximum
absorption for UV light of wavelength 365 nm. On exposure, the long chains crosslink,
causing polymerization and making the photoresist less soluble. Source
http://en.wikipedia.org/wiki/SU-8 photoresist.

chains cross-link making the resist insoluble. The cured cross-linked chains are stable in
vacuum, which is important when using the resist for vapor deposition. Typical photo resist
thickness on the wafer is around few hundred nm to tens of µm depending on the size of the
mask pattern. There are a large number of resists and developer groups that are used not
only in the IC industry but also for MEMS (micro electro mechanical systems) applications.

Mask making

The mask contains the hard copy of the pattern that has to be transferred to the different
wafers during lithography. For a given integrated circuit, there are multiple masks, which
have to be aligned for proper device fabrication. Masks have alignment markers included
with the pattern, which can be used for this purpose. Figure 5 shows three masks used for a
MEMS device called nanocalorimeter. The device required three masks, which have to be
aligned. This is done by using alignment markers, seen in the center of figure 5 (a) and (b).
The alignment markers are usually much smaller than the typical dimensions of the pattern.
The mask material is made of borosilicate glass or quartz with a sputter deposited chrome
layer on top. The chrome layer is 100 nm thick. There is also a photoresist layer deposited on
top of the chrome. A laser writer is used to ‘write’ the pattern on the mask. Different laser
wavelengths (365, 248 or 193 nm) and lenses are used to write the pattern on the mask. The
choice of the wavelength depends on the smallest dimension on the pattern. The

Figure 5: Masks for a nanocalorimeter. (a) Front (b) back (c) top and (d) combined. There
are alignment markers in (a) and (b) seen in the center.The colors are inverted to show
contrast and the wafer boundary is shown only in (a). Alignment markers are usually much
smaller than the pattern dimen- sions and are seen in the center of (a) and (b).
laser writing process is sequential (line by line) and can take hours depending on the
complexity of the pattern. The mask pattern shown in figure 5 took approximately 7 hours
to write, using a 365 nm laser wavelength. After the pattern is written, a suitable developer
is used to remove the unexposed photoresist. After that, the exposed chrome layer is
removed (using an acid bath etch) and then the remaining photoresist is removed to leave
behind the chrome desired pattern on glass. There are also cleaning and drying steps to
remove any excess solvent and keep the mask free of dust particles. The major steps in mask
making are summarized in figure 6. The integration of the mask making steps, in the overall
process flow for forming an IC, is shown in the flowchart in figure 7.

Photoresist application

Before the lithography step, the wafer surface should be clean and defect free. Presence of
defects, before and after lithography, can affect the pattern transfer process and produce a
non-working device. The various ways in which dust particles can interfere with the
lithographic mask are shown in figure 8. The dust particles are removed prior to lithography,
by washing with de-ionized water, spin drying (rotating the wafer at few thousand rpm), hot
nitrogen blow-off and a dehydration bake to remove any excess water. The wafers are then
inspected for defects and the process repeated, if needed. The photoresist layer is then
applied of the wafer. The resist should be uniformly spread on the surface since any
thickness variations can cause problems during developing and subsequent resist removal.
Typical resist thick- ness is around 0.5-1.5 µm. Resist application is done by a process
called spin coating, summarized in figure 9.
The photoresist is initially dispensed onto the wafer at rest, called static spin coating. Usually the
wafer is held on a vacuum chuck to prevent motion. The chuck is then slowly rotated to spread the
photoresist on the surface. This layer is not uniform. After that, the rotation speed is increased to a
few thousand rpm and the wafer is spun for few tens of seconds, so that excess resist is removed,
and there is a uniform film over the entire surface. The right amount of resist should be added, so
that coverage is uniform but not excessive, as shown in figure 10. The final resist thickness
depends on the amount of resist, spin speed, viscosity, surface tension, and drying char- acteristics
(solvent dependent). The relation between resist thickness and spin speed is shown in figure 11.
There are other variations to the photoresist dispersion. The wafer is rotated at slow speed, while
resist is dispersed, called dynamic disperse. The dispersion arm is moved on the wafer surface
Figure 6: Process flow for the mask making process. The resist exposure can be through
optical system or scanning e-beam system. The mask making process is similar to the
lithography process except for the scanning optical (laser) or e-beam system. Adapted from
Microchip fabrication - Peter van Zant.
Figure 7: Mask process integrated in the IC fabrication. Usually the first step in fabrication
is making the mask. This process is carried out external to the fab and the masks are
shipped for use. The number and type of masks depend on the circuit design. Adapted from
Microchip fabrication - Peter van Zant.

Figure 8: Dust particles can interfere with the lithography process and cause errors in the
pattern transfer. Some of the dust particles can act as killer defects i.e. degrade the IC
performace. Adapted from Fundamentals of semiconductor manufacturing and process
control - May and Spanos.
Figure 9: Steps in spin coating to get a uniform layer of resist. (a) A layer of resist is first
applied on the wafer (b) The wafer is rotated at low rpm to spread the resist (c) The wafer is
spun at high rpm so that an uniform coating is obtained and excess resist removed. Adapted
from Microchip fabrication
- Peter van Zant.
Figure 10: Resist coverage before and after ’spinning’ for (a) insufficient
resist (b) Correct amount of resist and (c) excess resist. Resist dispensing is
usually an automated process. Adapted from Microchip fabrication - Peter van
Zant.

Figure 11: Resist thickness vs. spin speed for different volumes of resist
dispersed on the wafers. The resist thickness is increases with the volume of
material dispensed. Also, as spin speed increases the thickness decreases.
Adapted from Microchip fabrication - Peter van Zant.
Figure 12: (a) Dynamic disperse (b) Moving arm disperse. Both are used to
achieve uniform coverage, especially for large wafers used in commercial IC
fabrication. Adapted from Microchip fabrication - Peter van Zant.

while dispersion, called moving arm disperse. All these different techniques are used to
achieve uniform coverage, especially for large wafers. The above mentioned techniques are
summarized in figure 12.
The photoresist application process is automated in commercial IC man- ufacturing. In most
research based facilities, for small (3”-4”) wafers, the dispersal is usually manual. After
spinning, the wafer is subjected to a soft bake process. This heats the wafer to 100-120 ◦C to
remove the solvent from the resist. After spin on process, the wafer surface should be
protected from ambient light (typically UV light) to prevent unintentional exposure of the
resist. This is done by keeping the photoresist application under special light- ing
conditions. The alignment and exposure system is usually kept close to the spin on process
equipment to minimize exposure.
Figure 13: Alignment marks for the mask shown in figure 5 (a). The marker
is located at the center of the mask region.

Alignment and exposure

The alignment and exposure process transfers the pattern from the mask to the photoresist
on the wafers. Alignment markers are used to align the mask with the wafer and also to
align one more masks with each other. Figure 13 shows alignment markers for the mask
shown in figure 5 (a). The pattern is transferred from the mask to the photoresist using
steppers. The transfer can be 1:1 i.e. direct transfer of the pattern onto the wafer. There are
also reduction steppers, where the reticles can be 5-10 times larger than the final dimensions
on the wafer. In such cases, the reticle is projected onto one area of the wafer and then
stepped to the next area. The advantage is that smaller dimensions can be achieved by using
a larger mask.
The stepper can be of a contact type, where the mask actually touches the wafer or a
proximity type, where there is a gap. These types are shown in figure 14. Contact aligners
can cause damage to the mask (since they have to repeatedly used on different wafers) and
have contamination issues. So proximity aligners are preferable, though there is a slight loss
of resolution due to scattering of light in the gap. Some sort of soft contact contact aligners
are also available. There are different modes of projection, as shown in figure 15.
E-beam lithography

Figure 14: Types of stepper (a) contact (b) proximity. Contact steppes can
achieve high registry but there is a chance of the mask getting contaminated.
Non-contact steppers cannot achieve the high resolution of contact steppers
but the wafer and mask are both protected from contamination. Adapted
from Fundamentals of semiconductor manufacturing and process control - May
and Spanos.

Figure 15: Types of projection systems (a) Scan (b) 1:1 step and repeat (c)
reduction step and repeat. The choice of projection system depends on the
dimensions of the mask and the desired dimensions of the pattern on the
wafer. Adapted from Microchip fabrication - Peter van Zant.
Figure 16: Electron beam lithography setup. The system works similar to a
scanning electron microscope. Electron beam produced by a source is
rastered on a surface by using deflection coils, to produce a specific pattern.
The wafer already has the resist layer coated. Adapted from Fundamentals of
semiconductor manufacturing and process control - May and Spanos.

In conventional lithography, a laser writer is used to create a hard copy of the pattern i.e.
mask, which is then transferred to the wafers. The size limitation comes from the smallest
features that can be written and this depends on the wavelength of light used (few hundred
nm). One way to circumvent this limitation is to use an electron beam, since this has a much
smaller wavelength (few nm depending on energy) and hence can theoretically achieve a
much higher resolution. In e-beam lithography, the electron beam is used to scan and write
the design directly on the wafer. This is called direct writing. The setup is shown in figure
16. It is similar to a scanning electron microscopy setup, with an electron source and lens
and deflector coils to scan the beam on the surface. Resolution better than conventional
optical lithography can be achieved, but the disadvantage is that each wafer has to be
written individually and the process is time-consuming. Also, e- beam lithography is a
scanning system while conventional lithography is a one shot exposure system.

Developing

After the alignment and exposure process, the wafers have to be developed . The
terminology is similar to that used in film photography. The wafers are reacted with a
suitable chemical (developer) that reacts with the exposed photoresist. The type of
developer chosen depends on the resist. For a positive photoresist, the exposed areas are
removed (more soluble) while for a negative resist, the unexposed areas are removed (less
soluble). SU-8 is a negative photoresist, whose structure shown in figure 4. After exposure,
the main developer used to remove the unexposed resist is 1-methoxy-2-propanol acetate.
Developing is usually a wet chemical process. The wafers are immersed in the developing
solution for a fixed time, until the resist is completely removed. They are then cleaned and
dried. After that, the wafers are baked to 200- 250 ◦C, called hard bake, to harden the
remaining resist. At this stage, the pattern that needs to be transferred to the wafer is still
only temporary. It is possible to remove the resist easily, usually by dry etching. The
developed wafers are then further processed to get the final pattern on the wafer. These
could include steps like
5.Doping - ion implantation only. For thermal diffusion, oxide layers are used as
masks.
6.Deposition - usually a physical vapor deposition process like sputtering or e-beam
evaporation. Chemical vapor deposition can react with the wafers.
7.Etching - plasma or reactive ion etching. Wet etching can damage the remaining
resists.
The resist protects the portion of the wafer that lies below it. After the final pattern is
obtained on the wafer, the remaining resist is removed, this is called resist stripping. This
can be a wet process, by using an acid mixture or a dry process, plasma etching with oxygen.
The wafers are then cleaned and dried and are ready for the next process. If there are
multiple lithography steps, the wafers then go back to the photoresist application process.

Lithography advances

The smallest feature size that can be patterned is related to the wavelength of the light used.
This relation is given by
λ
σ=k (1)
NA
Figure 17: Numerical aperture of a lens. The semi-angle of the aperture and the refractive
index of the medium determine the numerical aperture. Source
http://en.wikipedia.org/wiki/Numerical aperture

where σ is the feature size, k is Rayleigh constant (value of 0.5), λ is the wavelength and N
A is the numerical aperture of the lens system. For a mercury source of λ 436 nm, with N A
= 1, the resolution obtained is 218 nm (0.218 µm). This is the smallest feature size that can
be patterned but this much bigger than the current device technology (22 nm technology).
One way to reduce σ, is to reduce the wavelength. With 135 nm light, called extreme UV
lithography, the resolution is 68 nm (N A = 1). It is possible to reduce wavelength even
further by using x-rays, X-ray lithography. Wavelengths of a few nm are possible, but a
whole new mask system is required. This is because x-rays have high penetrating power so
that glass- chrome masks are not effective. Gold masks are usually required. Also, x-ray
lenses are not well developed, so new aligner systems need to be designed, which will
increase overall cost.
Looking at equation 1, another way to decrease feature size, is to increase
N A. The numerical aperture is given by

N A = µ sin α (2)

where µ is the refractive index of the medium between the lens and the wafer and α is the
semi-angle of the exit lens, as shown in figure 17. To increase N A, the value of µ, i.e.
refractive index, can be increased. This is called immersion lithography. If water is used
as the medium, then µ is 1.44 so that the new σ reduces by 0.70 to 47 nm. The setup is
shown in figure
18. But immersion lithography comes with its own wafer cleanliness issues. There are few
other techniques for further reducing the resolution from 47 nm to 22 nm.
Double patterning is one such technique for overcoming the limits of con- ventional
lithography. The process is summarized in figure 19. Here, pattern-
Figure 18: Immersion lithography system using purified water as
the medium to increase NA and increase the resolution. Source
http://www.nikon.com/about/technology/rd/core/optics/immersion e/index.htm

Figure 19: Steps in double patterning. Side-wall spaces and an etching step is
used to create patterns that are half of what can be achieved by the lithog-
raphy setup. Source http://en.wikipedia.org/wiki/Multiple patterning
 MM5017: Electronic materials, devices, and fabrication

ing is carried out in two steps. The first pattern is formed by conventional lithography. This
is used to define side-wall spacers, by a process of deposi- tion and dry etching. These
spacers are then used as hard masks to etch the layer below it. Since there are two side
walls, the spacing between them is half of what could be originally achieved using
lithography, see figure 19. For achieving even smaller dimensions, (14 nm and beyond)
double patterning can be extended to multiple patterning. There are other techniques as
well to try and beat the limits of lithography. But all of these add extra steps to the
fabrication process and increases cost and reduces yield. Thus, lithography advances are
most critical for continued IC miniaturization.

D.Etching and Deposition Techniques

1.Etching

Etching refers to the removal of material from the wafer surface. The process is usually
combined with lithography in order to select specific areas on the wafer from which
material is to be removed. Etching represents one way of permanently transferring the mask
pattern from the photoresist to the wafer surface. The complementary process to etching is
deposition (or growth), where new material is added. Unlike oxidation (or nitridation),
where the underlying Si is consumed to form the oxide (nitride) layer, in deposition, new
material is added without consuming the underlying wafer.

There are two main types of etching

1.Wet etching
2.Dry etching
 MM5017: Electronic materials, devices, and fabrication

Figure 1: Schematic of the wet etching process. A controlled portion of the

wafer surface is exposed to the etchant which then removes materials by
chemical reaction. Adapted from Fundamentals of semiconductor manufac-
turing and process control - May and Spanos.

Wet etching
In wet etching, the wafers are immersed in a tank of the etchant (mix of chemicals), as
shown in figure 1. There is a chemical reaction between the wafer surface and the etchants
that helps in material removal. Either a photoresist layer or a hard mask like oxide or nitride
layer is used to protect the rest of the wafer. The time for etching depends on the amount
and type of material that needs to be removed. KOH (potassium hydroxide) is a common
etchant used to remove Si. Usually, 30% KOH solution is used, which has a etch rate of 100
µm/hr at 90 ◦C. Thus, an entire 4” wafer, with thickness of 500 µm, can be etched through in
approximately 5 hours. The etch rate of Si (100) by 30 % KOH is shown in figure 2. After
∼ in DI water, for removal of etchant and then finally
etching, the wafers are rinsed, usually
dried.
Wet etching is used for removal of material from large areas (trench sizes
> 3 µm). For smaller areas, where greater precision in removal of material is required, dry
etch is preferred. The wet etching process is anisotropic i.e. the etch rate depends on the
plane of the Si wafer, from which atoms are being
Figure 2: Etch rate of Si in KOH as a function of temperature. There is a non-
linear increase in etch rate with increasing temperature. Typically, etching is
carried out at 90 ◦C. Source http://www.cleanroom.byu.edu/KOH.phtml

removed. The etch rate for Si (110), in the same 30 % KOH, is shown in figure 3. Compared to
Si(100) plane, figure 2, the rate is higher. This means that wet etching of Si(100) will produce a
trapezoidal profile, with a specific angle of 54.74 deg, as shown in figure 4. Etching uniformity
is important to get a uniform thickness over the entire wafer surface. This is usually determined
by process conditions like etchant temperature, concentration, and agitation (using stirrers).

Etching challenges
There are some process challenges related to etching. These are common to both wet and
dry etching, though they are more pronounced and harder to control in wet etching due to
the higher rate of material removal, compared to dry etching.

Incomplete etch
In incomplete etch, the time is not sufficient for complete material removal. This is usually
due to concentration or temperature not being sufficient. The concentration profile left
behind is usually a rough surface, due to local variations in material removal, as depicted in
figure 5.
Figure 3: Etch rate of Si(110) in KOH as a function of temperature. Com-
pared to the etch rate for Si (100), see figure 2, the etch rate is higher. Source
http://www.cleanroom.byu.edu/KOH.phtml

Figure 4: Anisotropic etching of Si by KOH. Because of the difference in the

etch rates of Si along the different crystallographic layers the final pro- file is
trapezoidal, with the angle determined by the etch rates. Source
http://www.cleanroom.byu.edu/KOH.phtml
Figure 5: Surface profile for incomplete etch of oxide layer on Si. A resist
layer protects the remaining oxide. A rough oxide layer is left behind due to
the local variations in rate of removal of the oxide layer. Adapted from
Microchip fabrication - Peter van Zant.

Figure 6: (a) A complete anisotropic etching produces vertical side walls. (b)
Most often etching is partially isotropic, so that side walls are formed at an
angle. Adapted from Microchip fabrication - Peter van Zant.

Over etch and undercutting

The opposite of incomplete etching is over etching. An ideal etchant is selective and
completely anisotropic. This is essential to get vertical sidewalls when a trench is created.
But, this is not always possible, so that sloped side walls are obtained, see figure 6. When
the etch time is larger than the required etch time, due to isotropic etching, material under
the photoresist can get removed. This is called over etching and in extreme cases it can also
lead to liftoff of the resist layer, see figure 7. This is harmful, since it exposes areas of the
wafer that the resist protects to the etching process.

Etch selectivity
Etching process should be selective to the material that has to be removed. This helps to
protect the material under the mask (within limits of isotropic etching) and also the mask
material itself (oxide, nitride, or resists). Consider
Figure 7: (a) Normal (b) Over etching and (c) Resist liftoff due to excess over
etching. The etching rate and time are crucial to prevent over etching since
resist removal can cause damage to portions of the wafer that have to be
protected from the etchant. Adapted from Microchip fabrication - Peter van
Zant.

Si etching, using KOH. The etch rate for Si(100) at 90 ◦C using 30 % KOH is 100 µm/hr,
∼ 2. If silicon nitride is used as mask, its etch rate, under the same conditions, is 1
see figure
∼
nm/hr, nearly 105 times slower than Si. Thus, silicon nitride is commonly used as a mask for
Si etching (especially for making Si cantilever based devices). On the other hand, silicon
∼ see figure 8. So, using silicon oxide
dioxide etch rate, under the same conditions, is 1 µm/hr,
as a mask will not be good enough or a very thick oxide layer is required.
Different etchants that are used for different layers and the corresponding etch rates, shown
in table1. For Si etching, KOH is used or a mixture of nitric acid and hydrofluoric acid (HF).
For silicon oxide etching, usually a mixture of HF and ammonium fluoride (NH4F) is used,
that produces∼a etch rate of 0.1 µm/hr at room temperature. This mixture does not etch Si, so
it provides very good selectivity. This etchant is called BOE (buffered oxide etchants). For
silicon nitride, usually a strong acid like hot phosphoric acid is used at high temperatures
(180 ◦C) since it is a very good passivating layer and hard to remove under normal
conditions.

Dry etching

Dry etching, as the name suggest, is removal of material in the absence of solvent. The
process was introduced because wet etching has some limitations in its applicability, which are
listed below.

1.Wet etching is used for large pattern sizes, usually larger than 2 µm.
2.It is an isotropic process - sloped sidewalls rather than straight walls.
Figure 8: Etch rate of SiO2 by KOH. Because of comparable etch rates to pure
Si, it cannot be used as a etch mask for Si etching. Silicon nitride is used as
the mask since its etch rate, under the same conditions, is of the order of
nm/hr. Source http://www.cleanroom.byu.edu/KOH.phtml

Table 1: Etching chemicals used for different layers and their etch rates,
under commonly used conditions. Adapted from Microchip fabrication - Peter
van Zant.
Material Common Etch Etch rate
etchant temperature (˚A/min)
SiO2 HF Room 700
NH4F (1:8) temperature
SiO2 Acetic acid Room 1000
NH4F (2:1) temperature
Aluminum HPO4 40-50 ◦C 2000
HNO (nitroxyl)
Acetic acid
water
Si3N4 H3PO4 150-180 ◦C 80
Poly Si HNO3 Room 1000
H2O HF temperature
Figure 9: (a) Starting surface after development of the resist (b) Surface after
wet etching (c) Surface after dry etching. Because of the anisotropic nature of
etching, dry etching produces more vertical side walls compared to wet
etching, but the removal rate is slower. Adapted from Fundamentals of
semiconductor manufacturing and process control - May and Spanos.

3.Wet etch has to be combined with subsequent rinse and dry steps. This increases
chances of defects or contamination.

4.Hazardous chemicals and conditions are used, so safety is an issue. Safe disposal
of chemicals is essential.

5.Undercutting and resist peel off can happen if time is not controlled or etch
conditions change during process.

The wet and dry etching process are compared in figure 9. Dry etching is a process that
overcomes some of these issues. Here, etchant gases are the primary medium for the
removal of material. The basic steps involved are summarized in figure 10. There are three
main types of dry etching

1.Plasma etch 2.Ion beam

milling 3.Reactive ion etch
Plasma etch

In plasma etch, the chemical etchant is introduced in the gas phase. For etching silicon
oxide, CF4 (tetrafluoromethane) is used. The chamber is first evacuated before introducing
the gas. Radio frequency (RF) electrodes are then used to generate the plasma that ionizes
the gas. This ionized gas attacks the oxide layer, removing the layer. Etch rates in plasma
etch are
1 10∼µm/hr,
− much smaller than wet etching. So, it more suitable for thin layers, but it also
provides greater thickness control. There are different configurations for plasma etching,
one such planar configuration is shown in
Figure 10: Various steps from (1) - (5) in the dry etch process. Gases are
transported to the wafer surface, where they adsorb and react with the wafer
surface material, at the step edges. The gases then desorb from the surface.
Adapted from Fundamentals of semiconductor manufacturing and process control -
May and Spanos.

Figure 11: Planar plasma etch configuration. The wafers are held on a
grounded chuck, close to the RF electrodes. Reactive gas introduced in the
chamber, is ionized and the ions helps in material removal. Adapted from
Microchip fabrication - Peter van Zant.
Table 2: Typical plasma etching chemicals for different film materials and
the corresponding gaseous products. Adapted from Microchip fabrication -
Peter van Zant.
Film Etchant Typical gas compounds
Al Chlorine BCl3, CCl4, Cl2, SiCl4
Mo Fluorine CF4, SF4, SF8
Polymers Oxygen DF4, SF4, SF8
Si Chlorine BCl3, CCl4, Cl2, SiCl4
Fluorine CF4, SF4, SF6
SiO2 Fluorine CF4, CHF3, C2F6, C3F8
Ta Fluorine CF4, CHF3, C2F6, C3F8
Ti Fluorine CF4, CHF3, C2F6, C3F8
W Fluorine CF4, CHF3, C2F6, C3F8

figure 11. The resist layer used to protect the wafer is also etched along with
the oxide. But the resist thickness is much larger than the oxide (few µm of
resist compared to tens of nm of oxide). This means that substantial amount
of resist is still available, after the etching process. Some of the different
etchant gases used for plasma etching of various films are shown in table 2.

Ion beam etch

Ion beam etching is similar to the ion beam milling process that is used for transmission
electron microscopy sample preparation. This is a physical process where ionized inert gas
ions (usually Ar) are used to remove material from the wafer. The process is not selective
but it is highly directional. The ion beam etching process is shown in figure 12.

Reactive ion etching

Reactive ion etching combines the plasma and ion beam etching process to achieve both
selectivity and directionality. There is an increase in selectivity compared to plasma etch,
for SiO2 and Si the selectivity ratio is 35:1 while for pure plasma etch the ratio is 10:1. This
reduces the thickness requirement on the mask. Dry etch process is also used for resist
stripping after patterning is complete. This is usually done by plasma etching using oxygen.
Figure 12: Schematic of the ion beam etching process. Ar gas is intro- duced
into the vacuum chamber where they are ionized by bombarding with
electrons. These ions are then directed on to the wafer where they remove
material by physical bombardment. Adapted from Microchip fabrication -
Peter van Zant.
Deposition

The deposition process is the opposite of etching. Here, material is added to the wafer
surface. The layers different from grown layers like oxide and nitride where the underlying
Si is consumed during a high temperature furnace processes. In deposition, the Si from the
wafer is not consumed and the wafer can be maintained at room temperature or at elevated
temperatures. Some of the layers, where deposited films are used, are

1. Epitaxial layers - usually poly Si is grown for use as a gate.

2. Dielectric layers - intermetallics (high k capacitors)

3. Trench capacitors
4. Intermetal conducting plugs
5. Metal layers – conductors
6. Passivation layers
There are two main growth techniques
1.Physical deposition
2. Chemical deposition

There are some important film parameters, which need to be controlled and these decide the
type of growth technique that is adopted.

1. Thickness and uniformity

2.Roughness

3.Composition control 4.Stress

5.Purity

6.Film integrity

In most cases, the underlying substrate is not flat. The choice of technique becomes
especially important when depositing in deep trenches/holes, with a high aspect ratio
(depth/width) that needs to be maintained. In such cases, physical deposition techniques will
not work since they will cover the hole before filling it. Physical techniques will be
discussed later in the context of metallization.
Figure 13: Various deposited layers in a typical integrated circuit. The
different components are listed below. The surface oxide layer is grown by
oxidation of the silicon, but the remaining layers are grown by either physical
or chemical deposition. Adapted from Microchip fabrication - Peter van Zant.

Chemical vapor deposition (CVD)

There are a large number of variations to this process, but the basic prin- ciple is that
chemicals containing the desired film/layer are introduced into a reactor (where the wafer is
held at high temperature) in the form of a vapor. These chemicals react on the wafer surface
to form the film on the wafer. Some common types of reactors for CVD process are shown
in figure
13. Some examples of the chemical reactions involved in various chemical deposition
processes are listed below.

Pyrolysis : SiH4 → Si + 2H2 Reduction : SiCl4 + 2H2 → Si + 4HCl Oxidation :

SiH4 + O2 → SiO2 + 2H2
(1)
Nitridation : 3SiH2Cl2 + 4N H3 → Si3N4 + 6HCl + 6H2

CVD process can be in atmospheric conditions or under low pressure (LPCVD). LPCVD is
usually used for growing silicon nitride, to reduce the comprehen- sive stress on the film.
For growing atomically thin films, a layer by layer growth process, called atomic layer
deposition (ALD), is used. In CVD, the reacting gases are introduced into the vacuum
chamber at the same time, but in ALD, the
Figure 14: Different types of CVD reactors (a) horizontal (b) pancake and
(c) barrel type. The basic process in all these reactors is the same, chemicals
introduced into the reactor form the final film on the wafer surface, which is
held at elevated temperature. The different configurations helps in control of
composition uniformity and thickness. Adapted from Fundamentals of
semiconductor manufacturing and process control - May and Spanos.
Figure 15: Schematic of the MBE growth chamber for GaAs. There are Ga and As
sources, that are used to produce molecular beams that are deposited on the
substrate and react to form the final film. Al and Si are used as dopants. The
advantage of MBE is that the dopant concentration can be precisely controlled
during deposition. Adapted from Microchip fabrication
- Peter van Zant.

gases are introduced one at a time. The first gas is introduced and it forms an atomically thin
adsorbed layer on the wafer. The gas is then pumped out and the second gas is introduced, which
reacts with the first adsorbed atomic layer and form the final film. The second gas is then pumped out
and the process repeated to grow new the new film one atomic layer at a time. The growth rate in
ALD is very slow compared to CVD, but it can produce films grown layer by layer with precise
control over thickness and composition.

Molecular beam epitaxy (MBE)

MBE is used mainly for rate control, low deposition temperature, and con- trolled film stoichiometry
(including dopant concentration). The MBE cham- ber is shown in figure 15. The chamber is under
ultra high vacuum (10−10 T orr) to prevent contamination. The constituents of the film that needs to

be formed, e.g. for GaAs it would be Ga and As, are taken in their elemental or pure form in effusion
cells. These are then evaporated and deposited on the substrate, where the Ga and As atoms react to
form the final GaAs. Thus, molecular beams are used to form the film. If the film needs to be doped,
the appropriate dopant atoms are also converted into a molecular beam and deposited along with the
Ga and As, in the required concentra- tion. By choosing the right substrate and growth conditions,
epitaxial growth is also possible i.e. the lattice spacing of the film can match the substrate.

Deposited Si
Si can also be deposited on the wafer, this can either be epitaxial Si or polycrystalline Si. Poly Si is
used as gate material in MOSFET provided it is heavily doped. Si is usually deposited by a CVD
process, where the dopant is added along with the reactant gases. It is usually produced by a
reduction process, as shown in 1, and listed below.

SiCl4 + 2H2 → Si + 4HCl

SiH4 → Si + 2H2
SiH2Cl2 → Si + 2HCl(2)
Depending on the wafer conditions, it is possible to get a wide variety of Si films.