Microarchitecture

Sam Amiri
Introduction
Application
programs
 Microarchitecture Software

 How to implement an architecture in hardware Operating

device drivers
Systems
 Processor instructions
Architecture
 Datapath: functional blocks registers

 Control: control signals Micro-

architecture
datapaths
controllers

adders
Logic
memories

Digital AND gates

Circuits NOT gates

Analog amplifiers
Circuits filters

transistors
Devices
diodes

Physics electrons
2
Microarchitecture

 Multiple implementations for a single architecture:

 Single-cycle: Each instruction executes in a single cycle
 Pipelined: Each instruction is broken up into series of steps & multiple
instructions execute at once

3
MIPS Processor

 Consider subset of MIPS instructions:

 R-type instructions: and, or, add, sub, slt
 Memory instructions: lw, sw
 Branch instructions: beq

4
MIPS Instruction Formats

5
Architectural State

 Determines everything about a processor:

 PC
 32 registers
 Memory

6
MIPS State Elements

CLK CLK CLK

PC' PC WE3 WE
32 32 5
A1 RD1 32
32
A RD 32
5
A2 RD2 32 A RD
Instruction 32 32
Memory Data
5
A3 Memory
Register
WD3 WD
32 File 32

7
Single-Cycle MIPS Processor

 Datapath
 Control

8
Single-Cycle Datapath: lw Fetch

 STEP 1: Fetch instruction

CLK CLK
CLK
PC Instr WE3 WE
PC' A1 RD1
A RD
A RD
Instruction
A2 RD2 Data
Memory
A3 Memory
Register
WD3 WD
File

9
Single-Cycle Datapath: lw Register

 STEP 2: Read source operands from RF

CLK CLK
CLK
25:21
WE3 WE
PC' PC Instr A1 RD1
A RD
A RD
Instruction
A2 RD2 Data
Memory
A3 Memory
Register
WD3 WD
File

10
Single-Cycle Datapath: lw Immediate

 STEP 3: Sign-extend the immediate

CLK CLK
CLK
25:21
WE3 WE
PC' PC Instr A1 RD1
A RD
A RD
Instruction
A2 RD2 Data
Memory
A3 Memory
Register
WD3 WD
File

15:0 SignImm
Sign Extend

11
Single-Cycle Datapath: lw Address

 STEP 4: Compute the memory address

ALUControl2:0
010
CLK CLK
CLK
25:21
WE3 SrcA Zero WE
PC' PC Instr A1 RD1
A RD

ALU
ALUResult
A RD
Instruction
A2 RD2 SrcB Data
Memory
A3 Memory
Register
WD3 WD
File

SignImm
15:0
Sign Extend

12
Single-Cycle Datapath: lw Memory

 STEP 5: Read data from memory and write it back to register file
RegWrite ALUControl2:0
1 010
CLK CLK
CLK
25:21
WE3 SrcA Zero WE
PC' PC Instr A1 RD1
A RD

ALU
ALUResult ReadData
A RD
Instruction
A2 RD2 SrcB Data
Memory 20:16
A3 Memory
Register
WD3 WD
File

SignImm
15:0
Sign Extend

13
Single-Cycle Datapath: lw PC Increment

 STEP 6: Determine address of next instruction

RegWrite ALUControl2:0
1 010
CLK CLK
CLK
25:21
WE3 SrcA Zero WE
PC' PC Instr A1 RD1
A RD

ALU
ALUResult ReadData
A RD
Instruction
A2 RD2 SrcB Data
Memory 20:16
A3 Memory
Register
WD3 WD
File

PCPlus4
+

SignImm
4 15:0
Sign Extend

Result

14
Single-Cycle Datapath: sw

 Write data in rt to memory

RegWrite ALUControl2:0 MemWrite
0 010 1
CLK CLK
CLK
25:21
WE3 SrcA Zero WE
PC' PC Instr A1 RD1
A RD

ALU
ALUResult ReadData
20:16 A RD
Instruction
A2 RD2 SrcB Data
Memory 20:16
A3 Memory
Register WriteData
WD3 WD
File

PCPlus4
+

SignImm
4 15:0
Sign Extend

Result

15
Single-Cycle Datapath: R-Type

 Read from rs and rt

 Write ALUResult to register file—Write to rd (instead of rt)
RegWrite RegDst ALUSrc ALUControl2:0 MemWrite MemtoReg
1 1 0 varies 0
CLK CLK 0
CLK
25:21
WE3 SrcA Zero WE
PC' PC Instr A1 RD1 0
A RD

ALU
ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
Sign Extend

Result
16
Single-Cycle Datapath: beq

 Determine whether values in rs and rt are equal

 Calculate “Branch Target Address” = (sign-extended immediate << 2) +
(PC+4) PCSrc

RegWrite RegDst ALUSrc ALUControl2:0 Branch MemWrite MemtoReg

0 x 0 110 1 x
CLK CLK 0
CLK
WE3 SrcA Zero WE
0 PC' PC Instr
25:21
A1 RD1
A RD 0

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
<<2
Sign Extend PCBranch

+
Result 17
Single-Cycle Processor
MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK
25:21 WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0
A RD

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
<<2
Sign Extend PCBranch

+
Result
18
Single-Cycle Control
Control
Unit MemtoReg
MemWrite
Branch
Opcode5:0 Main
ALUSrc
Decoder
RegDst
RegWrite

ALUOp1:0

ALU
Funct5:0 ALUControl2:0
Decoder

19
Review: ALU

F2:0 Function
000 A&B
A B
001 A|B
N N
010 A+B
011 not used
ALU 3F
100 A & ~B
N
101 A | ~B
Y
110 A-B
111 SLT 20
Review: ALU A B
N N

F2:0 Function
N 000 A&B

0
N
F2 001 A|B
010 A+B
Cout
011 not used
+
[N-1] S
100 A & ~B
Extend
Zero

101 A | ~B
N N N N
110 A-B
1

0
3

2 F1:0
N 111 SLT 21
Y
 Control Unit: ALU Decoder
ALUOp1:0 Meaning ALUOp1:0 Funct ALUControl2:0
00 Add 00 X 010 (Add)
01 Subtract X1 X 110 (Subtract)
10 Look at Funct 1X 100000 (add) 010 (Add)
11 Not Used 1X 100010 (sub) 110 (Subtract)
Control
Unit MemtoReg 1X 100100 (and) 000 (And)
MemWrite

Opcode5:0
Branch 1X 100101 (or) 001 (Or)
Main
ALUSrc
Decoder
RegDst 1X 101010 (slt) 111 (SLT)
RegWrite

ALUOp1:0

ALU
Funct5:0 ALUControl2:0
Decoder
22
Control Unit: Main Decoder
Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0
R-type 000000
lw 100011
sw 101011
beq 000100
MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK
25:21 WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0
A RD

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
<<2
Sign Extend PCBranch

+
Result
23
Control Unit: Main Decoder
Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0
R-type 000000 1 1 0 0 0 0 10
lw 100011 1 0 1 0 0 1 00
sw 101011 0 X 1 0 1 X 00
beq 000100 0 X 0 1 0 X 01
MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK
25:21 WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0
A RD

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
<<2
Sign Extend PCBranch

+
Result
24
Single-Cycle Datapath: or
MemtoReg
Control
MemWrite
Unit
Branch 0
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK 1 0
0 001 0
25:21
WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0
A RD

ALU
1 ALUResult ReadData
0 A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
1
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0 <<2
Sign Extend PCBranch

+
Result
25
Extended Functionality: addi
MemtoReg
No change Control
MemWrite
Unit
to datapath Branch
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK
25:21 WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0
A RD

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
<<2
Sign Extend PCBranch

+
26 Result
Control Unit: addi

Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0

R-type 000000 1 1 0 0 0 0 10
lw 100011 1 0 1 0 0 1 00
sw 101011 0 X 1 0 1 X 00
beq 000100 0 X 0 1 0 X 01
addi 001000

27
Control Unit: addi

Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0

R-type 000000 1 1 0 0 0 0 10
lw 100011 1 0 1 0 0 1 00
sw 101011 0 X 1 0 1 X 00
beq 000100 0 X 0 1 0 X 01
addi 001000 1 0 1 0 0 0 00

28
Extended Functionality: j
Jump MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK
0 PC' 25:21
WE3 SrcA Zero WE
0 PC Instr A1 RD1 0 Result
1 A RD

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
PCJump 15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
<<2
Sign Extend PCBranch

+
27:0 31:28

25:0
<<2

29
Control Unit: Main Decoder

Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0 Jump
R-type 000000 1 1 0 0 0 0 10 0
lw 100011 1 0 1 0 0 1 00 0
sw 101011 0 X 1 0 1 X 00 0
beq 000100 0 X 0 1 0 X 01 0
j 000010

30
Control Unit: Main Decoder

Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0 Jump
R-type 000000 1 1 0 0 0 0 10 0
lw 100011 1 0 1 0 0 1 00 0
sw 101011 0 X 1 0 1 X 00 0
beq 000100 0 X 0 1 0 X 01 0
j 000010 0 X X X 0 X XX 1

31
Review: Single-Cycle Processor
Jump MemtoReg
Control
MemWrite
Unit
Branch
ALUControl2:0 PCSrc
31:26
Op ALUSrc
5:0
Funct RegDst
RegWrite

CLK CLK
CLK
0 25:21
WE3 SrcA Zero WE
0 PC' PC Instr A1 RD1 0 Result
1 A RD

ALU
1 ALUResult ReadData
A RD 1
Instruction 20:16
A2 RD2 0 SrcB Data
Memory
A3 1 Memory
Register WriteData
WD3 WD
File
20:16
0
PCJump 15:11
1
WriteReg4:0
PCPlus4
+

SignImm
4 15:0
<<2
Sign Extend PCBranch

+
27:0 31:28

25:0
<<2

32
Thank You!

33