KON 509E: Design of Discrete

Control Systems

Design of Discrete Controllers

Assist. Prof. Dr. İlker Üstoğlu

6.1 Discrete Controller structures
• The most commonly ones are P, PI, PID, 2DOF PID
• different integration/derivation methods

• Besides, we can also design lead-lag Controllers

𝐾 𝑧+𝑏
𝐷 𝑧 =
𝑧+𝑎
or High-order Controllers

𝐾 𝑧 + 𝑏1 𝑧 + 𝑏2 𝑧 + 𝑏3 … 𝑧 + 𝑏𝑛
𝐷 𝑧 =
𝑧 + 𝑎1 𝑧 + 𝑎2 𝑧 + 𝑎3 … 𝑧 + 𝑎𝑚

Slide 2
Design𝐺 of𝑠 Discrete Controllers 𝐶 𝑠

𝐶 𝑧
𝐺 𝑧 𝐶 𝑧

Slide 3
6.2 Emulation Controller Design
• Design a 𝐶 s via 𝑮 𝒔 and then discretize it
1 𝑇𝑧+1 2𝑧−1
𝐶 𝑧 = 𝐾𝑐 1 + + 𝑇𝐷
𝑇𝐼 2 𝑧 − 1 𝑇𝑧+1
• Tustin Transformation- Trapezoidal Integration

Slide 4
6.2 Emulation Controller Design
• Design a 𝐶 s via 𝑮 𝒔 and then discretize it
1 𝑇𝑧+1 2𝑧−1
𝐶 𝑧 = 𝐾𝑐 1 + + 𝑇𝐷
𝑇𝐼 2 𝑧 − 1 𝑇𝑧+1
• Tustin Transformation- Trapezoidal Integration
• Especially the Tustin transformation is often used in practice.
• However, even this approach has its limitations and the emulated
discrete-time closed-loop system performance is only comparable
to the continuous-time performance if the sampling intervals are
sufficiently small.
• As long as the cross-over frequency 𝜔𝒄 and 𝑇 satisfy the inequality
𝜋
𝑇 <
5 𝜔𝒄
the emulated controller is likely to produce a satisfactory closed-
loop system behaviour.
Slide 5
6.2 Emulation Controller Design
• Using the three approximation methods, let us examine how the
discrete-time equivalent of the lead compensator.
10𝑠 + 1
𝐶 𝑠 =
𝑠 +1
for sampling periods T = 1, 0.5 and 0.1.
• For Forward difference
𝑧−1
10( ) + 1 10 𝑧 − 1 + 𝑇
𝐶 𝑧 = 𝑇 =
𝑧−1 𝑧 −1+𝑇
+1
𝑇
• For Backward difference
𝑧−1
10( ) + 1 10 𝑧 − 1 + 𝑧𝑇
𝐶 𝑧 = 𝑧𝑇 =
𝑧−1 𝑧 − 1 + 𝑧𝑇
+1
𝑧𝑇

Slide 6
6.2 Emulation Controller Design: Effect of the integration
• For Forward difference
𝑧−1
10( ) + 1 10 𝑧 − 1 + 𝑇
𝐶 𝑧 = 𝑇 =
𝑧−1 𝑧 −1+𝑇
+1
𝑇
• For Backward difference
𝑧−1
10( ) + 1 10 𝑧 − 1 + 𝑧𝑇
𝐶 𝑧 = 𝑧𝑇 =
𝑧−1 𝑧 − 1 + 𝑧𝑇
+1
𝑧𝑇
• For Tustin difference
2𝑧−1
10( ) + 1 20 𝑧 − 1 + 𝑇(𝑧 + 1)
𝐶 𝑧 = 𝑇 𝑧 + 1 =
2𝑧−1 2(𝑍 − 1) + 𝑇(𝑧 + 1)
+1
𝑇𝑧+1

Slide 7
6.2 Emulation Controller Design: Effect of the integration
• Bode Plots is a nice way to examine how the controller effects the
open loop magnitude and phase of the control system.
• How to draw them?
• You know it in continuous time,
• Asymptotic bode plots, Phase & Gain margin etc…
• You can transform the discrete controller back to continuous time
and draw them
• For discrete-time systems, to facilitate interpretation, the upper
half of the unit circle is used
𝑠𝑇 𝑗𝑤𝑇
𝜋
𝑧 = 𝑒 = 𝑒 , 0 ≤ 𝑤 ≤ 𝑤𝑠 =
𝑇
• The equivalent continuous-time frequency 𝑤 is used
• Note that, since we have a periodic function (remember primary
and secondary strip!), the Bode plot is periodic with period 2𝑤𝒔 and
thus the frequency response is only valid up to 𝑤𝑠
Slide 8
6.2 Emulation Controller Design: Effect of the integration
Frequency Response for 𝑇 = 1

Slide 9
6.2 Emulation Controller Design: Effect of the integration
Frequency Response for 𝑇 = 0.5

Assoc. Prof. Dr. T. Kumbasar Slide 10

6.2 Emulation Controller Design: Effect of the integration
Frequency Response for 𝑇 = 0.1

Assoc. Prof. Dr. T. Kumbasar Slide 11

6.2 Emulation Controller Design: Methods
• Design a 𝐶 s via 𝑮 𝒔 and then discretize it
1 𝑇𝑧+1 2𝑧−1
𝐶 𝑧 = 𝐾𝑐 1 + + 𝑇𝐷
𝑇𝐼 2 𝑧 − 1 𝑇𝑧+1
• Tustin Transformation- Trapezoidal Integration/difference
• In continuous time design, 𝐾𝑐 , 𝑇𝐼 , and 𝑇𝐷 could have been designed
by the means of methods such as
• Ziegler–Nichols, Cohen-Coon and Internal Model Control based
tuning methods…
• Root-Loci, Bode plots…
• To use such methods in discrete-time, we MUST take into account
• Sampling Time selection (as usual) but small as possible
• Dynamics of the "ZOH“

Assoc. Prof. Dr. T. Kumbasar Slide 12

6.2 Emulation Controller Design: Methods
• To use such methods in discrete-time, we MUST take into account
• Sampling Time selection (as usual) but small as possible
• Dynamics of the "ZOH"
𝑇𝑠 2
1 −𝑒 −𝑠𝑇 1 − 1 + 𝑇𝑠 − +⋯ 𝑇𝑠 𝑇
𝐺𝑍𝑂𝐻 𝑠 = ≈ 2 ≈ 1− ≈𝑒 −2𝑠
𝑠 𝑇𝑠 2

• Thus, the presence of "ZOH" can be considered as an additional

time delay equal to the half of the sampling time (T)!

Slide 13
6.2 Emulation Controller Design: Methods
Problem: Design a discrete PID, with a sampling time 𝑇 =?, for
1
𝐺 𝑠 = 4 𝑒 −0.25𝑠
𝑠+1
by employing the Ziegler–Nichols tuning methods

We need a FOPDT model

Slide 14
6.2 Emulation Controller Design: Methods
• We need a FOPDT model
1
𝐺1 𝑠 = 𝑒 −0.3𝑠
3s + 1
• Thus, the system parameters are:
• 𝐿 = 0.3, 𝜏 = 3, 𝐾 = 1
• Actual Time delay 𝐿∗ = 0.3 + 𝑇/2

• The Ziegler–Nichols tuning methods

𝜏
𝐾𝑐 =
𝐾𝐿
𝑇𝑖 = 2𝐿∗
𝑇𝑑 = 0.5𝐿∗

Slide 15
6.2 Emulation Controller Design: Matlab pidtuner
Eryilmaz B, Chen R, Gahinet P, inventors; MathWorksInc, assignee.
Automated pid controller design. United States patent application US
12/604,924. 2010 Dec 9.

The pidtune function

• is very robust
• any type of discrete or continuous time model.
• Stable, unstable, integrating and time delay

Slide 16
6.2 Emulation Controller Design: Matlab pidtuner
• The aim is stabilize the
loop while balancing two
measures of performance
• set-point tracking
(transient and steady
state) & disturbance
rejection
• The whole idea is to make
it easy to design a
controller with respect to
known measures of
stability and performance
• Phase Margin (PM) and
Crossover Frequency 𝑤𝑐

Slide 17
6.2 Emulation Controller Design: Matlab pidtuner
• The controller structure is in continuous time as follows :
(sin𝜙𝑧 )𝑠 + 𝜔𝑐 cos𝜙𝑧 sin𝛽 𝑠 + 𝜔𝑐 cos𝛽
𝐾 𝑠 = 𝜔𝑐
𝜔𝑐 𝑠 (sin𝛼)𝑠 + 𝜔𝑐 cos𝛼
while in discrete time as
𝜔𝑐 𝑇 (sin𝜑𝑧 )𝑧 − sin 𝜑𝑧 − 𝜔𝑐 𝑇 sin𝛽 𝑧 − sin 𝛽 − 𝜔𝑐 𝑇
𝐾(𝑧) = 2sin
2 (sin𝜔𝑐 𝑇)𝑧 − 1 (sin𝛼)𝑧 − sin 𝛼 − 𝜔𝑐 𝑇
• The controller is an interacting PID
• PD (with filter) +PI

Slide 18
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm
• The controller structure is in continuous time as follows :
(sin𝜙𝑧 )𝑠 + 𝜔𝑐 cos𝜙𝑧 sin𝛽 𝑠 + 𝜔𝑐 cos𝛽
𝐾 𝑠 = 𝜔𝑐
𝜔𝑐 𝑠 (sin𝛼)𝑠 + 𝜔𝑐 cos𝛼
• For a user specified gain crossover frequency 𝜔𝑐 and a PM 𝜃𝑐 at 𝜔𝑐,
the angles 𝜙𝑧 , 𝛽 and 𝛼 are the tuning parameters.
• 𝜙𝑧 ,𝛽 and 𝛼 vary between 0 and 90 degrees.
• The total phase shift contributed by the PID at the frequency 𝜔𝑐 is
given by
Δ𝜙 = 𝜙𝑧 + 𝛽 − 𝛼
which is defined as constraint as follows
Δ𝜙 − 𝜙𝑧 = 𝛽 − 𝛼
0 < 𝛽, 𝛼 < 90

Slide 19
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm
• The controller structure is in continuous time as follows :
(sin𝜙𝑧 )𝑠 + 𝜔𝑐 cos𝜙𝑧 sin𝛽 𝑠 + 𝜔𝑐 cos𝛽
𝐾 𝑠 = 𝜔𝑐
𝜔𝑐 𝑠 (sin𝛼)𝑠 + 𝜔𝑐 cos𝛼
• At first, an initial guess for 𝛼 and 𝛽 are used, then a plurality of the
free parameters are identified.
• Gridding technique is used to discard values of 𝛼 and 𝛽 that
violates the constraint or fail the Nyquist stability test.
Δ𝜙 − 𝜙𝑧 = 𝛽 − 𝛼
0 < 𝛽, 𝛼 < 90
• The patent states that the free parameters are calculated by
finding
• the smallest value of an objective function that includes a sensitivity
function and a complementary sensitivity function.
𝑆 = 𝐼 + 𝐺𝐾 −1 = 𝐼 + 𝐿 −1
𝑇 = 𝐼 + 𝐺𝐾 −1 𝐺𝐾 = 𝐼 + 𝐿 −1 𝐿
Slide 20
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm
• The patent states that the free parameters are calculated by
finding
• the smallest value of an objective function that includes a sensitivity
function and a complementary sensitivity function.
• A known robustness measure based on these transfer functions is
the 𝑀𝑆,𝑇 = max(𝑀𝑆, 𝑀𝑇)
𝑀𝑆 = max 𝑆(𝑗𝜔) 𝑀𝑇 = max 𝑇(𝑗𝜔)
𝜔 𝜔
• The objective function to be minimized is defined as follows:
min 𝐹 = max 𝑆 𝑗𝜔 − 2, 𝑇 𝑗𝜔 − 𝑇𝑚𝑎𝑥 , 𝑇𝑚𝑖𝑛 − 𝑇 𝑗𝜔
𝜔
where
1
𝑇𝑚𝑖𝑛 (𝜔) =
𝑚𝑎𝑥 1, 𝜔/ 𝜔0 /1.5
1
𝑇𝑚𝑎𝑥 (𝜔) =
𝑚𝑎𝑥 1, 𝜔/ 1.5𝜔0
Slide 21
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm
• The patent states that the values 𝛼&𝛽 are selected that minimizes
the following objective function :
min 𝐹 = max 𝑆 𝑗𝜔 − 2, 𝑇 𝑗𝜔 − 𝑇𝑚𝑎𝑥 , 𝑇𝑚𝑖𝑛 − 𝑇 𝑗𝜔
𝜔
where
1
𝑇𝑚𝑖𝑛(𝜔) =
𝑚𝑎𝑥 1, 𝜔/ 𝜔𝑜 /1.5
1
𝑇𝑚𝑎𝑥 (𝜔) =
𝑚𝑎𝑥 1, 𝜔/ 1.5𝜔𝑜
• The values of 𝛼&𝛽 are found via brute-force gridding, direct search,
or gradient-descent techniques.
• The patent states that a 𝐹𝑚𝑖𝑛 > 1 results with poor performance
and robustness for a given 𝜔𝑐.
• If 𝜔𝑐 is not provided by the uses the natural frequency value of the
process is used.
Slide 22
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm
• K=pidtune(sys, type or C0, wc, opts)
• sys: SISO dynamic system model
• type: ‘P’,’I’,’PD’,….’PID’, ‘PIDN’, ‘’PI2’,’PD2’,….’PID2’, ‘PIDN2’
C0: Predefined PID controller structure by the user
• wc: target value for the 0 dB gain crossover frequency of the tuned
open-loop response. The crossover frequency wc roughly sets the
control bandwidth.The closed-loop response time is approximately
1/wc. Defines the performance of the controller

Slide 23
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm
• opt = pidtuneOptions
• 'PhaseMargin‘: Defines the stability of the controller. Default
value 60.
• ‘DesignFocus’:
• 'balanced' (default) — For a given robustness, tune the controller to balance
reference tracking and disturbance rejection.
• 'reference-tracking' — Tune the controller to favor reference tracking, if possible.
• 'disturbance-rejection' — Tune the controller to favor disturbance rejection, if
possible.
• 'NumUnstablePoles’: Number of unstable poles in the plant.
• Nyquist criteria!

Slide 24
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm-Design Focus
• Using the design focus option enables the user to prioritize
reference tracking or disturbance rejection while keeping the
same crossover frequency.

Slide 25
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm-Design Focus
• Using the design focus option enables the user to prioritize
reference tracking or disturbance rejection while keeping the
same crossover frequency.

Slide 26
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm-Phase Margin
• Effect of various PM values.

Slide 27
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm-Phase Margin
• Specifying a lower phase margin gives more aggressive controllers
with higher controller gains. Look at the Gain Margin (GM)!

Slide 28
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm- Crossover frequency
• Effect of various crossover frequency values.

Slide 29
6.2 Emulation Controller Design: Mathworks PID tuning
algorithm- Crossover frequency
• The gain crossover frequency is related to the bandwidth!

Slide 30
Design𝐺 of𝑠 Discrete Controllers 𝐷 𝑠

𝐷 𝑧
𝐺 𝑧 𝐷 𝑧

Slide 31
6.3 Direct Discrete Controller Design via the Root Locus
• Closed loop Transfer function
𝑌 𝑧 𝐷 𝑧 𝐺𝐻 𝑧
𝑇 𝑧 = =
𝑅 𝑧 1 + 𝐷 𝑧 𝐺𝐻 𝑧
• Characteristic equation
𝑃 𝑧 = 1 + 𝐷 𝑧 𝐺𝐻 𝑧 = 0
𝑃 𝑧 = 1+𝐹 𝑧 = 0
where
𝐾𝐵 𝑧
𝐹 𝑧 =
𝐴 𝑧

Slide 32
6.3 Direct Discrete Controller Design via the Root Locus
• Open Loop Transfer Function
𝐾𝐵 𝑧
𝐹 𝑧 =
𝐴 𝑧
• Open-loop zeros
𝐵 𝑧 =0
• Open-loop poles
𝐴 𝑧 =0
• Closed Loop Transfer function
𝐾𝐵 𝑧
𝑇 𝑧 =
𝐴 𝑧 + 𝐾𝐵 𝑧
• Closed-loop zeros
𝐵 𝑧 =0
• Closed-loop poles
𝐴 𝑧 + 𝐾𝐵 𝑧 = 0
Slide 33
6.3 Direct Discrete Controller Design via the Root Locus
• Any closed-loop (for a K value) pole 𝑧 ∗ = 𝑎 + 𝑗𝑏 must satisfy

1 +𝐹 𝑧 =0
𝑧=𝑧 ∗
• Thus
𝐹 𝑧 ∗ = −1
• We can derive
• Angle Condition (for K>0):
∠𝐹 𝑧 ∗ = ±180 2𝑘 + 1 ,𝑘 = 0,1,2, …
• Magnitude Condition:
𝐹 𝑧∗ = 1

Slide 34
6.3 Direct Discrete Controller Design via the Root Locus
• We can derive
• Angle Condition:
∠𝐹 𝑧 ∗ = ±180 2𝑘 + 1 ,𝑘 = 0,1,2, …
• Magnitude Condition:
𝐹 𝑧∗ = 1

• Thus, any closed-loop pole location must satisfy the Angle and
Magnitude conditions.
• In the design of 𝐷 𝑧 , we have to tune the parameter of 𝐷 𝑧 such
that the desired closed loop pole locations satisfy the angle and
magnitude conditions.
• Drawing the Root-locus, in this context, will provide us a graphical
approach to obtain the necessary design parameters.

Slide 35
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
• How to draw Root-Locus?
• The steps are identical to ones in continuous time.
• All steps are derived from
𝑃 𝑧 =0
• Angle Condition:

∠𝐹 𝑧 ∗ = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …
𝐴𝑛𝑔𝑙𝑒𝑠 𝑜𝑓 𝑍𝑒𝑟𝑜𝑠 − 𝐴𝑛𝑔𝑙𝑒𝑠 𝑜𝑓 𝑃𝑜𝑙𝑒𝑠 = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …

• Magnitude Condition:
𝐹 𝑧∗ = 1

Slide 36
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
1. Obtain 𝐹 𝑧
𝐾 𝑧 + 𝑧1 𝑧 + 𝑧2 𝑧 + 𝑧3 … 𝑧 + 𝑧m
𝐹 𝑧 =
𝑧 + 𝑝1 𝑧 + 𝑝2 𝑧 + 𝑝3 … 𝑧 + 𝑝𝑛
• 𝑛: number of finite open loop poles
• 𝑚: number of finite open loop zeros

2. Find the starting and terminating points

• 𝐾 = 0 points are the open-loop pole locations
• 𝐾 = ∞ points are the open-loop zero locations

Note that if 𝑛 > 𝑚, then we have 𝑛 − 𝑚 zeros at ∞.

Slide 37
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
3. Determine the Root-locus on real axis via the angle conditions

∠𝐹 𝑧 ∗ = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …

4. Determine the asymptotes of the Root-locus

±180 2𝑘+1
• Angle of asymptotes = , 𝑘 = 0,1,2, …
𝑛−𝑚
• Intersection point asymptotes
− 𝑝1 + 𝑝1 + ⋯ + 𝑝𝑛 − 𝑧1 + 𝑧1 + ⋯ + 𝑧𝑚
−𝜎𝑥 =
𝑛−𝑚
• Note that, if 𝐧 = 𝐦 then, these definitions are not valid! No
asymptotes.

Slide 38
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
5. Find the break in/away points to/from the RL

𝐾𝐵 𝑧
𝐹 𝑧 = = −1
𝐴 𝑧
𝐴 𝑧
𝐾=−
𝐵 𝑧
• The points can be found via

𝑑𝐾 −𝐴′ 𝑧 𝐵 𝑧 − 𝐴 𝑧 𝐵′ 𝑧
= =0
𝑑𝑧 𝐵2 𝑧
Note that the solution will provide all the break in and break away
points −∞ < 𝐾 < ∞ . We only need the one valid for 0 < 𝐾 < ∞.

Slide 39
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
6. Determine the angle of departure/arrival via angle condition

∠𝐹 𝑧 ∗ = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …

𝜃𝑝3 = 180 − 𝜃𝑝1 + 𝜃𝑝2 − 𝜃𝑝𝑧

Slide 40
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
7. Find the intersection with imaginary-axis (Im)
1 + 𝐹 𝑧 ∗ = 0 + 𝑗𝑤
• Note that this step is quite meaningful in the s-domain since the jw
axis is the stability border. But it is NOT meaningful in z-domain.
• Stability test in z-Domain!
8. Find a corresponding gain value:
• If the angle condition is satisfied, then any point (closed-loop pole)
is on the RL and satisfies
𝐹 𝑧 =1
𝑧 + 𝑧1 𝑧 + 𝑧2 𝑧 + 𝑧3 … 𝑧 + 𝑧𝑚 1
=
𝑧 + 𝑝1 𝑧 + 𝑝2 𝑧 + 𝑝3 … 𝑧 + 𝑝𝒏 𝐾

Slide 41
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
• These 8 steps are useful to easily draw Root-Locus
• Angle and magnitude condition
• It is a sketch thus the RL is not precise.
• The Root-locus gives an idea of the overall dynamics of the system
• To analyze the system
• The Root-locus is also used to design a controller
• To analyze the design criteria.

Slide 42
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
• Problem: For the open-loop T.F.
𝐾
𝐺 𝑠 =
𝑠(𝑠 + 1)

Sketch the Root-Locus for 𝐾 > 0, with 𝑇 = 1𝑠

Slide 43
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
The discrete time representation of the system is :
1 − 𝑒 −𝑇𝑠 𝐾
𝐺 𝑧 =𝑍 ∙
𝑠 𝑠(𝑠 + 1)
0.3679𝐾 𝑧 + 0.7181
𝐺 𝑧 =
𝑧 − 1 𝑧 − 0.3679
The characteristic equation is
𝑃 𝑧 = 1+𝐺 𝑧

The open loop transfer function is

𝐾𝐵 𝑧 0.3679𝐾 𝑧 + 0.7181
𝐹 𝑧 = =
𝐴 𝑧 𝑧 − 1 𝑧 − 0.3679

Slide 44
6.3 Direct Discrete Controller Design via the Root Locus:
Sketching the RL
The open loop transfer function is
𝐾𝐵 𝑧 0.3679𝐾 𝑧 + 0.7181
𝐹 𝑧 = =
𝐴 𝑧 𝑧 − 1 𝑧 − 0.3679
2
𝑃 𝑧 = 𝑧 − 1.368 𝑧 + 0.3679 + 𝐾 0.3679 𝑧 + 0.2642 = 0
• Poles: 1.0000, 0.3679, Zero: -0.7181
• Break away/in points: 0.64, -2.08

Slide 45
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
Problem: Design a 𝐷 𝑧 (𝑇 = 0.2𝑠) controller such that
 𝑇𝑠 = 2𝑠, settling time 𝜁 = 0.5 ≈ 20% , damping ratio
Zero steady-state error
Reference tracking
Input disturbance
Output disturbance

Slide 46
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
Design Question 1: What should be the structure of the controller?
• P, PI, PD, PID, 2DOF PID
Design Question 2: What should the design criteria in z-domain?
• z-domain desired pole locations

Slide 47
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Time Domain Design Criteria
𝑇𝑠 = 2𝑠, 𝜁 = 0.5

• Let us firstly define the desired pole locations in the s-domain

4
𝑇𝑠 = ⇒ 𝜔𝑛 = 4
𝜁𝜔𝑛
• Thus,
𝑠1,2 = −𝜁𝜔𝑛 ± 𝑗𝜔𝑛 1 − 𝜁 2

𝑠1,2 = −2 ± 𝑗4 0.75
• Is the sampling Time 𝑇 = 0.2𝑠 sufficient?

Slide 48
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Is 𝑇 = 0.2𝑠 sufficient? Let us find the "damped natural frequency",
𝜔𝑑 in this context
𝜔𝑑 = 𝜔𝑛 1 − 𝜁 2
𝜔𝑑 = 3.464
and the sampling frequency,
2𝜋 2𝜋
𝑤𝑠 = = = 31.42
𝑇 0.2
𝜔 31.42
• Now, by calculating the ratio 𝑠, we can observe that ≈9
𝜔𝑑 3.46
samples will be collected in the damped oscillation response.
• Not BAD !
• But, anything else to consider?

Slide 49
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Time Domain Design Criteria
• 𝑇𝑠 = 2𝑠, 𝜁 = 0.5
• Let us firstly define the desired pole locations in the s-domain
4
𝑇𝑠 = ⇒ 𝜔𝑛 = 4
𝜁𝜔𝑛
• Thus,
𝑠1,2 = −𝜁𝜔𝑛 ± 𝑗𝜔𝑛 1 − 𝜁 2
𝑠1,2 = −2 ± 𝑗4 0.75
• The corresponding z-domain poles are obtained via 𝑧 = 𝑒 𝑠𝑇

𝑧1,2 = 𝑒 −2±𝑗4 0.75 0.2

Slide 50
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• The corresponding z-domain poles are obtained via 𝑧 = 𝑒 𝑠𝑇

𝑧1,2 = 𝑒 −0.4±𝑗0.8 0.75 = 𝑒 −0.4 cos 0.8 0.75 ± sin 0.8 0.75 𝑗

𝑧1,2 = 0.5158 ± 0.4281𝑗

• Note that
𝑒 𝑎+𝑏𝑗 = 𝑒 𝑎 𝑒𝑏𝑗 = 𝑒 𝑎 cos𝑏 + 𝑗 sin 𝑏

Slide 51
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Let us now find 𝐺 𝑧
1 − 𝑒 −𝑇𝑠 1
𝐺 𝑧 =𝑍 ∙
𝑠 𝑠 𝑠+2
• We obtain
0.01758 𝑧 + 0.8760
𝐺 𝑧 =
𝑧 − 1 𝑧 − 0.6703
• What should the structure of the controller?

Slide 52
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Let us set 𝐷 𝑧 = 𝐾 (a simple P controller)

• 𝐾 is the only parameter to be found.

• Desired pole locations
• Angle and magnitude conditions

Slide 53
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Angle condition

Slide 54
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Angle condition
∠𝐹 𝑧 ∗ = ±180 2𝑘 + 1 ,𝑘 = 0,1,2, …
𝐴𝑛𝑔𝑙𝑒 𝑜𝑓 𝑍𝑒𝑟𝑜𝑠 − 𝐴𝑛𝑔𝑙𝑒 𝑜𝑓 𝑃𝑜𝑙𝑒𝑠 = ±180 2𝑘 + 1 ,𝑘 = 0,1,2, …

• For the handled system

𝜃𝑧 − 𝜃𝑝1 + 𝜃𝑝2 = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …
where
0.4
𝜃𝑧 = tan−1 = 16.20
1.376
0.4
𝜃𝑝1 = 1800 − tan−1 = 1800 − 66.90 = 113.10
0.1703
0 −1
0.4
𝜃𝑝2 = 180 − tan = 1800 − 38.70 = 141.30
0.5

Slide 55
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• For the handled system
𝜃𝑧 − 𝜃𝑝1 + 𝜃𝑝2 = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …

16.20 − 113.10 − 141.30 = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …

−231.560 = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …
• There is a −51.560 angle deficiency. Thus,
• The desired closed loop are not on the Root Locus for a fixed gain
(K) value
• We need a positive angle compensation from the controller. Thus,
• Lead-lag
• PI, PD, PID

Slide 56
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
𝐾 𝑧+𝑎
• Let us set 𝐷 𝑧 = (a lead-lag controller)
𝑧+𝑏
• will add one zero and one pole
• 𝐾, 𝑎, 𝑏 are the parameter to be found.
• Desired pole locations
• Angle and magnitude conditions

Slide 57
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• From the angle condition, we can define now:
𝜃𝑧 + 𝜃𝐷𝑧 − 𝜃𝑝1 + 𝜃𝑝2 + 𝜃𝐷𝑝 = ± 2𝑘 + 1 1800
• Thus, the following condition must be satisfied
𝜃𝐷𝑧 − 𝜃𝐷𝑝 = 51.560
• Many possible solutions, we have to decide

Slide 58
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
𝜃𝐷𝑧 − 𝜃𝐷𝑝 = 51.560
• One of the possible solution is
• To cancel out the system pole with controller zero, 𝑧 = 0.6703

• Thus, the controller will be

𝐾 𝑧 − 0.6703
𝐷 𝑧 =
𝑧+𝑏

Slide 59
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Now, to end up with angle 51.560
𝜃𝑧 + 𝜃𝐷𝑧 − 𝜃𝑝1 + 𝜃𝑝2 = ± 2𝑘 + 1 1800
0.4
𝜃𝐷𝑧 = tan−1 = 51.560
0.5 − 𝑏
• The zero of the controller must be at
𝑏 = 0.2543
• Now, the only parameter to be found is the gain

𝐾 𝑧 − 0.6703
𝐷 𝑧 =
𝑧 − 0.2543

Slide 60
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Now, the only parameter to be found is the gain
𝐾 𝑧 − 0.6703
𝐷 𝑧 =
𝑧 − 0.2543
• Employ the magnitude condition to calculate 𝐾
𝐷 𝑧∗ 𝐺 𝑧∗ = 1

0.01758 𝑧 + 0.8760
𝐾 =1
𝑧 − 1 𝑧 − 0.2543 𝑧 ∗=0.5118+0.428𝑗
• 𝐾 = 12.67
• The resulting controller is
𝑈(𝑧) 12.67 𝑧 − 0.6703
𝐷 𝑧 = =
𝐸(𝑧) 𝑧 − 0.2543
• Then obtain the difference equations for deployment
𝑢 𝑘 =⋯
Slide 61
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Final Question: Are all design requirements satisfied?
 𝑇𝑠 = 2𝑠, 𝜁 = 0.5 ≈ 20%
Zero steady-state error
 Reference tracking
 Input disturbance
 Output disturbance

Slide 62
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
Problem: Design a 𝐷 𝑧 (𝑇 = 1𝑠) controller such that
 𝑤𝑛 = 0.72 𝜁 = 0.5 ≈ 20%
Zero steady-state error
Reference tracking
Input disturbance
Output disturbance

Slide 63
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
Design Question 1: What should be the structure of the controller?
• P, PI, PD, PID, 2DOF PID
Design Question 2: What should the design criteria in z-domain?
• z-domain desired pole locations

Slide 64
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Time Domain Design Criteria
𝑤𝑛 = 0.72, 𝜁 = 0.5

• Thus,
𝑠1,2 = −𝜁𝜔𝑛 ± 𝑗𝜔𝑛 1 − 𝜁 2

𝑠1,2 = −0.36 ± 𝑗0.72 0.75

• Is the sampling Time 𝑇 = 1𝑠 sufficient?
• Time Delay?
• Open-loop and closed loop dynamics?
• Zeros?

Slide 65
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• The corresponding z-domain poles are obtained via 𝑧 = 𝑒 𝑠𝑇
𝑧1,2 = 0.5158 ± 0.4281𝑗
• Let us now find 𝐺 𝑧
1 − 𝑒 −𝑇𝑠 𝑒 −2𝑠
𝐺 𝑧 =𝑍
𝑠 𝑠+1
• We obtain
0.6321
𝐺 𝑧 = 2
𝑧 𝑧 − 0.3675
• What should the structure of the controller?

Slide 66
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• We need a PI or PID controller. Let us set
𝐾𝑖
𝐷 𝑧 = 𝐾𝑝 +
1 − z−1

𝑧 −𝑎
𝐷 𝑧 =𝐾
𝑧−1
where
𝐾𝑝
𝐾 = 𝐾𝑝 + 𝐾𝑖 , 𝑎 =
𝐾𝑝 + 𝐾𝑖
• 𝐾, 𝑎 are the parameters to be found.
• Desired pole locations
• Angle and magnitude conditions

Slide 67
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Angle condition
∠𝐹 𝑧 ∗ = ±180 2𝑘 + 1 ,𝑘 = 0,1,2, …
0.6321
• For the handled system 𝐺 𝑧 = , 𝑧1,2 = 0.5158 ± 0.4281𝑗
𝑧 2 𝑧−0.3675

Slide 68
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Angle condition
∠𝐹 𝑧 ∗ = ±180 2𝑘 + 1 ,𝑘 = 0,1,2, …
• For the handled system
𝜃𝑑𝑧 − 𝜃𝑝1 + 𝜃𝑝2,3 + 𝜃𝑑𝑝 = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …
𝜃𝑑𝑧 − 136.90 + 36 + 36 + 64.62 = ±180 2𝑘 + 1 , 𝑘 = 0,1,2, …
• The zero of controller must contribute with 93.52 angle, Thus,
a ⇒ 𝑧 = 0.5881
• The controller is then
𝑧 − 0.5881
𝐷 𝑧 =𝐾
𝑧−1

Slide 69
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Now, the only parameter to be found is the gain
𝑧 − 0.5881
𝐷 𝑧 =𝐾
𝑧−1
• Employ the magnitude condition to calculate 𝐾
𝐷 𝑧∗ 𝐺 𝑧∗ = 1
𝑧 − 0.5881 0.6321
𝐾 =1
𝑧 − 1 𝑧 2 𝑧 − 0.3675 𝑧 ∗=0.5158+0.4281𝑗
• 𝐾 = 0.5070
• The resulting controller is
𝑈(𝑧) 𝑧 − 0.5881
𝐷 𝑧 = = 0.5070
𝐸(𝑧) 𝑧−1
• From 𝐾, 𝑎 values, obtain 𝐾𝑝 &𝐾𝑖
• Obtain the difference equations for deployment
𝑢 𝑘 =⋯
Slide 70
6.3 Direct Discrete Controller Design via the Root Locus:
Design Examples
• Final Question: Are all design requirements satisfied?
𝑤𝑛 = 0.72 𝜁 = 0.5
Zero steady-state error
 Reference tracking
 Input disturbance
 Output disturbance

Slide 71
6.4 Cascade and Feed Forward Control Structures
• Up to this point, we handled single feedback control loops.
• Alternative Control Structures
• Cascade control structure
• Feedforward control structure
• The selection of the control structures depends on
• the process
• the measurement variables
• Control objectives

Slide 72
6.4 Cascade and Feed Forward Control Structures
• Architectures for improved disturbance rejection
• Feed Forward
• Cascade
• Both require additional instrumentation and engineering time in
return for a controller better able to reject disturbances
• Neither architecture benefits nor detracts from set point tracking
performance

Slide 73
6.4.1 Cascade Control Structure
• Cascade control can improve control system performance over
single-loop control whenever either:
• Disturbances affect a measurable intermediate or secondary
process output that directly affects the primary process output that
we wish to control;
• the gain of the secondary process, including the actuator, is
nonlinear.

Slide 74

A shell and tube heat exchanger.

6.4.1 Cascade Control Structure
• Cascade control of effluent temperature via shell side pressure
control

Slide 75
6.4.1 Cascade Control Structure

Slide 76
6.4.1 Cascade Control Structure
• The design of the structure is accomplished in a two fold
• Design the inner loop controller such that it has short settling time
so that 𝑇𝑖𝑛𝑛𝑒𝑟 (𝑧) ≈ 1.
• Success requires that the settling time of the inner secondary inner loop is
significantly faster than that of the outer primary outer loop
• Design the outer loop controller to enhance the control system
performance

Slide 77
6.4.1 Cascade Control Structure: Misconceptions…
• Generally, adding a secondary controller does not make a feedback
control system faster
• Secondary controllers are often more complicated, e.g., PI or PID,
than they should be
• Cascade control is overused
• Must be a disturbance to localize by secondary control
• Often, system can be improved by removing cascade control
(replace with simpler single-loop systems)
• You are asking for trouble if the dynamics of the secondary loop
are similar to (or slower than!) the dynamics of the primary loop

Slide 78
6.4.2 Feedforward Control Structure
• So far, most of the focus of this course has been on feedback
control. In certain situations, the performance of control systems
can be enhanced greatly by the application of feedforward control.
What you need to look for are two key characteristics:
• An identifiable disturbance is affecting significantly the measured
variable, in spite of the attempts of a feedback control system to
regulate these effects
• This disturbance can be measured, perhaps with the addition of
instrumentation.
• Nice example: Car approaching hill
• See how steep the hill is (measurement)
• Push on pedal to keep steady speed
• Feedback is to wait for slowing before adjusting pedal

Slide 79
6.4.2 Feedforward Control Structure
• How do we manipulate 𝑈(𝑧) to cancel the effect that 𝐷(𝑧) will have
on 𝑌(𝑧)?

• We can define the output as

𝑌 𝑧 = 𝐷 𝑧 𝐺𝑑 (𝑧) + 𝑈 𝑧 𝐺𝑝 (𝑧)
• If 𝑌(𝑧) is to be unaffected by 𝐷(𝑧), then we want 𝑌(𝑧) = 0. Thus,
we can define
𝐺𝑑 𝑧
𝑈 𝑧 =− 𝐷 𝑧 = 𝐺𝑓𝑓 𝑧 𝐷(𝑧)
𝐺𝑝 𝑧

Slide 80
6.4.2 Feedforward Control Structure
𝐺𝑑 𝑧
𝑈 𝑧 =− 𝐷 𝑧 = 𝐺𝑓𝑓 𝑧 𝐷(𝑧)
𝐺𝑝 𝑧
• If 𝐺𝑑 (𝑧) and 𝐺𝑝 𝑧 are
𝐾𝑝 𝑧 −𝐿𝑝 𝐾𝑑 𝑧 −𝐿𝑑
𝐺𝑝 𝑧 = ; 𝐺 (𝑧) =
𝑇𝑝𝑧 + 1 𝑑 𝑇𝑑 𝑧 + 1
then
𝐾𝑑 𝑧 −𝐿𝑑
𝑇 𝑧+1 𝐾𝑑 𝑇𝑝 𝑧 + 1 −
𝐺𝑓𝑓 𝑧 = − 𝑑 −𝐿𝑝 = − 𝑧 𝐿𝑑−𝐿𝑝
𝐾𝑝 𝑧 𝐾𝑝 𝑇𝑑 𝑧 + 1
𝑇𝑝𝑧 + 1
or
𝐾𝑑 𝑇𝑝 + 1
𝐺𝑓𝑓 𝑧 = −
𝐾𝑝 𝑇𝑑 + 1

Slide 81
6.4.2 Feedforward Control Structure
𝐾𝑑 𝑧 −𝐿𝑑
𝑇𝑑 𝑧 + 1 𝐾𝑑 𝑇𝑝 𝑧 + 1 − 𝐿𝑑−𝐿𝑝
𝐺𝑓𝑓 𝑧 =− =− 𝑧
𝐾𝑝 𝑧 −𝐿𝑝 𝐾𝑝 𝑇𝑑 𝑧 + 1
𝑇𝑝𝑧 + 1
or
𝐾𝑑 𝑇𝑝 + 1
𝐺𝑓𝑓 𝑧 = −
𝐾𝑝 𝑇𝑑 + 1

Slide 82
6.4.2 Feedforward Control Structure
𝐾𝑑 𝑧 −𝐿𝑑
𝑇𝑑 𝑧 + 1 𝐾𝑑 𝑇𝑝 𝑧 + 1 − 𝐿𝑑−𝐿𝑝
𝐺𝑓𝑓 𝑧 =− =− 𝑧
𝐾𝑝 𝑧 −𝐿𝑝 𝐾𝑝 𝑇𝑑 𝑧 + 1
𝑇𝑝𝑧 + 1
or
𝐾𝑑 𝑇𝑝 + 1
𝐺𝑓𝑓 𝑧 = −
𝐾𝑝 𝑇𝑑 + 1

Slide 83
6.4.2 Feedforward Control Structure
𝐾𝑑 𝑧 −𝐿𝑑
𝑇𝑑 𝑧 + 1 𝐾𝑑 𝑇𝑝 𝑧 + 1 − 𝐿𝑑−𝐿𝑝
𝐺𝑓𝑓 𝑧 =− =− 𝑧
𝐾𝑝 𝑧 −𝐿𝑝 𝐾𝑝 𝑇𝑑 𝑧 + 1
𝑇𝑝𝑧 + 1
• The exponential term must be negative
𝐿𝑑 > 𝐿𝑝
• The order of the numerator must be less than or equal to that of the
denominator. Which of the following is realizable?
(𝑧 + 1)(𝑧 + 2)(𝑧 + 3)
𝐺𝑓𝑓 𝑧 =
(𝑧 + 4)(𝑧 + 5)
(𝑧 + 1)(𝑧 + 3)
𝐺𝑓𝑓 𝑧 =
(𝑧 + 4)(𝑧 + 5)
(𝑧 + 1)(𝑧 + 3)
𝐺𝑓𝑓 𝑧 = 3
𝑧 + 𝑧2 + 𝑧 + 1
Slide 84
6.4.2 Feedforward Control Structure
• Try first cascade control
• Use feedforward when
• Disturbance can be isolated and measured
• There is no “inner loop” variable that responds to the manipulated
variable
• Cannot use the same valve to control the disturbance

Slide 85