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3-Bit Asynchronous Counter.

This laboratory report describes the design and simulation of a 3-bit asynchronous up-down counter. It discusses the theory behind asynchronous counters and how they differ from synchronous counters. The report outlines the requirements, including the hardware and software tools used. It provides the circuit diagram and explains the procedure, describing how the output of each D flip-flop is chained to act as the clock for the next flip-flop. The observations show that the counter successfully counts from 000 to 111 and back to 000 when a clock pulse is applied. The conclusion confirms that a 3-bit asynchronous up-down counter has been successfully implemented through both Verilog code simulation and TinkerCAD circuit simulation.

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Priyanshu Modi
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772 views5 pages

3-Bit Asynchronous Counter.

This laboratory report describes the design and simulation of a 3-bit asynchronous up-down counter. It discusses the theory behind asynchronous counters and how they differ from synchronous counters. The report outlines the requirements, including the hardware and software tools used. It provides the circuit diagram and explains the procedure, describing how the output of each D flip-flop is chained to act as the clock for the next flip-flop. The observations show that the counter successfully counts from 000 to 111 and back to 000 when a clock pulse is applied. The conclusion confirms that a 3-bit asynchronous up-down counter has been successfully implemented through both Verilog code simulation and TinkerCAD circuit simulation.

Uploaded by

Priyanshu Modi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Laboratory Report

On

3-bit Asynchronous Counter

(DEC Lab)

Saurabh Padhi - 2029179


Aditya Chakraborty - 2029184
Saishree Chinthakindi - 2029186

B. Tech Programme in Computer Science and


Communication Engineering

School of Electronics Engineering Kalinga Institute


of Industrial Technology, Deemed to be University,
Bhubaneswar, India

November 2021
OBJECTIVE

● Simulation of 3- bit asynchronous up-down counter using Verilog HDL in EDA


Playground.
● Design and Verification of 3- bit asynchronous up-down counter using D Flip-Flop using
TinkerCAD

THEORY

A 3-bit asynchronous counter is a counter that counts values in the range 0-7, i.e 000, 001, 010,
011, 100, 101, 110, 111.

The difference between a synchronous counter and an asynchronous counter is that in a


synchronous counter the clock cycles and synced i.e they work in unison but in an asynchronous
counter, the clock cycle is not in sync.

Therefore to implement an asynchronous counter use the output of the first flip-flop as a clock
for the second and so on.

The output of all these flip flops is combined to get the counts from 0-7.

REQUIREMENTS

For Design and Coding: Online Compiler- EDA Playground.

For Circuit Combination:

1. Online Simulator- TinkerCAD.


2. LED (x3)
3. Resistor (x3)
4. IC- 74HC73 (x2)
5. IC- 74HC00 (x2)
6. Function Generator
7. Power Supply
8. Connecting wires

CIRCUIT DIAGRAM

PROCEDURE
To implement a 3-bit asynchronous counter, we first design a flip flop which does the following:-
If reset is set to 0, it alters the input provided to it to produce the output. This means if ‘0’is ‘1’
and vice versa.
To implement the asynchronous counter we initially pass reset, clock, and initial value to the first
flip flop. The output of this flip flop marks the L.S.B of the output.
Then the Qbar value of the first input/output flip flop is passed as a clock to the second flip flop.
The reset value remains the same. The output of this flip flop is the value of the second bit.
The same is repeated for the third flip flop which takes the clock from the Qbar value of the
second output and provides the 3rd bit or M.S.B. All three of this input when seen together
makes a 3-bit counter.
HDL CODE DEVELOPMENT
OBSERVATIONS/RESULTS

DISCUSSION OF RESULTS:

This TinkerCAD simulation shows that the ICs used have been configured to operate as toggles
giving a maximum count of zero (000), advancing through 001, 010 to seven (111), and back to
zero again, when clock pulse is shifted the count starts from 111, 110 to 000.

CONCLUSION:

Thus, we have successfully implemented the 3-bit Asynchronous up-down Counter in both the
software and its simulation.

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